repo_name
stringlengths 6
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1.04M
⌀ | license
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|---|---|---|---|---|---|
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif.vhd
|
4
|
5686
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/i2s_ctrl.vhd
|
3
|
16906
|
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng.vhd
|
2
|
4028
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.vhd
|
1
|
11785
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes.vhd
|
1
|
5073
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng.vhd
|
1
|
4001
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth.vhd
|
1
|
11105
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 39,
C_DOUT_WIDTH => 39,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 39,
C_DIN_WIDTH => 39,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 39,
C_DIN_WIDTH => 39,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_1_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen.vhd
|
1
|
6070
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
gen_fifo_stim: IF(C_CH_TYPE /= 2) GENERATE
-- DIN_WIDTH < DOUT_WIDTH
gen_din_lt_dout: IF(C_DIN_WIDTH < C_DOUT_WIDTH) GENERATE
BEGIN
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END GENERATE gen_din_lt_dout;
-- DIN_WIDTH >= DOUT_WIDTH
gen_din_gteq_dout:IF(C_DIN_WIDTH >= C_DOUT_WIDTH) GENERATE
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END GENERATE gen_din_gteq_dout;
END GENERATE gen_fifo_stim;
----------------------------------------------
-- Wiring logic stimulus generation
----------------------------------------------
gen_wiring_stim: IF (C_CH_TYPE = 2) GENERATE
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
pr_w_en <= PRC_WR_EN;
END GENERATE gen_wiring_stim;
END ARCHITECTURE;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
|
1
|
16635
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
paulmoon/seng440
|
huffman/adder_testbench.vhd
|
1
|
2522
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:55:12 07/31/2014
-- Design Name:
-- Module Name: C:/Documents and Settings/paulmoon/Desktop/SENG440/huffman/adder_testbench.vhd
-- Project Name: huffman
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY adder_testbench IS
END adder_testbench;
ARCHITECTURE behavior OF adder_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT adder
PORT(
clock : IN std_logic;
a : IN std_logic_vector(31 downto 0);
b : IN std_logic_vector(31 downto 0);
result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal a : std_logic_vector(31 downto 0) := (others => '0');
signal b : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal result : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: adder PORT MAP (
clock => clock,
a => a,
b => b,
result => result
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- insert stimulus here
a <= std_logic_vector(to_unsigned(1, 32));
b <= std_logic_vector(to_unsigned(1, 32));
wait;
end process;
END;
|
mit
|
meninge/dauphin
|
myaxifullmaster_v1_0_M00_AXI.vhd
|
1
|
30895
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myaxifullmaster_v1_0_M00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
C_M_AXI_BURST_LEN : integer := 16;
-- Thread ID Width
C_M_AXI_ID_WIDTH : integer := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : integer := 32;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : integer := 0;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : integer := 0;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : integer := 0;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : integer := 0;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
mymaster_addr_inw : in std_logic_vector(31 downto 0);
mymaster_addr_inr : in std_logic_vector(31 downto 0);
mymaster_burstnb_inw : in std_logic_vector(31 downto 0);
mymaster_burstnb_inr : in std_logic_vector(31 downto 0);
mymaster_startw : in std_logic;
mymaster_startr : in std_logic;
mymaster_busyw : out std_logic;
mymaster_busyr : out std_logic;
mymaster_sensor : out std_logic_vector(31 downto 0); -- For various debug signals
mymaster_fifor_data : out std_logic_vector(31 downto 0);
mymaster_fifor_en : out std_logic;
mymaster_fifor_cnt : in std_logic_vector(15 downto 0);
mymaster_fifow_data : in std_logic_vector(31 downto 0);
mymaster_fifow_en : out std_logic;
mymaster_fifow_cnt : in std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal.
M_AXI_ACLK : in std_logic;
-- Global Reset Singal. This Signal is Active Low
M_AXI_ARESETN : in std_logic;
-- Master Interface Write Address ID
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Master Interface Write Address
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
M_AXI_AWLOCK : out std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each write transaction.
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and control information.
M_AXI_AWVALID : out std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated control signals
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data.
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
-- Write last. This signal indicates the last transfer in a write burst.
M_AXI_WLAST : out std_logic;
-- Optional User-defined signal in the write data channel.
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available
M_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response.
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status of the write transaction.
M_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
M_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address.
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
M_AXI_ARLOCK : out std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each read transaction
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and control information
M_AXI_ARVALID : out std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated control signals
M_AXI_ARREADY : in std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Master Read Data
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer
M_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer in a read burst
M_AXI_RLAST : in std_logic;
-- Optional User-defined signal in the read address channel.
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
M_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
M_AXI_RREADY : out std_logic
);
end myaxifullmaster_v1_0_M00_AXI;
architecture implementation of myaxifullmaster_v1_0_M00_AXI is
-- Function called clogb2 that the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- C_TRANSACTIONS_NUM is the width of the index counter for
-- number of beats in a burst write or burst read transaction.
constant C_TRANSACTIONS_NUM : integer := clogb2(C_M_AXI_BURST_LEN-1);
-- State machine to initialize counter, initialize write transactions,
-- initialize read transactions and comparison of read data with the written data words.
signal write_busy : std_logic := '0';
signal read_busy : std_logic := '0';
-- AXI4FULL signals
--AXI4 internal temp signals
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
-- Beat counts in current bursts
signal write_index : unsigned(C_TRANSACTIONS_NUM downto 0);
signal read_index : unsigned(C_TRANSACTIONS_NUM downto 0);
-- Buffered flags to indicate end of current bursts
signal write_index_end : std_logic := '0';
signal read_index_end : std_logic := '0';
-- Size of C_M_AXI_BURST_LEN length burst in bytes
signal burst_size_bytes : std_logic_vector(31 downto 0);
-- Burst counters
signal write_burst_counter : unsigned(31 downto 0);
signal read_burst_counter : unsigned(31 downto 0);
-- Buffered flags to indicate end of bursts
signal write_burst_end : std_logic := '0';
signal read_burst_end : std_logic := '0';
signal start_single_burst_write : std_logic;
signal start_single_burst_read : std_logic;
signal writes_done : std_logic;
signal reads_done : std_logic;
signal burst_write_active : std_logic;
signal burst_read_active : std_logic;
--Interface response error flags
signal write_resp_error : std_logic;
signal read_resp_error : std_logic;
signal wnext : std_logic;
signal rnext : std_logic;
begin
----------------------
-- I/O Connections assignments
----------------------
--I/O Connections. Write Address (AW)
M_AXI_AWID <= (others => '0');
--The AXI address is a concatenation of the target base address + active offset range
M_AXI_AWADDR <= axi_awaddr;
--Burst LENgth is number of transaction beats, minus 1
M_AXI_AWLEN <= std_logic_vector( to_unsigned(C_M_AXI_BURST_LEN - 1, 8) );
--Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
M_AXI_AWSIZE <= std_logic_vector( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
--INCR burst type is usually used, except for keyhole bursts
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= '0';
--Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (others => '1');
M_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
M_AXI_WDATA <= axi_wdata;
--WARNING: In the current code, all bursts are complete and aligned
M_AXI_WSTRB <= (others => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
--Write Response (B)
M_AXI_BREADY <= axi_bready;
--Read Address (AR)
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= axi_araddr;
--Burst LENgth is number of transaction beats, minus 1
M_AXI_ARLEN <= std_logic_vector( to_unsigned(C_M_AXI_BURST_LEN - 1, 8) );
--Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
M_AXI_ARSIZE <= std_logic_vector( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
--INCR burst type is usually used, except for keyhole bursts
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= '0';
--Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (others => '1');
M_AXI_ARVALID <= axi_arvalid;
--Read and Read Response (R)
M_AXI_RREADY <= axi_rready;
-- Utility signal: burst size in bytes
burst_size_bytes <= std_logic_vector(to_unsigned(C_M_AXI_BURST_LEN * (C_M_AXI_DATA_WIDTH/8), burst_size_bytes'length));
----------------------
-- Write Address Channel
----------------------
-- The purpose of the write address channel is to request the address and
-- command information for the entire transaction. It is a single beat
-- of information.
-- The AXI4 Write address channel in this example will continue to initiate
-- write commands as fast as it is allowed by the slave/interconnect.
-- The address will be incremented on each accepted address transaction,
-- by burst_size_byte to point to the next address.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_awvalid <= '0';
else
-- If previously not valid , start next transaction
if (axi_awvalid = '0') and (start_single_burst_write = '1') then
axi_awvalid <= '1';
-- Once asserted, VALIDs cannot be deasserted,
-- so axi_awvalid must wait until transaction is accepted
elsif (M_AXI_AWREADY = '1') and (axi_awvalid = '1') then
axi_awvalid <= '0';
else
axi_awvalid <= axi_awvalid;
end if;
end if;
end if;
end process;
-- Next address after AWREADY indicates previous address acceptance
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_awaddr <= mymaster_addr_inw;
else
if (M_AXI_AWREADY= '1') and (axi_awvalid = '1') then
axi_awaddr <= std_logic_vector(unsigned(axi_awaddr) + unsigned(burst_size_bytes));
end if;
end if;
end if;
end process;
----------------------
-- Write Data Channel
----------------------
--The write data will continually try to push write data across the interface.
--The amount of data accepted will depend on the AXI slave and the AXI
--Interconnect settings, such as if there are FIFOs enabled in interconnect.
--Note that there is no explicit timing relationship to the write address channel.
--The write channel has its own throttling flag, separate from the AW channel.
--Synchronization between the channels must be determined by the user.
--The simpliest but lowest performance would be to only issue one address write
--and write data burst at a time.
--In this example they are kept in sync by using the same address increment
--and burst sizes. Then the AW and W channels have their transactions measured
--with threshold counters as part of the user logic, to make sure neither
--channel gets too far ahead of each other.
--Forward movement occurs when the write channel is valid and ready
wnext <= M_AXI_WREADY and axi_wvalid;
-- WVALID logic, similar to the axi_awvalid always block above
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_wvalid <= '0';
else
if (axi_wvalid = '0') and (start_single_burst_write = '1') then
-- If previously not valid, start next transaction
axi_wvalid <= '1';
-- If WREADY and too many writes, throttle WVALID
-- Once asserted, VALIDs cannot be deasserted, so WVALID must wait until burst is complete with WLAST
elsif (wnext = '1') and (axi_wlast = '1') then
axi_wvalid <= '0';
else
axi_wvalid <= axi_wvalid;
end if;
end if;
end if;
end process;
-- WLAST generation on the MSB of a counter underflow
-- WVALID logic, similar to the axi_awvalid always block above
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_wlast <= '0';
-- axi_wlast is asserted when the write index
-- count reaches the penultimate count to synchronize
-- with the last write data when write_index is b1111
-- elsif (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
else
if (( (write_index = C_M_AXI_BURST_LEN-2) and C_M_AXI_BURST_LEN >= 2) and wnext = '1' ) or (C_M_AXI_BURST_LEN = 1) then
axi_wlast <= '1';
-- Deassert axi_wlast when the last write data has been
-- accepted by the slave with a valid response
elsif wnext = '1' then
axi_wlast <= '0';
elsif (axi_wlast = '1') and (C_M_AXI_BURST_LEN = 1) then
axi_wlast <= '0';
end if;
end if;
end if;
end process;
-- Burst length counter
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (start_single_burst_write = '1') or (mymaster_startw = '1') then
write_index <= (others => '0');
else
if (wnext = '1') and (write_index /= C_M_AXI_BURST_LEN-1) then
write_index <= write_index + 1;
end if;
end if;
end if;
end process;
------------------------------
-- Write Response (B) Channel
------------------------------
--The write response channel provides feedback that the write has committed
--to memory. BREADY will occur when all of the data and the write address
--has arrived and been accepted by the slave.
--The write issuance (number of outstanding write addresses) is started by
--the Address Write transfer, and is completed by a BREADY/BRESP.
--While negating BREADY will eventually throttle the AWREADY signal,
--it is best not to throttle the whole data channel this way.
--The BRESP bit [1] is used indicate any errors from the interconnect or
--slave for the entire write burst. This example will capture the error
--into the ERROR output.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_bready <= '0';
-- accept/acknowledge bresp with axi_bready by the master
-- when M_AXI_BVALID is asserted by slave
else
if (M_AXI_BVALID = '1') and (axi_bready = '0') then
axi_bready <= '1';
-- deassert after one clock cycle
elsif axi_bready = '1' then
axi_bready <= '0';
end if;
end if;
end if;
end process;
-- Flag any write response errors
write_resp_error <= axi_bready and M_AXI_BVALID and M_AXI_BRESP(1);
------------------------------
-- Read Address Channel
------------------------------
--The Read Address Channel (AW) provides a similar function to the
--Write Address channel- to provide the tranfer qualifiers for the burst.
--In this example, the read address increments in the same
--manner as the write address channel.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_arvalid <= '0';
-- If previously not valid , start next transaction
else
if (axi_arvalid = '0') and (start_single_burst_read = '1') then
axi_arvalid <= '1';
elsif (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
-- Next address after ARREADY indicates previous address acceptance
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_araddr <= mymaster_addr_inr;
else
if (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
axi_araddr <= std_logic_vector(unsigned(axi_araddr) + unsigned(burst_size_bytes));
end if;
end if;
end if;
end process;
----------------------------------
-- Read Data (and Response) Channel
----------------------------------
-- Forward movement occurs when the channel is valid and ready
rnext <= M_AXI_RVALID and axi_rready;
-- Burst length counter. Uses extra counter register bit to indicate
-- terminal count to reduce decode logic
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (start_single_burst_read = '1') or (mymaster_startr = '1') then
read_index <= (others => '0');
else
if (rnext = '1') and (read_index <= C_M_AXI_BURST_LEN-1) then
read_index <= read_index + 1;
end if;
end if;
end if;
end process;
-- The Read Data channel returns the results of the read request
-- Note: in this component the data consumer (FIFO) is already known to be able to take all the data at full speed,
-- so no need to throttle the RREADY signal
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_rready <= '0';
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when M_AXI_RVALID is asserted by slave
else
if M_AXI_RVALID = '1' then
if (M_AXI_RLAST = '1') and (axi_rready = '1') then
axi_rready <= '0';
else
axi_rready <= '1';
end if;
end if;
end if;
end if;
end process;
-- Flag any read response errors
read_resp_error <= axi_rready and M_AXI_RVALID and M_AXI_RRESP(1);
------------------------------------
-- Error register, status register
------------------------------------
-- Register and hold read/write interface errors
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
mymaster_sensor <= (others => '0');
else
if write_resp_error = '1' then
mymaster_sensor(0) <= '1';
end if;
if mymaster_startw = '1' then
mymaster_sensor(15 downto 0) <= (others => '0');
end if;
if read_resp_error = '1' then
mymaster_sensor(16) <= '1';
end if;
if mymaster_startr = '1' then
mymaster_sensor(31 downto 16) <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------------
-- Example design throttling
----------------------------------
-- For maximum port throughput, this user example code will try to allow
-- each channel to run as independently and as quickly as possible.
-- However, there are times when the flow of data needs to be throtted by
-- the user application. This example application requires that data is
-- not read before it is written and that the write channels do not
-- advance beyond an arbitrary threshold (say to prevent an
-- overrun of the current read address by the write address).
-- From AXI4 Specification, 13.13.1: "If a master requires ordering between
-- read and write transactions, it must ensure that a response is received
-- for the previous transaction before issuing the next transaction."
-- This example accomplishes this user application throttling through:
-- -Reads wait for writes to fully complete
-- -Address writes wait when not read + issued transaction counts pass
-- a parameterized threshold
-- -Writes wait when a not read + active data burst count pass
-- a parameterized threshold
-- write_burst_counter counter keeps track with the number of burst transactions initiated
-- against the number of burst transactions the master needs to initiate
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
write_burst_counter <= unsigned(mymaster_burstnb_inw);
write_burst_end <= '0';
if unsigned(mymaster_burstnb_inw) = 1 then
write_burst_end <= '1';
end if;
else
if (M_AXI_AWREADY = '1') and (axi_awvalid = '1') then
write_burst_end <= '0';
if write_burst_counter = 1 then
write_burst_end <= '1';
end if;
if write_burst_end = '0' then
write_burst_counter <= write_burst_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- read_burst_counter counter keeps track with the number of burst transaction initiated
-- against the number of burst transactions the master needs to initiate
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
read_burst_counter <= unsigned(mymaster_burstnb_inr);
read_burst_end <= '0';
if unsigned(mymaster_burstnb_inr) = 1 then
read_burst_end <= '1';
end if;
else
if (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
read_burst_end <= '0';
if read_burst_counter = 1 then
read_burst_end <= '1';
end if;
if read_burst_end = '0' then
read_burst_counter <= read_burst_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- burst_write_active signal is asserted when there is a burst write transaction
-- is initiated by the assertion of start_single_burst_write. burst_write_active
-- signal remains asserted until the burst write is accepted by the slave
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
burst_write_active <= '0';
--The burst_write_active is asserted when a write burst transaction is initiated
else
if start_single_burst_write = '1' then
burst_write_active <= '1';
elsif (M_AXI_BVALID = '1') and (axi_bready = '1') then
burst_write_active <= '0';
end if;
end if;
end if;
end process;
-- Check for last write completion.
-- This logic is to qualify the last write count with the final write response.
-- This demonstrates how to confirm that a write has been committed.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
writes_done <= '0';
--The reads_done should be associated with a rready response
--elsif (M_AXI_RVALID && axi_rready && (read_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_rlast)
else
if (M_AXI_BVALID = '1') and (axi_bready = '1') and (write_burst_end = '1') then
writes_done <= '1';
end if;
end if;
end if;
end process;
-- burst_read_active signal is asserted when there is a burst write transaction
-- is initiated by the assertion of start_single_burst_write. start_single_burst_read
-- signal remains asserted until the burst read is accepted by the master
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
burst_read_active <= '0';
-- The burst_write_active is asserted when a write burst transaction is initiated
else
if start_single_burst_read = '1' then
burst_read_active <= '1';
elsif (M_AXI_RVALID = '1') and (axi_rready = '1') and (M_AXI_RLAST = '1') then
burst_read_active <= '0';
end if;
end if;
end if;
end process;
-- Check for last read completion.
-- This logic is to qualify the last read count with the final read response.
-- This demonstrates how to confirm that a read has been committed.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
reads_done <= '0';
--The reads_done should be associated with a rready response
--elsif (M_AXI_RVALID && axi_rready && (read_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_rlast)
else
if (M_AXI_RVALID = '1') and (axi_rready = '1') and (read_index = C_M_AXI_BURST_LEN-1) and (read_burst_end = '1') then
reads_done <= '1';
end if;
end if;
end if;
end process;
----------------------------------
-- Main functionality
----------------------------------
-- State machine for Write operations
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
-- reset condition
-- All the signals are set default values under reset condition
write_busy <= '0';
start_single_burst_write <= '0';
else
-- State transition
case write_busy is
when '0' =>
-- Detect when to launch bursts
if mymaster_startw = '1' and (unsigned(mymaster_burstnb_inw) > 0) then
write_busy <= '1';
else
write_busy <= '0';
end if;
when '1' =>
-- This state is responsible to issue start_single_write pulse to initiate a write transaction.
-- Write transactions will be issued until burst_write_active signal is asserted.
if writes_done = '1' then
write_busy <= '0';
else
write_busy <= '1';
-- Launch write bursts only when the FIFO is full enough
if
(axi_awvalid = '0') and (start_single_burst_write = '0') and
(burst_write_active = '0') and (unsigned(mymaster_fifow_cnt) >= C_M_AXI_BURST_LEN)
then
start_single_burst_write <= '1';
else
-- Immediately clear to generate a pulse
start_single_burst_write <= '0';
end if;
end if;
when others =>
write_busy <= '0';
end case;
end if; -- Not reset
end if; -- Clock
end process;
-- State machine for Read operations
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
-- reset condition
-- All the signals are set default values under reset condition
read_busy <= '0';
start_single_burst_read <= '0';
else
-- state transition
case read_busy is
when '0' =>
-- Detect when to launch bursts
if (mymaster_startr = '1') and (unsigned(mymaster_burstnb_inr) > 0) then
read_busy <= '1';
else
read_busy <= '0';
end if;
when '1' =>
-- This state is responsible to issue start_single_read pulse to initiate a read transaction.
-- Read transactions will be issued until burst_read_active signal is asserted.
if reads_done = '1' then
read_busy <= '0';
else
read_busy <= '1';
-- Launch read bursts only when the FIFO is empty enough
if
(axi_arvalid = '0') and (burst_read_active = '0') and
(start_single_burst_read = '0') and (unsigned(mymaster_fifor_cnt) >= C_M_AXI_BURST_LEN)
then
start_single_burst_read <= '1';
else
-- Immediately clear to generate a pulse
start_single_burst_read <= '0';
end if;
end if;
when others =>
read_busy <= '0';
end case;
end if; -- Not reset
end if; -- Clock
end process;
mymaster_busyw <= write_busy;
mymaster_busyr <= read_busy;
mymaster_fifor_data <= M_AXI_RDATA;
axi_wdata <= mymaster_fifow_data;
mymaster_fifor_en <= '1' when (M_AXI_ARESETN = '1') and (mymaster_startr = '0') and (rnext = '1') else '0';
mymaster_fifow_en <= '1' when (M_AXI_ARESETN = '1') and (mymaster_startw = '0') and (wnext = '1') else '0';
end implementation;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
|
1
|
11106
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 38,
C_DOUT_WIDTH => 38,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 38,
C_DIN_WIDTH => 38,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 38,
C_DIN_WIDTH => 38,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_3_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
meninge/dauphin
|
nnlayer.vhd
|
1
|
13589
|
-- This is one layer of a neural network
-- It contains several neurons that process input frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for frame and number of neurons
FSIZE : natural := 784;
NBNEU : natural := 200;
-- fifo count
CNTW : natural := 16
);
port (
clk : in std_logic;
-- reset
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0) ;
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(CNTW - 1 downto 0)
);
end nnlayer;
architecture synth of nnlayer is
-- Max fanout for signals distributed to all BRAM-based blocks
constant FANOUT : natural := 4;
-- The address to access neuron memory, read and write
constant WADDR : natural := 10;
-- Arrays of signals to instantiate the neurons
signal arr_write_data : std_logic_vector(NBNEU*WDATA-1 downto 0) := (others => '0');
-- Input data
signal arr_data_in : std_logic_vector(NBNEU*WDATA-1 downto 0) := (others => '0');
-- Controls signals, go to every neuron through distribuf
signal sg_ctrl_we_mode : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_we_shift : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_we_valid : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_accu_clear : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_accu_add : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_shift_en : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_shift_copy : std_logic_vector(0 downto 0):= (others => '0');
-- Address signal
signal sg_addr : std_logic_vector(WADDR - 1 downto 0):= (others => '0');
-- Signal to connect the sensor we valid from the good fifo to the fsm inside the nnlayer
signal sg_sensor_we_valid : std_logic := '0';
-- Corresponding arrays
signal arr_ctrl_we_mode : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_we_shift : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_we_valid : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_accu_clear : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_accu_add : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_shift_en : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_shift_copy : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_addr : std_logic_vector(NBNEU * WADDR - 1 downto 0) := (others => '0');
-- Declaration of signal array to wire we_next and we_prev of every
-- neuron
-- We need 1 wire between two neurons and 2 more for first and last one.
-- Hence NBNEU + 1 values.
type match_array is array (0 to NBNEU) of std_logic;
signal we_match : match_array := (others => '0');
type match_array_waccu is array (0 to NBNEU) of std_logic_vector(WACCU - 1 downto 0);
-- Declaration of sh_data array with NBNEU wires
signal sh_data_match : match_array_waccu := (others => (others => '0'));
-- Declaration of sensor arrays
-- We use only the first one of this array
signal sensors_shift_match : match_array:= (others => '0');
signal sensors_copy_match : match_array:= (others => '0');
signal sensors_we_mode_match : match_array:= (others => '0');
signal sensors_we_shift_match : match_array:= (others => '0');
signal sensors_we_valid_match : match_array:= (others => '0');
-- FIFO management signals
signal sg_in_fifo_out_ack : std_logic := '0';
--signal sg_out_fifo_in_ack : std_logic;
signal sg_out_fifo_in_cnt : std_logic_vector(CNTW - 1 downto 0) := (others => '0');
-- Component declaration: one neuron
component neuron is
generic (
-- Parameters for the neurons
WDATA : natural := 32;
WWEIGHT : natural := 16;
WACCU : natural := 32;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
-- Control signals
ctrl_we_mode : in std_logic;
ctrl_we_shift : in std_logic;
ctrl_we_valid : in std_logic;
ctrl_accu_clear : in std_logic;
ctrl_accu_add : in std_logic;
ctrl_shift_en : in std_logic;
ctrl_shift_copy : in std_logic;
-- Address used for Read and Write
addr : in std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
we_prev : in std_logic;
we_next : out std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
-- Scan chain to extract values
sh_data_in : in std_logic_vector(WACCU-1 downto 0);
sh_data_out : out std_logic_vector(WACCU-1 downto 0);
-- Sensors, for synchronization with the controller
sensor_shift : out std_logic;
sensor_copy : out std_logic;
sensor_we_mode : out std_logic;
sensor_we_shift : out std_logic;
sensor_we_valid : out std_logic
);
end component;
-- FSM for this layer
component fsm is
generic (
-- global parameters of layers
NB_NEURONS: natural := 200;
-- parameters of a neuron
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
reset : in std_logic;
clk : in std_logic;
-- Control signals
-- (go to all neurons)
ctrl_we_mode : out std_logic;
ctrl_we_shift : out std_logic;
ctrl_we_valid : out std_logic;
ctrl_accu_clear : out std_logic;
ctrl_accu_add : out std_logic;
ctrl_shift_en : out std_logic;
ctrl_shift_copy : out std_logic;
-- Address used for Read and Write
-- (go to all neurons)
addr : out std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
-- go to first neuron
n0_we_prev : out std_logic;
-- come from last neuron
nN_we_next : in std_logic;
-- Sensors, for synchronization with the controller
-- go to first neurons
sensor_shift : in std_logic;
sensor_copy : in std_logic;
sensor_we_mode : in std_logic;
sensor_we_shift : in std_logic;
sensor_we_valid : in std_logic;
-- inputs
fsm_mode : in std_logic;
-- input FIFO control
out_fifo_in_cnt : in std_logic_vector(CNTW-1 downto 0)
-- output FIFO control
--out_fifo_in_ack : out std_logic
);
end component;
-- Component declaration: distribution tree to limit fanout
component distribuf is
generic(
WDATA : natural := 32;
NBOUT : natural := 32;
FANOUT : natural := 32
);
port(
clk : in std_logic;
-- Input
idata : in std_logic_vector(WDATA-1 downto 0);
-- Outputs
odata : out std_logic_vector(WDATA*NBOUT-1 downto 0)
);
end component;
begin
-------------------------------------------------------------------
-- Instantiate the fanout distribution trees
-------------------------------------------------------------------
-- Fanout distribution tree: write_data
i_buf_write_data: distribuf
generic map (
WDATA => WDATA,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => write_data,
odata => arr_write_data
);
-- Fanout distribution tree: data_in
i_buf_data_in: distribuf
generic map (
WDATA => WDATA,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => data_in,
odata => arr_data_in
);
-- ctrl_we_mode distribution tree
i_ctrl_we_mode: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_mode,
odata => arr_ctrl_we_mode
);
-- ctrl_we_shift distribution tree
i_ctrl_we_shift: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_shift,
odata => arr_ctrl_we_shift
);
-- ctrl_we_valid distribution tree
i_ctrl_we_valid: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_valid,
odata => arr_ctrl_we_valid
);
-- ctrl_accu_clear distribution tree
i_ctrl_accu_clear: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_accu_clear,
odata => arr_ctrl_accu_clear
);
-- ctrl_accu_add distribution tree
i_ctrl_accu_add: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_accu_add,
odata => arr_ctrl_accu_add
);
-- ctrl_shift_en distribution tree
i_ctrl_shift_en: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_shift_en,
odata => arr_ctrl_shift_en
);
-- ctrl_shift_copy distribution tree
i_ctrl_shift_copy: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_shift_copy,
odata => arr_ctrl_shift_copy
);
-- we_mode distribution tree
i_addr: distribuf
generic map (
WDATA => WADDR,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_addr,
odata => arr_addr
);
-------------------------------------------------------------------
-- Instantiate the neurons
-------------------------------------------------------------------
gen_neu: for i in 0 to NBNEU-1 generate
i_neu_normal: neuron
generic map (
-- Parameters for the neurons
WDATA => WDATA,
WWEIGHT => WWEIGHT,
WACCU => WACCU,
-- Parameters for the frame size
FSIZE => FSIZE,
WADDR => WADDR
)
port map (
clk => clk,
-- Control signals
ctrl_we_mode => arr_ctrl_we_mode(i),
ctrl_we_shift => arr_ctrl_we_shift(i),
ctrl_we_valid => arr_ctrl_we_valid(i),
ctrl_accu_clear => arr_ctrl_accu_clear(i),
ctrl_accu_add => arr_ctrl_accu_add(i),
ctrl_shift_en => arr_ctrl_shift_en(i),
ctrl_shift_copy => arr_ctrl_shift_copy(i),
-- Address used for Read and Write
addr => arr_addr((i+1)*WADDR-1 downto i*WADDR),
-- Ports for Write Enable
we_prev => we_match(i),
we_next => we_match(i + 1),
write_data => arr_write_data((i+1)*WDATA-1 downto i*WDATA),
-- Data input, 2 bits
data_in => arr_data_in((i+1)*WDATA-1 downto i*WDATA),
-- Scan chain to extract values
-- Inversed from we_prev and we_next
sh_data_in => sh_data_match(i+1),
sh_data_out => sh_data_match(i),
-- Sensors, for synchronization with the controller
-- We use only the first (we suppose that synthesis will remove wires)
sensor_shift => sensors_shift_match(i),
sensor_copy => sensors_copy_match(i),
sensor_we_mode => sensors_we_mode_match(i),
sensor_we_shift => sensors_we_shift_match(i),
-- Not used
sensor_we_valid => open
);
end generate;
-------------------------------------------------------------------
-- Instantiate the FSM
-------------------------------------------------------------------
fsm_gen: fsm
generic map (
NB_NEURONS => NBNEU,
WDATA => WDATA,
WWEIGHT => WWEIGHT,
WACCU => WACCU,
FSIZE => FSIZE,
WADDR => WADDR
)
port map (
reset => clear,
clk => clk,
ctrl_we_mode => sg_ctrl_we_mode(0),
ctrl_we_shift => sg_ctrl_we_shift(0),
ctrl_we_valid => sg_ctrl_we_valid(0),
ctrl_accu_clear => sg_ctrl_accu_clear(0),
ctrl_accu_add => sg_ctrl_accu_add(0),
ctrl_shift_en => sg_ctrl_shift_en(0),
ctrl_shift_copy => sg_ctrl_shift_copy(0),
addr => sg_addr,
n0_we_prev => we_match(0),
nN_we_next => we_match(NBNEU),
sensor_shift => sensors_shift_match(0),
sensor_copy => sensors_copy_match(0),
sensor_we_mode => sensors_we_mode_match(0),
sensor_we_shift => sensors_we_shift_match(0),
sensor_we_valid => sg_sensor_we_valid,
fsm_mode => write_mode,
out_fifo_in_cnt => sg_out_fifo_in_cnt
--out_fifo_in_ack => sg_out_fifo_in_ack
);
sg_sensor_we_valid <= (data_in_valid and not(write_mode)) or (write_enable and write_mode);
data_in_ready <= sg_ctrl_accu_add(0) and not(write_mode);
write_ready <= sg_ctrl_we_valid(0) and write_mode;
sg_out_fifo_in_cnt <= out_fifo_room;
data_out <= sh_data_match(0);
sh_data_match(NBNEU) <= std_logic_vector(to_unsigned(0, sh_data_match(NBNEU)'length));
--data_out_valid <= sg_out_fifo_in_ack;
data_out_valid <= sensors_shift_match(0);
end_of_frame <= '0';
end architecture;
|
mit
|
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_Distortion_1.0/sources_1/new/Distortion.vhd
|
1
|
12598
|
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--************* Distortion /Overdrive ************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Distortion is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end Distortion;
architecture Behavioral of Distortion is
signal y_temp_s : signed(31 downto 0):= x"00000000";
begin
process(clk_48, options)
begin
if en(0)= '1' then
if rising_edge(clk_48) then
if options="1000" then --weak overdrive
if signed(x(23 downto 0)) >= 70000 then
y<=std_logic_vector(to_signed(70000,32));
elsif signed(x(23 downto 0)) <= -70000 then
y<=std_logic_vector(to_signed(-70000,32));
else
y<=x;
end if;
end if;
if options="0100" then --strong overdrive
if signed(x(23 downto 0)) >= 70000 then
y<=std_logic_vector(to_signed(90000,32));
elsif signed(x(23 downto 0)) <= -70000 then
y<=std_logic_vector(to_signed(-90000,32));
else
y<=x;
end if;
end if;
if options="0010" then --overdrive
if signed(x(23 downto 0)) >= 50000 then
y <= std_logic_vector(to_signed(50000,32));
elsif signed(x(23 downto 0)) <= -50000 then
y <= std_logic_vector(to_signed(-50000,32));
else
y<=x;
end if;
end if;
if options="0001" then --distortion
if signed(x(23 downto 0)) >= 0 and signed(x(23 downto 0)) < 50 then
y<=std_logic_vector(to_signed(200,32));
elsif signed(x(23 downto 0)) >= 50 and signed(x(23 downto 0)) < 100 then
y<=std_logic_vector(to_signed(500,32));
elsif signed(x(23 downto 0)) >= 100 and signed(x(23 downto 0)) < 200 then
y<=std_logic_vector(to_signed(1000,32));
elsif signed(x(23 downto 0)) >= 200 and signed(x(23 downto 0)) < 500 then
y<=std_logic_vector(to_signed(2000,32));
elsif signed(x(23 downto 0)) >= 500 and signed(x(23 downto 0)) < 1000 then
y<=std_logic_vector(to_signed(3000,32));
elsif signed(x(23 downto 0)) >= 1000 and signed(x(23 downto 0)) < 2000 then
y<=std_logic_vector(to_signed(4000,32));
elsif signed(x(23 downto 0)) >= 2000 and signed(x(23 downto 0)) < 3000 then
y<=std_logic_vector(to_signed(5000,32));
elsif signed(x(23 downto 0)) >= 3000 and signed(x(23 downto 0)) < 4500 then
y<=std_logic_vector(to_signed(5500,32));
elsif signed(x(23 downto 0)) >= 4000 and signed(x(23 downto 0)) < 5000 then
y<=std_logic_vector(to_signed(6000,32));
elsif signed(x(23 downto 0)) >= 5000 and signed(x(23 downto 0)) < 5500 then
y<=std_logic_vector(to_signed(7000,32));
elsif signed(x(23 downto 0)) >= 5500 and signed(x(23 downto 0)) < 6000 then
y<=std_logic_vector(to_signed(8000,32));
elsif signed(x(23 downto 0)) >= 6000 and signed(x(23 downto 0)) < 6500 then
y<=std_logic_vector(to_signed(9000,32));
elsif signed(x(23 downto 0)) >= 6500 and signed(x(23 downto 0)) < 7000 then
y<=std_logic_vector(to_signed(10000,32));
elsif signed(x(23 downto 0)) >= 7000 and signed(x(23 downto 0)) < 7500 then
y<=std_logic_vector(to_signed(20000,32));
elsif signed(x(23 downto 0)) >= 7500 and signed(x(23 downto 0)) < 8000 then
y<=std_logic_vector(to_signed(30000,32));
elsif signed(x(23 downto 0)) >= 8000 and signed(x(23 downto 0)) < 8500 then
y<=std_logic_vector(to_signed(50000,32));
elsif signed(x(23 downto 0)) >= 8500 and signed(x(23 downto 0)) < 9000 then
y<=std_logic_vector(to_signed(70000,32));
elsif signed(x(23 downto 0)) >= 9000 and signed(x(23 downto 0)) < 9500 then
y<=std_logic_vector(to_signed(95000,32));
elsif signed(x(23 downto 0)) >= 9500 and signed(x(23 downto 0)) < 10000 then
y<=std_logic_vector(to_signed(105000,32));
elsif signed(x(23 downto 0)) >= 10000 and signed(x(23 downto 0)) < 15000 then
y<=std_logic_vector(to_signed(110000,32));
elsif signed(x(23 downto 0)) >= 15000 and signed(x(23 downto 0)) < 20000 then
y<=std_logic_vector(to_signed(115000,32));
elsif signed(x(23 downto 0)) >= 20000 and signed(x(23 downto 0)) < 25000 then
y<=std_logic_vector(to_signed(120000,32));
elsif signed(x(23 downto 0)) >= 25000 and signed(x(23 downto 0)) < 30000 then
y<=std_logic_vector(to_signed(125000,32));
elsif signed(x(23 downto 0)) >= 30000 and signed(x(23 downto 0)) < 35000 then
y<=std_logic_vector(to_signed(130000,32));
elsif signed(x(23 downto 0)) >= 35000 and signed(x(23 downto 0)) < 40000 then
y<=std_logic_vector(to_signed(135000,32));
elsif signed(x(23 downto 0)) >= 40000 and signed(x(23 downto 0)) < 45000 then
y<=std_logic_vector(to_signed(140000,32));
elsif signed(x(23 downto 0)) >= 45000 and signed(x(23 downto 0)) < 50000 then
y<=std_logic_vector(to_signed(145000,32));
elsif signed(x(23 downto 0)) >= 50000 and signed(x(23 downto 0)) < 60000 then
y<=std_logic_vector(to_signed(150000,32));
elsif signed(x(23 downto 0)) >= 60000 and signed(x(23 downto 0)) < 70000 then
y<=std_logic_vector(to_signed(160000,32));
elsif signed(x(23 downto 0)) >= 70000 and signed(x(23 downto 0)) < 80000 then
y<=std_logic_vector(to_signed(170000,32));
elsif signed(x(23 downto 0)) >= 80000 and signed(x(23 downto 0)) < 90000 then
y<=std_logic_vector(to_signed(180000,32));
elsif signed(x(23 downto 0)) >= 90000 and signed(x(23 downto 0)) < 100000 then
y<=std_logic_vector(to_signed(190000,32));
elsif signed(x(23 downto 0)) >= 100000 and signed(x(23 downto 0)) < 120000 then
y<=std_logic_vector(to_signed(200000,32));
elsif signed(x(23 downto 0)) >= 120000 and signed(x(23 downto 0)) < 140000 then
y<=std_logic_vector(to_signed(220000,32));
elsif signed(x(23 downto 0)) >= 140000 and signed(x(23 downto 0)) < 160000 then
y<=std_logic_vector(to_signed(240000,32));
elsif signed(x(23 downto 0)) >= 160000 and signed(x(23 downto 0)) < 170000 then
y<=std_logic_vector(to_signed(260000,32));
elsif signed(x(23 downto 0)) >= 170000 and signed(x(23 downto 0)) < 190000 then
y<=std_logic_vector(to_signed(270000,32));
elsif signed(x(23 downto 0)) >= 190000 and signed(x(23 downto 0)) < 200000 then
y<=std_logic_vector(to_signed(290000,32));
elsif signed(x(23 downto 0)) >= 200000 and signed(x(23 downto 0)) < 220000 then
y<=std_logic_vector(to_signed(300000,32));
elsif signed(x(23 downto 0)) >= 220000 and signed(x(23 downto 0)) < 240000 then
y<=std_logic_vector(to_signed(320000,32));
elsif signed(x(23 downto 0)) >= 240000 and signed(x(23 downto 0)) < 260000 then
y<=std_logic_vector(to_signed(340000,32));
elsif signed(x(23 downto 0)) >= 260000 and signed(x(23 downto 0)) < 280000 then
y<=std_logic_vector(to_signed(360000,32));
elsif signed(x(23 downto 0)) >= 280000 and signed(x(23 downto 0)) < 300000 then
y<=std_logic_vector(to_signed(380000,32));
elsif signed(x(23 downto 0)) >= 300000 then
y<=std_logic_vector(to_signed(400000,32));
elsif signed(x(23 downto 0)) <= 0 and signed(x(23 downto 0)) > -50 then
y<=std_logic_vector(to_signed(-200,32));
elsif signed(x(23 downto 0)) <= -50 and signed(x(23 downto 0)) > -100 then
y<=std_logic_vector(to_signed(-500,32));
elsif signed(x(23 downto 0)) <= -100 and signed(x(23 downto 0)) > -200 then
y<=std_logic_vector(to_signed(-1000,32));
elsif signed(x(23 downto 0)) <= -200 and signed(x(23 downto 0)) > -500 then
y<=std_logic_vector(to_signed(-2000,32));
elsif signed(x(23 downto 0)) <= -500 and signed(x(23 downto 0)) > -1000 then
y<=std_logic_vector(to_signed(-3000,32));
elsif signed(x(23 downto 0)) <= -1000 and signed(x(23 downto 0)) > -2000 then
y<=std_logic_vector(to_signed(-4000,32));
elsif signed(x(23 downto 0)) <= -2000 and signed(x(23 downto 0)) > -3000 then
y<=std_logic_vector(to_signed(-5000,32));
elsif signed(x(23 downto 0)) <= -3000 and signed(x(23 downto 0)) > -4500 then
y<=std_logic_vector(to_signed(-5500,32));
elsif signed(x(23 downto 0)) <= -4000 and signed(x(23 downto 0)) > -5000 then
y<=std_logic_vector(to_signed(-6000,32));
elsif signed(x(23 downto 0)) <= -5000 and signed(x(23 downto 0)) > -5500 then
y<=std_logic_vector(to_signed(-7000,32));
elsif signed(x(23 downto 0)) <= -5500 and signed(x(23 downto 0)) > -6000 then
y<=std_logic_vector(to_signed(-8000,32));
elsif signed(x(23 downto 0)) <= -6000 and signed(x(23 downto 0)) > -6500 then
y<=std_logic_vector(to_signed(-9000,32));
elsif signed(x(23 downto 0)) <= -6500 and signed(x(23 downto 0)) > -7000 then
y<=std_logic_vector(to_signed(-10000,32));
elsif signed(x(23 downto 0)) <= -7000 and signed(x(23 downto 0)) > -7500 then
y<=std_logic_vector(to_signed(-20000,32));
elsif signed(x(23 downto 0)) <= -7500 and signed(x(23 downto 0)) > -8000 then
y<=std_logic_vector(to_signed(-30000,32));
elsif signed(x(23 downto 0)) <= -8000 and signed(x(23 downto 0)) > -8500 then
y<=std_logic_vector(to_signed(-50000,32));
elsif signed(x(23 downto 0)) <= -8500 and signed(x(23 downto 0)) > -9000 then
y<=std_logic_vector(to_signed(-70000,32));
elsif signed(x(23 downto 0)) <= -9000 and signed(x(23 downto 0)) > -9500 then
y<=std_logic_vector(to_signed(-95000,32));
elsif signed(x(23 downto 0)) <= -9500 and signed(x(23 downto 0)) > -10000 then
y<=std_logic_vector(to_signed(-105000,32));
elsif signed(x(23 downto 0)) <= -10000 and signed(x(23 downto 0)) > -15000 then
y<=std_logic_vector(to_signed(-110000,32));
elsif signed(x(23 downto 0)) <= -15000 and signed(x(23 downto 0)) > -20000 then
y<=std_logic_vector(to_signed(-115000,32));
elsif signed(x(23 downto 0)) <= -20000 and signed(x(23 downto 0)) > -25000 then
y<=std_logic_vector(to_signed(-120000,32));
elsif signed(x(23 downto 0)) <= -25000 and signed(x(23 downto 0)) > -30000 then
y<=std_logic_vector(to_signed(-125000,32));
elsif signed(x(23 downto 0)) <= -30000 and signed(x(23 downto 0)) > -35000 then
y<=std_logic_vector(to_signed(-130000,32));
elsif signed(x(23 downto 0)) <= -35000 and signed(x(23 downto 0)) > -40000 then
y<=std_logic_vector(to_signed(-135000,32));
elsif signed(x(23 downto 0)) <= -40000 and signed(x(23 downto 0)) > -45000 then
y<=std_logic_vector(to_signed(-140000,32));
elsif signed(x(23 downto 0)) <= -45000 and signed(x(23 downto 0)) > -50000 then
y<=std_logic_vector(to_signed(-145000,32));
elsif signed(x(23 downto 0)) <= -50000 and signed(x(23 downto 0)) > -60000 then
y<=std_logic_vector(to_signed(-150000,32));
elsif signed(x(23 downto 0)) <= -60000 and signed(x(23 downto 0)) > -70000 then
y<=std_logic_vector(to_signed(-160000,32));
elsif signed(x(23 downto 0)) <= -70000 and signed(x(23 downto 0)) > -80000 then
y<=std_logic_vector(to_signed(-170000,32));
elsif signed(x(23 downto 0)) <= -80000 and signed(x(23 downto 0)) > -90000 then
y<=std_logic_vector(to_signed(-180000,32));
elsif signed(x(23 downto 0)) <= -90000 and signed(x(23 downto 0)) > -100000 then
y<=std_logic_vector(to_signed(-190000,32));
elsif signed(x(23 downto 0)) <= -100000 and signed(x(23 downto 0)) > -120000 then
y<=std_logic_vector(to_signed(-200000,32));
elsif signed(x(23 downto 0)) <= -120000 and signed(x(23 downto 0)) > -140000 then
y<=std_logic_vector(to_signed(-240000,32));
elsif signed(x(23 downto 0)) <= -140000 and signed(x(23 downto 0)) > -160000 then
y<=std_logic_vector(to_signed(-240000,32));
elsif signed(x(23 downto 0)) <= -160000 and signed(x(23 downto 0)) > -170000 then
y<=std_logic_vector(to_signed(-260000,32));
elsif signed(x(23 downto 0)) <= -170000 and signed(x(23 downto 0)) > -190000 then
y<=std_logic_vector(to_signed(-270000,32));
elsif signed(x(23 downto 0)) <= -190000 and signed(x(23 downto 0)) > -200000 then
y<=std_logic_vector(to_signed(-290000,32));
elsif signed(x(23 downto 0)) <= -200000 and signed(x(23 downto 0)) > -220000 then
y<=std_logic_vector(to_signed(-300000,32));
elsif signed(x(23 downto 0)) <= -220000 and signed(x(23 downto 0)) > -240000 then
y<=std_logic_vector(to_signed(-320000,32));
elsif signed(x(23 downto 0)) <= -240000 and signed(x(23 downto 0)) > -260000 then
y<=std_logic_vector(to_signed(-340000,32));
elsif signed(x(23 downto 0)) <= -260000 and signed(x(23 downto 0)) > -280000 then
y<=std_logic_vector(to_signed(-360000,32));
elsif signed(x(23 downto 0)) <= -280000 and signed(x(23 downto 0)) > -300000 then
y<=std_logic_vector(to_signed(-380000,32));
elsif signed(x(23 downto 0)) <= -300000 then
y<=std_logic_vector(to_signed(-400000,32));
else
y<=x;
end if;
end if;
end if; --rising_edge(clk)
else --if effect not enabled
y<=x;
end if;--en
end process;
end Behavioral;
|
mit
|
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng.vhd
|
4
|
3998
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/parallel2serial.vhd
|
1
|
2570
|
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity parallel2serial is
generic (
DATA_WIDTH : integer := 8;
TX_WIDTH : integer := 1
);
port (
clk_i : in std_logic;
en_i : in std_logic;
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(TX_WIDTH-1 downto 0);
ss_o : out std_logic
) ;
end parallel2serial;
architecture behave of parallel2serial is
----------------------------------
constant SHIFT_STAGES : integer := integer(ceil(real(DATA_WIDTH)/real(TX_WIDTH)));
----------------------------------
signal shift_count : integer range 0 to SHIFT_STAGES := SHIFT_STAGES-1;
signal send_data : std_logic_vector(SHIFT_STAGES*TX_WIDTH-1 downto 0) := (others=>'0');
signal sending : std_logic := '0';
signal tx_done : std_logic := '0';
----------------------------------
begin
send_ctrl: process(clk_i, en_i, data_i, sending, tx_done)
begin
if rising_edge(clk_i) then
if en_i = '1' and sending='0' then
send_data <= (others=>'0');
send_data(DATA_WIDTH-1 downto 0) <= data_i; --register new data to send when not sending
sending <= '1';
elsif sending='1' and tx_done='1' then
sending <= '0';
end if;
end if;
end process;
shift_out: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
if sending = '1' and tx_done='0' and send_i='1' then
shift_o <= send_data((shift_count)*(TX_WIDTH)+(TX_WIDTH)-1 downto (shift_count)*(TX_WIDTH)); --MSB first
else
shift_o <= (others=>'0');
end if;
end if;
end process;
count_shift: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
if sending = '1' and tx_done='0' and send_i='1' then
if shift_count = 0 then
shift_count <= SHIFT_STAGES-1;
tx_done <= '1';
else
shift_count <= shift_count - 1;
end if;
ss_o <= '0';
else
tx_done <= '0';
ss_o <= '1';
end if;
end if;
end process;
busy_o <= sending;
done_o <= tx_done;
end behave;
|
mit
|
ktemkin/ruby-adept
|
firmware/epp_stream/epp_controller.vhd
|
1
|
5976
|
----------------------------------------------------------------------------------
-- EPP Controller
--
-- Original Author: Chris McClelland
-- Altered for use with EPP periperhals by Kyle Temkin
--
-- Portions copyright (c) 2013 Binghamton University
-- Copyright (c) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.-
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iThisR3 when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
mit
|
Dasio/FIT-Projects
|
INC/fsm.vhd
|
1
|
10689
|
-- fsm.vhd: Finite State Machine
-- Author(s): David Mikus([email protected])
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
-- Input signals
KEY : in std_logic_vector(15 downto 0);
CNT_OF : in std_logic;
-- Output signals
FSM_CNT_CE : out std_logic;
FSM_MX_MEM : out std_logic;
FSM_MX_LCD : out std_logic;
FSM_LCD_WR : out std_logic;
FSM_LCD_CLR : out std_logic
);
end entity fsm;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of fsm is
type t_state is (TEST,TEST1_1,TEST1_2,TEST1_3,TEST1_4,TEST1_5,TEST1_6,TEST1_7,TEST1_8,TEST1_9,
TEST2_1,TEST2_2,TEST2_3,TEST2_4,TEST2_5,TEST2_6,TEST2_7,TEST2_8,TEST2_9,TEST2_10,PRINT_MESSAGE_OK,PRINT_MESSAGE_FAIL, FINISH_OK,FINISH_FAIL,FINISH);
signal present_state, next_state : t_state;
begin
-- -------------------------------------------------------
sync_logic : process(RESET, CLK)
begin
if (RESET = '1') then
present_state <= TEST;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
-- -------------------------------------------------------
next_state_logic : process(present_state, KEY, CNT_OF)
begin
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST =>
next_state <= TEST;
if (KEY(8) = '1') then
next_state <= TEST1_1;
elsif (KEY(1) = '1') then
next_state <= TEST2_1;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_1 =>
next_state <= TEST1_1;
if (KEY(4) = '1') then
next_state <= TEST1_2;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_2 =>
next_state <= TEST1_2;
if (KEY(3) = '1') then
next_state <= TEST1_3;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_3 =>
next_state <= TEST1_3;
if (KEY(2) = '1') then
next_state <= TEST1_4;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_4 =>
next_state <= TEST1_4;
if (KEY(1) = '1') then
next_state <= TEST1_5;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_5 =>
next_state <= TEST1_5;
if (KEY(5) = '1') then
next_state <= TEST1_6;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_6 =>
next_state <= TEST1_6;
if (KEY(7) = '1') then
next_state <= TEST1_7;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_7 =>
next_state <= TEST1_7;
if (KEY(5) = '1') then
next_state <= TEST1_8;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_8 =>
next_state <= TEST1_8;
if (KEY(5) = '1') then
next_state <= FINISH_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_1 =>
next_state <= TEST2_1;
if (KEY(5) = '1') then
next_state <= TEST2_2;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_2 =>
next_state <= TEST2_2;
if (KEY(1) = '1') then
next_state <= TEST2_3;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_3 =>
next_state <= TEST2_3;
if (KEY(7) = '1') then
next_state <= TEST2_4;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_4 =>
next_state <= TEST2_4;
if (KEY(7) = '1') then
next_state <= TEST2_5;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_5 =>
next_state <= TEST2_5;
if (KEY(8) = '1') then
next_state <= TEST2_6;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_6 =>
next_state <= TEST2_6;
if (KEY(8) = '1') then
next_state <= TEST2_7;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_7 =>
next_state <= TEST2_7;
if (KEY(3) = '1') then
next_state <= TEST2_8;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_8 =>
next_state <= TEST2_8;
if (KEY(6) = '1') then
next_state <= TEST2_9;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_9 =>
next_state <= TEST2_9;
if (KEY(0) = '1') then
next_state <= TEST2_10;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_10 =>
next_state <= TEST2_10;
if (KEY(0) = '1') then
next_state <= FINISH_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_OK =>
next_state <= PRINT_MESSAGE_OK;
if (CNT_OF = '1') then
next_state <= FINISH;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_FAIL =>
next_state <= PRINT_MESSAGE_FAIL;
if (CNT_OF = '1') then
next_state <= FINISH;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH_OK =>
next_state <= FINISH_OK;
if (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH_FAIL =>
next_state <= FINISH_FAIL;
if (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH =>
next_state <= FINISH;
if (KEY(15) = '1') then
next_state <= TEST;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
next_state <= TEST;
end case;
end process next_state_logic;
-- -------------------------------------------------------
output_logic : process(present_state, KEY)
begin
FSM_CNT_CE <= '0';
FSM_MX_MEM <= '0';
FSM_MX_LCD <= '0';
FSM_LCD_WR <= '0';
FSM_LCD_CLR <= '0';
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST | TEST1_1 | TEST1_2 | TEST1_3 | TEST1_4 | TEST1_5 | TEST1_6 | TEST1_7 | TEST1_8 | TEST1_9 | TEST2_1 | TEST2_2 | TEST2_3 | TEST2_4 | TEST2_5 | TEST2_6 | TEST2_7| TEST2_8 | TEST2_9 | TEST2_10 | FINISH_OK | FINISH_FAIL =>
if (KEY(14 downto 0) /= "000000000000000") then
FSM_LCD_WR <= '1';
end if;
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
when PRINT_MESSAGE_OK =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
FSM_MX_MEM <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_FAIL =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
FSM_MX_MEM <= '0';
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH =>
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
end case;
end process output_logic;
end architecture behavioral;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_ila_0_0/synth/DemoInterconnect_ila_0_0.vhd
|
1
|
315547
|
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_ila_0_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DemoInterconnect_ila_0_0;
ARCHITECTURE DemoInterconnect_ila_0_0_arch OF DemoInterconnect_ila_0_0 IS
COMPONENT ila_v6_2_4_ila IS
GENERIC (
C_XLNX_HW_PROBE_INFO : STRING;
C_XDEVICEFAMILY : STRING;
C_CORE_TYPE : INTEGER;
C_CORE_INFO1 : INTEGER;
C_CORE_INFO2 : INTEGER;
C_CAPTURE_TYPE : INTEGER;
C_MU_TYPE : INTEGER;
C_TC_TYPE : INTEGER;
C_NUM_OF_PROBES : INTEGER;
C_DATA_DEPTH : INTEGER;
C_MAJOR_VERSION : INTEGER;
C_MINOR_VERSION : INTEGER;
C_BUILD_REVISION : INTEGER;
C_CORE_MAJOR_VER : INTEGER;
C_CORE_MINOR_VER : INTEGER;
C_XSDB_SLAVE_TYPE : INTEGER;
C_NEXT_SLAVE : INTEGER;
C_CSE_DRV_VER : INTEGER;
C_USE_TEST_REG : INTEGER;
C_PIPE_IFACE : INTEGER;
C_RAM_STYLE : STRING;
C_TRIGOUT_EN : INTEGER;
C_TRIGIN_EN : INTEGER;
C_ADV_TRIGGER : INTEGER;
C_EN_DDR_ILA : INTEGER;
C_EN_STRG_QUAL : INTEGER;
C_INPUT_PIPE_STAGES : INTEGER;
C_EN_TIME_TAG : INTEGER;
C_TIME_TAG_WIDTH : INTEGER;
C_ILA_CLK_FREQ : INTEGER;
C_PROBE0_WIDTH : INTEGER;
C_PROBE1_WIDTH : INTEGER;
C_PROBE2_WIDTH : INTEGER;
C_PROBE3_WIDTH : INTEGER;
C_PROBE4_WIDTH : INTEGER;
C_PROBE5_WIDTH : INTEGER;
C_PROBE6_WIDTH : INTEGER;
C_PROBE7_WIDTH : INTEGER;
C_PROBE8_WIDTH : INTEGER;
C_PROBE9_WIDTH : INTEGER;
C_PROBE10_WIDTH : INTEGER;
C_PROBE11_WIDTH : INTEGER;
C_PROBE12_WIDTH : INTEGER;
C_PROBE13_WIDTH : INTEGER;
C_PROBE14_WIDTH : INTEGER;
C_PROBE15_WIDTH : INTEGER;
C_PROBE16_WIDTH : INTEGER;
C_PROBE17_WIDTH : INTEGER;
C_PROBE18_WIDTH : INTEGER;
C_PROBE19_WIDTH : INTEGER;
C_PROBE20_WIDTH : INTEGER;
C_PROBE21_WIDTH : INTEGER;
C_PROBE22_WIDTH : INTEGER;
C_PROBE23_WIDTH : INTEGER;
C_PROBE24_WIDTH : INTEGER;
C_PROBE25_WIDTH : INTEGER;
C_PROBE26_WIDTH : INTEGER;
C_PROBE27_WIDTH : INTEGER;
C_PROBE28_WIDTH : INTEGER;
C_PROBE29_WIDTH : INTEGER;
C_PROBE30_WIDTH : INTEGER;
C_PROBE31_WIDTH : INTEGER;
C_PROBE32_WIDTH : INTEGER;
C_PROBE33_WIDTH : INTEGER;
C_PROBE34_WIDTH : INTEGER;
C_PROBE35_WIDTH : INTEGER;
C_PROBE36_WIDTH : INTEGER;
C_PROBE37_WIDTH : INTEGER;
C_PROBE38_WIDTH : INTEGER;
C_PROBE39_WIDTH : INTEGER;
C_PROBE40_WIDTH : INTEGER;
C_PROBE41_WIDTH : INTEGER;
C_PROBE42_WIDTH : INTEGER;
C_PROBE43_WIDTH : INTEGER;
C_PROBE44_WIDTH : INTEGER;
C_PROBE45_WIDTH : INTEGER;
C_PROBE46_WIDTH : INTEGER;
C_PROBE47_WIDTH : INTEGER;
C_PROBE48_WIDTH : INTEGER;
C_PROBE49_WIDTH : INTEGER;
C_PROBE50_WIDTH : INTEGER;
C_PROBE51_WIDTH : INTEGER;
C_PROBE52_WIDTH : INTEGER;
C_PROBE53_WIDTH : INTEGER;
C_PROBE54_WIDTH : INTEGER;
C_PROBE55_WIDTH : INTEGER;
C_PROBE56_WIDTH : INTEGER;
C_PROBE57_WIDTH : INTEGER;
C_PROBE58_WIDTH : INTEGER;
C_PROBE59_WIDTH : INTEGER;
C_PROBE60_WIDTH : INTEGER;
C_PROBE61_WIDTH : INTEGER;
C_PROBE62_WIDTH : INTEGER;
C_PROBE63_WIDTH : INTEGER;
C_PROBE64_WIDTH : INTEGER;
C_PROBE65_WIDTH : INTEGER;
C_PROBE66_WIDTH : INTEGER;
C_PROBE67_WIDTH : INTEGER;
C_PROBE68_WIDTH : INTEGER;
C_PROBE69_WIDTH : INTEGER;
C_PROBE70_WIDTH : INTEGER;
C_PROBE71_WIDTH : INTEGER;
C_PROBE72_WIDTH : INTEGER;
C_PROBE73_WIDTH : INTEGER;
C_PROBE74_WIDTH : INTEGER;
C_PROBE75_WIDTH : INTEGER;
C_PROBE76_WIDTH : INTEGER;
C_PROBE77_WIDTH : INTEGER;
C_PROBE78_WIDTH : INTEGER;
C_PROBE79_WIDTH : INTEGER;
C_PROBE80_WIDTH : INTEGER;
C_PROBE81_WIDTH : INTEGER;
C_PROBE82_WIDTH : INTEGER;
C_PROBE83_WIDTH : INTEGER;
C_PROBE84_WIDTH : INTEGER;
C_PROBE85_WIDTH : INTEGER;
C_PROBE86_WIDTH : INTEGER;
C_PROBE87_WIDTH : INTEGER;
C_PROBE88_WIDTH : INTEGER;
C_PROBE89_WIDTH : INTEGER;
C_PROBE90_WIDTH : INTEGER;
C_PROBE91_WIDTH : INTEGER;
C_PROBE92_WIDTH : INTEGER;
C_PROBE93_WIDTH : INTEGER;
C_PROBE94_WIDTH : INTEGER;
C_PROBE95_WIDTH : INTEGER;
C_PROBE96_WIDTH : INTEGER;
C_PROBE97_WIDTH : INTEGER;
C_PROBE98_WIDTH : INTEGER;
C_PROBE99_WIDTH : INTEGER;
C_PROBE100_WIDTH : INTEGER;
C_PROBE101_WIDTH : INTEGER;
C_PROBE102_WIDTH : INTEGER;
C_PROBE103_WIDTH : INTEGER;
C_PROBE104_WIDTH : INTEGER;
C_PROBE105_WIDTH : INTEGER;
C_PROBE106_WIDTH : INTEGER;
C_PROBE107_WIDTH : INTEGER;
C_PROBE108_WIDTH : INTEGER;
C_PROBE109_WIDTH : INTEGER;
C_PROBE110_WIDTH : INTEGER;
C_PROBE111_WIDTH : INTEGER;
C_PROBE112_WIDTH : INTEGER;
C_PROBE113_WIDTH : INTEGER;
C_PROBE114_WIDTH : INTEGER;
C_PROBE115_WIDTH : INTEGER;
C_PROBE116_WIDTH : INTEGER;
C_PROBE117_WIDTH : INTEGER;
C_PROBE118_WIDTH : INTEGER;
C_PROBE119_WIDTH : INTEGER;
C_PROBE120_WIDTH : INTEGER;
C_PROBE121_WIDTH : INTEGER;
C_PROBE122_WIDTH : INTEGER;
C_PROBE123_WIDTH : INTEGER;
C_PROBE124_WIDTH : INTEGER;
C_PROBE125_WIDTH : INTEGER;
C_PROBE126_WIDTH : INTEGER;
C_PROBE127_WIDTH : INTEGER;
C_PROBE128_WIDTH : INTEGER;
C_PROBE129_WIDTH : INTEGER;
C_PROBE130_WIDTH : INTEGER;
C_PROBE131_WIDTH : INTEGER;
C_PROBE132_WIDTH : INTEGER;
C_PROBE133_WIDTH : INTEGER;
C_PROBE134_WIDTH : INTEGER;
C_PROBE135_WIDTH : INTEGER;
C_PROBE136_WIDTH : INTEGER;
C_PROBE137_WIDTH : INTEGER;
C_PROBE138_WIDTH : INTEGER;
C_PROBE139_WIDTH : INTEGER;
C_PROBE140_WIDTH : INTEGER;
C_PROBE141_WIDTH : INTEGER;
C_PROBE142_WIDTH : INTEGER;
C_PROBE143_WIDTH : INTEGER;
C_PROBE144_WIDTH : INTEGER;
C_PROBE145_WIDTH : INTEGER;
C_PROBE146_WIDTH : INTEGER;
C_PROBE147_WIDTH : INTEGER;
C_PROBE148_WIDTH : INTEGER;
C_PROBE149_WIDTH : INTEGER;
C_PROBE150_WIDTH : INTEGER;
C_PROBE151_WIDTH : INTEGER;
C_PROBE152_WIDTH : INTEGER;
C_PROBE153_WIDTH : INTEGER;
C_PROBE154_WIDTH : INTEGER;
C_PROBE155_WIDTH : INTEGER;
C_PROBE156_WIDTH : INTEGER;
C_PROBE157_WIDTH : INTEGER;
C_PROBE158_WIDTH : INTEGER;
C_PROBE159_WIDTH : INTEGER;
C_PROBE160_WIDTH : INTEGER;
C_PROBE161_WIDTH : INTEGER;
C_PROBE162_WIDTH : INTEGER;
C_PROBE163_WIDTH : INTEGER;
C_PROBE164_WIDTH : INTEGER;
C_PROBE165_WIDTH : INTEGER;
C_PROBE166_WIDTH : INTEGER;
C_PROBE167_WIDTH : INTEGER;
C_PROBE168_WIDTH : INTEGER;
C_PROBE169_WIDTH : INTEGER;
C_PROBE170_WIDTH : INTEGER;
C_PROBE171_WIDTH : INTEGER;
C_PROBE172_WIDTH : INTEGER;
C_PROBE173_WIDTH : INTEGER;
C_PROBE174_WIDTH : INTEGER;
C_PROBE175_WIDTH : INTEGER;
C_PROBE176_WIDTH : INTEGER;
C_PROBE177_WIDTH : INTEGER;
C_PROBE178_WIDTH : INTEGER;
C_PROBE179_WIDTH : INTEGER;
C_PROBE180_WIDTH : INTEGER;
C_PROBE181_WIDTH : INTEGER;
C_PROBE182_WIDTH : INTEGER;
C_PROBE183_WIDTH : INTEGER;
C_PROBE184_WIDTH : INTEGER;
C_PROBE185_WIDTH : INTEGER;
C_PROBE186_WIDTH : INTEGER;
C_PROBE187_WIDTH : INTEGER;
C_PROBE188_WIDTH : INTEGER;
C_PROBE189_WIDTH : INTEGER;
C_PROBE190_WIDTH : INTEGER;
C_PROBE191_WIDTH : INTEGER;
C_PROBE192_WIDTH : INTEGER;
C_PROBE193_WIDTH : INTEGER;
C_PROBE194_WIDTH : INTEGER;
C_PROBE195_WIDTH : INTEGER;
C_PROBE196_WIDTH : INTEGER;
C_PROBE197_WIDTH : INTEGER;
C_PROBE198_WIDTH : INTEGER;
C_PROBE199_WIDTH : INTEGER;
C_PROBE200_WIDTH : INTEGER;
C_PROBE201_WIDTH : INTEGER;
C_PROBE202_WIDTH : INTEGER;
C_PROBE203_WIDTH : INTEGER;
C_PROBE204_WIDTH : INTEGER;
C_PROBE205_WIDTH : INTEGER;
C_PROBE206_WIDTH : INTEGER;
C_PROBE207_WIDTH : INTEGER;
C_PROBE208_WIDTH : INTEGER;
C_PROBE209_WIDTH : INTEGER;
C_PROBE210_WIDTH : INTEGER;
C_PROBE211_WIDTH : INTEGER;
C_PROBE212_WIDTH : INTEGER;
C_PROBE213_WIDTH : INTEGER;
C_PROBE214_WIDTH : INTEGER;
C_PROBE215_WIDTH : INTEGER;
C_PROBE216_WIDTH : INTEGER;
C_PROBE217_WIDTH : INTEGER;
C_PROBE218_WIDTH : INTEGER;
C_PROBE219_WIDTH : INTEGER;
C_PROBE220_WIDTH : INTEGER;
C_PROBE221_WIDTH : INTEGER;
C_PROBE222_WIDTH : INTEGER;
C_PROBE223_WIDTH : INTEGER;
C_PROBE224_WIDTH : INTEGER;
C_PROBE225_WIDTH : INTEGER;
C_PROBE226_WIDTH : INTEGER;
C_PROBE227_WIDTH : INTEGER;
C_PROBE228_WIDTH : INTEGER;
C_PROBE229_WIDTH : INTEGER;
C_PROBE230_WIDTH : INTEGER;
C_PROBE231_WIDTH : INTEGER;
C_PROBE232_WIDTH : INTEGER;
C_PROBE233_WIDTH : INTEGER;
C_PROBE234_WIDTH : INTEGER;
C_PROBE235_WIDTH : INTEGER;
C_PROBE236_WIDTH : INTEGER;
C_PROBE237_WIDTH : INTEGER;
C_PROBE238_WIDTH : INTEGER;
C_PROBE239_WIDTH : INTEGER;
C_PROBE240_WIDTH : INTEGER;
C_PROBE241_WIDTH : INTEGER;
C_PROBE242_WIDTH : INTEGER;
C_PROBE243_WIDTH : INTEGER;
C_PROBE244_WIDTH : INTEGER;
C_PROBE245_WIDTH : INTEGER;
C_PROBE246_WIDTH : INTEGER;
C_PROBE247_WIDTH : INTEGER;
C_PROBE248_WIDTH : INTEGER;
C_PROBE249_WIDTH : INTEGER;
C_PROBE250_WIDTH : INTEGER;
C_PROBE251_WIDTH : INTEGER;
C_PROBE252_WIDTH : INTEGER;
C_PROBE253_WIDTH : INTEGER;
C_PROBE254_WIDTH : INTEGER;
C_PROBE255_WIDTH : INTEGER;
C_PROBE256_WIDTH : INTEGER;
C_PROBE257_WIDTH : INTEGER;
C_PROBE258_WIDTH : INTEGER;
C_PROBE259_WIDTH : INTEGER;
C_PROBE260_WIDTH : INTEGER;
C_PROBE261_WIDTH : INTEGER;
C_PROBE262_WIDTH : INTEGER;
C_PROBE263_WIDTH : INTEGER;
C_PROBE264_WIDTH : INTEGER;
C_PROBE265_WIDTH : INTEGER;
C_PROBE266_WIDTH : INTEGER;
C_PROBE267_WIDTH : INTEGER;
C_PROBE268_WIDTH : INTEGER;
C_PROBE269_WIDTH : INTEGER;
C_PROBE270_WIDTH : INTEGER;
C_PROBE271_WIDTH : INTEGER;
C_PROBE272_WIDTH : INTEGER;
C_PROBE273_WIDTH : INTEGER;
C_PROBE274_WIDTH : INTEGER;
C_PROBE275_WIDTH : INTEGER;
C_PROBE276_WIDTH : INTEGER;
C_PROBE277_WIDTH : INTEGER;
C_PROBE278_WIDTH : INTEGER;
C_PROBE279_WIDTH : INTEGER;
C_PROBE280_WIDTH : INTEGER;
C_PROBE281_WIDTH : INTEGER;
C_PROBE282_WIDTH : INTEGER;
C_PROBE283_WIDTH : INTEGER;
C_PROBE284_WIDTH : INTEGER;
C_PROBE285_WIDTH : INTEGER;
C_PROBE286_WIDTH : INTEGER;
C_PROBE287_WIDTH : INTEGER;
C_PROBE288_WIDTH : INTEGER;
C_PROBE289_WIDTH : INTEGER;
C_PROBE290_WIDTH : INTEGER;
C_PROBE291_WIDTH : INTEGER;
C_PROBE292_WIDTH : INTEGER;
C_PROBE293_WIDTH : INTEGER;
C_PROBE294_WIDTH : INTEGER;
C_PROBE295_WIDTH : INTEGER;
C_PROBE296_WIDTH : INTEGER;
C_PROBE297_WIDTH : INTEGER;
C_PROBE298_WIDTH : INTEGER;
C_PROBE299_WIDTH : INTEGER;
C_PROBE300_WIDTH : INTEGER;
C_PROBE301_WIDTH : INTEGER;
C_PROBE302_WIDTH : INTEGER;
C_PROBE303_WIDTH : INTEGER;
C_PROBE304_WIDTH : INTEGER;
C_PROBE305_WIDTH : INTEGER;
C_PROBE306_WIDTH : INTEGER;
C_PROBE307_WIDTH : INTEGER;
C_PROBE308_WIDTH : INTEGER;
C_PROBE309_WIDTH : INTEGER;
C_PROBE310_WIDTH : INTEGER;
C_PROBE311_WIDTH : INTEGER;
C_PROBE312_WIDTH : INTEGER;
C_PROBE313_WIDTH : INTEGER;
C_PROBE314_WIDTH : INTEGER;
C_PROBE315_WIDTH : INTEGER;
C_PROBE316_WIDTH : INTEGER;
C_PROBE317_WIDTH : INTEGER;
C_PROBE318_WIDTH : INTEGER;
C_PROBE319_WIDTH : INTEGER;
C_PROBE320_WIDTH : INTEGER;
C_PROBE321_WIDTH : INTEGER;
C_PROBE322_WIDTH : INTEGER;
C_PROBE323_WIDTH : INTEGER;
C_PROBE324_WIDTH : INTEGER;
C_PROBE325_WIDTH : INTEGER;
C_PROBE326_WIDTH : INTEGER;
C_PROBE327_WIDTH : INTEGER;
C_PROBE328_WIDTH : INTEGER;
C_PROBE329_WIDTH : INTEGER;
C_PROBE330_WIDTH : INTEGER;
C_PROBE331_WIDTH : INTEGER;
C_PROBE332_WIDTH : INTEGER;
C_PROBE333_WIDTH : INTEGER;
C_PROBE334_WIDTH : INTEGER;
C_PROBE335_WIDTH : INTEGER;
C_PROBE336_WIDTH : INTEGER;
C_PROBE337_WIDTH : INTEGER;
C_PROBE338_WIDTH : INTEGER;
C_PROBE339_WIDTH : INTEGER;
C_PROBE340_WIDTH : INTEGER;
C_PROBE341_WIDTH : INTEGER;
C_PROBE342_WIDTH : INTEGER;
C_PROBE343_WIDTH : INTEGER;
C_PROBE344_WIDTH : INTEGER;
C_PROBE345_WIDTH : INTEGER;
C_PROBE346_WIDTH : INTEGER;
C_PROBE347_WIDTH : INTEGER;
C_PROBE348_WIDTH : INTEGER;
C_PROBE349_WIDTH : INTEGER;
C_PROBE350_WIDTH : INTEGER;
C_PROBE351_WIDTH : INTEGER;
C_PROBE352_WIDTH : INTEGER;
C_PROBE353_WIDTH : INTEGER;
C_PROBE354_WIDTH : INTEGER;
C_PROBE355_WIDTH : INTEGER;
C_PROBE356_WIDTH : INTEGER;
C_PROBE357_WIDTH : INTEGER;
C_PROBE358_WIDTH : INTEGER;
C_PROBE359_WIDTH : INTEGER;
C_PROBE360_WIDTH : INTEGER;
C_PROBE361_WIDTH : INTEGER;
C_PROBE362_WIDTH : INTEGER;
C_PROBE363_WIDTH : INTEGER;
C_PROBE364_WIDTH : INTEGER;
C_PROBE365_WIDTH : INTEGER;
C_PROBE366_WIDTH : INTEGER;
C_PROBE367_WIDTH : INTEGER;
C_PROBE368_WIDTH : INTEGER;
C_PROBE369_WIDTH : INTEGER;
C_PROBE370_WIDTH : INTEGER;
C_PROBE371_WIDTH : INTEGER;
C_PROBE372_WIDTH : INTEGER;
C_PROBE373_WIDTH : INTEGER;
C_PROBE374_WIDTH : INTEGER;
C_PROBE375_WIDTH : INTEGER;
C_PROBE376_WIDTH : INTEGER;
C_PROBE377_WIDTH : INTEGER;
C_PROBE378_WIDTH : INTEGER;
C_PROBE379_WIDTH : INTEGER;
C_PROBE380_WIDTH : INTEGER;
C_PROBE381_WIDTH : INTEGER;
C_PROBE382_WIDTH : INTEGER;
C_PROBE383_WIDTH : INTEGER;
C_PROBE384_WIDTH : INTEGER;
C_PROBE385_WIDTH : INTEGER;
C_PROBE386_WIDTH : INTEGER;
C_PROBE387_WIDTH : INTEGER;
C_PROBE388_WIDTH : INTEGER;
C_PROBE389_WIDTH : INTEGER;
C_PROBE390_WIDTH : INTEGER;
C_PROBE391_WIDTH : INTEGER;
C_PROBE392_WIDTH : INTEGER;
C_PROBE393_WIDTH : INTEGER;
C_PROBE394_WIDTH : INTEGER;
C_PROBE395_WIDTH : INTEGER;
C_PROBE396_WIDTH : INTEGER;
C_PROBE397_WIDTH : INTEGER;
C_PROBE398_WIDTH : INTEGER;
C_PROBE399_WIDTH : INTEGER;
C_PROBE400_WIDTH : INTEGER;
C_PROBE401_WIDTH : INTEGER;
C_PROBE402_WIDTH : INTEGER;
C_PROBE403_WIDTH : INTEGER;
C_PROBE404_WIDTH : INTEGER;
C_PROBE405_WIDTH : INTEGER;
C_PROBE406_WIDTH : INTEGER;
C_PROBE407_WIDTH : INTEGER;
C_PROBE408_WIDTH : INTEGER;
C_PROBE409_WIDTH : INTEGER;
C_PROBE410_WIDTH : INTEGER;
C_PROBE411_WIDTH : INTEGER;
C_PROBE412_WIDTH : INTEGER;
C_PROBE413_WIDTH : INTEGER;
C_PROBE414_WIDTH : INTEGER;
C_PROBE415_WIDTH : INTEGER;
C_PROBE416_WIDTH : INTEGER;
C_PROBE417_WIDTH : INTEGER;
C_PROBE418_WIDTH : INTEGER;
C_PROBE419_WIDTH : INTEGER;
C_PROBE420_WIDTH : INTEGER;
C_PROBE421_WIDTH : INTEGER;
C_PROBE422_WIDTH : INTEGER;
C_PROBE423_WIDTH : INTEGER;
C_PROBE424_WIDTH : INTEGER;
C_PROBE425_WIDTH : INTEGER;
C_PROBE426_WIDTH : INTEGER;
C_PROBE427_WIDTH : INTEGER;
C_PROBE428_WIDTH : INTEGER;
C_PROBE429_WIDTH : INTEGER;
C_PROBE430_WIDTH : INTEGER;
C_PROBE431_WIDTH : INTEGER;
C_PROBE432_WIDTH : INTEGER;
C_PROBE433_WIDTH : INTEGER;
C_PROBE434_WIDTH : INTEGER;
C_PROBE435_WIDTH : INTEGER;
C_PROBE436_WIDTH : INTEGER;
C_PROBE437_WIDTH : INTEGER;
C_PROBE438_WIDTH : INTEGER;
C_PROBE439_WIDTH : INTEGER;
C_PROBE440_WIDTH : INTEGER;
C_PROBE441_WIDTH : INTEGER;
C_PROBE442_WIDTH : INTEGER;
C_PROBE443_WIDTH : INTEGER;
C_PROBE444_WIDTH : INTEGER;
C_PROBE445_WIDTH : INTEGER;
C_PROBE446_WIDTH : INTEGER;
C_PROBE447_WIDTH : INTEGER;
C_PROBE448_WIDTH : INTEGER;
C_PROBE449_WIDTH : INTEGER;
C_PROBE450_WIDTH : INTEGER;
C_PROBE451_WIDTH : INTEGER;
C_PROBE452_WIDTH : INTEGER;
C_PROBE453_WIDTH : INTEGER;
C_PROBE454_WIDTH : INTEGER;
C_PROBE455_WIDTH : INTEGER;
C_PROBE456_WIDTH : INTEGER;
C_PROBE457_WIDTH : INTEGER;
C_PROBE458_WIDTH : INTEGER;
C_PROBE459_WIDTH : INTEGER;
C_PROBE460_WIDTH : INTEGER;
C_PROBE461_WIDTH : INTEGER;
C_PROBE462_WIDTH : INTEGER;
C_PROBE463_WIDTH : INTEGER;
C_PROBE464_WIDTH : INTEGER;
C_PROBE465_WIDTH : INTEGER;
C_PROBE466_WIDTH : INTEGER;
C_PROBE467_WIDTH : INTEGER;
C_PROBE468_WIDTH : INTEGER;
C_PROBE469_WIDTH : INTEGER;
C_PROBE470_WIDTH : INTEGER;
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C_PROBE99_MU_CNT : INTEGER;
C_PROBE100_MU_CNT : INTEGER;
C_PROBE101_MU_CNT : INTEGER;
C_PROBE102_MU_CNT : INTEGER;
C_PROBE103_MU_CNT : INTEGER;
C_PROBE104_MU_CNT : INTEGER;
C_PROBE105_MU_CNT : INTEGER;
C_PROBE106_MU_CNT : INTEGER;
C_PROBE107_MU_CNT : INTEGER;
C_PROBE108_MU_CNT : INTEGER;
C_PROBE109_MU_CNT : INTEGER;
C_PROBE110_MU_CNT : INTEGER;
C_PROBE111_MU_CNT : INTEGER;
C_PROBE112_MU_CNT : INTEGER;
C_PROBE113_MU_CNT : INTEGER;
C_PROBE114_MU_CNT : INTEGER;
C_PROBE115_MU_CNT : INTEGER;
C_PROBE116_MU_CNT : INTEGER;
C_PROBE117_MU_CNT : INTEGER;
C_PROBE118_MU_CNT : INTEGER;
C_PROBE119_MU_CNT : INTEGER;
C_PROBE120_MU_CNT : INTEGER;
C_PROBE121_MU_CNT : INTEGER;
C_PROBE122_MU_CNT : INTEGER;
C_PROBE123_MU_CNT : INTEGER;
C_PROBE124_MU_CNT : INTEGER;
C_PROBE125_MU_CNT : INTEGER;
C_PROBE126_MU_CNT : INTEGER;
C_PROBE127_MU_CNT : INTEGER;
C_PROBE128_MU_CNT : INTEGER;
C_PROBE129_MU_CNT : INTEGER;
C_PROBE130_MU_CNT : INTEGER;
C_PROBE131_MU_CNT : INTEGER;
C_PROBE132_MU_CNT : INTEGER;
C_PROBE133_MU_CNT : INTEGER;
C_PROBE134_MU_CNT : INTEGER;
C_PROBE135_MU_CNT : INTEGER;
C_PROBE136_MU_CNT : INTEGER;
C_PROBE137_MU_CNT : INTEGER;
C_PROBE138_MU_CNT : INTEGER;
C_PROBE139_MU_CNT : INTEGER;
C_PROBE140_MU_CNT : INTEGER;
C_PROBE141_MU_CNT : INTEGER;
C_PROBE142_MU_CNT : INTEGER;
C_PROBE143_MU_CNT : INTEGER;
C_PROBE144_MU_CNT : INTEGER;
C_PROBE145_MU_CNT : INTEGER;
C_PROBE146_MU_CNT : INTEGER;
C_PROBE147_MU_CNT : INTEGER;
C_PROBE148_MU_CNT : INTEGER;
C_PROBE149_MU_CNT : INTEGER;
C_PROBE150_MU_CNT : INTEGER;
C_PROBE151_MU_CNT : INTEGER;
C_PROBE152_MU_CNT : INTEGER;
C_PROBE153_MU_CNT : INTEGER;
C_PROBE154_MU_CNT : INTEGER;
C_PROBE155_MU_CNT : INTEGER;
C_PROBE156_MU_CNT : INTEGER;
C_PROBE157_MU_CNT : INTEGER;
C_PROBE158_MU_CNT : INTEGER;
C_PROBE159_MU_CNT : INTEGER;
C_PROBE160_MU_CNT : INTEGER;
C_PROBE161_MU_CNT : INTEGER;
C_PROBE162_MU_CNT : INTEGER;
C_PROBE163_MU_CNT : INTEGER;
C_PROBE164_MU_CNT : INTEGER;
C_PROBE165_MU_CNT : INTEGER;
C_PROBE166_MU_CNT : INTEGER;
C_PROBE167_MU_CNT : INTEGER;
C_PROBE168_MU_CNT : INTEGER;
C_PROBE169_MU_CNT : INTEGER;
C_PROBE170_MU_CNT : INTEGER;
C_PROBE171_MU_CNT : INTEGER;
C_PROBE172_MU_CNT : INTEGER;
C_PROBE173_MU_CNT : INTEGER;
C_PROBE174_MU_CNT : INTEGER;
C_PROBE175_MU_CNT : INTEGER;
C_PROBE176_MU_CNT : INTEGER;
C_PROBE177_MU_CNT : INTEGER;
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C_PROBE179_MU_CNT : INTEGER;
C_PROBE180_MU_CNT : INTEGER;
C_PROBE181_MU_CNT : INTEGER;
C_PROBE182_MU_CNT : INTEGER;
C_PROBE183_MU_CNT : INTEGER;
C_PROBE184_MU_CNT : INTEGER;
C_PROBE185_MU_CNT : INTEGER;
C_PROBE186_MU_CNT : INTEGER;
C_PROBE187_MU_CNT : INTEGER;
C_PROBE188_MU_CNT : INTEGER;
C_PROBE189_MU_CNT : INTEGER;
C_PROBE190_MU_CNT : INTEGER;
C_PROBE191_MU_CNT : INTEGER;
C_PROBE192_MU_CNT : INTEGER;
C_PROBE193_MU_CNT : INTEGER;
C_PROBE194_MU_CNT : INTEGER;
C_PROBE195_MU_CNT : INTEGER;
C_PROBE196_MU_CNT : INTEGER;
C_PROBE197_MU_CNT : INTEGER;
C_PROBE198_MU_CNT : INTEGER;
C_PROBE199_MU_CNT : INTEGER;
C_PROBE200_MU_CNT : INTEGER;
C_PROBE201_MU_CNT : INTEGER;
C_PROBE202_MU_CNT : INTEGER;
C_PROBE203_MU_CNT : INTEGER;
C_PROBE204_MU_CNT : INTEGER;
C_PROBE205_MU_CNT : INTEGER;
C_PROBE206_MU_CNT : INTEGER;
C_PROBE207_MU_CNT : INTEGER;
C_PROBE208_MU_CNT : INTEGER;
C_PROBE209_MU_CNT : INTEGER;
C_PROBE210_MU_CNT : INTEGER;
C_PROBE211_MU_CNT : INTEGER;
C_PROBE212_MU_CNT : INTEGER;
C_PROBE213_MU_CNT : INTEGER;
C_PROBE214_MU_CNT : INTEGER;
C_PROBE215_MU_CNT : INTEGER;
C_PROBE216_MU_CNT : INTEGER;
C_PROBE217_MU_CNT : INTEGER;
C_PROBE218_MU_CNT : INTEGER;
C_PROBE219_MU_CNT : INTEGER;
C_PROBE220_MU_CNT : INTEGER;
C_PROBE221_MU_CNT : INTEGER;
C_PROBE222_MU_CNT : INTEGER;
C_PROBE223_MU_CNT : INTEGER;
C_PROBE224_MU_CNT : INTEGER;
C_PROBE225_MU_CNT : INTEGER;
C_PROBE226_MU_CNT : INTEGER;
C_PROBE227_MU_CNT : INTEGER;
C_PROBE228_MU_CNT : INTEGER;
C_PROBE229_MU_CNT : INTEGER;
C_PROBE230_MU_CNT : INTEGER;
C_PROBE231_MU_CNT : INTEGER;
C_PROBE232_MU_CNT : INTEGER;
C_PROBE233_MU_CNT : INTEGER;
C_PROBE234_MU_CNT : INTEGER;
C_PROBE235_MU_CNT : INTEGER;
C_PROBE236_MU_CNT : INTEGER;
C_PROBE237_MU_CNT : INTEGER;
C_PROBE238_MU_CNT : INTEGER;
C_PROBE239_MU_CNT : INTEGER;
C_PROBE240_MU_CNT : INTEGER;
C_PROBE241_MU_CNT : INTEGER;
C_PROBE242_MU_CNT : INTEGER;
C_PROBE243_MU_CNT : INTEGER;
C_PROBE244_MU_CNT : INTEGER;
C_PROBE245_MU_CNT : INTEGER;
C_PROBE246_MU_CNT : INTEGER;
C_PROBE247_MU_CNT : INTEGER;
C_PROBE248_MU_CNT : INTEGER;
C_PROBE249_MU_CNT : INTEGER;
C_PROBE250_MU_CNT : INTEGER;
C_PROBE251_MU_CNT : INTEGER;
C_PROBE252_MU_CNT : INTEGER;
C_PROBE253_MU_CNT : INTEGER;
C_PROBE254_MU_CNT : INTEGER;
C_PROBE255_MU_CNT : INTEGER;
C_PROBE256_MU_CNT : INTEGER;
C_PROBE257_MU_CNT : INTEGER;
C_PROBE258_MU_CNT : INTEGER;
C_PROBE259_MU_CNT : INTEGER;
C_PROBE260_MU_CNT : INTEGER;
C_PROBE261_MU_CNT : INTEGER;
C_PROBE262_MU_CNT : INTEGER;
C_PROBE263_MU_CNT : INTEGER;
C_PROBE264_MU_CNT : INTEGER;
C_PROBE265_MU_CNT : INTEGER;
C_PROBE266_MU_CNT : INTEGER;
C_PROBE267_MU_CNT : INTEGER;
C_PROBE268_MU_CNT : INTEGER;
C_PROBE269_MU_CNT : INTEGER;
C_PROBE270_MU_CNT : INTEGER;
C_PROBE271_MU_CNT : INTEGER;
C_PROBE272_MU_CNT : INTEGER;
C_PROBE273_MU_CNT : INTEGER;
C_PROBE274_MU_CNT : INTEGER;
C_PROBE275_MU_CNT : INTEGER;
C_PROBE276_MU_CNT : INTEGER;
C_PROBE277_MU_CNT : INTEGER;
C_PROBE278_MU_CNT : INTEGER;
C_PROBE279_MU_CNT : INTEGER;
C_PROBE280_MU_CNT : INTEGER;
C_PROBE281_MU_CNT : INTEGER;
C_PROBE282_MU_CNT : INTEGER;
C_PROBE283_MU_CNT : INTEGER;
C_PROBE284_MU_CNT : INTEGER;
C_PROBE285_MU_CNT : INTEGER;
C_PROBE286_MU_CNT : INTEGER;
C_PROBE287_MU_CNT : INTEGER;
C_PROBE288_MU_CNT : INTEGER;
C_PROBE289_MU_CNT : INTEGER;
C_PROBE290_MU_CNT : INTEGER;
C_PROBE291_MU_CNT : INTEGER;
C_PROBE292_MU_CNT : INTEGER;
C_PROBE293_MU_CNT : INTEGER;
C_PROBE294_MU_CNT : INTEGER;
C_PROBE295_MU_CNT : INTEGER;
C_PROBE296_MU_CNT : INTEGER;
C_PROBE297_MU_CNT : INTEGER;
C_PROBE298_MU_CNT : INTEGER;
C_PROBE299_MU_CNT : INTEGER;
C_PROBE300_MU_CNT : INTEGER;
C_PROBE301_MU_CNT : INTEGER;
C_PROBE302_MU_CNT : INTEGER;
C_PROBE303_MU_CNT : INTEGER;
C_PROBE304_MU_CNT : INTEGER;
C_PROBE305_MU_CNT : INTEGER;
C_PROBE306_MU_CNT : INTEGER;
C_PROBE307_MU_CNT : INTEGER;
C_PROBE308_MU_CNT : INTEGER;
C_PROBE309_MU_CNT : INTEGER;
C_PROBE310_MU_CNT : INTEGER;
C_PROBE311_MU_CNT : INTEGER;
C_PROBE312_MU_CNT : INTEGER;
C_PROBE313_MU_CNT : INTEGER;
C_PROBE314_MU_CNT : INTEGER;
C_PROBE315_MU_CNT : INTEGER;
C_PROBE316_MU_CNT : INTEGER;
C_PROBE317_MU_CNT : INTEGER;
C_PROBE318_MU_CNT : INTEGER;
C_PROBE319_MU_CNT : INTEGER;
C_PROBE320_MU_CNT : INTEGER;
C_PROBE321_MU_CNT : INTEGER;
C_PROBE322_MU_CNT : INTEGER;
C_PROBE323_MU_CNT : INTEGER;
C_PROBE324_MU_CNT : INTEGER;
C_PROBE325_MU_CNT : INTEGER;
C_PROBE326_MU_CNT : INTEGER;
C_PROBE327_MU_CNT : INTEGER;
C_PROBE328_MU_CNT : INTEGER;
C_PROBE329_MU_CNT : INTEGER;
C_PROBE330_MU_CNT : INTEGER;
C_PROBE331_MU_CNT : INTEGER;
C_PROBE332_MU_CNT : INTEGER;
C_PROBE333_MU_CNT : INTEGER;
C_PROBE334_MU_CNT : INTEGER;
C_PROBE335_MU_CNT : INTEGER;
C_PROBE336_MU_CNT : INTEGER;
C_PROBE337_MU_CNT : INTEGER;
C_PROBE338_MU_CNT : INTEGER;
C_PROBE339_MU_CNT : INTEGER;
C_PROBE340_MU_CNT : INTEGER;
C_PROBE341_MU_CNT : INTEGER;
C_PROBE342_MU_CNT : INTEGER;
C_PROBE343_MU_CNT : INTEGER;
C_PROBE344_MU_CNT : INTEGER;
C_PROBE345_MU_CNT : INTEGER;
C_PROBE346_MU_CNT : INTEGER;
C_PROBE347_MU_CNT : INTEGER;
C_PROBE348_MU_CNT : INTEGER;
C_PROBE349_MU_CNT : INTEGER;
C_PROBE350_MU_CNT : INTEGER;
C_PROBE351_MU_CNT : INTEGER;
C_PROBE352_MU_CNT : INTEGER;
C_PROBE353_MU_CNT : INTEGER;
C_PROBE354_MU_CNT : INTEGER;
C_PROBE355_MU_CNT : INTEGER;
C_PROBE356_MU_CNT : INTEGER;
C_PROBE357_MU_CNT : INTEGER;
C_PROBE358_MU_CNT : INTEGER;
C_PROBE359_MU_CNT : INTEGER;
C_PROBE360_MU_CNT : INTEGER;
C_PROBE361_MU_CNT : INTEGER;
C_PROBE362_MU_CNT : INTEGER;
C_PROBE363_MU_CNT : INTEGER;
C_PROBE364_MU_CNT : INTEGER;
C_PROBE365_MU_CNT : INTEGER;
C_PROBE366_MU_CNT : INTEGER;
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C_PROBE368_MU_CNT : INTEGER;
C_PROBE369_MU_CNT : INTEGER;
C_PROBE370_MU_CNT : INTEGER;
C_PROBE371_MU_CNT : INTEGER;
C_PROBE372_MU_CNT : INTEGER;
C_PROBE373_MU_CNT : INTEGER;
C_PROBE374_MU_CNT : INTEGER;
C_PROBE375_MU_CNT : INTEGER;
C_PROBE376_MU_CNT : INTEGER;
C_PROBE377_MU_CNT : INTEGER;
C_PROBE378_MU_CNT : INTEGER;
C_PROBE379_MU_CNT : INTEGER;
C_PROBE380_MU_CNT : INTEGER;
C_PROBE381_MU_CNT : INTEGER;
C_PROBE382_MU_CNT : INTEGER;
C_PROBE383_MU_CNT : INTEGER;
C_PROBE384_MU_CNT : INTEGER;
C_PROBE385_MU_CNT : INTEGER;
C_PROBE386_MU_CNT : INTEGER;
C_PROBE387_MU_CNT : INTEGER;
C_PROBE388_MU_CNT : INTEGER;
C_PROBE389_MU_CNT : INTEGER;
C_PROBE390_MU_CNT : INTEGER;
C_PROBE391_MU_CNT : INTEGER;
C_PROBE392_MU_CNT : INTEGER;
C_PROBE393_MU_CNT : INTEGER;
C_PROBE394_MU_CNT : INTEGER;
C_PROBE395_MU_CNT : INTEGER;
C_PROBE396_MU_CNT : INTEGER;
C_PROBE397_MU_CNT : INTEGER;
C_PROBE398_MU_CNT : INTEGER;
C_PROBE399_MU_CNT : INTEGER;
C_PROBE400_MU_CNT : INTEGER;
C_PROBE401_MU_CNT : INTEGER;
C_PROBE402_MU_CNT : INTEGER;
C_PROBE403_MU_CNT : INTEGER;
C_PROBE404_MU_CNT : INTEGER;
C_PROBE405_MU_CNT : INTEGER;
C_PROBE406_MU_CNT : INTEGER;
C_PROBE407_MU_CNT : INTEGER;
C_PROBE408_MU_CNT : INTEGER;
C_PROBE409_MU_CNT : INTEGER;
C_PROBE410_MU_CNT : INTEGER;
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C_PROBE412_MU_CNT : INTEGER;
C_PROBE413_MU_CNT : INTEGER;
C_PROBE414_MU_CNT : INTEGER;
C_PROBE415_MU_CNT : INTEGER;
C_PROBE416_MU_CNT : INTEGER;
C_PROBE417_MU_CNT : INTEGER;
C_PROBE418_MU_CNT : INTEGER;
C_PROBE419_MU_CNT : INTEGER;
C_PROBE420_MU_CNT : INTEGER;
C_PROBE421_MU_CNT : INTEGER;
C_PROBE422_MU_CNT : INTEGER;
C_PROBE423_MU_CNT : INTEGER;
C_PROBE424_MU_CNT : INTEGER;
C_PROBE425_MU_CNT : INTEGER;
C_PROBE426_MU_CNT : INTEGER;
C_PROBE427_MU_CNT : INTEGER;
C_PROBE428_MU_CNT : INTEGER;
C_PROBE429_MU_CNT : INTEGER;
C_PROBE430_MU_CNT : INTEGER;
C_PROBE431_MU_CNT : INTEGER;
C_PROBE432_MU_CNT : INTEGER;
C_PROBE433_MU_CNT : INTEGER;
C_PROBE434_MU_CNT : INTEGER;
C_PROBE435_MU_CNT : INTEGER;
C_PROBE436_MU_CNT : INTEGER;
C_PROBE437_MU_CNT : INTEGER;
C_PROBE438_MU_CNT : INTEGER;
C_PROBE439_MU_CNT : INTEGER;
C_PROBE440_MU_CNT : INTEGER;
C_PROBE441_MU_CNT : INTEGER;
C_PROBE442_MU_CNT : INTEGER;
C_PROBE443_MU_CNT : INTEGER;
C_PROBE444_MU_CNT : INTEGER;
C_PROBE445_MU_CNT : INTEGER;
C_PROBE446_MU_CNT : INTEGER;
C_PROBE447_MU_CNT : INTEGER;
C_PROBE448_MU_CNT : INTEGER;
C_PROBE449_MU_CNT : INTEGER;
C_PROBE450_MU_CNT : INTEGER;
C_PROBE451_MU_CNT : INTEGER;
C_PROBE452_MU_CNT : INTEGER;
C_PROBE453_MU_CNT : INTEGER;
C_PROBE454_MU_CNT : INTEGER;
C_PROBE455_MU_CNT : INTEGER;
C_PROBE456_MU_CNT : INTEGER;
C_PROBE457_MU_CNT : INTEGER;
C_PROBE458_MU_CNT : INTEGER;
C_PROBE459_MU_CNT : INTEGER;
C_PROBE460_MU_CNT : INTEGER;
C_PROBE461_MU_CNT : INTEGER;
C_PROBE462_MU_CNT : INTEGER;
C_PROBE463_MU_CNT : INTEGER;
C_PROBE464_MU_CNT : INTEGER;
C_PROBE465_MU_CNT : INTEGER;
C_PROBE466_MU_CNT : INTEGER;
C_PROBE467_MU_CNT : INTEGER;
C_PROBE468_MU_CNT : INTEGER;
C_PROBE469_MU_CNT : INTEGER;
C_PROBE470_MU_CNT : INTEGER;
C_PROBE471_MU_CNT : INTEGER;
C_PROBE472_MU_CNT : INTEGER;
C_PROBE473_MU_CNT : INTEGER;
C_PROBE474_MU_CNT : INTEGER;
C_PROBE475_MU_CNT : INTEGER;
C_PROBE476_MU_CNT : INTEGER;
C_PROBE477_MU_CNT : INTEGER;
C_PROBE478_MU_CNT : INTEGER;
C_PROBE479_MU_CNT : INTEGER;
C_PROBE480_MU_CNT : INTEGER;
C_PROBE481_MU_CNT : INTEGER;
C_PROBE482_MU_CNT : INTEGER;
C_PROBE483_MU_CNT : INTEGER;
C_PROBE484_MU_CNT : INTEGER;
C_PROBE485_MU_CNT : INTEGER;
C_PROBE486_MU_CNT : INTEGER;
C_PROBE487_MU_CNT : INTEGER;
C_PROBE488_MU_CNT : INTEGER;
C_PROBE489_MU_CNT : INTEGER;
C_PROBE490_MU_CNT : INTEGER;
C_PROBE491_MU_CNT : INTEGER;
C_PROBE492_MU_CNT : INTEGER;
C_PROBE493_MU_CNT : INTEGER;
C_PROBE494_MU_CNT : INTEGER;
C_PROBE495_MU_CNT : INTEGER;
C_PROBE496_MU_CNT : INTEGER;
C_PROBE497_MU_CNT : INTEGER;
C_PROBE498_MU_CNT : INTEGER;
C_PROBE499_MU_CNT : INTEGER;
C_PROBE500_MU_CNT : INTEGER;
C_PROBE501_MU_CNT : INTEGER;
C_PROBE502_MU_CNT : INTEGER;
C_PROBE503_MU_CNT : INTEGER;
C_PROBE504_MU_CNT : INTEGER;
C_PROBE505_MU_CNT : INTEGER;
C_PROBE506_MU_CNT : INTEGER;
C_PROBE507_MU_CNT : INTEGER;
C_PROBE508_MU_CNT : INTEGER;
C_PROBE509_MU_CNT : INTEGER;
C_PROBE510_MU_CNT : INTEGER;
C_PROBE511_MU_CNT : INTEGER;
C_PROBE512_MU_CNT : INTEGER;
C_PROBE513_MU_CNT : INTEGER;
C_PROBE514_MU_CNT : INTEGER;
C_PROBE515_MU_CNT : INTEGER;
C_PROBE516_MU_CNT : INTEGER;
C_PROBE517_MU_CNT : INTEGER;
C_PROBE518_MU_CNT : INTEGER;
C_PROBE519_MU_CNT : INTEGER;
C_PROBE520_MU_CNT : INTEGER;
C_PROBE521_MU_CNT : INTEGER;
C_PROBE522_MU_CNT : INTEGER;
C_PROBE523_MU_CNT : INTEGER;
C_PROBE524_MU_CNT : INTEGER;
C_PROBE525_MU_CNT : INTEGER;
C_PROBE526_MU_CNT : INTEGER;
C_PROBE527_MU_CNT : INTEGER;
C_PROBE528_MU_CNT : INTEGER;
C_PROBE529_MU_CNT : INTEGER;
C_PROBE530_MU_CNT : INTEGER;
C_PROBE531_MU_CNT : INTEGER;
C_PROBE532_MU_CNT : INTEGER;
C_PROBE533_MU_CNT : INTEGER;
C_PROBE534_MU_CNT : INTEGER;
C_PROBE535_MU_CNT : INTEGER;
C_PROBE536_MU_CNT : INTEGER;
C_PROBE537_MU_CNT : INTEGER;
C_PROBE538_MU_CNT : INTEGER;
C_PROBE539_MU_CNT : INTEGER;
C_PROBE540_MU_CNT : INTEGER;
C_PROBE541_MU_CNT : INTEGER;
C_PROBE542_MU_CNT : INTEGER;
C_PROBE543_MU_CNT : INTEGER;
C_PROBE544_MU_CNT : INTEGER;
C_PROBE545_MU_CNT : INTEGER;
C_PROBE546_MU_CNT : INTEGER;
C_PROBE547_MU_CNT : INTEGER;
C_PROBE548_MU_CNT : INTEGER;
C_PROBE549_MU_CNT : INTEGER;
C_PROBE550_MU_CNT : INTEGER;
C_PROBE551_MU_CNT : INTEGER;
C_PROBE552_MU_CNT : INTEGER;
C_PROBE553_MU_CNT : INTEGER;
C_PROBE554_MU_CNT : INTEGER;
C_PROBE555_MU_CNT : INTEGER;
C_PROBE556_MU_CNT : INTEGER;
C_PROBE557_MU_CNT : INTEGER;
C_PROBE558_MU_CNT : INTEGER;
C_PROBE559_MU_CNT : INTEGER;
C_PROBE560_MU_CNT : INTEGER;
C_PROBE561_MU_CNT : INTEGER;
C_PROBE562_MU_CNT : INTEGER;
C_PROBE563_MU_CNT : INTEGER;
C_PROBE564_MU_CNT : INTEGER;
C_PROBE565_MU_CNT : INTEGER;
C_PROBE566_MU_CNT : INTEGER;
C_PROBE567_MU_CNT : INTEGER;
C_PROBE568_MU_CNT : INTEGER;
C_PROBE569_MU_CNT : INTEGER;
C_PROBE570_MU_CNT : INTEGER;
C_PROBE571_MU_CNT : INTEGER;
C_PROBE572_MU_CNT : INTEGER;
C_PROBE573_MU_CNT : INTEGER;
C_PROBE574_MU_CNT : INTEGER;
C_PROBE575_MU_CNT : INTEGER;
C_PROBE576_MU_CNT : INTEGER;
C_PROBE577_MU_CNT : INTEGER;
C_PROBE578_MU_CNT : INTEGER;
C_PROBE579_MU_CNT : INTEGER;
C_PROBE580_MU_CNT : INTEGER;
C_PROBE581_MU_CNT : INTEGER;
C_PROBE582_MU_CNT : INTEGER;
C_PROBE583_MU_CNT : INTEGER;
C_PROBE584_MU_CNT : INTEGER;
C_PROBE585_MU_CNT : INTEGER;
C_PROBE586_MU_CNT : INTEGER;
C_PROBE587_MU_CNT : INTEGER;
C_PROBE588_MU_CNT : INTEGER;
C_PROBE589_MU_CNT : INTEGER;
C_PROBE590_MU_CNT : INTEGER;
C_PROBE591_MU_CNT : INTEGER;
C_PROBE592_MU_CNT : INTEGER;
C_PROBE593_MU_CNT : INTEGER;
C_PROBE594_MU_CNT : INTEGER;
C_PROBE595_MU_CNT : INTEGER;
C_PROBE596_MU_CNT : INTEGER;
C_PROBE597_MU_CNT : INTEGER;
C_PROBE598_MU_CNT : INTEGER;
C_PROBE599_MU_CNT : INTEGER;
C_PROBE600_MU_CNT : INTEGER;
C_PROBE601_MU_CNT : INTEGER;
C_PROBE602_MU_CNT : INTEGER;
C_PROBE603_MU_CNT : INTEGER;
C_PROBE604_MU_CNT : INTEGER;
C_PROBE605_MU_CNT : INTEGER;
C_PROBE606_MU_CNT : INTEGER;
C_PROBE607_MU_CNT : INTEGER;
C_PROBE608_MU_CNT : INTEGER;
C_PROBE609_MU_CNT : INTEGER;
C_PROBE610_MU_CNT : INTEGER;
C_PROBE611_MU_CNT : INTEGER;
C_PROBE612_MU_CNT : INTEGER;
C_PROBE613_MU_CNT : INTEGER;
C_PROBE614_MU_CNT : INTEGER;
C_PROBE615_MU_CNT : INTEGER;
C_PROBE616_MU_CNT : INTEGER;
C_PROBE617_MU_CNT : INTEGER;
C_PROBE618_MU_CNT : INTEGER;
C_PROBE619_MU_CNT : INTEGER;
C_PROBE620_MU_CNT : INTEGER;
C_PROBE621_MU_CNT : INTEGER;
C_PROBE622_MU_CNT : INTEGER;
C_PROBE623_MU_CNT : INTEGER;
C_PROBE624_MU_CNT : INTEGER;
C_PROBE625_MU_CNT : INTEGER;
C_PROBE626_MU_CNT : INTEGER;
C_PROBE627_MU_CNT : INTEGER;
C_PROBE628_MU_CNT : INTEGER;
C_PROBE629_MU_CNT : INTEGER;
C_PROBE630_MU_CNT : INTEGER;
C_PROBE631_MU_CNT : INTEGER;
C_PROBE632_MU_CNT : INTEGER;
C_PROBE633_MU_CNT : INTEGER;
C_PROBE634_MU_CNT : INTEGER;
C_PROBE635_MU_CNT : INTEGER;
C_PROBE636_MU_CNT : INTEGER;
C_PROBE637_MU_CNT : INTEGER;
C_PROBE638_MU_CNT : INTEGER;
C_PROBE639_MU_CNT : INTEGER;
C_PROBE640_MU_CNT : INTEGER;
C_PROBE641_MU_CNT : INTEGER;
C_PROBE642_MU_CNT : INTEGER;
C_PROBE643_MU_CNT : INTEGER;
C_PROBE644_MU_CNT : INTEGER;
C_PROBE645_MU_CNT : INTEGER;
C_PROBE646_MU_CNT : INTEGER;
C_PROBE647_MU_CNT : INTEGER;
C_PROBE648_MU_CNT : INTEGER;
C_PROBE649_MU_CNT : INTEGER;
C_PROBE650_MU_CNT : INTEGER;
C_PROBE651_MU_CNT : INTEGER;
C_PROBE652_MU_CNT : INTEGER;
C_PROBE653_MU_CNT : INTEGER;
C_PROBE654_MU_CNT : INTEGER;
C_PROBE655_MU_CNT : INTEGER;
C_PROBE656_MU_CNT : INTEGER;
C_PROBE657_MU_CNT : INTEGER;
C_PROBE658_MU_CNT : INTEGER;
C_PROBE659_MU_CNT : INTEGER;
C_PROBE660_MU_CNT : INTEGER;
C_PROBE661_MU_CNT : INTEGER;
C_PROBE662_MU_CNT : INTEGER;
C_PROBE663_MU_CNT : INTEGER;
C_PROBE664_MU_CNT : INTEGER;
C_PROBE665_MU_CNT : INTEGER;
C_PROBE666_MU_CNT : INTEGER;
C_PROBE667_MU_CNT : INTEGER;
C_PROBE668_MU_CNT : INTEGER;
C_PROBE669_MU_CNT : INTEGER;
C_PROBE670_MU_CNT : INTEGER;
C_PROBE671_MU_CNT : INTEGER;
C_PROBE672_MU_CNT : INTEGER;
C_PROBE673_MU_CNT : INTEGER;
C_PROBE674_MU_CNT : INTEGER;
C_PROBE675_MU_CNT : INTEGER;
C_PROBE676_MU_CNT : INTEGER;
C_PROBE677_MU_CNT : INTEGER;
C_PROBE678_MU_CNT : INTEGER;
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C_PROBE938_TYPE : INTEGER;
C_PROBE939_TYPE : INTEGER;
C_PROBE940_TYPE : INTEGER;
C_PROBE941_TYPE : INTEGER;
C_PROBE942_TYPE : INTEGER;
C_PROBE943_TYPE : INTEGER;
C_PROBE944_TYPE : INTEGER;
C_PROBE945_TYPE : INTEGER;
C_PROBE946_TYPE : INTEGER;
C_PROBE947_TYPE : INTEGER;
C_PROBE948_TYPE : INTEGER;
C_PROBE949_TYPE : INTEGER;
C_PROBE950_TYPE : INTEGER;
C_PROBE951_TYPE : INTEGER;
C_PROBE952_TYPE : INTEGER;
C_PROBE953_TYPE : INTEGER;
C_PROBE954_TYPE : INTEGER;
C_PROBE955_TYPE : INTEGER;
C_PROBE956_TYPE : INTEGER;
C_PROBE957_TYPE : INTEGER;
C_PROBE958_TYPE : INTEGER;
C_PROBE959_TYPE : INTEGER;
C_PROBE960_TYPE : INTEGER;
C_PROBE961_TYPE : INTEGER;
C_PROBE962_TYPE : INTEGER;
C_PROBE963_TYPE : INTEGER;
C_PROBE964_TYPE : INTEGER;
C_PROBE965_TYPE : INTEGER;
C_PROBE966_TYPE : INTEGER;
C_PROBE967_TYPE : INTEGER;
C_PROBE968_TYPE : INTEGER;
C_PROBE969_TYPE : INTEGER;
C_PROBE970_TYPE : INTEGER;
C_PROBE971_TYPE : INTEGER;
C_PROBE972_TYPE : INTEGER;
C_PROBE973_TYPE : INTEGER;
C_PROBE974_TYPE : INTEGER;
C_PROBE975_TYPE : INTEGER;
C_PROBE976_TYPE : INTEGER;
C_PROBE977_TYPE : INTEGER;
C_PROBE978_TYPE : INTEGER;
C_PROBE979_TYPE : INTEGER;
C_PROBE980_TYPE : INTEGER;
C_PROBE981_TYPE : INTEGER;
C_PROBE982_TYPE : INTEGER;
C_PROBE983_TYPE : INTEGER;
C_PROBE984_TYPE : INTEGER;
C_PROBE985_TYPE : INTEGER;
C_PROBE986_TYPE : INTEGER;
C_PROBE987_TYPE : INTEGER;
C_PROBE988_TYPE : INTEGER;
C_PROBE989_TYPE : INTEGER;
C_PROBE990_TYPE : INTEGER;
C_PROBE991_TYPE : INTEGER;
C_PROBE992_TYPE : INTEGER;
C_PROBE993_TYPE : INTEGER;
C_PROBE994_TYPE : INTEGER;
C_PROBE995_TYPE : INTEGER;
C_PROBE996_TYPE : INTEGER;
C_PROBE997_TYPE : INTEGER;
C_PROBE998_TYPE : INTEGER;
C_PROBE999_TYPE : INTEGER;
C_PROBE1000_TYPE : INTEGER;
C_PROBE1001_TYPE : INTEGER;
C_PROBE1002_TYPE : INTEGER;
C_PROBE1003_TYPE : INTEGER;
C_PROBE1004_TYPE : INTEGER;
C_PROBE1005_TYPE : INTEGER;
C_PROBE1006_TYPE : INTEGER;
C_PROBE1007_TYPE : INTEGER;
C_PROBE1008_TYPE : INTEGER;
C_PROBE1009_TYPE : INTEGER;
C_PROBE1010_TYPE : INTEGER;
C_PROBE1011_TYPE : INTEGER;
C_PROBE1012_TYPE : INTEGER;
C_PROBE1013_TYPE : INTEGER;
C_PROBE1014_TYPE : INTEGER;
C_PROBE1015_TYPE : INTEGER;
C_PROBE1016_TYPE : INTEGER;
C_PROBE1017_TYPE : INTEGER;
C_PROBE1018_TYPE : INTEGER;
C_PROBE1019_TYPE : INTEGER;
C_PROBE1020_TYPE : INTEGER;
C_PROBE1021_TYPE : INTEGER;
C_PROBE1022_TYPE : INTEGER;
C_PROBE1023_TYPE : INTEGER
);
PORT (
clk : IN STD_LOGIC;
sl_iport0 : IN STD_LOGIC_VECTOR (36 downto 0);
sl_oport0 : OUT STD_LOGIC_VECTOR (16 downto 0);
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe38 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe39 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe45 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe46 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe47 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe48 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe49 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe52 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe53 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe54 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe55 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe56 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe57 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe58 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe59 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe60 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe61 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe62 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe63 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe64 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe65 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe66 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe67 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe68 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe69 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe70 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe71 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe72 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe73 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe74 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe75 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe76 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe77 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe78 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe79 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe80 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe81 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe82 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe83 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe84 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe85 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe86 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe87 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe88 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe89 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe90 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe91 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe92 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe93 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe94 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe95 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe96 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe97 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe98 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe99 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe100 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe101 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe102 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe103 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe104 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe105 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe106 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe107 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe108 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe109 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe110 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe111 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe112 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe113 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe114 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe115 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe116 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe117 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe118 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe119 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe120 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe121 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe122 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe123 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe124 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe125 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe126 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe127 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe128 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe129 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe130 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe131 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe132 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe133 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe134 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe135 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe136 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe137 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe138 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe139 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe140 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe141 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe142 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe143 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe144 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe145 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe146 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe147 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe148 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe149 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe150 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe151 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe152 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe153 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe154 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe155 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe156 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe157 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe158 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe159 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe160 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe161 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe162 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe163 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe164 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe165 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe166 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe167 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe168 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe169 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe170 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe171 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe172 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe173 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe174 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe175 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe176 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe177 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe178 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe179 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe180 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe181 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe182 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe183 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe184 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe185 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe186 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe187 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe188 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe189 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe190 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe191 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe192 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe193 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe194 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe195 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe196 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe197 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe198 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe199 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe200 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe201 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe202 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe203 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe204 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe205 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe206 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe207 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe208 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe209 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe210 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe211 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe212 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe213 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe214 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe215 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe216 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe217 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe218 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe219 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe220 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe221 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe222 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe223 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe224 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe225 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe226 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe227 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe228 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe229 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe230 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe231 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe232 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe233 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe234 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe235 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe236 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe237 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe238 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe239 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe240 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe241 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe242 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe243 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe244 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe245 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe246 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe247 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe248 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe249 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe250 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe251 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe252 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe253 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe254 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe255 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe256 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe257 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe258 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe259 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe260 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe261 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe262 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe263 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe264 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe265 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe266 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe267 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe268 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe269 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe270 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe271 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe272 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe273 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe274 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe275 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe276 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe277 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe278 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe279 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe280 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe281 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe282 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe283 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe284 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe285 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe286 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe287 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe288 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe289 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe290 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe291 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe292 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe293 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe294 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe295 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe296 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe297 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe298 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe299 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe300 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe301 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe302 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe303 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe304 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe305 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe306 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe307 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe308 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe309 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe310 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe311 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe312 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe313 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe314 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe315 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe316 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe317 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe318 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe319 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe320 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe321 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe322 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe323 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe324 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe325 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe326 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe327 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe328 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe329 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe330 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe331 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe332 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe333 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe334 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe335 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe336 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe337 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe338 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe339 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe340 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe341 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe342 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe343 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe344 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe345 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe346 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe347 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe348 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe349 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe350 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe351 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe352 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe353 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe354 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe355 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe356 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe357 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe358 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe359 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe360 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe361 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe362 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe363 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe364 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe365 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe366 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe367 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe368 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe369 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe370 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe371 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe372 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe373 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe374 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe375 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe376 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe377 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe378 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe379 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe380 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe381 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe382 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe383 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe384 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe385 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe386 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe387 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe388 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe389 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe390 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe391 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe392 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe393 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe394 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe395 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe396 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe397 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe398 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe399 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe400 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe401 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe402 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe403 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe404 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe405 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe406 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe407 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe408 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe409 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe410 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe411 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe412 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe413 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe414 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe415 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe416 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe417 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe418 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe419 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe420 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe421 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe422 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe423 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe424 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe425 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe426 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe427 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe428 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe429 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe430 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe431 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe432 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe433 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe434 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe435 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe436 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe437 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe438 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe439 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe440 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe441 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe442 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe443 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe444 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe445 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe446 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe447 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe448 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe449 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe450 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe451 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe452 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe453 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe454 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe455 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe456 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe457 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe458 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe459 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe460 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe461 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe462 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe463 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe464 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe465 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe466 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe467 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe468 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe469 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe470 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe471 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe472 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe473 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe474 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe475 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe476 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe477 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe478 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe479 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe480 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe481 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe482 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe483 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe484 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe485 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe486 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe487 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe488 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe489 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe490 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe491 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe492 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe493 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe494 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe495 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe496 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe497 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe498 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe499 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe500 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe501 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe502 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe503 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe504 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe505 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe506 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe507 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe508 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe509 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe510 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe511 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe512 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe513 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe514 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe515 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe516 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe517 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe518 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe519 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe520 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe521 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe522 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe523 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe524 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe525 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe526 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe527 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe528 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe529 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe530 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe531 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe532 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe533 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe534 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe535 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe536 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe537 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe538 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe539 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe540 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe541 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe542 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe543 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe544 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe545 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe546 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe547 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe548 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe549 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe550 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe551 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe552 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe553 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe554 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe555 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe556 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe557 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe558 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe559 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe560 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe561 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe562 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe563 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe564 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe565 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe566 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe567 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe568 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe569 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe570 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe571 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe572 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe573 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe574 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe575 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe576 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe577 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe578 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe579 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe580 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe581 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe582 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe583 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe584 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe585 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe586 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe587 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe588 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe589 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe590 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe591 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe592 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe593 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe594 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe595 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe596 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe597 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe598 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe599 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe600 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe601 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe602 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe603 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe604 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe605 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe606 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe607 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe608 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe609 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe610 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe611 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe612 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe613 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe614 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe615 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe616 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe617 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe618 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe619 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe620 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe621 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe622 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe623 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe624 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe625 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe626 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe627 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe628 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe629 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe630 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe631 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe632 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe633 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe634 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe635 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe636 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe637 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe638 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe639 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe640 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe641 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe642 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe643 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe644 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe645 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe646 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe647 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe648 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe649 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe650 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe651 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe652 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe653 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe654 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe655 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe656 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe657 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe658 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe659 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe660 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe661 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe662 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe663 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe664 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe665 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe666 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe667 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe668 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe669 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe670 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe671 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe672 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe673 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe674 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe675 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe676 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe677 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe678 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe679 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe680 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe681 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe682 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe683 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe684 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe685 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe686 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe687 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe688 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe689 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe690 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe691 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe692 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe693 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe694 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe695 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe696 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe697 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe698 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe699 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe700 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe701 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe702 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe703 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe704 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe705 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe706 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe707 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe708 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe709 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe710 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe711 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe712 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe713 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe714 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe715 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe716 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe717 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe718 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe719 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe720 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe721 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe722 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe723 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe724 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe725 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe726 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe727 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe728 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe729 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe730 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe731 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe732 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe733 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe734 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe735 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe736 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe737 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe738 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe739 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe740 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe741 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe742 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe743 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe744 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe745 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe746 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe747 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe748 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe749 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe750 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe751 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe752 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe753 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe754 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe755 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe756 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe757 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe758 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe759 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe760 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe761 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe762 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe763 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe764 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe765 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe766 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe767 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe768 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe769 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe770 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe771 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe772 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe773 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe774 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe775 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe776 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe777 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe778 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe779 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe780 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe781 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe782 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe783 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe784 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe785 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe786 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe787 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe788 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe789 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe790 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe791 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe792 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe793 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe794 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe795 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe796 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe797 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe798 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe799 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe800 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe801 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe802 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe803 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe804 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe805 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe806 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe807 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe808 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe809 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe810 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe811 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe812 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe813 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe814 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe815 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe816 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe817 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe818 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe819 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe820 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe821 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe822 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe823 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe824 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe825 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe826 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe827 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe828 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe829 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe830 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe831 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe832 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe833 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe834 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe835 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe836 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe837 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe838 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe839 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe840 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe841 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe842 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe843 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe844 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe845 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe846 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe847 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe848 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe849 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe850 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe851 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe852 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe853 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe854 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe855 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe856 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe857 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe858 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe859 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe860 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe861 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe862 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe863 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe864 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe865 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe866 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe867 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe868 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe869 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe870 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe871 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe872 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe873 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe874 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe875 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe876 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe877 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe878 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe879 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe880 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe881 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe882 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe883 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe884 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe885 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe886 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe887 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe888 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe889 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe890 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe891 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe892 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe893 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe894 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe895 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe896 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe897 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe898 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe899 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe900 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe901 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe902 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe903 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe904 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe905 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe906 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe907 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe908 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe909 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe910 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe911 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe912 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe913 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe914 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe915 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe916 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe917 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe918 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe919 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe920 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe921 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe922 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe923 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe924 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe925 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe926 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe927 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe928 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe929 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe930 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe931 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe932 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe933 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe934 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe935 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe936 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe937 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe938 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe939 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe940 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe941 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe942 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe943 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe944 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe945 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe946 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe947 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe948 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe949 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe950 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe951 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe952 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe953 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe954 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe955 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe956 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe957 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe958 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe959 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe960 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe961 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe962 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe963 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe964 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe965 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe966 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe967 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe968 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe969 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe970 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe971 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe972 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe973 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe974 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe975 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe976 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe977 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe978 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe979 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe980 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe981 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe982 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe983 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe984 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe985 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe986 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe987 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe988 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe989 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe990 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe991 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe992 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe993 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe994 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe995 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe996 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe997 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe998 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe999 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1000 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1001 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1002 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1003 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1004 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1005 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1006 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1007 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1008 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1009 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1010 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1011 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1012 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1013 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1014 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1015 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1016 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1017 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1018 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1019 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1020 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1021 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1022 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1023 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ila_v6_2_4_ila;
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "yes";
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "ila,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila_v6_2_4_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=artix7,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=4,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2017,C_MINOR_VERSION=3,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=1,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=2,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=72000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=8,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=8,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
"C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,"&
"C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE529_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE553_WIDTH=1,"&
"C_PROBE554_WIDTH=1,C_PROBE555_WIDTH=1,C_PROBE556_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE608_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE653_WIDTH=1,"&
"C_PROBE654_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE660_WIDTH=1,C_PROBE661_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE687_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE713_WIDTH=1,C_PROBE714_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE739_WIDTH=1,C_PROBE740_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE753_WIDTH=1,"&
"C_PROBE754_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE766_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE792_WIDTH=1,C_PROBE793_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE818_WIDTH=1,C_PROBE819_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE844_WIDTH=1,C_PROBE845_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE853_WIDTH=1,"&
"C_PROBE854_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE871_WIDTH=1,C_PROBE872_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE897_WIDTH=1,C_PROBE898_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE923_WIDTH=1,C_PROBE924_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE950_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE953_WIDTH=1,"&
"C_PROBE954_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=2,C_PROBE1_MU_CNT=2,C_PROBE2_MU_CNT=2,C_PROBE3_MU_CNT=2,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,"&
"C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,"&
"C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,"&
"C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,"&
"C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,"&
"C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,"&
"C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,"&
"C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,"&
"C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,"&
"C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,"&
"C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=1,C_PROBE2_TYPE=0,C_PROBE3_TYPE=1,C_PROBE4_TYPE=1,C_PROBE5_TYPE=1,"&
"C_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
"C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,"&
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"C_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1},";
attribute syn_noprune : boolean;
attribute syn_noprune of U0 : label is true;
SIGNAL sl_iport0 : STD_LOGIC_VECTOR (36 downto 0);
SIGNAL sl_oport0 : STD_LOGIC_VECTOR (16 downto 0);
BEGIN
U0 : ila_v6_2_4_ila
GENERIC MAP (
C_XLNX_HW_PROBE_INFO => "DEFAULT",
C_XDEVICEFAMILY => "artix7",
C_CORE_TYPE => 1,
C_CORE_INFO1 => 0,
C_CORE_INFO2 => 0,
C_CAPTURE_TYPE => 0,
C_MU_TYPE => 0,
C_TC_TYPE => 0,
C_NUM_OF_PROBES => 4,
C_DATA_DEPTH => 8192,
C_MAJOR_VERSION => 2017,
C_MINOR_VERSION => 3,
C_BUILD_REVISION => 0,
C_CORE_MAJOR_VER => 6,
C_CORE_MINOR_VER => 2,
C_XSDB_SLAVE_TYPE => 17,
C_NEXT_SLAVE => 0,
C_CSE_DRV_VER => 2,
C_USE_TEST_REG => 1,
C_PIPE_IFACE => 1,
C_RAM_STYLE => "SUBCORE",
C_TRIGOUT_EN => 0,
C_TRIGIN_EN => 0,
C_ADV_TRIGGER => 0,
C_EN_DDR_ILA => 0,
C_EN_STRG_QUAL => 1,
C_INPUT_PIPE_STAGES => 0,
C_EN_TIME_TAG => 0,
C_TIME_TAG_WIDTH => 32,
C_ILA_CLK_FREQ => 72000000,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 8,
C_PROBE2_WIDTH => 1,
C_PROBE3_WIDTH => 8,
C_PROBE4_WIDTH => 1,
C_PROBE5_WIDTH => 1,
C_PROBE6_WIDTH => 1,
C_PROBE7_WIDTH => 1,
C_PROBE8_WIDTH => 1,
C_PROBE9_WIDTH => 1,
C_PROBE10_WIDTH => 1,
C_PROBE11_WIDTH => 1,
C_PROBE12_WIDTH => 1,
C_PROBE13_WIDTH => 1,
C_PROBE14_WIDTH => 1,
C_PROBE15_WIDTH => 1,
C_PROBE16_WIDTH => 1,
C_PROBE17_WIDTH => 1,
C_PROBE18_WIDTH => 1,
C_PROBE19_WIDTH => 1,
C_PROBE20_WIDTH => 1,
C_PROBE21_WIDTH => 1,
C_PROBE22_WIDTH => 1,
C_PROBE23_WIDTH => 1,
C_PROBE24_WIDTH => 1,
C_PROBE25_WIDTH => 1,
C_PROBE26_WIDTH => 1,
C_PROBE27_WIDTH => 1,
C_PROBE28_WIDTH => 1,
C_PROBE29_WIDTH => 1,
C_PROBE30_WIDTH => 1,
C_PROBE31_WIDTH => 1,
C_PROBE32_WIDTH => 1,
C_PROBE33_WIDTH => 1,
C_PROBE34_WIDTH => 1,
C_PROBE35_WIDTH => 1,
C_PROBE36_WIDTH => 1,
C_PROBE37_WIDTH => 1,
C_PROBE38_WIDTH => 1,
C_PROBE39_WIDTH => 1,
C_PROBE40_WIDTH => 1,
C_PROBE41_WIDTH => 1,
C_PROBE42_WIDTH => 1,
C_PROBE43_WIDTH => 1,
C_PROBE44_WIDTH => 1,
C_PROBE45_WIDTH => 1,
C_PROBE46_WIDTH => 1,
C_PROBE47_WIDTH => 1,
C_PROBE48_WIDTH => 1,
C_PROBE49_WIDTH => 1,
C_PROBE50_WIDTH => 1,
C_PROBE51_WIDTH => 1,
C_PROBE52_WIDTH => 1,
C_PROBE53_WIDTH => 1,
C_PROBE54_WIDTH => 1,
C_PROBE55_WIDTH => 1,
C_PROBE56_WIDTH => 1,
C_PROBE57_WIDTH => 1,
C_PROBE58_WIDTH => 1,
C_PROBE59_WIDTH => 1,
C_PROBE60_WIDTH => 1,
C_PROBE61_WIDTH => 1,
C_PROBE62_WIDTH => 1,
C_PROBE63_WIDTH => 1,
C_PROBE64_WIDTH => 1,
C_PROBE65_WIDTH => 1,
C_PROBE66_WIDTH => 1,
C_PROBE67_WIDTH => 1,
C_PROBE68_WIDTH => 1,
C_PROBE69_WIDTH => 1,
C_PROBE70_WIDTH => 1,
C_PROBE71_WIDTH => 1,
C_PROBE72_WIDTH => 1,
C_PROBE73_WIDTH => 1,
C_PROBE74_WIDTH => 1,
C_PROBE75_WIDTH => 1,
C_PROBE76_WIDTH => 1,
C_PROBE77_WIDTH => 1,
C_PROBE78_WIDTH => 1,
C_PROBE79_WIDTH => 1,
C_PROBE80_WIDTH => 1,
C_PROBE81_WIDTH => 1,
C_PROBE82_WIDTH => 1,
C_PROBE83_WIDTH => 1,
C_PROBE84_WIDTH => 1,
C_PROBE85_WIDTH => 1,
C_PROBE86_WIDTH => 1,
C_PROBE87_WIDTH => 1,
C_PROBE88_WIDTH => 1,
C_PROBE89_WIDTH => 1,
C_PROBE90_WIDTH => 1,
C_PROBE91_WIDTH => 1,
C_PROBE92_WIDTH => 1,
C_PROBE93_WIDTH => 1,
C_PROBE94_WIDTH => 1,
C_PROBE95_WIDTH => 1,
C_PROBE96_WIDTH => 1,
C_PROBE97_WIDTH => 1,
C_PROBE98_WIDTH => 1,
C_PROBE99_WIDTH => 1,
C_PROBE100_WIDTH => 1,
C_PROBE101_WIDTH => 1,
C_PROBE102_WIDTH => 1,
C_PROBE103_WIDTH => 1,
C_PROBE104_WIDTH => 1,
C_PROBE105_WIDTH => 1,
C_PROBE106_WIDTH => 1,
C_PROBE107_WIDTH => 1,
C_PROBE108_WIDTH => 1,
C_PROBE109_WIDTH => 1,
C_PROBE110_WIDTH => 1,
C_PROBE111_WIDTH => 1,
C_PROBE112_WIDTH => 1,
C_PROBE113_WIDTH => 1,
C_PROBE114_WIDTH => 1,
C_PROBE115_WIDTH => 1,
C_PROBE116_WIDTH => 1,
C_PROBE117_WIDTH => 1,
C_PROBE118_WIDTH => 1,
C_PROBE119_WIDTH => 1,
C_PROBE120_WIDTH => 1,
C_PROBE121_WIDTH => 1,
C_PROBE122_WIDTH => 1,
C_PROBE123_WIDTH => 1,
C_PROBE124_WIDTH => 1,
C_PROBE125_WIDTH => 1,
C_PROBE126_WIDTH => 1,
C_PROBE127_WIDTH => 1,
C_PROBE128_WIDTH => 1,
C_PROBE129_WIDTH => 1,
C_PROBE130_WIDTH => 1,
C_PROBE131_WIDTH => 1,
C_PROBE132_WIDTH => 1,
C_PROBE133_WIDTH => 1,
C_PROBE134_WIDTH => 1,
C_PROBE135_WIDTH => 1,
C_PROBE136_WIDTH => 1,
C_PROBE137_WIDTH => 1,
C_PROBE138_WIDTH => 1,
C_PROBE139_WIDTH => 1,
C_PROBE140_WIDTH => 1,
C_PROBE141_WIDTH => 1,
C_PROBE142_WIDTH => 1,
C_PROBE143_WIDTH => 1,
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C_PROBE209_WIDTH => 1,
C_PROBE210_WIDTH => 1,
C_PROBE211_WIDTH => 1,
C_PROBE212_WIDTH => 1,
C_PROBE213_WIDTH => 1,
C_PROBE214_WIDTH => 1,
C_PROBE215_WIDTH => 1,
C_PROBE216_WIDTH => 1,
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C_PROBE218_WIDTH => 1,
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C_PROBE988_WIDTH => 1,
C_PROBE989_WIDTH => 1,
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C_PROBE998_WIDTH => 1,
C_PROBE999_WIDTH => 1,
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C_PROBE1003_WIDTH => 1,
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C_PROBE1005_WIDTH => 1,
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C_PROBE1007_WIDTH => 1,
C_PROBE1008_WIDTH => 1,
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C_PROBE1010_WIDTH => 1,
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C_PROBE1012_WIDTH => 1,
C_PROBE1013_WIDTH => 1,
C_PROBE1014_WIDTH => 1,
C_PROBE1015_WIDTH => 1,
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C_PROBE1019_WIDTH => 1,
C_PROBE1020_WIDTH => 1,
C_PROBE1021_WIDTH => 1,
C_PROBE1022_WIDTH => 1,
C_PROBE1023_WIDTH => 1,
C_PROBE0_MU_CNT => 2,
C_PROBE1_MU_CNT => 2,
C_PROBE2_MU_CNT => 2,
C_PROBE3_MU_CNT => 2,
C_PROBE4_MU_CNT => 1,
C_PROBE5_MU_CNT => 1,
C_PROBE6_MU_CNT => 1,
C_PROBE7_MU_CNT => 1,
C_PROBE8_MU_CNT => 1,
C_PROBE9_MU_CNT => 1,
C_PROBE10_MU_CNT => 1,
C_PROBE11_MU_CNT => 1,
C_PROBE12_MU_CNT => 1,
C_PROBE13_MU_CNT => 1,
C_PROBE14_MU_CNT => 1,
C_PROBE15_MU_CNT => 1,
C_PROBE16_MU_CNT => 1,
C_PROBE17_MU_CNT => 1,
C_PROBE18_MU_CNT => 1,
C_PROBE19_MU_CNT => 1,
C_PROBE20_MU_CNT => 1,
C_PROBE21_MU_CNT => 1,
C_PROBE22_MU_CNT => 1,
C_PROBE23_MU_CNT => 1,
C_PROBE24_MU_CNT => 1,
C_PROBE25_MU_CNT => 1,
C_PROBE26_MU_CNT => 1,
C_PROBE27_MU_CNT => 1,
C_PROBE28_MU_CNT => 1,
C_PROBE29_MU_CNT => 1,
C_PROBE30_MU_CNT => 1,
C_PROBE31_MU_CNT => 1,
C_PROBE32_MU_CNT => 1,
C_PROBE33_MU_CNT => 1,
C_PROBE34_MU_CNT => 1,
C_PROBE35_MU_CNT => 1,
C_PROBE36_MU_CNT => 1,
C_PROBE37_MU_CNT => 1,
C_PROBE38_MU_CNT => 1,
C_PROBE39_MU_CNT => 1,
C_PROBE40_MU_CNT => 1,
C_PROBE41_MU_CNT => 1,
C_PROBE42_MU_CNT => 1,
C_PROBE43_MU_CNT => 1,
C_PROBE44_MU_CNT => 1,
C_PROBE45_MU_CNT => 1,
C_PROBE46_MU_CNT => 1,
C_PROBE47_MU_CNT => 1,
C_PROBE48_MU_CNT => 1,
C_PROBE49_MU_CNT => 1,
C_PROBE50_MU_CNT => 1,
C_PROBE51_MU_CNT => 1,
C_PROBE52_MU_CNT => 1,
C_PROBE53_MU_CNT => 1,
C_PROBE54_MU_CNT => 1,
C_PROBE55_MU_CNT => 1,
C_PROBE56_MU_CNT => 1,
C_PROBE57_MU_CNT => 1,
C_PROBE58_MU_CNT => 1,
C_PROBE59_MU_CNT => 1,
C_PROBE60_MU_CNT => 1,
C_PROBE61_MU_CNT => 1,
C_PROBE62_MU_CNT => 1,
C_PROBE63_MU_CNT => 1,
C_PROBE64_MU_CNT => 1,
C_PROBE65_MU_CNT => 1,
C_PROBE66_MU_CNT => 1,
C_PROBE67_MU_CNT => 1,
C_PROBE68_MU_CNT => 1,
C_PROBE69_MU_CNT => 1,
C_PROBE70_MU_CNT => 1,
C_PROBE71_MU_CNT => 1,
C_PROBE72_MU_CNT => 1,
C_PROBE73_MU_CNT => 1,
C_PROBE74_MU_CNT => 1,
C_PROBE75_MU_CNT => 1,
C_PROBE76_MU_CNT => 1,
C_PROBE77_MU_CNT => 1,
C_PROBE78_MU_CNT => 1,
C_PROBE79_MU_CNT => 1,
C_PROBE80_MU_CNT => 1,
C_PROBE81_MU_CNT => 1,
C_PROBE82_MU_CNT => 1,
C_PROBE83_MU_CNT => 1,
C_PROBE84_MU_CNT => 1,
C_PROBE85_MU_CNT => 1,
C_PROBE86_MU_CNT => 1,
C_PROBE87_MU_CNT => 1,
C_PROBE88_MU_CNT => 1,
C_PROBE89_MU_CNT => 1,
C_PROBE90_MU_CNT => 1,
C_PROBE91_MU_CNT => 1,
C_PROBE92_MU_CNT => 1,
C_PROBE93_MU_CNT => 1,
C_PROBE94_MU_CNT => 1,
C_PROBE95_MU_CNT => 1,
C_PROBE96_MU_CNT => 1,
C_PROBE97_MU_CNT => 1,
C_PROBE98_MU_CNT => 1,
C_PROBE99_MU_CNT => 1,
C_PROBE100_MU_CNT => 1,
C_PROBE101_MU_CNT => 1,
C_PROBE102_MU_CNT => 1,
C_PROBE103_MU_CNT => 1,
C_PROBE104_MU_CNT => 1,
C_PROBE105_MU_CNT => 1,
C_PROBE106_MU_CNT => 1,
C_PROBE107_MU_CNT => 1,
C_PROBE108_MU_CNT => 1,
C_PROBE109_MU_CNT => 1,
C_PROBE110_MU_CNT => 1,
C_PROBE111_MU_CNT => 1,
C_PROBE112_MU_CNT => 1,
C_PROBE113_MU_CNT => 1,
C_PROBE114_MU_CNT => 1,
C_PROBE115_MU_CNT => 1,
C_PROBE116_MU_CNT => 1,
C_PROBE117_MU_CNT => 1,
C_PROBE118_MU_CNT => 1,
C_PROBE119_MU_CNT => 1,
C_PROBE120_MU_CNT => 1,
C_PROBE121_MU_CNT => 1,
C_PROBE122_MU_CNT => 1,
C_PROBE123_MU_CNT => 1,
C_PROBE124_MU_CNT => 1,
C_PROBE125_MU_CNT => 1,
C_PROBE126_MU_CNT => 1,
C_PROBE127_MU_CNT => 1,
C_PROBE128_MU_CNT => 1,
C_PROBE129_MU_CNT => 1,
C_PROBE130_MU_CNT => 1,
C_PROBE131_MU_CNT => 1,
C_PROBE132_MU_CNT => 1,
C_PROBE133_MU_CNT => 1,
C_PROBE134_MU_CNT => 1,
C_PROBE135_MU_CNT => 1,
C_PROBE136_MU_CNT => 1,
C_PROBE137_MU_CNT => 1,
C_PROBE138_MU_CNT => 1,
C_PROBE139_MU_CNT => 1,
C_PROBE140_MU_CNT => 1,
C_PROBE141_MU_CNT => 1,
C_PROBE142_MU_CNT => 1,
C_PROBE143_MU_CNT => 1,
C_PROBE144_MU_CNT => 1,
C_PROBE145_MU_CNT => 1,
C_PROBE146_MU_CNT => 1,
C_PROBE147_MU_CNT => 1,
C_PROBE148_MU_CNT => 1,
C_PROBE149_MU_CNT => 1,
C_PROBE150_MU_CNT => 1,
C_PROBE151_MU_CNT => 1,
C_PROBE152_MU_CNT => 1,
C_PROBE153_MU_CNT => 1,
C_PROBE154_MU_CNT => 1,
C_PROBE155_MU_CNT => 1,
C_PROBE156_MU_CNT => 1,
C_PROBE157_MU_CNT => 1,
C_PROBE158_MU_CNT => 1,
C_PROBE159_MU_CNT => 1,
C_PROBE160_MU_CNT => 1,
C_PROBE161_MU_CNT => 1,
C_PROBE162_MU_CNT => 1,
C_PROBE163_MU_CNT => 1,
C_PROBE164_MU_CNT => 1,
C_PROBE165_MU_CNT => 1,
C_PROBE166_MU_CNT => 1,
C_PROBE167_MU_CNT => 1,
C_PROBE168_MU_CNT => 1,
C_PROBE169_MU_CNT => 1,
C_PROBE170_MU_CNT => 1,
C_PROBE171_MU_CNT => 1,
C_PROBE172_MU_CNT => 1,
C_PROBE173_MU_CNT => 1,
C_PROBE174_MU_CNT => 1,
C_PROBE175_MU_CNT => 1,
C_PROBE176_MU_CNT => 1,
C_PROBE177_MU_CNT => 1,
C_PROBE178_MU_CNT => 1,
C_PROBE179_MU_CNT => 1,
C_PROBE180_MU_CNT => 1,
C_PROBE181_MU_CNT => 1,
C_PROBE182_MU_CNT => 1,
C_PROBE183_MU_CNT => 1,
C_PROBE184_MU_CNT => 1,
C_PROBE185_MU_CNT => 1,
C_PROBE186_MU_CNT => 1,
C_PROBE187_MU_CNT => 1,
C_PROBE188_MU_CNT => 1,
C_PROBE189_MU_CNT => 1,
C_PROBE190_MU_CNT => 1,
C_PROBE191_MU_CNT => 1,
C_PROBE192_MU_CNT => 1,
C_PROBE193_MU_CNT => 1,
C_PROBE194_MU_CNT => 1,
C_PROBE195_MU_CNT => 1,
C_PROBE196_MU_CNT => 1,
C_PROBE197_MU_CNT => 1,
C_PROBE198_MU_CNT => 1,
C_PROBE199_MU_CNT => 1,
C_PROBE200_MU_CNT => 1,
C_PROBE201_MU_CNT => 1,
C_PROBE202_MU_CNT => 1,
C_PROBE203_MU_CNT => 1,
C_PROBE204_MU_CNT => 1,
C_PROBE205_MU_CNT => 1,
C_PROBE206_MU_CNT => 1,
C_PROBE207_MU_CNT => 1,
C_PROBE208_MU_CNT => 1,
C_PROBE209_MU_CNT => 1,
C_PROBE210_MU_CNT => 1,
C_PROBE211_MU_CNT => 1,
C_PROBE212_MU_CNT => 1,
C_PROBE213_MU_CNT => 1,
C_PROBE214_MU_CNT => 1,
C_PROBE215_MU_CNT => 1,
C_PROBE216_MU_CNT => 1,
C_PROBE217_MU_CNT => 1,
C_PROBE218_MU_CNT => 1,
C_PROBE219_MU_CNT => 1,
C_PROBE220_MU_CNT => 1,
C_PROBE221_MU_CNT => 1,
C_PROBE222_MU_CNT => 1,
C_PROBE223_MU_CNT => 1,
C_PROBE224_MU_CNT => 1,
C_PROBE225_MU_CNT => 1,
C_PROBE226_MU_CNT => 1,
C_PROBE227_MU_CNT => 1,
C_PROBE228_MU_CNT => 1,
C_PROBE229_MU_CNT => 1,
C_PROBE230_MU_CNT => 1,
C_PROBE231_MU_CNT => 1,
C_PROBE232_MU_CNT => 1,
C_PROBE233_MU_CNT => 1,
C_PROBE234_MU_CNT => 1,
C_PROBE235_MU_CNT => 1,
C_PROBE236_MU_CNT => 1,
C_PROBE237_MU_CNT => 1,
C_PROBE238_MU_CNT => 1,
C_PROBE239_MU_CNT => 1,
C_PROBE240_MU_CNT => 1,
C_PROBE241_MU_CNT => 1,
C_PROBE242_MU_CNT => 1,
C_PROBE243_MU_CNT => 1,
C_PROBE244_MU_CNT => 1,
C_PROBE245_MU_CNT => 1,
C_PROBE246_MU_CNT => 1,
C_PROBE247_MU_CNT => 1,
C_PROBE248_MU_CNT => 1,
C_PROBE249_MU_CNT => 1,
C_PROBE250_MU_CNT => 1,
C_PROBE251_MU_CNT => 1,
C_PROBE252_MU_CNT => 1,
C_PROBE253_MU_CNT => 1,
C_PROBE254_MU_CNT => 1,
C_PROBE255_MU_CNT => 1,
C_PROBE256_MU_CNT => 1,
C_PROBE257_MU_CNT => 1,
C_PROBE258_MU_CNT => 1,
C_PROBE259_MU_CNT => 1,
C_PROBE260_MU_CNT => 1,
C_PROBE261_MU_CNT => 1,
C_PROBE262_MU_CNT => 1,
C_PROBE263_MU_CNT => 1,
C_PROBE264_MU_CNT => 1,
C_PROBE265_MU_CNT => 1,
C_PROBE266_MU_CNT => 1,
C_PROBE267_MU_CNT => 1,
C_PROBE268_MU_CNT => 1,
C_PROBE269_MU_CNT => 1,
C_PROBE270_MU_CNT => 1,
C_PROBE271_MU_CNT => 1,
C_PROBE272_MU_CNT => 1,
C_PROBE273_MU_CNT => 1,
C_PROBE274_MU_CNT => 1,
C_PROBE275_MU_CNT => 1,
C_PROBE276_MU_CNT => 1,
C_PROBE277_MU_CNT => 1,
C_PROBE278_MU_CNT => 1,
C_PROBE279_MU_CNT => 1,
C_PROBE280_MU_CNT => 1,
C_PROBE281_MU_CNT => 1,
C_PROBE282_MU_CNT => 1,
C_PROBE283_MU_CNT => 1,
C_PROBE284_MU_CNT => 1,
C_PROBE285_MU_CNT => 1,
C_PROBE286_MU_CNT => 1,
C_PROBE287_MU_CNT => 1,
C_PROBE288_MU_CNT => 1,
C_PROBE289_MU_CNT => 1,
C_PROBE290_MU_CNT => 1,
C_PROBE291_MU_CNT => 1,
C_PROBE292_MU_CNT => 1,
C_PROBE293_MU_CNT => 1,
C_PROBE294_MU_CNT => 1,
C_PROBE295_MU_CNT => 1,
C_PROBE296_MU_CNT => 1,
C_PROBE297_MU_CNT => 1,
C_PROBE298_MU_CNT => 1,
C_PROBE299_MU_CNT => 1,
C_PROBE300_MU_CNT => 1,
C_PROBE301_MU_CNT => 1,
C_PROBE302_MU_CNT => 1,
C_PROBE303_MU_CNT => 1,
C_PROBE304_MU_CNT => 1,
C_PROBE305_MU_CNT => 1,
C_PROBE306_MU_CNT => 1,
C_PROBE307_MU_CNT => 1,
C_PROBE308_MU_CNT => 1,
C_PROBE309_MU_CNT => 1,
C_PROBE310_MU_CNT => 1,
C_PROBE311_MU_CNT => 1,
C_PROBE312_MU_CNT => 1,
C_PROBE313_MU_CNT => 1,
C_PROBE314_MU_CNT => 1,
C_PROBE315_MU_CNT => 1,
C_PROBE316_MU_CNT => 1,
C_PROBE317_MU_CNT => 1,
C_PROBE318_MU_CNT => 1,
C_PROBE319_MU_CNT => 1,
C_PROBE320_MU_CNT => 1,
C_PROBE321_MU_CNT => 1,
C_PROBE322_MU_CNT => 1,
C_PROBE323_MU_CNT => 1,
C_PROBE324_MU_CNT => 1,
C_PROBE325_MU_CNT => 1,
C_PROBE326_MU_CNT => 1,
C_PROBE327_MU_CNT => 1,
C_PROBE328_MU_CNT => 1,
C_PROBE329_MU_CNT => 1,
C_PROBE330_MU_CNT => 1,
C_PROBE331_MU_CNT => 1,
C_PROBE332_MU_CNT => 1,
C_PROBE333_MU_CNT => 1,
C_PROBE334_MU_CNT => 1,
C_PROBE335_MU_CNT => 1,
C_PROBE336_MU_CNT => 1,
C_PROBE337_MU_CNT => 1,
C_PROBE338_MU_CNT => 1,
C_PROBE339_MU_CNT => 1,
C_PROBE340_MU_CNT => 1,
C_PROBE341_MU_CNT => 1,
C_PROBE342_MU_CNT => 1,
C_PROBE343_MU_CNT => 1,
C_PROBE344_MU_CNT => 1,
C_PROBE345_MU_CNT => 1,
C_PROBE346_MU_CNT => 1,
C_PROBE347_MU_CNT => 1,
C_PROBE348_MU_CNT => 1,
C_PROBE349_MU_CNT => 1,
C_PROBE350_MU_CNT => 1,
C_PROBE351_MU_CNT => 1,
C_PROBE352_MU_CNT => 1,
C_PROBE353_MU_CNT => 1,
C_PROBE354_MU_CNT => 1,
C_PROBE355_MU_CNT => 1,
C_PROBE356_MU_CNT => 1,
C_PROBE357_MU_CNT => 1,
C_PROBE358_MU_CNT => 1,
C_PROBE359_MU_CNT => 1,
C_PROBE360_MU_CNT => 1,
C_PROBE361_MU_CNT => 1,
C_PROBE362_MU_CNT => 1,
C_PROBE363_MU_CNT => 1,
C_PROBE364_MU_CNT => 1,
C_PROBE365_MU_CNT => 1,
C_PROBE366_MU_CNT => 1,
C_PROBE367_MU_CNT => 1,
C_PROBE368_MU_CNT => 1,
C_PROBE369_MU_CNT => 1,
C_PROBE370_MU_CNT => 1,
C_PROBE371_MU_CNT => 1,
C_PROBE372_MU_CNT => 1,
C_PROBE373_MU_CNT => 1,
C_PROBE374_MU_CNT => 1,
C_PROBE375_MU_CNT => 1,
C_PROBE376_MU_CNT => 1,
C_PROBE377_MU_CNT => 1,
C_PROBE378_MU_CNT => 1,
C_PROBE379_MU_CNT => 1,
C_PROBE380_MU_CNT => 1,
C_PROBE381_MU_CNT => 1,
C_PROBE382_MU_CNT => 1,
C_PROBE383_MU_CNT => 1,
C_PROBE384_MU_CNT => 1,
C_PROBE385_MU_CNT => 1,
C_PROBE386_MU_CNT => 1,
C_PROBE387_MU_CNT => 1,
C_PROBE388_MU_CNT => 1,
C_PROBE389_MU_CNT => 1,
C_PROBE390_MU_CNT => 1,
C_PROBE391_MU_CNT => 1,
C_PROBE392_MU_CNT => 1,
C_PROBE393_MU_CNT => 1,
C_PROBE394_MU_CNT => 1,
C_PROBE395_MU_CNT => 1,
C_PROBE396_MU_CNT => 1,
C_PROBE397_MU_CNT => 1,
C_PROBE398_MU_CNT => 1,
C_PROBE399_MU_CNT => 1,
C_PROBE400_MU_CNT => 1,
C_PROBE401_MU_CNT => 1,
C_PROBE402_MU_CNT => 1,
C_PROBE403_MU_CNT => 1,
C_PROBE404_MU_CNT => 1,
C_PROBE405_MU_CNT => 1,
C_PROBE406_MU_CNT => 1,
C_PROBE407_MU_CNT => 1,
C_PROBE408_MU_CNT => 1,
C_PROBE409_MU_CNT => 1,
C_PROBE410_MU_CNT => 1,
C_PROBE411_MU_CNT => 1,
C_PROBE412_MU_CNT => 1,
C_PROBE413_MU_CNT => 1,
C_PROBE414_MU_CNT => 1,
C_PROBE415_MU_CNT => 1,
C_PROBE416_MU_CNT => 1,
C_PROBE417_MU_CNT => 1,
C_PROBE418_MU_CNT => 1,
C_PROBE419_MU_CNT => 1,
C_PROBE420_MU_CNT => 1,
C_PROBE421_MU_CNT => 1,
C_PROBE422_MU_CNT => 1,
C_PROBE423_MU_CNT => 1,
C_PROBE424_MU_CNT => 1,
C_PROBE425_MU_CNT => 1,
C_PROBE426_MU_CNT => 1,
C_PROBE427_MU_CNT => 1,
C_PROBE428_MU_CNT => 1,
C_PROBE429_MU_CNT => 1,
C_PROBE430_MU_CNT => 1,
C_PROBE431_MU_CNT => 1,
C_PROBE432_MU_CNT => 1,
C_PROBE433_MU_CNT => 1,
C_PROBE434_MU_CNT => 1,
C_PROBE435_MU_CNT => 1,
C_PROBE436_MU_CNT => 1,
C_PROBE437_MU_CNT => 1,
C_PROBE438_MU_CNT => 1,
C_PROBE439_MU_CNT => 1,
C_PROBE440_MU_CNT => 1,
C_PROBE441_MU_CNT => 1,
C_PROBE442_MU_CNT => 1,
C_PROBE443_MU_CNT => 1,
C_PROBE444_MU_CNT => 1,
C_PROBE445_MU_CNT => 1,
C_PROBE446_MU_CNT => 1,
C_PROBE447_MU_CNT => 1,
C_PROBE448_MU_CNT => 1,
C_PROBE449_MU_CNT => 1,
C_PROBE450_MU_CNT => 1,
C_PROBE451_MU_CNT => 1,
C_PROBE452_MU_CNT => 1,
C_PROBE453_MU_CNT => 1,
C_PROBE454_MU_CNT => 1,
C_PROBE455_MU_CNT => 1,
C_PROBE456_MU_CNT => 1,
C_PROBE457_MU_CNT => 1,
C_PROBE458_MU_CNT => 1,
C_PROBE459_MU_CNT => 1,
C_PROBE460_MU_CNT => 1,
C_PROBE461_MU_CNT => 1,
C_PROBE462_MU_CNT => 1,
C_PROBE463_MU_CNT => 1,
C_PROBE464_MU_CNT => 1,
C_PROBE465_MU_CNT => 1,
C_PROBE466_MU_CNT => 1,
C_PROBE467_MU_CNT => 1,
C_PROBE468_MU_CNT => 1,
C_PROBE469_MU_CNT => 1,
C_PROBE470_MU_CNT => 1,
C_PROBE471_MU_CNT => 1,
C_PROBE472_MU_CNT => 1,
C_PROBE473_MU_CNT => 1,
C_PROBE474_MU_CNT => 1,
C_PROBE475_MU_CNT => 1,
C_PROBE476_MU_CNT => 1,
C_PROBE477_MU_CNT => 1,
C_PROBE478_MU_CNT => 1,
C_PROBE479_MU_CNT => 1,
C_PROBE480_MU_CNT => 1,
C_PROBE481_MU_CNT => 1,
C_PROBE482_MU_CNT => 1,
C_PROBE483_MU_CNT => 1,
C_PROBE484_MU_CNT => 1,
C_PROBE485_MU_CNT => 1,
C_PROBE486_MU_CNT => 1,
C_PROBE487_MU_CNT => 1,
C_PROBE488_MU_CNT => 1,
C_PROBE489_MU_CNT => 1,
C_PROBE490_MU_CNT => 1,
C_PROBE491_MU_CNT => 1,
C_PROBE492_MU_CNT => 1,
C_PROBE493_MU_CNT => 1,
C_PROBE494_MU_CNT => 1,
C_PROBE495_MU_CNT => 1,
C_PROBE496_MU_CNT => 1,
C_PROBE497_MU_CNT => 1,
C_PROBE498_MU_CNT => 1,
C_PROBE499_MU_CNT => 1,
C_PROBE500_MU_CNT => 1,
C_PROBE501_MU_CNT => 1,
C_PROBE502_MU_CNT => 1,
C_PROBE503_MU_CNT => 1,
C_PROBE504_MU_CNT => 1,
C_PROBE505_MU_CNT => 1,
C_PROBE506_MU_CNT => 1,
C_PROBE507_MU_CNT => 1,
C_PROBE508_MU_CNT => 1,
C_PROBE509_MU_CNT => 1,
C_PROBE510_MU_CNT => 1,
C_PROBE511_MU_CNT => 1,
C_PROBE512_MU_CNT => 1,
C_PROBE513_MU_CNT => 1,
C_PROBE514_MU_CNT => 1,
C_PROBE515_MU_CNT => 1,
C_PROBE516_MU_CNT => 1,
C_PROBE517_MU_CNT => 1,
C_PROBE518_MU_CNT => 1,
C_PROBE519_MU_CNT => 1,
C_PROBE520_MU_CNT => 1,
C_PROBE521_MU_CNT => 1,
C_PROBE522_MU_CNT => 1,
C_PROBE523_MU_CNT => 1,
C_PROBE524_MU_CNT => 1,
C_PROBE525_MU_CNT => 1,
C_PROBE526_MU_CNT => 1,
C_PROBE527_MU_CNT => 1,
C_PROBE528_MU_CNT => 1,
C_PROBE529_MU_CNT => 1,
C_PROBE530_MU_CNT => 1,
C_PROBE531_MU_CNT => 1,
C_PROBE532_MU_CNT => 1,
C_PROBE533_MU_CNT => 1,
C_PROBE534_MU_CNT => 1,
C_PROBE535_MU_CNT => 1,
C_PROBE536_MU_CNT => 1,
C_PROBE537_MU_CNT => 1,
C_PROBE538_MU_CNT => 1,
C_PROBE539_MU_CNT => 1,
C_PROBE540_MU_CNT => 1,
C_PROBE541_MU_CNT => 1,
C_PROBE542_MU_CNT => 1,
C_PROBE543_MU_CNT => 1,
C_PROBE544_MU_CNT => 1,
C_PROBE545_MU_CNT => 1,
C_PROBE546_MU_CNT => 1,
C_PROBE547_MU_CNT => 1,
C_PROBE548_MU_CNT => 1,
C_PROBE549_MU_CNT => 1,
C_PROBE550_MU_CNT => 1,
C_PROBE551_MU_CNT => 1,
C_PROBE552_MU_CNT => 1,
C_PROBE553_MU_CNT => 1,
C_PROBE554_MU_CNT => 1,
C_PROBE555_MU_CNT => 1,
C_PROBE556_MU_CNT => 1,
C_PROBE557_MU_CNT => 1,
C_PROBE558_MU_CNT => 1,
C_PROBE559_MU_CNT => 1,
C_PROBE560_MU_CNT => 1,
C_PROBE561_MU_CNT => 1,
C_PROBE562_MU_CNT => 1,
C_PROBE563_MU_CNT => 1,
C_PROBE564_MU_CNT => 1,
C_PROBE565_MU_CNT => 1,
C_PROBE566_MU_CNT => 1,
C_PROBE567_MU_CNT => 1,
C_PROBE568_MU_CNT => 1,
C_PROBE569_MU_CNT => 1,
C_PROBE570_MU_CNT => 1,
C_PROBE571_MU_CNT => 1,
C_PROBE572_MU_CNT => 1,
C_PROBE573_MU_CNT => 1,
C_PROBE574_MU_CNT => 1,
C_PROBE575_MU_CNT => 1,
C_PROBE576_MU_CNT => 1,
C_PROBE577_MU_CNT => 1,
C_PROBE578_MU_CNT => 1,
C_PROBE579_MU_CNT => 1,
C_PROBE580_MU_CNT => 1,
C_PROBE581_MU_CNT => 1,
C_PROBE582_MU_CNT => 1,
C_PROBE583_MU_CNT => 1,
C_PROBE584_MU_CNT => 1,
C_PROBE585_MU_CNT => 1,
C_PROBE586_MU_CNT => 1,
C_PROBE587_MU_CNT => 1,
C_PROBE588_MU_CNT => 1,
C_PROBE589_MU_CNT => 1,
C_PROBE590_MU_CNT => 1,
C_PROBE591_MU_CNT => 1,
C_PROBE592_MU_CNT => 1,
C_PROBE593_MU_CNT => 1,
C_PROBE594_MU_CNT => 1,
C_PROBE595_MU_CNT => 1,
C_PROBE596_MU_CNT => 1,
C_PROBE597_MU_CNT => 1,
C_PROBE598_MU_CNT => 1,
C_PROBE599_MU_CNT => 1,
C_PROBE600_MU_CNT => 1,
C_PROBE601_MU_CNT => 1,
C_PROBE602_MU_CNT => 1,
C_PROBE603_MU_CNT => 1,
C_PROBE604_MU_CNT => 1,
C_PROBE605_MU_CNT => 1,
C_PROBE606_MU_CNT => 1,
C_PROBE607_MU_CNT => 1,
C_PROBE608_MU_CNT => 1,
C_PROBE609_MU_CNT => 1,
C_PROBE610_MU_CNT => 1,
C_PROBE611_MU_CNT => 1,
C_PROBE612_MU_CNT => 1,
C_PROBE613_MU_CNT => 1,
C_PROBE614_MU_CNT => 1,
C_PROBE615_MU_CNT => 1,
C_PROBE616_MU_CNT => 1,
C_PROBE617_MU_CNT => 1,
C_PROBE618_MU_CNT => 1,
C_PROBE619_MU_CNT => 1,
C_PROBE620_MU_CNT => 1,
C_PROBE621_MU_CNT => 1,
C_PROBE622_MU_CNT => 1,
C_PROBE623_MU_CNT => 1,
C_PROBE624_MU_CNT => 1,
C_PROBE625_MU_CNT => 1,
C_PROBE626_MU_CNT => 1,
C_PROBE627_MU_CNT => 1,
C_PROBE628_MU_CNT => 1,
C_PROBE629_MU_CNT => 1,
C_PROBE630_MU_CNT => 1,
C_PROBE631_MU_CNT => 1,
C_PROBE632_MU_CNT => 1,
C_PROBE633_MU_CNT => 1,
C_PROBE634_MU_CNT => 1,
C_PROBE635_MU_CNT => 1,
C_PROBE636_MU_CNT => 1,
C_PROBE637_MU_CNT => 1,
C_PROBE638_MU_CNT => 1,
C_PROBE639_MU_CNT => 1,
C_PROBE640_MU_CNT => 1,
C_PROBE641_MU_CNT => 1,
C_PROBE642_MU_CNT => 1,
C_PROBE643_MU_CNT => 1,
C_PROBE644_MU_CNT => 1,
C_PROBE645_MU_CNT => 1,
C_PROBE646_MU_CNT => 1,
C_PROBE647_MU_CNT => 1,
C_PROBE648_MU_CNT => 1,
C_PROBE649_MU_CNT => 1,
C_PROBE650_MU_CNT => 1,
C_PROBE651_MU_CNT => 1,
C_PROBE652_MU_CNT => 1,
C_PROBE653_MU_CNT => 1,
C_PROBE654_MU_CNT => 1,
C_PROBE655_MU_CNT => 1,
C_PROBE656_MU_CNT => 1,
C_PROBE657_MU_CNT => 1,
C_PROBE658_MU_CNT => 1,
C_PROBE659_MU_CNT => 1,
C_PROBE660_MU_CNT => 1,
C_PROBE661_MU_CNT => 1,
C_PROBE662_MU_CNT => 1,
C_PROBE663_MU_CNT => 1,
C_PROBE664_MU_CNT => 1,
C_PROBE665_MU_CNT => 1,
C_PROBE666_MU_CNT => 1,
C_PROBE667_MU_CNT => 1,
C_PROBE668_MU_CNT => 1,
C_PROBE669_MU_CNT => 1,
C_PROBE670_MU_CNT => 1,
C_PROBE671_MU_CNT => 1,
C_PROBE672_MU_CNT => 1,
C_PROBE673_MU_CNT => 1,
C_PROBE674_MU_CNT => 1,
C_PROBE675_MU_CNT => 1,
C_PROBE676_MU_CNT => 1,
C_PROBE677_MU_CNT => 1,
C_PROBE678_MU_CNT => 1,
C_PROBE679_MU_CNT => 1,
C_PROBE680_MU_CNT => 1,
C_PROBE681_MU_CNT => 1,
C_PROBE682_MU_CNT => 1,
C_PROBE683_MU_CNT => 1,
C_PROBE684_MU_CNT => 1,
C_PROBE685_MU_CNT => 1,
C_PROBE686_MU_CNT => 1,
C_PROBE687_MU_CNT => 1,
C_PROBE688_MU_CNT => 1,
C_PROBE689_MU_CNT => 1,
C_PROBE690_MU_CNT => 1,
C_PROBE691_MU_CNT => 1,
C_PROBE692_MU_CNT => 1,
C_PROBE693_MU_CNT => 1,
C_PROBE694_MU_CNT => 1,
C_PROBE695_MU_CNT => 1,
C_PROBE696_MU_CNT => 1,
C_PROBE697_MU_CNT => 1,
C_PROBE698_MU_CNT => 1,
C_PROBE699_MU_CNT => 1,
C_PROBE700_MU_CNT => 1,
C_PROBE701_MU_CNT => 1,
C_PROBE702_MU_CNT => 1,
C_PROBE703_MU_CNT => 1,
C_PROBE704_MU_CNT => 1,
C_PROBE705_MU_CNT => 1,
C_PROBE706_MU_CNT => 1,
C_PROBE707_MU_CNT => 1,
C_PROBE708_MU_CNT => 1,
C_PROBE709_MU_CNT => 1,
C_PROBE710_MU_CNT => 1,
C_PROBE711_MU_CNT => 1,
C_PROBE712_MU_CNT => 1,
C_PROBE713_MU_CNT => 1,
C_PROBE714_MU_CNT => 1,
C_PROBE715_MU_CNT => 1,
C_PROBE716_MU_CNT => 1,
C_PROBE717_MU_CNT => 1,
C_PROBE718_MU_CNT => 1,
C_PROBE719_MU_CNT => 1,
C_PROBE720_MU_CNT => 1,
C_PROBE721_MU_CNT => 1,
C_PROBE722_MU_CNT => 1,
C_PROBE723_MU_CNT => 1,
C_PROBE724_MU_CNT => 1,
C_PROBE725_MU_CNT => 1,
C_PROBE726_MU_CNT => 1,
C_PROBE727_MU_CNT => 1,
C_PROBE728_MU_CNT => 1,
C_PROBE729_MU_CNT => 1,
C_PROBE730_MU_CNT => 1,
C_PROBE731_MU_CNT => 1,
C_PROBE732_MU_CNT => 1,
C_PROBE733_MU_CNT => 1,
C_PROBE734_MU_CNT => 1,
C_PROBE735_MU_CNT => 1,
C_PROBE736_MU_CNT => 1,
C_PROBE737_MU_CNT => 1,
C_PROBE738_MU_CNT => 1,
C_PROBE739_MU_CNT => 1,
C_PROBE740_MU_CNT => 1,
C_PROBE741_MU_CNT => 1,
C_PROBE742_MU_CNT => 1,
C_PROBE743_MU_CNT => 1,
C_PROBE744_MU_CNT => 1,
C_PROBE745_MU_CNT => 1,
C_PROBE746_MU_CNT => 1,
C_PROBE747_MU_CNT => 1,
C_PROBE748_MU_CNT => 1,
C_PROBE749_MU_CNT => 1,
C_PROBE750_MU_CNT => 1,
C_PROBE751_MU_CNT => 1,
C_PROBE752_MU_CNT => 1,
C_PROBE753_MU_CNT => 1,
C_PROBE754_MU_CNT => 1,
C_PROBE755_MU_CNT => 1,
C_PROBE756_MU_CNT => 1,
C_PROBE757_MU_CNT => 1,
C_PROBE758_MU_CNT => 1,
C_PROBE759_MU_CNT => 1,
C_PROBE760_MU_CNT => 1,
C_PROBE761_MU_CNT => 1,
C_PROBE762_MU_CNT => 1,
C_PROBE763_MU_CNT => 1,
C_PROBE764_MU_CNT => 1,
C_PROBE765_MU_CNT => 1,
C_PROBE766_MU_CNT => 1,
C_PROBE767_MU_CNT => 1,
C_PROBE768_MU_CNT => 1,
C_PROBE769_MU_CNT => 1,
C_PROBE770_MU_CNT => 1,
C_PROBE771_MU_CNT => 1,
C_PROBE772_MU_CNT => 1,
C_PROBE773_MU_CNT => 1,
C_PROBE774_MU_CNT => 1,
C_PROBE775_MU_CNT => 1,
C_PROBE776_MU_CNT => 1,
C_PROBE777_MU_CNT => 1,
C_PROBE778_MU_CNT => 1,
C_PROBE779_MU_CNT => 1,
C_PROBE780_MU_CNT => 1,
C_PROBE781_MU_CNT => 1,
C_PROBE782_MU_CNT => 1,
C_PROBE783_MU_CNT => 1,
C_PROBE784_MU_CNT => 1,
C_PROBE785_MU_CNT => 1,
C_PROBE786_MU_CNT => 1,
C_PROBE787_MU_CNT => 1,
C_PROBE788_MU_CNT => 1,
C_PROBE789_MU_CNT => 1,
C_PROBE790_MU_CNT => 1,
C_PROBE791_MU_CNT => 1,
C_PROBE792_MU_CNT => 1,
C_PROBE793_MU_CNT => 1,
C_PROBE794_MU_CNT => 1,
C_PROBE795_MU_CNT => 1,
C_PROBE796_MU_CNT => 1,
C_PROBE797_MU_CNT => 1,
C_PROBE798_MU_CNT => 1,
C_PROBE799_MU_CNT => 1,
C_PROBE800_MU_CNT => 1,
C_PROBE801_MU_CNT => 1,
C_PROBE802_MU_CNT => 1,
C_PROBE803_MU_CNT => 1,
C_PROBE804_MU_CNT => 1,
C_PROBE805_MU_CNT => 1,
C_PROBE806_MU_CNT => 1,
C_PROBE807_MU_CNT => 1,
C_PROBE808_MU_CNT => 1,
C_PROBE809_MU_CNT => 1,
C_PROBE810_MU_CNT => 1,
C_PROBE811_MU_CNT => 1,
C_PROBE812_MU_CNT => 1,
C_PROBE813_MU_CNT => 1,
C_PROBE814_MU_CNT => 1,
C_PROBE815_MU_CNT => 1,
C_PROBE816_MU_CNT => 1,
C_PROBE817_MU_CNT => 1,
C_PROBE818_MU_CNT => 1,
C_PROBE819_MU_CNT => 1,
C_PROBE820_MU_CNT => 1,
C_PROBE821_MU_CNT => 1,
C_PROBE822_MU_CNT => 1,
C_PROBE823_MU_CNT => 1,
C_PROBE824_MU_CNT => 1,
C_PROBE825_MU_CNT => 1,
C_PROBE826_MU_CNT => 1,
C_PROBE827_MU_CNT => 1,
C_PROBE828_MU_CNT => 1,
C_PROBE829_MU_CNT => 1,
C_PROBE830_MU_CNT => 1,
C_PROBE831_MU_CNT => 1,
C_PROBE832_MU_CNT => 1,
C_PROBE833_MU_CNT => 1,
C_PROBE834_MU_CNT => 1,
C_PROBE835_MU_CNT => 1,
C_PROBE836_MU_CNT => 1,
C_PROBE837_MU_CNT => 1,
C_PROBE838_MU_CNT => 1,
C_PROBE839_MU_CNT => 1,
C_PROBE840_MU_CNT => 1,
C_PROBE841_MU_CNT => 1,
C_PROBE842_MU_CNT => 1,
C_PROBE843_MU_CNT => 1,
C_PROBE844_MU_CNT => 1,
C_PROBE845_MU_CNT => 1,
C_PROBE846_MU_CNT => 1,
C_PROBE847_MU_CNT => 1,
C_PROBE848_MU_CNT => 1,
C_PROBE849_MU_CNT => 1,
C_PROBE850_MU_CNT => 1,
C_PROBE851_MU_CNT => 1,
C_PROBE852_MU_CNT => 1,
C_PROBE853_MU_CNT => 1,
C_PROBE854_MU_CNT => 1,
C_PROBE855_MU_CNT => 1,
C_PROBE856_MU_CNT => 1,
C_PROBE857_MU_CNT => 1,
C_PROBE858_MU_CNT => 1,
C_PROBE859_MU_CNT => 1,
C_PROBE860_MU_CNT => 1,
C_PROBE861_MU_CNT => 1,
C_PROBE862_MU_CNT => 1,
C_PROBE863_MU_CNT => 1,
C_PROBE864_MU_CNT => 1,
C_PROBE865_MU_CNT => 1,
C_PROBE866_MU_CNT => 1,
C_PROBE867_MU_CNT => 1,
C_PROBE868_MU_CNT => 1,
C_PROBE869_MU_CNT => 1,
C_PROBE870_MU_CNT => 1,
C_PROBE871_MU_CNT => 1,
C_PROBE872_MU_CNT => 1,
C_PROBE873_MU_CNT => 1,
C_PROBE874_MU_CNT => 1,
C_PROBE875_MU_CNT => 1,
C_PROBE876_MU_CNT => 1,
C_PROBE877_MU_CNT => 1,
C_PROBE878_MU_CNT => 1,
C_PROBE879_MU_CNT => 1,
C_PROBE880_MU_CNT => 1,
C_PROBE881_MU_CNT => 1,
C_PROBE882_MU_CNT => 1,
C_PROBE883_MU_CNT => 1,
C_PROBE884_MU_CNT => 1,
C_PROBE885_MU_CNT => 1,
C_PROBE886_MU_CNT => 1,
C_PROBE887_MU_CNT => 1,
C_PROBE888_MU_CNT => 1,
C_PROBE889_MU_CNT => 1,
C_PROBE890_MU_CNT => 1,
C_PROBE891_MU_CNT => 1,
C_PROBE892_MU_CNT => 1,
C_PROBE893_MU_CNT => 1,
C_PROBE894_MU_CNT => 1,
C_PROBE895_MU_CNT => 1,
C_PROBE896_MU_CNT => 1,
C_PROBE897_MU_CNT => 1,
C_PROBE898_MU_CNT => 1,
C_PROBE899_MU_CNT => 1,
C_PROBE900_MU_CNT => 1,
C_PROBE901_MU_CNT => 1,
C_PROBE902_MU_CNT => 1,
C_PROBE903_MU_CNT => 1,
C_PROBE904_MU_CNT => 1,
C_PROBE905_MU_CNT => 1,
C_PROBE906_MU_CNT => 1,
C_PROBE907_MU_CNT => 1,
C_PROBE908_MU_CNT => 1,
C_PROBE909_MU_CNT => 1,
C_PROBE910_MU_CNT => 1,
C_PROBE911_MU_CNT => 1,
C_PROBE912_MU_CNT => 1,
C_PROBE913_MU_CNT => 1,
C_PROBE914_MU_CNT => 1,
C_PROBE915_MU_CNT => 1,
C_PROBE916_MU_CNT => 1,
C_PROBE917_MU_CNT => 1,
C_PROBE918_MU_CNT => 1,
C_PROBE919_MU_CNT => 1,
C_PROBE920_MU_CNT => 1,
C_PROBE921_MU_CNT => 1,
C_PROBE922_MU_CNT => 1,
C_PROBE923_MU_CNT => 1,
C_PROBE924_MU_CNT => 1,
C_PROBE925_MU_CNT => 1,
C_PROBE926_MU_CNT => 1,
C_PROBE927_MU_CNT => 1,
C_PROBE928_MU_CNT => 1,
C_PROBE929_MU_CNT => 1,
C_PROBE930_MU_CNT => 1,
C_PROBE931_MU_CNT => 1,
C_PROBE932_MU_CNT => 1,
C_PROBE933_MU_CNT => 1,
C_PROBE934_MU_CNT => 1,
C_PROBE935_MU_CNT => 1,
C_PROBE936_MU_CNT => 1,
C_PROBE937_MU_CNT => 1,
C_PROBE938_MU_CNT => 1,
C_PROBE939_MU_CNT => 1,
C_PROBE940_MU_CNT => 1,
C_PROBE941_MU_CNT => 1,
C_PROBE942_MU_CNT => 1,
C_PROBE943_MU_CNT => 1,
C_PROBE944_MU_CNT => 1,
C_PROBE945_MU_CNT => 1,
C_PROBE946_MU_CNT => 1,
C_PROBE947_MU_CNT => 1,
C_PROBE948_MU_CNT => 1,
C_PROBE949_MU_CNT => 1,
C_PROBE950_MU_CNT => 1,
C_PROBE951_MU_CNT => 1,
C_PROBE952_MU_CNT => 1,
C_PROBE953_MU_CNT => 1,
C_PROBE954_MU_CNT => 1,
C_PROBE955_MU_CNT => 1,
C_PROBE956_MU_CNT => 1,
C_PROBE957_MU_CNT => 1,
C_PROBE958_MU_CNT => 1,
C_PROBE959_MU_CNT => 1,
C_PROBE960_MU_CNT => 1,
C_PROBE961_MU_CNT => 1,
C_PROBE962_MU_CNT => 1,
C_PROBE963_MU_CNT => 1,
C_PROBE964_MU_CNT => 1,
C_PROBE965_MU_CNT => 1,
C_PROBE966_MU_CNT => 1,
C_PROBE967_MU_CNT => 1,
C_PROBE968_MU_CNT => 1,
C_PROBE969_MU_CNT => 1,
C_PROBE970_MU_CNT => 1,
C_PROBE971_MU_CNT => 1,
C_PROBE972_MU_CNT => 1,
C_PROBE973_MU_CNT => 1,
C_PROBE974_MU_CNT => 1,
C_PROBE975_MU_CNT => 1,
C_PROBE976_MU_CNT => 1,
C_PROBE977_MU_CNT => 1,
C_PROBE978_MU_CNT => 1,
C_PROBE979_MU_CNT => 1,
C_PROBE980_MU_CNT => 1,
C_PROBE981_MU_CNT => 1,
C_PROBE982_MU_CNT => 1,
C_PROBE983_MU_CNT => 1,
C_PROBE984_MU_CNT => 1,
C_PROBE985_MU_CNT => 1,
C_PROBE986_MU_CNT => 1,
C_PROBE987_MU_CNT => 1,
C_PROBE988_MU_CNT => 1,
C_PROBE989_MU_CNT => 1,
C_PROBE990_MU_CNT => 1,
C_PROBE991_MU_CNT => 1,
C_PROBE992_MU_CNT => 1,
C_PROBE993_MU_CNT => 1,
C_PROBE994_MU_CNT => 1,
C_PROBE995_MU_CNT => 1,
C_PROBE996_MU_CNT => 1,
C_PROBE997_MU_CNT => 1,
C_PROBE998_MU_CNT => 1,
C_PROBE999_MU_CNT => 1,
C_PROBE1000_MU_CNT => 1,
C_PROBE1001_MU_CNT => 1,
C_PROBE1002_MU_CNT => 1,
C_PROBE1003_MU_CNT => 1,
C_PROBE1004_MU_CNT => 1,
C_PROBE1005_MU_CNT => 1,
C_PROBE1006_MU_CNT => 1,
C_PROBE1007_MU_CNT => 1,
C_PROBE1008_MU_CNT => 1,
C_PROBE1009_MU_CNT => 1,
C_PROBE1010_MU_CNT => 1,
C_PROBE1011_MU_CNT => 1,
C_PROBE1012_MU_CNT => 1,
C_PROBE1013_MU_CNT => 1,
C_PROBE1014_MU_CNT => 1,
C_PROBE1015_MU_CNT => 1,
C_PROBE1016_MU_CNT => 1,
C_PROBE1017_MU_CNT => 1,
C_PROBE1018_MU_CNT => 1,
C_PROBE1019_MU_CNT => 1,
C_PROBE1020_MU_CNT => 1,
C_PROBE1021_MU_CNT => 1,
C_PROBE1022_MU_CNT => 1,
C_PROBE1023_MU_CNT => 1,
C_PROBE0_TYPE => 0,
C_PROBE1_TYPE => 1,
C_PROBE2_TYPE => 0,
C_PROBE3_TYPE => 1,
C_PROBE4_TYPE => 1,
C_PROBE5_TYPE => 1,
C_PROBE6_TYPE => 1,
C_PROBE7_TYPE => 1,
C_PROBE8_TYPE => 1,
C_PROBE9_TYPE => 1,
C_PROBE10_TYPE => 1,
C_PROBE11_TYPE => 1,
C_PROBE12_TYPE => 1,
C_PROBE13_TYPE => 1,
C_PROBE14_TYPE => 1,
C_PROBE15_TYPE => 1,
C_PROBE16_TYPE => 1,
C_PROBE17_TYPE => 1,
C_PROBE18_TYPE => 1,
C_PROBE19_TYPE => 1,
C_PROBE20_TYPE => 1,
C_PROBE21_TYPE => 1,
C_PROBE22_TYPE => 1,
C_PROBE23_TYPE => 1,
C_PROBE24_TYPE => 1,
C_PROBE25_TYPE => 1,
C_PROBE26_TYPE => 1,
C_PROBE27_TYPE => 1,
C_PROBE28_TYPE => 1,
C_PROBE29_TYPE => 1,
C_PROBE30_TYPE => 1,
C_PROBE31_TYPE => 1,
C_PROBE32_TYPE => 1,
C_PROBE33_TYPE => 1,
C_PROBE34_TYPE => 1,
C_PROBE35_TYPE => 1,
C_PROBE36_TYPE => 1,
C_PROBE37_TYPE => 1,
C_PROBE38_TYPE => 1,
C_PROBE39_TYPE => 1,
C_PROBE40_TYPE => 1,
C_PROBE41_TYPE => 1,
C_PROBE42_TYPE => 1,
C_PROBE43_TYPE => 1,
C_PROBE44_TYPE => 1,
C_PROBE45_TYPE => 1,
C_PROBE46_TYPE => 1,
C_PROBE47_TYPE => 1,
C_PROBE48_TYPE => 1,
C_PROBE49_TYPE => 1,
C_PROBE50_TYPE => 1,
C_PROBE51_TYPE => 1,
C_PROBE52_TYPE => 1,
C_PROBE53_TYPE => 1,
C_PROBE54_TYPE => 1,
C_PROBE55_TYPE => 1,
C_PROBE56_TYPE => 1,
C_PROBE57_TYPE => 1,
C_PROBE58_TYPE => 1,
C_PROBE59_TYPE => 1,
C_PROBE60_TYPE => 1,
C_PROBE61_TYPE => 1,
C_PROBE62_TYPE => 1,
C_PROBE63_TYPE => 1,
C_PROBE64_TYPE => 1,
C_PROBE65_TYPE => 1,
C_PROBE66_TYPE => 1,
C_PROBE67_TYPE => 1,
C_PROBE68_TYPE => 1,
C_PROBE69_TYPE => 1,
C_PROBE70_TYPE => 1,
C_PROBE71_TYPE => 1,
C_PROBE72_TYPE => 1,
C_PROBE73_TYPE => 1,
C_PROBE74_TYPE => 1,
C_PROBE75_TYPE => 1,
C_PROBE76_TYPE => 1,
C_PROBE77_TYPE => 1,
C_PROBE78_TYPE => 1,
C_PROBE79_TYPE => 1,
C_PROBE80_TYPE => 1,
C_PROBE81_TYPE => 1,
C_PROBE82_TYPE => 1,
C_PROBE83_TYPE => 1,
C_PROBE84_TYPE => 1,
C_PROBE85_TYPE => 1,
C_PROBE86_TYPE => 1,
C_PROBE87_TYPE => 1,
C_PROBE88_TYPE => 1,
C_PROBE89_TYPE => 1,
C_PROBE90_TYPE => 1,
C_PROBE91_TYPE => 1,
C_PROBE92_TYPE => 1,
C_PROBE93_TYPE => 1,
C_PROBE94_TYPE => 1,
C_PROBE95_TYPE => 1,
C_PROBE96_TYPE => 1,
C_PROBE97_TYPE => 1,
C_PROBE98_TYPE => 1,
C_PROBE99_TYPE => 1,
C_PROBE100_TYPE => 1,
C_PROBE101_TYPE => 1,
C_PROBE102_TYPE => 1,
C_PROBE103_TYPE => 1,
C_PROBE104_TYPE => 1,
C_PROBE105_TYPE => 1,
C_PROBE106_TYPE => 1,
C_PROBE107_TYPE => 1,
C_PROBE108_TYPE => 1,
C_PROBE109_TYPE => 1,
C_PROBE110_TYPE => 1,
C_PROBE111_TYPE => 1,
C_PROBE112_TYPE => 1,
C_PROBE113_TYPE => 1,
C_PROBE114_TYPE => 1,
C_PROBE115_TYPE => 1,
C_PROBE116_TYPE => 1,
C_PROBE117_TYPE => 1,
C_PROBE118_TYPE => 1,
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C_PROBE120_TYPE => 1,
C_PROBE121_TYPE => 1,
C_PROBE122_TYPE => 1,
C_PROBE123_TYPE => 1,
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C_PROBE125_TYPE => 1,
C_PROBE126_TYPE => 1,
C_PROBE127_TYPE => 1,
C_PROBE128_TYPE => 1,
C_PROBE129_TYPE => 1,
C_PROBE130_TYPE => 1,
C_PROBE131_TYPE => 1,
C_PROBE132_TYPE => 1,
C_PROBE133_TYPE => 1,
C_PROBE134_TYPE => 1,
C_PROBE135_TYPE => 1,
C_PROBE136_TYPE => 1,
C_PROBE137_TYPE => 1,
C_PROBE138_TYPE => 1,
C_PROBE139_TYPE => 1,
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C_PROBE141_TYPE => 1,
C_PROBE142_TYPE => 1,
C_PROBE143_TYPE => 1,
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C_PROBE147_TYPE => 1,
C_PROBE148_TYPE => 1,
C_PROBE149_TYPE => 1,
C_PROBE150_TYPE => 1,
C_PROBE151_TYPE => 1,
C_PROBE152_TYPE => 1,
C_PROBE153_TYPE => 1,
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C_PROBE155_TYPE => 1,
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C_PROBE157_TYPE => 1,
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C_PROBE922_TYPE => 1,
C_PROBE923_TYPE => 1,
C_PROBE924_TYPE => 1,
C_PROBE925_TYPE => 1,
C_PROBE926_TYPE => 1,
C_PROBE927_TYPE => 1,
C_PROBE928_TYPE => 1,
C_PROBE929_TYPE => 1,
C_PROBE930_TYPE => 1,
C_PROBE931_TYPE => 1,
C_PROBE932_TYPE => 1,
C_PROBE933_TYPE => 1,
C_PROBE934_TYPE => 1,
C_PROBE935_TYPE => 1,
C_PROBE936_TYPE => 1,
C_PROBE937_TYPE => 1,
C_PROBE938_TYPE => 1,
C_PROBE939_TYPE => 1,
C_PROBE940_TYPE => 1,
C_PROBE941_TYPE => 1,
C_PROBE942_TYPE => 1,
C_PROBE943_TYPE => 1,
C_PROBE944_TYPE => 1,
C_PROBE945_TYPE => 1,
C_PROBE946_TYPE => 1,
C_PROBE947_TYPE => 1,
C_PROBE948_TYPE => 1,
C_PROBE949_TYPE => 1,
C_PROBE950_TYPE => 1,
C_PROBE951_TYPE => 1,
C_PROBE952_TYPE => 1,
C_PROBE953_TYPE => 1,
C_PROBE954_TYPE => 1,
C_PROBE955_TYPE => 1,
C_PROBE956_TYPE => 1,
C_PROBE957_TYPE => 1,
C_PROBE958_TYPE => 1,
C_PROBE959_TYPE => 1,
C_PROBE960_TYPE => 1,
C_PROBE961_TYPE => 1,
C_PROBE962_TYPE => 1,
C_PROBE963_TYPE => 1,
C_PROBE964_TYPE => 1,
C_PROBE965_TYPE => 1,
C_PROBE966_TYPE => 1,
C_PROBE967_TYPE => 1,
C_PROBE968_TYPE => 1,
C_PROBE969_TYPE => 1,
C_PROBE970_TYPE => 1,
C_PROBE971_TYPE => 1,
C_PROBE972_TYPE => 1,
C_PROBE973_TYPE => 1,
C_PROBE974_TYPE => 1,
C_PROBE975_TYPE => 1,
C_PROBE976_TYPE => 1,
C_PROBE977_TYPE => 1,
C_PROBE978_TYPE => 1,
C_PROBE979_TYPE => 1,
C_PROBE980_TYPE => 1,
C_PROBE981_TYPE => 1,
C_PROBE982_TYPE => 1,
C_PROBE983_TYPE => 1,
C_PROBE984_TYPE => 1,
C_PROBE985_TYPE => 1,
C_PROBE986_TYPE => 1,
C_PROBE987_TYPE => 1,
C_PROBE988_TYPE => 1,
C_PROBE989_TYPE => 1,
C_PROBE990_TYPE => 1,
C_PROBE991_TYPE => 1,
C_PROBE992_TYPE => 1,
C_PROBE993_TYPE => 1,
C_PROBE994_TYPE => 1,
C_PROBE995_TYPE => 1,
C_PROBE996_TYPE => 1,
C_PROBE997_TYPE => 1,
C_PROBE998_TYPE => 1,
C_PROBE999_TYPE => 1,
C_PROBE1000_TYPE => 1,
C_PROBE1001_TYPE => 1,
C_PROBE1002_TYPE => 1,
C_PROBE1003_TYPE => 1,
C_PROBE1004_TYPE => 1,
C_PROBE1005_TYPE => 1,
C_PROBE1006_TYPE => 1,
C_PROBE1007_TYPE => 1,
C_PROBE1008_TYPE => 1,
C_PROBE1009_TYPE => 1,
C_PROBE1010_TYPE => 1,
C_PROBE1011_TYPE => 1,
C_PROBE1012_TYPE => 1,
C_PROBE1013_TYPE => 1,
C_PROBE1014_TYPE => 1,
C_PROBE1015_TYPE => 1,
C_PROBE1016_TYPE => 1,
C_PROBE1017_TYPE => 1,
C_PROBE1018_TYPE => 1,
C_PROBE1019_TYPE => 1,
C_PROBE1020_TYPE => 1,
C_PROBE1021_TYPE => 1,
C_PROBE1022_TYPE => 1,
C_PROBE1023_TYPE => 1
)
PORT MAP (
clk => clk,
sl_iport0 => sl_iport0,
sl_oport0 => sl_oport0,
trig_out => open,
trig_out_ack => '0',
trig_in => '0',
trig_in_ack => open,
probe0 => probe0,
probe1 => probe1,
probe2 => probe2,
probe3 => probe3,
probe4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe32 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe33 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe34 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe35 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe36 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe37 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe38 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe39 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe40 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe41 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe42 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe43 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe44 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe45 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe46 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe47 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe48 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe49 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe50 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe51 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe52 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe53 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe54 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe55 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe56 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe57 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe58 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe59 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe60 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe61 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe62 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe63 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe64 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe65 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe66 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe67 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe68 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe69 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe70 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe71 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe72 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe73 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe74 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe75 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe76 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe77 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe78 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe79 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe80 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe81 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe82 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe83 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe84 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe85 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe86 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe87 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe88 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe89 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe90 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe91 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe92 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe93 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe94 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe95 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe96 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe97 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe98 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe99 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe100 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe101 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe102 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe103 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe104 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe105 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe106 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe107 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe108 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe109 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe110 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe111 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe112 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe113 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe114 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe115 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe116 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe117 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe118 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe119 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe120 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe121 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe122 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe123 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe124 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe125 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe126 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe127 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe128 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe129 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe130 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe131 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe132 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe133 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe134 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe135 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe136 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe137 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe138 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe139 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe140 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe141 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe142 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe143 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe144 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe145 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe146 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe147 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe148 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe149 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe150 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe151 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe152 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe153 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe154 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe155 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe156 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe157 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe158 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe159 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe160 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe161 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe162 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe163 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe164 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe165 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe166 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe167 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe168 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe169 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe170 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe171 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe172 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe173 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe174 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe175 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe176 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe177 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe178 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe179 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe180 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe181 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe182 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe183 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe184 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe185 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe186 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe187 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe188 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe189 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe190 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe191 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe192 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe193 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe194 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe195 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe196 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe197 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe198 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe199 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe200 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe201 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe202 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe203 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe204 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe205 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe206 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe207 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe208 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe209 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe210 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe211 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe212 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe213 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe214 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe215 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe216 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe217 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe218 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe219 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe220 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe221 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe222 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe223 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe224 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe225 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe226 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe227 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe228 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe229 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe230 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe231 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe232 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe233 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe234 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe235 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe236 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe237 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe238 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe239 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe240 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe241 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe242 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe243 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe244 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe245 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe246 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe247 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe248 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe249 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe250 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe251 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe252 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe253 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe254 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe255 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe256 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe257 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe258 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe259 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe260 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe261 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe262 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe263 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe264 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe265 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe266 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe267 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe268 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe269 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe270 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe271 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe272 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe273 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe274 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe275 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe276 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe277 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe278 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe279 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe280 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe281 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe282 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe283 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe284 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe285 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe286 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe287 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe288 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe289 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe290 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe291 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe292 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe293 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe294 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe295 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe296 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe297 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe298 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe299 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe300 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe301 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe302 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe303 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe304 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe305 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe306 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe307 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe308 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe309 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe310 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe311 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe312 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe313 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe314 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe315 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe316 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe317 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe318 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe319 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe320 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe321 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe322 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe323 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe324 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe325 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe326 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe327 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe328 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe329 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe330 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe331 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe332 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe333 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe334 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe335 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe336 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe337 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe338 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe339 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe340 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe341 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe342 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe343 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe344 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe345 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe346 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe347 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe348 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe349 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe350 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe351 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe352 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe353 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe354 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe355 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe356 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe357 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe358 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe359 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe360 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe361 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe362 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe363 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe364 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe365 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe366 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe367 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe368 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe369 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe370 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe371 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe372 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe373 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe374 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe375 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe376 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe377 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe378 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe379 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe380 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe381 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe382 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe383 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe384 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe385 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe386 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe387 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe388 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe389 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe390 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe391 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe392 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe393 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe394 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe395 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe396 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe397 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe398 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe399 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe400 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe401 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe402 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe403 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe404 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe405 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe406 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe407 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe408 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe409 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe410 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe411 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe412 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe413 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe414 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe415 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe416 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe417 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe418 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe419 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe420 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe421 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe422 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe423 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe424 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe425 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe426 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe427 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe428 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe429 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe430 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe431 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe432 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe433 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe434 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe435 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe436 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe437 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe438 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe439 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe440 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe441 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe442 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe443 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe444 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe445 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe446 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe447 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe448 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe449 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe450 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe451 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe452 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe453 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe454 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe455 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe456 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe457 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe458 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe459 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe460 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe461 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe462 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe463 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe464 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe465 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe466 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe467 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe468 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe469 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe470 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe471 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe472 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe473 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe474 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe475 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe476 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe477 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe478 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe479 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe480 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe481 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe482 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe483 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe484 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe485 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe486 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe487 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe488 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe489 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe490 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe491 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe492 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe493 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe494 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe495 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe496 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe497 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe498 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe499 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe500 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe501 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe502 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe503 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe504 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe505 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe506 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe507 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe508 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe509 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe510 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe511 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe512 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe513 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe514 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe515 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe516 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe517 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe518 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe519 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe520 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe521 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe522 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe523 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe524 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe525 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe526 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe527 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe528 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe529 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe530 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe531 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe532 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe533 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe534 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe535 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe536 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe537 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe538 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe539 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe540 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe541 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe542 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe543 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe544 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe545 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe546 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe547 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe548 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe549 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe550 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe551 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe552 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe553 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe554 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe555 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe556 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe557 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe558 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe559 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe560 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe561 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe562 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe563 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe564 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe565 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe566 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe567 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe568 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe569 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe570 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe571 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe572 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe573 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe574 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe575 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe576 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe577 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe578 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe579 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe580 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe581 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe582 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe583 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe584 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe585 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe586 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe587 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe588 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe589 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe590 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe591 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe592 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe593 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe594 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe595 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe596 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe597 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe598 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe599 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe600 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe601 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe602 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe603 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe604 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe605 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe606 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe607 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe608 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe609 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe610 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe611 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe612 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe613 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe614 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe615 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe616 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe617 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe618 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe619 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe620 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe621 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe622 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe623 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe624 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe625 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe626 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe627 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe628 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe629 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe630 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe631 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe632 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe633 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe634 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe635 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe636 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe637 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe638 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe639 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe640 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe641 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe642 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe643 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe644 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe645 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe646 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe647 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe648 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe649 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe650 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe651 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe652 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe653 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe654 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe655 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe656 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe657 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe658 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe659 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe660 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe661 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe662 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe663 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe664 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe665 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe666 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe667 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe668 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe669 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe670 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe671 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe672 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe673 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe674 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe675 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe676 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe677 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe678 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe679 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe680 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe681 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe682 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe683 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe684 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe685 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe686 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe687 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe688 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe689 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe690 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe691 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe692 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe693 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe694 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe695 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe696 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe697 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe698 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe699 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe700 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe701 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe702 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe703 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe704 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe705 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe706 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe707 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe708 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe709 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe710 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe711 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe712 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe713 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe714 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe715 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe716 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe717 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe718 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe719 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe720 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe721 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe722 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe723 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe724 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe725 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe726 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe727 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe728 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe729 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe730 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe731 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe732 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe733 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe734 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe735 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe736 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe737 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe738 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe739 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe740 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe741 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe742 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe743 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe744 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe745 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe746 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe747 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe748 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe749 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe750 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe751 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe752 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe753 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe754 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe755 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe756 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe757 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe758 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe759 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe760 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe761 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe762 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe763 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe764 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe765 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe766 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe767 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe768 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe769 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe770 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe771 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe772 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe773 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe774 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe775 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe776 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe777 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe778 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe779 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe780 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe781 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe782 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe783 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe784 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe785 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe786 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe787 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe788 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe789 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe790 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe791 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe792 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe793 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe794 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe795 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe796 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe797 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe798 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe799 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe800 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe801 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe802 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe803 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe804 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe805 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe806 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe807 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe808 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe809 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe810 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe811 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe812 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe813 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe814 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe815 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe816 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe817 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe818 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe819 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe820 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe821 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe822 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe823 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe824 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe825 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe826 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe827 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe828 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe829 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe830 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe831 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe832 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe833 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe834 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe835 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe836 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe837 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe838 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe839 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe840 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe841 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe842 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe843 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe844 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe845 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe846 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe847 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe848 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe849 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe850 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe851 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe852 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe853 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe854 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe855 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe856 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe857 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe858 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe859 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe860 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe861 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe862 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe863 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe864 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe865 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe866 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe867 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe868 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe869 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe870 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe871 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe872 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe873 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe874 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe875 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe876 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe877 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe878 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe879 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe880 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe881 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe882 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe883 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe884 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe885 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe886 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe887 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe888 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe889 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe890 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe891 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe892 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe893 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe894 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe895 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe896 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe897 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe898 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe899 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe900 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe901 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe902 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe903 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe904 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe905 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe906 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe907 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe908 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe909 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe910 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe911 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe912 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe913 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe914 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe915 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe916 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe917 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe918 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe919 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe920 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe921 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe922 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe923 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe924 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe925 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe926 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe927 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe928 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe929 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe930 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe931 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe932 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe933 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe934 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe935 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe936 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe937 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe938 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe939 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe940 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe941 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe942 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe943 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe944 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe945 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe946 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe947 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe948 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe949 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe950 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe951 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe952 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe953 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe954 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe955 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe956 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe957 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe958 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe959 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe960 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe961 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe962 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe963 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe964 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe965 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe966 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe967 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe968 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe969 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe970 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe971 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe972 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe973 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe974 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe975 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe976 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe977 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe978 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe979 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe980 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe981 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe982 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe983 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe984 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe985 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe986 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe987 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe988 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe989 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe990 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe991 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe992 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe993 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe994 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe995 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe996 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe997 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe998 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe999 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1000 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1001 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1002 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1003 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1004 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1005 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1006 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1007 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1008 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1009 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1010 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1011 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1012 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1013 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1014 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1015 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1016 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1017 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1018 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1019 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1020 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1021 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1022 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1023 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1))
);
END DemoInterconnect_ila_0_0_arch;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ipshared/c931/src/internoc_ni_type_map.vhd
|
2
|
3501
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/16/2017 07:50:07 PM
-- Design Name:
-- Module Name: internoc_ni_type_map - behave
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.internoc_pack.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity internoc_interface_type_map is
Port (
clk_i : in STD_LOGIC;
addr_i : in STD_LOGIC_VECTOR (4 downto 0);
type_o : out STD_LOGIC_VECTOR (2 downto 0);
mode_o : out STD_LOGIC
);
end internoc_interface_type_map;
architecture behave of internoc_interface_type_map is
constant INTERFACE_MAP_ROM : INTERFACE_MAP_T := (
("00000", SLAVE_MODE, I2C_INTERFACE), --1
("00001", SLAVE_MODE, SPI_INTERFACE), --2
("00010", SLAVE_MODE, INVALID_INTERFACE), --3
("00011", SLAVE_MODE, INVALID_INTERFACE), --4
("00100", SLAVE_MODE, INVALID_INTERFACE), --5
("00101", SLAVE_MODE, INVALID_INTERFACE), --6
("00110", SLAVE_MODE, INVALID_INTERFACE), --7
("00111", SLAVE_MODE, INVALID_INTERFACE), --8
("01000", SLAVE_MODE, INVALID_INTERFACE), --9
("01001", SLAVE_MODE, INVALID_INTERFACE), --10
("01010", SLAVE_MODE, INVALID_INTERFACE), --11
("01011", SLAVE_MODE, INVALID_INTERFACE), --12
("01100", SLAVE_MODE, INVALID_INTERFACE), --13
("01101", SLAVE_MODE, INVALID_INTERFACE), --14
("01110", SLAVE_MODE, INVALID_INTERFACE), --15
("01111", SLAVE_MODE, INVALID_INTERFACE), --16
("10000", MASTER_MODE, UART_INTERFACE), --17
("10001", MASTER_MODE, UART_INTERFACE), --18
("10010", MASTER_MODE, INVALID_INTERFACE), --19
("10011", MASTER_MODE, INVALID_INTERFACE), --20
("10100", MASTER_MODE, INVALID_INTERFACE), --21
("10101", MASTER_MODE, INVALID_INTERFACE), --22
("10110", MASTER_MODE, INVALID_INTERFACE), --23
("10111", MASTER_MODE, INVALID_INTERFACE), --24
("11000", MASTER_MODE, INVALID_INTERFACE), --25
("11001", MASTER_MODE, INVALID_INTERFACE), --26
("11010", MASTER_MODE, INVALID_INTERFACE), --27
("11011", MASTER_MODE, INVALID_INTERFACE), --28
("11100", MASTER_MODE, INVALID_INTERFACE), --29
("11101", MASTER_MODE, INVALID_INTERFACE), --30
("11110", MASTER_MODE, INVALID_INTERFACE), --31
("11111", MASTER_MODE, INVALID_INTERFACE) --32
);
signal interface_type : std_logic_vector(2 downto 0) := (others=>'1');
signal interface_mode : std_logic := '0';
begin
type_o <= interface_type;
mode_o <= interface_mode;
rom_p: process(clk_i)
begin
if rising_edge(clk_i) then
interface_type <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).interface;
interface_mode <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).mode;
end if;
end process;
end behave;
|
mit
|
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/internoc_ni_type_map.vhd
|
2
|
3501
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/16/2017 07:50:07 PM
-- Design Name:
-- Module Name: internoc_ni_type_map - behave
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.internoc_pack.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity internoc_interface_type_map is
Port (
clk_i : in STD_LOGIC;
addr_i : in STD_LOGIC_VECTOR (4 downto 0);
type_o : out STD_LOGIC_VECTOR (2 downto 0);
mode_o : out STD_LOGIC
);
end internoc_interface_type_map;
architecture behave of internoc_interface_type_map is
constant INTERFACE_MAP_ROM : INTERFACE_MAP_T := (
("00000", SLAVE_MODE, I2C_INTERFACE), --1
("00001", SLAVE_MODE, SPI_INTERFACE), --2
("00010", SLAVE_MODE, INVALID_INTERFACE), --3
("00011", SLAVE_MODE, INVALID_INTERFACE), --4
("00100", SLAVE_MODE, INVALID_INTERFACE), --5
("00101", SLAVE_MODE, INVALID_INTERFACE), --6
("00110", SLAVE_MODE, INVALID_INTERFACE), --7
("00111", SLAVE_MODE, INVALID_INTERFACE), --8
("01000", SLAVE_MODE, INVALID_INTERFACE), --9
("01001", SLAVE_MODE, INVALID_INTERFACE), --10
("01010", SLAVE_MODE, INVALID_INTERFACE), --11
("01011", SLAVE_MODE, INVALID_INTERFACE), --12
("01100", SLAVE_MODE, INVALID_INTERFACE), --13
("01101", SLAVE_MODE, INVALID_INTERFACE), --14
("01110", SLAVE_MODE, INVALID_INTERFACE), --15
("01111", SLAVE_MODE, INVALID_INTERFACE), --16
("10000", MASTER_MODE, UART_INTERFACE), --17
("10001", MASTER_MODE, UART_INTERFACE), --18
("10010", MASTER_MODE, INVALID_INTERFACE), --19
("10011", MASTER_MODE, INVALID_INTERFACE), --20
("10100", MASTER_MODE, INVALID_INTERFACE), --21
("10101", MASTER_MODE, INVALID_INTERFACE), --22
("10110", MASTER_MODE, INVALID_INTERFACE), --23
("10111", MASTER_MODE, INVALID_INTERFACE), --24
("11000", MASTER_MODE, INVALID_INTERFACE), --25
("11001", MASTER_MODE, INVALID_INTERFACE), --26
("11010", MASTER_MODE, INVALID_INTERFACE), --27
("11011", MASTER_MODE, INVALID_INTERFACE), --28
("11100", MASTER_MODE, INVALID_INTERFACE), --29
("11101", MASTER_MODE, INVALID_INTERFACE), --30
("11110", MASTER_MODE, INVALID_INTERFACE), --31
("11111", MASTER_MODE, INVALID_INTERFACE) --32
);
signal interface_type : std_logic_vector(2 downto 0) := (others=>'1');
signal interface_mode : std_logic := '0';
begin
type_o <= interface_type;
mode_o <= interface_mode;
rom_p: process(clk_i)
begin
if rising_edge(clk_i) then
interface_type <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).interface;
interface_mode <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).mode;
end if;
end process;
end behave;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_mutex_0_0/sim/DemoInterconnect_mutex_0_0.vhd
|
2
|
28100
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mutex:2.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mutex_v2_1_8;
USE mutex_v2_1_8.mutex;
ENTITY DemoInterconnect_mutex_0_0 IS
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC
);
END DemoInterconnect_mutex_0_0;
ARCHITECTURE DemoInterconnect_mutex_0_0_arch OF DemoInterconnect_mutex_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mutex IS
GENERIC (
C_FAMILY : STRING;
C_NUM_AXI : INTEGER;
C_S0_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S0_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S0_AXI_ADDR_WIDTH : INTEGER;
C_S0_AXI_DATA_WIDTH : INTEGER;
C_S1_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S1_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S1_AXI_ADDR_WIDTH : INTEGER;
C_S1_AXI_DATA_WIDTH : INTEGER;
C_S2_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S2_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S2_AXI_ADDR_WIDTH : INTEGER;
C_S2_AXI_DATA_WIDTH : INTEGER;
C_S3_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S3_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S3_AXI_ADDR_WIDTH : INTEGER;
C_S3_AXI_DATA_WIDTH : INTEGER;
C_S4_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S4_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S4_AXI_ADDR_WIDTH : INTEGER;
C_S4_AXI_DATA_WIDTH : INTEGER;
C_S5_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S5_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S5_AXI_ADDR_WIDTH : INTEGER;
C_S5_AXI_DATA_WIDTH : INTEGER;
C_S6_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S6_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S6_AXI_ADDR_WIDTH : INTEGER;
C_S6_AXI_DATA_WIDTH : INTEGER;
C_S7_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S7_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S7_AXI_ADDR_WIDTH : INTEGER;
C_S7_AXI_DATA_WIDTH : INTEGER;
C_ASYNC_CLKS : INTEGER;
C_NUM_SYNC_FF : INTEGER;
C_ENABLE_USER : INTEGER;
C_OWNER_ID_WIDTH : INTEGER;
C_ENABLE_HW_PROT : INTEGER;
C_NUM_MUTEX : INTEGER
);
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC;
S3_AXI_ACLK : IN STD_LOGIC;
S3_AXI_ARESETN : IN STD_LOGIC;
S3_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_AWVALID : IN STD_LOGIC;
S3_AXI_AWREADY : OUT STD_LOGIC;
S3_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S3_AXI_WVALID : IN STD_LOGIC;
S3_AXI_WREADY : OUT STD_LOGIC;
S3_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_BVALID : OUT STD_LOGIC;
S3_AXI_BREADY : IN STD_LOGIC;
S3_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_ARVALID : IN STD_LOGIC;
S3_AXI_ARREADY : OUT STD_LOGIC;
S3_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_RVALID : OUT STD_LOGIC;
S3_AXI_RREADY : IN STD_LOGIC;
S4_AXI_ACLK : IN STD_LOGIC;
S4_AXI_ARESETN : IN STD_LOGIC;
S4_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_AWVALID : IN STD_LOGIC;
S4_AXI_AWREADY : OUT STD_LOGIC;
S4_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4_AXI_WVALID : IN STD_LOGIC;
S4_AXI_WREADY : OUT STD_LOGIC;
S4_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_BVALID : OUT STD_LOGIC;
S4_AXI_BREADY : IN STD_LOGIC;
S4_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_ARVALID : IN STD_LOGIC;
S4_AXI_ARREADY : OUT STD_LOGIC;
S4_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_RVALID : OUT STD_LOGIC;
S4_AXI_RREADY : IN STD_LOGIC;
S5_AXI_ACLK : IN STD_LOGIC;
S5_AXI_ARESETN : IN STD_LOGIC;
S5_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_AWVALID : IN STD_LOGIC;
S5_AXI_AWREADY : OUT STD_LOGIC;
S5_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S5_AXI_WVALID : IN STD_LOGIC;
S5_AXI_WREADY : OUT STD_LOGIC;
S5_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_BVALID : OUT STD_LOGIC;
S5_AXI_BREADY : IN STD_LOGIC;
S5_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_ARVALID : IN STD_LOGIC;
S5_AXI_ARREADY : OUT STD_LOGIC;
S5_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_RVALID : OUT STD_LOGIC;
S5_AXI_RREADY : IN STD_LOGIC;
S6_AXI_ACLK : IN STD_LOGIC;
S6_AXI_ARESETN : IN STD_LOGIC;
S6_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_AWVALID : IN STD_LOGIC;
S6_AXI_AWREADY : OUT STD_LOGIC;
S6_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S6_AXI_WVALID : IN STD_LOGIC;
S6_AXI_WREADY : OUT STD_LOGIC;
S6_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_BVALID : OUT STD_LOGIC;
S6_AXI_BREADY : IN STD_LOGIC;
S6_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_ARVALID : IN STD_LOGIC;
S6_AXI_ARREADY : OUT STD_LOGIC;
S6_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_RVALID : OUT STD_LOGIC;
S6_AXI_RREADY : IN STD_LOGIC;
S7_AXI_ACLK : IN STD_LOGIC;
S7_AXI_ARESETN : IN STD_LOGIC;
S7_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_AWVALID : IN STD_LOGIC;
S7_AXI_AWREADY : OUT STD_LOGIC;
S7_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S7_AXI_WVALID : IN STD_LOGIC;
S7_AXI_WREADY : OUT STD_LOGIC;
S7_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_BVALID : OUT STD_LOGIC;
S7_AXI_BREADY : IN STD_LOGIC;
S7_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_ARVALID : IN STD_LOGIC;
S7_AXI_ARREADY : OUT STD_LOGIC;
S7_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_RVALID : OUT STD_LOGIC;
S7_AXI_RREADY : IN STD_LOGIC
);
END COMPONENT mutex;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S2_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S2_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S2_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S2_AXI_ACLK, ASSOCIATED_BUSIF S2_AXI, ASSOCIATED_RESET S2_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S2_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S1_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S1_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S1_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S1_AXI_ACLK, ASSOCIATED_BUSIF S1_AXI, ASSOCIATED_RESET S1_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S1_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S0_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S0_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S0_AXI_ACLK, ASSOCIATED_BUSIF S0_AXI, ASSOCIATED_RESET S0_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S0_AXI_ACLK CLK";
BEGIN
U0 : mutex
GENERIC MAP (
C_FAMILY => "artix7",
C_NUM_AXI => 3,
C_S0_AXI_BASEADDR => X"00100000",
C_S0_AXI_HIGHADDR => X"0010FFFF",
C_S0_AXI_ADDR_WIDTH => 32,
C_S0_AXI_DATA_WIDTH => 32,
C_S1_AXI_BASEADDR => X"00200000",
C_S1_AXI_HIGHADDR => X"0020FFFF",
C_S1_AXI_ADDR_WIDTH => 32,
C_S1_AXI_DATA_WIDTH => 32,
C_S2_AXI_BASEADDR => X"00300000",
C_S2_AXI_HIGHADDR => X"0030FFFF",
C_S2_AXI_ADDR_WIDTH => 32,
C_S2_AXI_DATA_WIDTH => 32,
C_S3_AXI_BASEADDR => X"FFFFFFFF",
C_S3_AXI_HIGHADDR => X"00000000",
C_S3_AXI_ADDR_WIDTH => 32,
C_S3_AXI_DATA_WIDTH => 32,
C_S4_AXI_BASEADDR => X"FFFFFFFF",
C_S4_AXI_HIGHADDR => X"00000000",
C_S4_AXI_ADDR_WIDTH => 32,
C_S4_AXI_DATA_WIDTH => 32,
C_S5_AXI_BASEADDR => X"FFFFFFFF",
C_S5_AXI_HIGHADDR => X"00000000",
C_S5_AXI_ADDR_WIDTH => 32,
C_S5_AXI_DATA_WIDTH => 32,
C_S6_AXI_BASEADDR => X"FFFFFFFF",
C_S6_AXI_HIGHADDR => X"00000000",
C_S6_AXI_ADDR_WIDTH => 32,
C_S6_AXI_DATA_WIDTH => 32,
C_S7_AXI_BASEADDR => X"FFFFFFFF",
C_S7_AXI_HIGHADDR => X"00000000",
C_S7_AXI_ADDR_WIDTH => 32,
C_S7_AXI_DATA_WIDTH => 32,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => 2,
C_ENABLE_USER => 1,
C_OWNER_ID_WIDTH => 8,
C_ENABLE_HW_PROT => 1,
C_NUM_MUTEX => 16
)
PORT MAP (
S0_AXI_ACLK => S0_AXI_ACLK,
S0_AXI_ARESETN => S0_AXI_ARESETN,
S0_AXI_AWADDR => S0_AXI_AWADDR,
S0_AXI_AWVALID => S0_AXI_AWVALID,
S0_AXI_AWREADY => S0_AXI_AWREADY,
S0_AXI_WDATA => S0_AXI_WDATA,
S0_AXI_WSTRB => S0_AXI_WSTRB,
S0_AXI_WVALID => S0_AXI_WVALID,
S0_AXI_WREADY => S0_AXI_WREADY,
S0_AXI_BRESP => S0_AXI_BRESP,
S0_AXI_BVALID => S0_AXI_BVALID,
S0_AXI_BREADY => S0_AXI_BREADY,
S0_AXI_ARADDR => S0_AXI_ARADDR,
S0_AXI_ARVALID => S0_AXI_ARVALID,
S0_AXI_ARREADY => S0_AXI_ARREADY,
S0_AXI_RDATA => S0_AXI_RDATA,
S0_AXI_RRESP => S0_AXI_RRESP,
S0_AXI_RVALID => S0_AXI_RVALID,
S0_AXI_RREADY => S0_AXI_RREADY,
S1_AXI_ACLK => S1_AXI_ACLK,
S1_AXI_ARESETN => S1_AXI_ARESETN,
S1_AXI_AWADDR => S1_AXI_AWADDR,
S1_AXI_AWVALID => S1_AXI_AWVALID,
S1_AXI_AWREADY => S1_AXI_AWREADY,
S1_AXI_WDATA => S1_AXI_WDATA,
S1_AXI_WSTRB => S1_AXI_WSTRB,
S1_AXI_WVALID => S1_AXI_WVALID,
S1_AXI_WREADY => S1_AXI_WREADY,
S1_AXI_BRESP => S1_AXI_BRESP,
S1_AXI_BVALID => S1_AXI_BVALID,
S1_AXI_BREADY => S1_AXI_BREADY,
S1_AXI_ARADDR => S1_AXI_ARADDR,
S1_AXI_ARVALID => S1_AXI_ARVALID,
S1_AXI_ARREADY => S1_AXI_ARREADY,
S1_AXI_RDATA => S1_AXI_RDATA,
S1_AXI_RRESP => S1_AXI_RRESP,
S1_AXI_RVALID => S1_AXI_RVALID,
S1_AXI_RREADY => S1_AXI_RREADY,
S2_AXI_ACLK => S2_AXI_ACLK,
S2_AXI_ARESETN => S2_AXI_ARESETN,
S2_AXI_AWADDR => S2_AXI_AWADDR,
S2_AXI_AWVALID => S2_AXI_AWVALID,
S2_AXI_AWREADY => S2_AXI_AWREADY,
S2_AXI_WDATA => S2_AXI_WDATA,
S2_AXI_WSTRB => S2_AXI_WSTRB,
S2_AXI_WVALID => S2_AXI_WVALID,
S2_AXI_WREADY => S2_AXI_WREADY,
S2_AXI_BRESP => S2_AXI_BRESP,
S2_AXI_BVALID => S2_AXI_BVALID,
S2_AXI_BREADY => S2_AXI_BREADY,
S2_AXI_ARADDR => S2_AXI_ARADDR,
S2_AXI_ARVALID => S2_AXI_ARVALID,
S2_AXI_ARREADY => S2_AXI_ARREADY,
S2_AXI_RDATA => S2_AXI_RDATA,
S2_AXI_RRESP => S2_AXI_RRESP,
S2_AXI_RVALID => S2_AXI_RVALID,
S2_AXI_RREADY => S2_AXI_RREADY,
S3_AXI_ACLK => '0',
S3_AXI_ARESETN => '0',
S3_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_AWVALID => '0',
S3_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S3_AXI_WVALID => '0',
S3_AXI_BREADY => '0',
S3_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_ARVALID => '0',
S3_AXI_RREADY => '0',
S4_AXI_ACLK => '0',
S4_AXI_ARESETN => '0',
S4_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_AWVALID => '0',
S4_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S4_AXI_WVALID => '0',
S4_AXI_BREADY => '0',
S4_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_ARVALID => '0',
S4_AXI_RREADY => '0',
S5_AXI_ACLK => '0',
S5_AXI_ARESETN => '0',
S5_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_AWVALID => '0',
S5_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S5_AXI_WVALID => '0',
S5_AXI_BREADY => '0',
S5_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_ARVALID => '0',
S5_AXI_RREADY => '0',
S6_AXI_ACLK => '0',
S6_AXI_ARESETN => '0',
S6_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_AWVALID => '0',
S6_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S6_AXI_WVALID => '0',
S6_AXI_BREADY => '0',
S6_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_ARVALID => '0',
S6_AXI_RREADY => '0',
S7_AXI_ACLK => '0',
S7_AXI_ARESETN => '0',
S7_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_AWVALID => '0',
S7_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S7_AXI_WVALID => '0',
S7_AXI_BREADY => '0',
S7_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_ARVALID => '0',
S7_AXI_RREADY => '0'
);
END DemoInterconnect_mutex_0_0_arch;
|
mit
|
Dasio/FIT-Projects
|
INP/proj1/fpga/sim/ledc8x8_tb.vhd
|
4
|
754
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity testbench is
end testbench;
architecture behv of testbench is
component ledc8x8 is
port ( SMCLK, RESET: in std_logic;
ROW, LED: out std_logic_vector(0 to 7)
);
end component;
signal smclk: std_logic := '0';
signal reset: std_logic;
signal row, led: std_logic_vector(0 to 7);
constant period: time := 20 ns;
begin
uut: ledc8x8 port map(smclk, reset, row, led);
smclk <= not smclk after period / 2;
test: process
begin
reset <= '1';
wait until smclk'event and smclk = '1';
reset <= '0';
wait;
end process;
end behv;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_1_0/sim/DemoInterconnect_internoc_ni_axi_master_1_0.vhd
|
2
|
10681
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_internoc_ni_axi_master_1_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_1_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_1_0_arch OF DemoInterconnect_internoc_ni_axi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_1_0_arch;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ipshared/68e9/hdl/axi_spi_master_v1_0.vhd
|
3
|
4388
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0 is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
m_spi_mosi : out std_logic;
m_spi_miso : in std_logic;
m_spi_ss : out std_logic;
m_spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_spi_master_v1_0;
architecture arch_imp of axi_spi_master_v1_0 is
-- component declaration
component axi_spi_master_v1_0_S00_AXI is
generic (
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_spi_master_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_spi_master_v1_0_S00_AXI_inst : axi_spi_master_v1_0_S00_AXI
generic map (
SPI_DATA_WIDTH => SPI_DATA_WIDTH,
SPI_CLK_DIV => SPI_CLK_DIV,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
spi_mosi => m_spi_mosi,
spi_miso => m_spi_miso,
spi_ss => m_spi_ss,
spi_sclk => m_spi_sclk,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_ila_0_0/sim/DemoInterconnect_ila_0_0.vhd
|
2
|
2706
|
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_ila_0_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DemoInterconnect_ila_0_0;
ARCHITECTURE DemoInterconnect_ila_0_0_arch OF DemoInterconnect_ila_0_0 IS
BEGIN
END DemoInterconnect_ila_0_0_arch;
|
mit
|
rdveiga/Neander_VHDL
|
vhdl/memory.vhd
|
1
|
5727
|
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file memory.vhd when simulating
-- the core, memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END memory;
ARCHITECTURE memory_a OF memory IS
-- synthesis translate_off
COMPONENT wrapped_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 256,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END memory_a;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_jtag_axi_0_0/synth/DemoInterconnect_jtag_axi_0_0.vhd
|
1
|
14174
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:jtag_axi:1.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY jtag_axi;
USE jtag_axi.jtag_axi_v1_2_4_jtag_axi;
ENTITY DemoInterconnect_jtag_axi_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC;
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC;
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC
);
END DemoInterconnect_jtag_axi_0_0;
ARCHITECTURE DemoInterconnect_jtag_axi_0_0_arch OF DemoInterconnect_jtag_axi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT jtag_axi_v1_2_4_jtag_axi IS
GENERIC (
RD_TXN_QUEUE_LENGTH : INTEGER;
WR_TXN_QUEUE_LENGTH : INTEGER;
M_AXI_ID_WIDTH : INTEGER;
M_AXI_ADDR_WIDTH : INTEGER;
FAMILY : STRING;
M_AXI_DATA_WIDTH : INTEGER;
M_HAS_BURST : INTEGER;
PROTOCOL : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC;
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC;
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC
);
END COMPONENT jtag_axi_v1_2_4_jtag_axi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "jtag_axi_v1_2_4_jtag_axi,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_jtag_axi_0_0_arch : ARCHITECTURE IS "DemoInterconnect_jtag_axi_0_0,jtag_axi_v1_2_4_jtag_axi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "DemoInterconnect_jtag_axi_0_0,jtag_axi_v1_2_4_jtag_axi,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=jtag_axi,x_ipVersion=1.2,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RD_TXN_QUEUE_LENGTH=1,WR_TXN_QUEUE_LENGTH=1,M_AXI_ID_WIDTH=1,M_AXI_ADDR_WIDTH=32,FAMILY=artix7,M_AXI_DATA_WIDTH=32,M_HAS_BURST=1,PROTOCOL=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_awid: SIGNAL IS "XIL_INTERFACENAME M_AXI, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, BUSER_WIDTH 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 72000000, ID_WIDTH 1, ADDR_WIDTH 32, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
BEGIN
U0 : jtag_axi_v1_2_4_jtag_axi
GENERIC MAP (
RD_TXN_QUEUE_LENGTH => 1,
WR_TXN_QUEUE_LENGTH => 1,
M_AXI_ID_WIDTH => 1,
M_AXI_ADDR_WIDTH => 32,
FAMILY => "artix7",
M_AXI_DATA_WIDTH => 32,
M_HAS_BURST => 1,
PROTOCOL => 0
)
PORT MAP (
aclk => aclk,
aresetn => aresetn,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
END DemoInterconnect_jtag_axi_0_0_arch;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ipshared/859e/hdl/mutex_v2_1_vh_rfs.vhd
|
1
|
116298
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
-------------------------------------------------------------------------------
-- gen_dram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Author: satish
--
-- History:
-- satish 2004-03-24 New Version
-- rikardw 2006-10-19 Single port version
--
-- Description:
-- Code to infer synchronous single port lut ram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity Gen_DRAM;
architecture syn of Gen_DRAM is
type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
-- signal RAM : ram_type := (others => (others => '0'));
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a));
end syn;
-------------------------------------------------------------------------------
-- multi_channel_register.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_register.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.Gen_DRAM;
entity multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end entity multi_channel_register;
architecture IMP of multi_channel_register is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component Gen_DRAM;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Single channel storage
-----------------------------------------------------------------------------
Use_Single_Ch_Reg: if( C_NUM_CHANNELS = 1 ) generate
begin
Store_Cnt: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Data_Out <= (others=>'0');
elsif( Write_Strobe = '1' ) then
Data_Out <= Data_In;
end if;
end if;
end process Store_Cnt;
end generate Use_Single_Ch_Reg;
-----------------------------------------------------------------------------
-- Multiple channel storage
-----------------------------------------------------------------------------
Use_Multi_Ch_Reg: if( C_NUM_CHANNELS > 1 ) generate
begin
-- Counter storage.
RAM_Storage: Gen_DRAM
generic map(
C_DWIDTH => C_DWIDTH,
C_AWIDTH => C_AWIDTH
)
port map(
clk => Clk,
we => Write_Strobe,
a => Channel,
di => Data_In,
do => Data_Out
);
end generate Use_Multi_Ch_Reg;
end architecture IMP;
-------------------------------------------------------------------------------
-- multi_channel_mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.multi_channel_register;
entity multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end entity multi_channel_mutex;
architecture IMP of multi_channel_mutex is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal Mutex_I : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
signal Mutex_New : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Channel Counter Storage
-----------------------------------------------------------------------------
Mutex_Store: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_CHANNELS,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH + C_OWNER_ID_WIDTH
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe,
Channel => Channel,
Data_In => Mutex_New,
Data_Out => Mutex_I
);
-----------------------------------------------------------------------------
-- Write to lock and pure write to release function
-----------------------------------------------------------------------------
Write_2_Lock: process(Data_In, Mutex_I)
variable OwnerMatched : boolean;
begin
-- Check if the owner is writing.
if( C_OWNER_ID_WIDTH > 0 ) then
OwnerMatched := Mutex_I(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH) =
Data_In(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH);
else
OwnerMatched := true;
end if;
-- Update mutex accordingly.
if( Mutex_I(0) /= '1' or OwnerMatched ) then
-- Write new value.
if( Data_In(0) = '0' ) then
Mutex_New <= (others=>'0');
else
Mutex_New <= Data_In;
end if;
else
-- Keep old value.
Mutex_New <= Mutex_I;
end if;
end process Write_2_Lock;
-----------------------------------------------------------------------------
-- Rename output signals
-----------------------------------------------------------------------------
New_Mutex_Out <= Mutex_New;
Mutex_Out <= Mutex_I;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex_core.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end entity mutex_core;
library unisim;
use unisim.all;
architecture IMP of mutex_core is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end component multi_channel_mutex;
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal arbitrated signals
signal Mutex_Access_I : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Ack_I : std_logic;
signal Access_In_Progress : std_logic;
signal Write_Strobe_Mutex : std_logic;
signal Write_Strobe_User : std_logic;
signal Second_Cycle : std_logic;
signal Read_Data_Type : std_logic_vector(0 to 1);
-- Configuration register related.
signal User_Reg : std_logic_vector(0 to C_DWIDTH_USER_REG - 1);
signal User_Reg_I : std_logic_vector(0 to C_DWIDTH - 1);
-- Mutex related.
signal Mutex : std_logic_vector(0 to C_DWIDTH_MUTEX + C_OWNER_ID_WIDTH - 1);
signal Mutex_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Interface arbitration
-----------------------------------------------------------------------------
Using_SingleIf_Mutex: if C_NUM_INTERFACE = 1 generate
begin
-- Only one interface to all Mutexes.
-- => Simply connect w/o any arbitration.
Access_In_Progress <= Mutex_Access(0);
Mutex_Access_I <= Mutex_Access(0 to 0);
Mutex_RnW_I <= Mutex_RnW(0);
Mutex_HW_Id_I <= Mutex_HW_Id(0 to C_HW_ID_WIDTH - 1) & '0';
Mutex_Addr_I <= Mutex_Addr(0 to C_AWIDTH - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(0 to C_DWIDTH - 1);
Mutex_Ack <= (others=>Mutex_Ack_I);
end generate Using_SingleIf_Mutex;
-- Multiple interfaces.
Using_MultiIf_Mutex: if C_NUM_INTERFACE > 1 generate
begin
Interface_Arbitration: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
Mutex_RnW_I <= '0';
Mutex_HW_Id_I <= (others=>'0');
Mutex_Addr_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( Access_In_Progress = '1' ) then
if( ( Mutex_Access_I and Mutex_Access ) = (Mutex_Access'range=>'0') ) then
-- Selected interface has acknowledged that this end
-- has performed all its tasks.
-- => Get ready for the next access.
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
end if;
else
for I in natural range C_NUM_INTERFACE - 1 downto 0 loop
-- Loop in ascending priority order.
if( Mutex_Access(I) = '1' ) then
-- This interface wants to access a mutexes in this bank.
-- => Forward information to the rest of the core.
Access_In_Progress <= '1';
Mutex_Access_I <= (others=>'0');
Mutex_Access_I(I) <= '1';
Mutex_RnW_I <= Mutex_RnW(I);
Mutex_HW_Id_I <= Mutex_HW_Id(C_HW_ID_WIDTH * I to C_HW_ID_WIDTH * (I + 1) - 1) &
std_logic_vector(to_unsigned(I, Get_Num_Bits(C_NUM_INTERFACE)));
Mutex_Addr_I <= Mutex_Addr(C_AWIDTH * I to C_AWIDTH * (I + 1) - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(C_DWIDTH * I to C_DWIDTH * (I + 1) - 1);
end if;
end loop;
end if;
-- Assign the Acknowledge signal.
Mutex_Ack <= (Mutex_Ack'range=>Mutex_Ack_I) and Mutex_Access_I and Mutex_Access;
end if;
end if;
end process Interface_Arbitration;
end generate Using_MultiIf_Mutex;
-----------------------------------------------------------------------------
-- Access control
-----------------------------------------------------------------------------
Access_Handle: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
-- Reset.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
Mutex_Ack_I <= '0';
Second_Cycle <= '0';
Read_Data_Type <= (others=>'0');
else
-- Generate second cycle.
Second_Cycle <= (not Second_Cycle ) and Access_In_Progress and (not Mutex_Ack_I);
-- Default assignment.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
-- Control read data mux.
Read_Data_Type <= Mutex_Addr_I(Mutex_Addr_I'right - 1 - 2 to Mutex_Addr_I'right - 2);
-- Create write strobes for resources.
if( Mutex_Addr_I(Mutex_Addr_I'right - 2) = '0' ) then
-- Access mutex registers.
Write_Strobe_Mutex <= Access_In_Progress and (not Mutex_RnW_I);
else
-- Access Configuration/Address register.
if( C_ENABLE_USER /= 0 ) then
Write_Strobe_User <= Access_In_Progress and (not Mutex_RnW_I);
end if;
end if;
-- Finish access.
Mutex_Ack_I <= Second_Cycle or (Access_In_Progress and (not Mutex_RnW_I)) or (Mutex_Ack_I and Access_In_Progress);
end if;
end if;
end process Access_Handle;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Register
-----------------------------------------------------------------------------
Using_HW_Protection: if( C_ENABLE_HW_PROT /= 0 ) generate
signal Mutex_Wr_Data_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
signal Mutex_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
begin
Protected_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE),
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_II,
New_Mutex_Out => open,
Mutex_Out => Mutex_II
);
-- Append and remove hardware information invisibly.
Mutex_Wr_Data_II <= Mutex_HW_Id_I & Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1);
Mutex <= Mutex_II(C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) to Mutex_II'right);
end generate Using_HW_Protection;
No_HW_Protection: if( C_ENABLE_HW_PROT = 0 ) generate
begin
Normal_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1),
New_Mutex_Out => open,
Mutex_Out => Mutex
);
end generate No_HW_Protection;
-----------------------------------------------------------------------------
-- Instantiating USER Register
-----------------------------------------------------------------------------
Using_User_Reg: if( C_ENABLE_USER /= 0 ) generate
begin
User_Reg_Inst: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_USER_REG
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_User,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1),
Data_Out => User_Reg
);
end generate Using_User_Reg;
No_User_Reg: if( C_ENABLE_USER = 0 ) generate
begin
User_Reg <= (others=>'0');
end generate No_User_Reg;
-----------------------------------------------------------------------------
-- Read multiplexer
-----------------------------------------------------------------------------
ReadDataMux: process(Read_Data_Type, User_Reg, Mutex)
begin
-- Extend the data to full width.
-- User_Reg_I <= (others=>'0');
-- User_Reg_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
-- Mutex_I <= (others=>'0');
-- Mutex_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
-- Default assignment.
Mutex_Rd_Data_I <= (others=>'0');
case Read_Data_Type is
when "00" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
when "01" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
when others =>
-- Reserved registers.
null;
end case;
end process ReadDataMux;
ReadDataMux_DFF: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Mutex_Rd_Data <= (others=>'0');
elsif( Second_Cycle = '1' ) then
Mutex_Rd_Data <= Mutex_Rd_Data_I;
end if;
end if;
end process ReadDataMux_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- axi_decode.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_decode.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_decode.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2007-03-27 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end entity axi_decode;
library unisim;
use unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.all;
architecture IMP of axi_decode is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal valid_read_data : std_logic;
signal new_write_access_cmb : std_logic;
signal new_read_access_cmb : std_logic;
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal end_write : std_logic; -- Write cycle end.
signal end_read : std_logic; -- Read cycle end.
signal completed_write : std_logic; -- Write response acknowledged.
signal completed_read : std_logic; -- Read response acknowledged.
signal access_end : std_logic; -- Access is completed.
signal Mutex_Access_I : std_logic;
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(C_DWIDTH - 1 downto 0);
signal Mutex_Ack_I : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Write has priority.
-- Make sure new write is blocked if it arrives after a read is acknowledged (prior to Mutex_Access_I is set).
new_write_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_AWVALID and S_AXI_WVALID and
(not new_read_access);
new_read_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_ARVALID and
(not new_write_access_cmb);
Start_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
new_write_access <= '0';
new_read_access <= '0';
else
-- Make sure it is a one cycle pulse only.
new_write_access <= new_write_access_cmb and not new_write_access;
new_read_access <= new_read_access_cmb and not new_read_access;
end if;
end if;
end process Start_of_Transfer_Control;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Capture new access.
AccessAck: process (S_AXI_ACLK) is
begin -- process AddrAck
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
Mutex_Access_I <= '0';
Mutex_RnW_I <= '0';
Mutex_Addr_I <= (others=>'0');
Mutex_HW_Id_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( new_write_access = '1' or new_read_access = '1' ) then
-- Get data for new access.
if( new_write_access = '1' ) then
Mutex_Addr_I <= S_AXI_AWADDR(C_AWIDTH-1 downto 0);
else
Mutex_Addr_I <= S_AXI_ARADDR(C_AWIDTH-1 downto 0);
end if;
Mutex_Wr_Data_I <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
Mutex_HW_Id_I <= (others=>'0');
Mutex_RnW_I <= new_read_access;
Mutex_Access_I <= '1';
elsif( access_end = '1' ) then
Mutex_Access_I <= '0';
end if;
end if;
end if;
end process AccessAck;
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (B/R)
-----------------------------------------------------------------------------
End_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
end_write <= '0';
end_read <= '0';
else
if( completed_write = '1' ) then
end_write <= '0';
elsif( Mutex_Access_I = '1' and Mutex_Ack_I = '1' and Mutex_RnW_I = '0' ) then
end_write <= '1';
end if;
if( completed_read = '1' ) then
end_read <= '0';
elsif( valid_read_data = '1' ) then
end_read <= '1';
end if;
end if;
end if;
end process End_of_Transfer_Control;
valid_read_data <= Mutex_Access_I and Mutex_Ack_I and Mutex_RnW_I;
S_AXI_BVALID <= end_write;
S_AXI_RVALID <= end_read;
S_AXI_BRESP <= (others=>'0');
S_AXI_RRESP <= (others=>'0');
completed_write <= end_write and S_AXI_BREADY;
completed_read <= end_read and S_AXI_RREADY;
access_end <= completed_write or completed_read;
Read_Align: process (Mutex_Rd_Data) is
begin -- process Read_Mux
Mutex_Rd_Data_i <= (others=>'0');
Mutex_Rd_Data_i(C_DWIDTH - 1 downto 0) <= Mutex_Rd_Data;
end process Read_Align;
Not_All_32_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_32_Bits_Are_Used;
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I), -- [out std_logic]
C => S_AXI_ACLK, -- [in std_logic]
CE => valid_read_data, -- [in std_logic]
D => Mutex_Rd_Data_i(I), -- [in std_logic]
R => completed_read); -- [in std_logic]
end generate S_AXI_RDATA_DFF;
-----------------------------------------------------------------------------
-- Domain synchronization
-----------------------------------------------------------------------------
-- Always move the data signals directly accross.
-- Sync signals will guarantee safe crossing.
Mutex_RnW <= Mutex_RnW_I;
Mutex_HW_Id <= Mutex_HW_Id_I;
Mutex_Addr <= Mutex_Addr_I;
Mutex_Wr_Data <= Mutex_Wr_Data_I;
Mutex_Rd_Data_I <= Mutex_Rd_Data;
No_Crossing: if( C_ASYNC_CLKS = 0 ) generate
begin
-- No need to synchronize.
Mutex_Access <= Mutex_Access_I;
Mutex_Ack_I <= Mutex_Ack;
end generate No_Crossing;
Domain_Crossing: if( C_ASYNC_CLKS /= 0 ) generate
signal Mutex_Access_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal Mutex_Ack_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal S_AXI_ARESET : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of Mutex_Access_d : signal is "TRUE";
-- attribute ASYNC_REG of Mutex_Ack_d : signal is "TRUE";
begin
-- Handle transfer of asynchronous interface sync signal transfer
-- with unknown clock relation.
--
-- C_NUM_SYNC_FF = 2 (default):
--
-- MutexClk -------+-----+-----------+
-- | | |
-- | | +---------+
-- Event ----FF----FF----FF---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+-----+ | |
-- | | | |
-- Ack <-----------FF----FF-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
--
-- General case for C_NUM_SYNC_FF:
--
-- MutexClk -------+----------------+
-- | |
-- | +---------+
-- Event ----FF----(FF x n)---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+ | |
-- | | |
-- Ack <-----------(FF x n)-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
S_AXI_ARESET <= not S_AXI_ARESETN;
-- Move the out bound access signal to the common domain.
Mutex_Access_d(0) <= Mutex_Access_I;
Cross_Out: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Access_d(I),
C => Mutex_Clk,
D => Mutex_Access_d(I-1),
R => Mutex_Rst
);
end block Block_Gen;
end generate Cross_Out;
-- Select synchronized bit.
Mutex_Access <= Mutex_Access_d(C_NUM_SYNC_FF);
-- Get back to interface domain.
Mutex_Ack_d(0) <= Mutex_Ack;
Cross_Back: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Ack_d(I),
C => S_AXI_ACLK,
D => Mutex_Ack_d(I-1),
R => S_AXI_ARESET
);
end block Block_Gen;
end generate Cross_Back;
-- Select synchronized bit.
Mutex_Ack_I <= Mutex_Ack_d(C_NUM_SYNC_FF);
end generate Domain_Crossing;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex.vhd
-- axi_decode.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
-- mutex_core.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-- stefana 2012-12-14 Removed legacy interfaces
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- AXI4 interface #0 specific.
C_S0_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S0_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S0_AXI_ADDR_WIDTH : integer := 32;
C_S0_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #1 specific.
C_S1_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S1_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S1_AXI_ADDR_WIDTH : integer := 32;
C_S1_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #2 specific.
C_S2_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S2_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S2_AXI_ADDR_WIDTH : integer := 32;
C_S2_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #3 specific.
C_S3_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S3_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S3_AXI_ADDR_WIDTH : integer := 32;
C_S3_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #4 specific.
C_S4_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S4_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S4_AXI_ADDR_WIDTH : integer := 32;
C_S4_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #5 specific.
C_S5_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S5_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S5_AXI_ADDR_WIDTH : integer := 32;
C_S5_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #6 specific.
C_S6_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S6_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S6_AXI_ADDR_WIDTH : integer := 32;
C_S6_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #7 specific.
C_S7_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S7_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S7_AXI_ADDR_WIDTH : integer := 32;
C_S7_AXI_DATA_WIDTH : integer := 32;
-- Mutex specific.
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_NUM_AXI : integer range 0 to 8 := 2; -- Number of AXI to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 0; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16 -- Number of mutexes.
);
port (
-- AXI4-Lite interface #0 slave signals.
S0_AXI_ACLK : in std_logic;
S0_AXI_ARESETN : in std_logic;
S0_AXI_AWADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_AWVALID : in std_logic;
S0_AXI_AWREADY : out std_logic;
S0_AXI_WDATA : in std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_WSTRB : in std_logic_vector((C_S0_AXI_DATA_WIDTH/8)-1 downto 0);
S0_AXI_WVALID : in std_logic;
S0_AXI_WREADY : out std_logic;
S0_AXI_BRESP : out std_logic_vector(1 downto 0);
S0_AXI_BVALID : out std_logic;
S0_AXI_BREADY : in std_logic;
S0_AXI_ARADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_ARVALID : in std_logic;
S0_AXI_ARREADY : out std_logic;
S0_AXI_RDATA : out std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_RRESP : out std_logic_vector(1 downto 0);
S0_AXI_RVALID : out std_logic;
S0_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #1 slave signals.
S1_AXI_ACLK : in std_logic;
S1_AXI_ARESETN : in std_logic;
S1_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_AWVALID : in std_logic;
S1_AXI_AWREADY : out std_logic;
S1_AXI_WDATA : in std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_WSTRB : in std_logic_vector((C_S1_AXI_DATA_WIDTH/8)-1 downto 0);
S1_AXI_WVALID : in std_logic;
S1_AXI_WREADY : out std_logic;
S1_AXI_BRESP : out std_logic_vector(1 downto 0);
S1_AXI_BVALID : out std_logic;
S1_AXI_BREADY : in std_logic;
S1_AXI_ARADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_ARVALID : in std_logic;
S1_AXI_ARREADY : out std_logic;
S1_AXI_RDATA : out std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_RRESP : out std_logic_vector(1 downto 0);
S1_AXI_RVALID : out std_logic;
S1_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #2 slave signals.
S2_AXI_ACLK : in std_logic;
S2_AXI_ARESETN : in std_logic;
S2_AXI_AWADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_AWVALID : in std_logic;
S2_AXI_AWREADY : out std_logic;
S2_AXI_WDATA : in std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_WSTRB : in std_logic_vector((C_S2_AXI_DATA_WIDTH/8)-1 downto 0);
S2_AXI_WVALID : in std_logic;
S2_AXI_WREADY : out std_logic;
S2_AXI_BRESP : out std_logic_vector(1 downto 0);
S2_AXI_BVALID : out std_logic;
S2_AXI_BREADY : in std_logic;
S2_AXI_ARADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_ARVALID : in std_logic;
S2_AXI_ARREADY : out std_logic;
S2_AXI_RDATA : out std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_RRESP : out std_logic_vector(1 downto 0);
S2_AXI_RVALID : out std_logic;
S2_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #3 slave signals.
S3_AXI_ACLK : in std_logic;
S3_AXI_ARESETN : in std_logic;
S3_AXI_AWADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_AWVALID : in std_logic;
S3_AXI_AWREADY : out std_logic;
S3_AXI_WDATA : in std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_WSTRB : in std_logic_vector((C_S3_AXI_DATA_WIDTH/8)-1 downto 0);
S3_AXI_WVALID : in std_logic;
S3_AXI_WREADY : out std_logic;
S3_AXI_BRESP : out std_logic_vector(1 downto 0);
S3_AXI_BVALID : out std_logic;
S3_AXI_BREADY : in std_logic;
S3_AXI_ARADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_ARVALID : in std_logic;
S3_AXI_ARREADY : out std_logic;
S3_AXI_RDATA : out std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_RRESP : out std_logic_vector(1 downto 0);
S3_AXI_RVALID : out std_logic;
S3_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #4 slave signals.
S4_AXI_ACLK : in std_logic;
S4_AXI_ARESETN : in std_logic;
S4_AXI_AWADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_AWVALID : in std_logic;
S4_AXI_AWREADY : out std_logic;
S4_AXI_WDATA : in std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_WSTRB : in std_logic_vector((C_S4_AXI_DATA_WIDTH/8)-1 downto 0);
S4_AXI_WVALID : in std_logic;
S4_AXI_WREADY : out std_logic;
S4_AXI_BRESP : out std_logic_vector(1 downto 0);
S4_AXI_BVALID : out std_logic;
S4_AXI_BREADY : in std_logic;
S4_AXI_ARADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_ARVALID : in std_logic;
S4_AXI_ARREADY : out std_logic;
S4_AXI_RDATA : out std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_RRESP : out std_logic_vector(1 downto 0);
S4_AXI_RVALID : out std_logic;
S4_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #5 slave signals.
S5_AXI_ACLK : in std_logic;
S5_AXI_ARESETN : in std_logic;
S5_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_AWVALID : in std_logic;
S5_AXI_AWREADY : out std_logic;
S5_AXI_WDATA : in std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_WSTRB : in std_logic_vector((C_S5_AXI_DATA_WIDTH/8)-1 downto 0);
S5_AXI_WVALID : in std_logic;
S5_AXI_WREADY : out std_logic;
S5_AXI_BRESP : out std_logic_vector(1 downto 0);
S5_AXI_BVALID : out std_logic;
S5_AXI_BREADY : in std_logic;
S5_AXI_ARADDR : in std_logic_vector(C_S5_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_ARVALID : in std_logic;
S5_AXI_ARREADY : out std_logic;
S5_AXI_RDATA : out std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_RRESP : out std_logic_vector(1 downto 0);
S5_AXI_RVALID : out std_logic;
S5_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #6 slave signals.
S6_AXI_ACLK : in std_logic;
S6_AXI_ARESETN : in std_logic;
S6_AXI_AWADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_AWVALID : in std_logic;
S6_AXI_AWREADY : out std_logic;
S6_AXI_WDATA : in std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_WSTRB : in std_logic_vector((C_S6_AXI_DATA_WIDTH/8)-1 downto 0);
S6_AXI_WVALID : in std_logic;
S6_AXI_WREADY : out std_logic;
S6_AXI_BRESP : out std_logic_vector(1 downto 0);
S6_AXI_BVALID : out std_logic;
S6_AXI_BREADY : in std_logic;
S6_AXI_ARADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_ARVALID : in std_logic;
S6_AXI_ARREADY : out std_logic;
S6_AXI_RDATA : out std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_RRESP : out std_logic_vector(1 downto 0);
S6_AXI_RVALID : out std_logic;
S6_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #7 slave signals.
S7_AXI_ACLK : in std_logic;
S7_AXI_ARESETN : in std_logic;
S7_AXI_AWADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_AWVALID : in std_logic;
S7_AXI_AWREADY : out std_logic;
S7_AXI_WDATA : in std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_WSTRB : in std_logic_vector((C_S7_AXI_DATA_WIDTH/8)-1 downto 0);
S7_AXI_WVALID : in std_logic;
S7_AXI_WREADY : out std_logic;
S7_AXI_BRESP : out std_logic_vector(1 downto 0);
S7_AXI_BVALID : out std_logic;
S7_AXI_BREADY : in std_logic;
S7_AXI_ARADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_ARVALID : in std_logic;
S7_AXI_ARREADY : out std_logic;
S7_AXI_RDATA : out std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_RRESP : out std_logic_vector(1 downto 0);
S7_AXI_RVALID : out std_logic;
S7_AXI_RREADY : in std_logic
);
end entity mutex;
library unisim;
use unisim.all;
architecture IMP of mutex is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-- Returns at least 1
function MakePos(a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
-- Returns the minimum value of the two parameters
function IntMin(a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
-- Returns the maximum value of the two parameters
function IntMax(a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function IntMax;
-- Returns the maximum value of the two parameters
function IntSelect(s : boolean; a, b : integer) return integer is
begin
if s then
return a;
else
return b;
end if;
end function IntSelect;
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-- Mutex specific.
constant C_NUM_INTERFACE : integer range 1 to 16 := C_NUM_AXI;
-- Number of interfaces to access Mutexes.
constant C_AXI_HW_ID_WIDTH : integer:= IntMax(IntMax(IntMax(IntSelect(C_NUM_AXI>0,1,0),
IntSelect(C_NUM_AXI>1,1,0)),
IntMax(IntSelect(C_NUM_AXI>2,1,0),
IntSelect(C_NUM_AXI>3,1,0))),
IntMax(IntMax(IntSelect(C_NUM_AXI>4,1,0),
IntSelect(C_NUM_AXI>5,1,0)),
IntMax(IntSelect(C_NUM_AXI>6,1,0),
IntSelect(C_NUM_AXI>7,1,0))));
constant C_HW_ID_WIDTH : integer:= C_AXI_HW_ID_WIDTH;
constant C_REGISTER_WIDTH : integer := 8; -- Width of register offset.
constant C_AWIDTH : integer := C_REGISTER_WIDTH + Get_Num_Bits(C_NUM_MUTEX);
-- Address bits including register offset.
constant C_DWIDTH : integer := 32; -- Width of data bus.
constant C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
constant C_DWIDTH_MUTEX : integer := 1; -- Width of mutex field (usually 1).
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end component axi_decode;
component mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end component mutex_core;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal MUTEX signals.
signal Mutex_Clk : std_logic;
signal Mutex_Rst : std_logic;
signal Mutex_Access : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_HW_Id : std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
signal Mutex_Addr : std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
signal Mutex_Wr_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Rd_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Ack : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #0
-----------------------------------------------------------------------------
Using_AXI_0: if C_NUM_AXI > 0 generate
begin
AXI_If_0: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S0_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S0_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S0_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S0_AXI_DATA_WIDTH,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S0_AXI_ACLK,
S_AXI_ARESETN => S0_AXI_ARESETN,
S_AXI_AWADDR => S0_AXI_AWADDR,
S_AXI_AWVALID => S0_AXI_AWVALID,
S_AXI_AWREADY => S0_AXI_AWREADY,
S_AXI_WDATA => S0_AXI_WDATA,
S_AXI_WSTRB => S0_AXI_WSTRB,
S_AXI_WVALID => S0_AXI_WVALID,
S_AXI_WREADY => S0_AXI_WREADY,
S_AXI_BRESP => S0_AXI_BRESP,
S_AXI_BVALID => S0_AXI_BVALID,
S_AXI_BREADY => S0_AXI_BREADY,
S_AXI_ARADDR => S0_AXI_ARADDR,
S_AXI_ARVALID => S0_AXI_ARVALID,
S_AXI_ARREADY => S0_AXI_ARREADY,
S_AXI_RDATA => S0_AXI_RDATA,
S_AXI_RRESP => S0_AXI_RRESP,
S_AXI_RVALID => S0_AXI_RVALID,
S_AXI_RREADY => S0_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(0),
Mutex_RnW => Mutex_RnW(0),
Mutex_HW_Id => Mutex_HW_Id((0) * C_HW_ID_WIDTH to (1) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((0) * C_AWIDTH to (1) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(0)
);
end generate Using_AXI_0;
No_AXI_0: if C_NUM_AXI < 1 generate
begin
S0_AXI_AWREADY <= '0';
S0_AXI_WREADY <= '0';
S0_AXI_BRESP <= (others=>'0');
S0_AXI_BVALID <= '0';
S0_AXI_ARREADY <= '0';
S0_AXI_RDATA <= (others=>'0');
S0_AXI_RRESP <= (others=>'0');
S0_AXI_RVALID <= '0';
end generate No_AXI_0;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #1
-----------------------------------------------------------------------------
Using_AXI_1: if C_NUM_AXI > 1 generate
begin
AXI_If_1: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S1_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S1_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S1_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S1_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S1_AXI_ACLK,
S_AXI_ARESETN => S1_AXI_ARESETN,
S_AXI_AWADDR => S1_AXI_AWADDR,
S_AXI_AWVALID => S1_AXI_AWVALID,
S_AXI_AWREADY => S1_AXI_AWREADY,
S_AXI_WDATA => S1_AXI_WDATA,
S_AXI_WSTRB => S1_AXI_WSTRB,
S_AXI_WVALID => S1_AXI_WVALID,
S_AXI_WREADY => S1_AXI_WREADY,
S_AXI_BRESP => S1_AXI_BRESP,
S_AXI_BVALID => S1_AXI_BVALID,
S_AXI_BREADY => S1_AXI_BREADY,
S_AXI_ARADDR => S1_AXI_ARADDR,
S_AXI_ARVALID => S1_AXI_ARVALID,
S_AXI_ARREADY => S1_AXI_ARREADY,
S_AXI_RDATA => S1_AXI_RDATA,
S_AXI_RRESP => S1_AXI_RRESP,
S_AXI_RVALID => S1_AXI_RVALID,
S_AXI_RREADY => S1_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(1),
Mutex_RnW => Mutex_RnW(1),
Mutex_HW_Id => Mutex_HW_Id((1) * C_HW_ID_WIDTH to (2) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((1) * C_AWIDTH to (2) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(1)
);
end generate Using_AXI_1;
No_AXI_1: if C_NUM_AXI < 2 generate
begin
S1_AXI_AWREADY <= '0';
S1_AXI_WREADY <= '0';
S1_AXI_BRESP <= (others=>'0');
S1_AXI_BVALID <= '0';
S1_AXI_ARREADY <= '0';
S1_AXI_RDATA <= (others=>'0');
S1_AXI_RRESP <= (others=>'0');
S1_AXI_RVALID <= '0';
end generate No_AXI_1;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #2
-----------------------------------------------------------------------------
Using_AXI_2: if C_NUM_AXI > 2 generate
begin
AXI_If_2: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S2_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S2_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S2_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S2_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S2_AXI_ACLK,
S_AXI_ARESETN => S2_AXI_ARESETN,
S_AXI_AWADDR => S2_AXI_AWADDR,
S_AXI_AWVALID => S2_AXI_AWVALID,
S_AXI_AWREADY => S2_AXI_AWREADY,
S_AXI_WDATA => S2_AXI_WDATA,
S_AXI_WSTRB => S2_AXI_WSTRB,
S_AXI_WVALID => S2_AXI_WVALID,
S_AXI_WREADY => S2_AXI_WREADY,
S_AXI_BRESP => S2_AXI_BRESP,
S_AXI_BVALID => S2_AXI_BVALID,
S_AXI_BREADY => S2_AXI_BREADY,
S_AXI_ARADDR => S2_AXI_ARADDR,
S_AXI_ARVALID => S2_AXI_ARVALID,
S_AXI_ARREADY => S2_AXI_ARREADY,
S_AXI_RDATA => S2_AXI_RDATA,
S_AXI_RRESP => S2_AXI_RRESP,
S_AXI_RVALID => S2_AXI_RVALID,
S_AXI_RREADY => S2_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(2),
Mutex_RnW => Mutex_RnW(2),
Mutex_HW_Id => Mutex_HW_Id((2) * C_HW_ID_WIDTH to (3) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((2) * C_AWIDTH to (3) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(2)
);
end generate Using_AXI_2;
No_AXI_2: if C_NUM_AXI < 3 generate
begin
S2_AXI_AWREADY <= '0';
S2_AXI_WREADY <= '0';
S2_AXI_BRESP <= (others=>'0');
S2_AXI_BVALID <= '0';
S2_AXI_ARREADY <= '0';
S2_AXI_RDATA <= (others=>'0');
S2_AXI_RRESP <= (others=>'0');
S2_AXI_RVALID <= '0';
end generate No_AXI_2;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #3
-----------------------------------------------------------------------------
Using_AXI_3: if C_NUM_AXI > 3 generate
begin
AXI_If_3: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S3_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S3_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S3_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S3_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S3_AXI_ACLK,
S_AXI_ARESETN => S3_AXI_ARESETN,
S_AXI_AWADDR => S3_AXI_AWADDR,
S_AXI_AWVALID => S3_AXI_AWVALID,
S_AXI_AWREADY => S3_AXI_AWREADY,
S_AXI_WDATA => S3_AXI_WDATA,
S_AXI_WSTRB => S3_AXI_WSTRB,
S_AXI_WVALID => S3_AXI_WVALID,
S_AXI_WREADY => S3_AXI_WREADY,
S_AXI_BRESP => S3_AXI_BRESP,
S_AXI_BVALID => S3_AXI_BVALID,
S_AXI_BREADY => S3_AXI_BREADY,
S_AXI_ARADDR => S3_AXI_ARADDR,
S_AXI_ARVALID => S3_AXI_ARVALID,
S_AXI_ARREADY => S3_AXI_ARREADY,
S_AXI_RDATA => S3_AXI_RDATA,
S_AXI_RRESP => S3_AXI_RRESP,
S_AXI_RVALID => S3_AXI_RVALID,
S_AXI_RREADY => S3_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(3),
Mutex_RnW => Mutex_RnW(3),
Mutex_HW_Id => Mutex_HW_Id((3) * C_HW_ID_WIDTH to (4) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((3) * C_AWIDTH to (4) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(3)
);
end generate Using_AXI_3;
No_AXI_3: if C_NUM_AXI < 4 generate
begin
S3_AXI_AWREADY <= '0';
S3_AXI_WREADY <= '0';
S3_AXI_BRESP <= (others=>'0');
S3_AXI_BVALID <= '0';
S3_AXI_ARREADY <= '0';
S3_AXI_RDATA <= (others=>'0');
S3_AXI_RRESP <= (others=>'0');
S3_AXI_RVALID <= '0';
end generate No_AXI_3;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #4
-----------------------------------------------------------------------------
Using_AXI_4: if C_NUM_AXI > 4 generate
begin
AXI_If_4: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S4_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S4_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S4_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S4_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S4_AXI_ACLK,
S_AXI_ARESETN => S4_AXI_ARESETN,
S_AXI_AWADDR => S4_AXI_AWADDR,
S_AXI_AWVALID => S4_AXI_AWVALID,
S_AXI_AWREADY => S4_AXI_AWREADY,
S_AXI_WDATA => S4_AXI_WDATA,
S_AXI_WSTRB => S4_AXI_WSTRB,
S_AXI_WVALID => S4_AXI_WVALID,
S_AXI_WREADY => S4_AXI_WREADY,
S_AXI_BRESP => S4_AXI_BRESP,
S_AXI_BVALID => S4_AXI_BVALID,
S_AXI_BREADY => S4_AXI_BREADY,
S_AXI_ARADDR => S4_AXI_ARADDR,
S_AXI_ARVALID => S4_AXI_ARVALID,
S_AXI_ARREADY => S4_AXI_ARREADY,
S_AXI_RDATA => S4_AXI_RDATA,
S_AXI_RRESP => S4_AXI_RRESP,
S_AXI_RVALID => S4_AXI_RVALID,
S_AXI_RREADY => S4_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(4),
Mutex_RnW => Mutex_RnW(4),
Mutex_HW_Id => Mutex_HW_Id((4) * C_HW_ID_WIDTH to (5) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((4) * C_AWIDTH to (5) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(4)
);
end generate Using_AXI_4;
No_AXI_4: if C_NUM_AXI < 5 generate
begin
S4_AXI_AWREADY <= '0';
S4_AXI_WREADY <= '0';
S4_AXI_BRESP <= (others=>'0');
S4_AXI_BVALID <= '0';
S4_AXI_ARREADY <= '0';
S4_AXI_RDATA <= (others=>'0');
S4_AXI_RRESP <= (others=>'0');
S4_AXI_RVALID <= '0';
end generate No_AXI_4;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #5
-----------------------------------------------------------------------------
Using_AXI_5: if C_NUM_AXI > 5 generate
begin
AXI_If_5: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S5_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S5_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S5_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S5_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S5_AXI_ACLK,
S_AXI_ARESETN => S5_AXI_ARESETN,
S_AXI_AWADDR => S5_AXI_AWADDR,
S_AXI_AWVALID => S5_AXI_AWVALID,
S_AXI_AWREADY => S5_AXI_AWREADY,
S_AXI_WDATA => S5_AXI_WDATA,
S_AXI_WSTRB => S5_AXI_WSTRB,
S_AXI_WVALID => S5_AXI_WVALID,
S_AXI_WREADY => S5_AXI_WREADY,
S_AXI_BRESP => S5_AXI_BRESP,
S_AXI_BVALID => S5_AXI_BVALID,
S_AXI_BREADY => S5_AXI_BREADY,
S_AXI_ARADDR => S5_AXI_ARADDR,
S_AXI_ARVALID => S5_AXI_ARVALID,
S_AXI_ARREADY => S5_AXI_ARREADY,
S_AXI_RDATA => S5_AXI_RDATA,
S_AXI_RRESP => S5_AXI_RRESP,
S_AXI_RVALID => S5_AXI_RVALID,
S_AXI_RREADY => S5_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(5),
Mutex_RnW => Mutex_RnW(5),
Mutex_HW_Id => Mutex_HW_Id((5) * C_HW_ID_WIDTH to (6) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((5) * C_AWIDTH to (6) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(5)
);
end generate Using_AXI_5;
No_AXI_5: if C_NUM_AXI < 6 generate
begin
S5_AXI_AWREADY <= '0';
S5_AXI_WREADY <= '0';
S5_AXI_BRESP <= (others=>'0');
S5_AXI_BVALID <= '0';
S5_AXI_ARREADY <= '0';
S5_AXI_RDATA <= (others=>'0');
S5_AXI_RRESP <= (others=>'0');
S5_AXI_RVALID <= '0';
end generate No_AXI_5;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #6
-----------------------------------------------------------------------------
Using_AXI_6: if C_NUM_AXI > 6 generate
begin
AXI_If_6: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S6_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S6_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S6_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S6_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S6_AXI_ACLK,
S_AXI_ARESETN => S6_AXI_ARESETN,
S_AXI_AWADDR => S6_AXI_AWADDR,
S_AXI_AWVALID => S6_AXI_AWVALID,
S_AXI_AWREADY => S6_AXI_AWREADY,
S_AXI_WDATA => S6_AXI_WDATA,
S_AXI_WSTRB => S6_AXI_WSTRB,
S_AXI_WVALID => S6_AXI_WVALID,
S_AXI_WREADY => S6_AXI_WREADY,
S_AXI_BRESP => S6_AXI_BRESP,
S_AXI_BVALID => S6_AXI_BVALID,
S_AXI_BREADY => S6_AXI_BREADY,
S_AXI_ARADDR => S6_AXI_ARADDR,
S_AXI_ARVALID => S6_AXI_ARVALID,
S_AXI_ARREADY => S6_AXI_ARREADY,
S_AXI_RDATA => S6_AXI_RDATA,
S_AXI_RRESP => S6_AXI_RRESP,
S_AXI_RVALID => S6_AXI_RVALID,
S_AXI_RREADY => S6_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(6),
Mutex_RnW => Mutex_RnW(6),
Mutex_HW_Id => Mutex_HW_Id((6) * C_HW_ID_WIDTH to (7) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((6) * C_AWIDTH to (7) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(6)
);
end generate Using_AXI_6;
No_AXI_6: if C_NUM_AXI < 7 generate
begin
S6_AXI_AWREADY <= '0';
S6_AXI_WREADY <= '0';
S6_AXI_BRESP <= (others=>'0');
S6_AXI_BVALID <= '0';
S6_AXI_ARREADY <= '0';
S6_AXI_RDATA <= (others=>'0');
S6_AXI_RRESP <= (others=>'0');
S6_AXI_RVALID <= '0';
end generate No_AXI_6;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #7
-----------------------------------------------------------------------------
Using_AXI_7: if C_NUM_AXI > 7 generate
begin
AXI_If_7: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S7_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S7_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S7_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S7_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S7_AXI_ACLK,
S_AXI_ARESETN => S7_AXI_ARESETN,
S_AXI_AWADDR => S7_AXI_AWADDR,
S_AXI_AWVALID => S7_AXI_AWVALID,
S_AXI_AWREADY => S7_AXI_AWREADY,
S_AXI_WDATA => S7_AXI_WDATA,
S_AXI_WSTRB => S7_AXI_WSTRB,
S_AXI_WVALID => S7_AXI_WVALID,
S_AXI_WREADY => S7_AXI_WREADY,
S_AXI_BRESP => S7_AXI_BRESP,
S_AXI_BVALID => S7_AXI_BVALID,
S_AXI_BREADY => S7_AXI_BREADY,
S_AXI_ARADDR => S7_AXI_ARADDR,
S_AXI_ARVALID => S7_AXI_ARVALID,
S_AXI_ARREADY => S7_AXI_ARREADY,
S_AXI_RDATA => S7_AXI_RDATA,
S_AXI_RRESP => S7_AXI_RRESP,
S_AXI_RVALID => S7_AXI_RVALID,
S_AXI_RREADY => S7_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(7),
Mutex_RnW => Mutex_RnW(7),
Mutex_HW_Id => Mutex_HW_Id((7) * C_HW_ID_WIDTH to (8) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((7) * C_AWIDTH to (8) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(7)
);
end generate Using_AXI_7;
No_AXI_7: if C_NUM_AXI < 8 generate
begin
S7_AXI_AWREADY <= '0';
S7_AXI_WREADY <= '0';
S7_AXI_BRESP <= (others=>'0');
S7_AXI_BVALID <= '0';
S7_AXI_ARREADY <= '0';
S7_AXI_RDATA <= (others=>'0');
S7_AXI_RRESP <= (others=>'0');
S7_AXI_RVALID <= '0';
end generate No_AXI_7;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Core
-----------------------------------------------------------------------------
Mutex_Clk <= S0_AXI_ACLK;
Mutex_Rst <= not S0_AXI_ARESETN;
SingleAccess: mutex_core
generic map(
-- General.
C_FAMILY => C_FAMILY,
-- Mutex specific.
C_NUM_INTERFACE => C_NUM_INTERFACE,
C_ENABLE_USER => C_ENABLE_USER,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_ENABLE_HW_PROT => C_ENABLE_HW_PROT,
C_NUM_MUTEX => C_NUM_MUTEX,
C_MUTEX_NUMBER => 0,
C_AWIDTH => C_AWIDTH,
C_REGISTER_WIDTH => C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH,
C_DWIDTH_MUTEX => C_DWIDTH_MUTEX
)
port map(
-- System signals
Clk => Mutex_Clk,
Rst => Mutex_Rst,
-- Bus slave signals
Mutex_Access => Mutex_Access,
Mutex_RnW => Mutex_RnW,
Mutex_HW_Id => Mutex_HW_Id,
Mutex_Addr => Mutex_Addr,
Mutex_Wr_Data => Mutex_Wr_Data,
Mutex_Rd_Data => Mutex_Rd_Data_I,
Mutex_Ack => Mutex_Ack
);
-- Distribute result to all interfaces.
If_Num_Distr: for I in 0 to C_NUM_INTERFACE - 1 generate
begin
Mutex_Rd_Data(I * C_DWIDTH to (I + 1) * C_DWIDTH - 1) <= Mutex_Rd_Data_I;
end generate If_Num_Distr;
end architecture IMP;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ipshared/c931/hdl/internoc_ni_axi_master_v1_0.vhd
|
2
|
12458
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity internoc_ni_axi_master_v1_0 is
generic (
-- Users to add parameters here
C_IF00_DATA_WIDTH : integer := 8;
C_PACKET_WIDTH : integer := 40;
C_PACKET_CTRL_WIDTH : integer := 3;
C_PACKET_ADDR_WIDTH : integer := 5;
C_PACKET_DATA_WIDTH : integer := 32;
C_AXI_PACKET_ADDR_OFFSET : integer := 16;
C_M00_AXI_ADDR_WIDTH : integer := 32;
C_M00_SELF_ADDR : integer := 10;
C_TIMEOUT_PERIOD : integer := 65535
);
port (
-- Users to add ports here
if00_data_in : in std_logic_vector(C_IF00_DATA_WIDTH-1 downto 0);
if00_load_in : in std_logic;
if00_data_out : out std_logic_vector(C_IF00_DATA_WIDTH-1 downto 0);
if00_load_out : out std_logic;
if00_send_done : in std_logic;
if00_send_busy : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Master Bus Interface M00_AXI;
m00_axi_aclk : in std_logic;
m00_axi_aresetn : in std_logic;
m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_awprot : out std_logic_vector(2 downto 0);
m00_axi_awvalid : out std_logic;
m00_axi_awready : in std_logic;
m00_axi_wdata : out std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0);
m00_axi_wstrb : out std_logic_vector(C_PACKET_DATA_WIDTH/8-1 downto 0);
m00_axi_wvalid : out std_logic;
m00_axi_wready : in std_logic;
m00_axi_bresp : in std_logic_vector(1 downto 0);
m00_axi_bvalid : in std_logic;
m00_axi_bready : out std_logic;
m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_arprot : out std_logic_vector(2 downto 0);
m00_axi_arvalid : out std_logic;
m00_axi_arready : in std_logic;
m00_axi_rdata : in std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0);
m00_axi_rresp : in std_logic_vector(1 downto 0);
m00_axi_rvalid : in std_logic;
m00_axi_rready : out std_logic
);
end internoc_ni_axi_master_v1_0;
architecture arch_imp of internoc_ni_axi_master_v1_0 is
-- component declaration
component internoc_ni_axi_master_v1_0_M00_AXI is
generic (
C_IF00_DATA_WIDTH : integer;
C_PACKET_WIDTH : integer;
C_PACKET_ADDR_WIDTH : integer;
C_PACKET_DATA_WIDTH : integer;
C_AXI_PACKET_ADDR_OFFSET : integer;
C_M_AXI_DATA_WIDTH : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_PACKET_CTRL_WIDTH : integer
);
port (
PACKET_TX : in std_logic_vector(C_PACKET_WIDTH-1 downto 0);
RXN_DATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
SLV_TYPE : in std_logic_vector(2 downto 0);
INIT_AXI_TXN : in std_logic;
INIT_AXI_RXN : in std_logic;
ERROR : out std_logic;
TXN_DONE : out std_logic;
RXN_DONE : out std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component internoc_ni_axi_master_v1_0_M00_AXI;
component internoc_interface_type_map is
Port (
clk_i : in STD_LOGIC;
addr_i : in STD_LOGIC_VECTOR (4 downto 0);
type_o : out STD_LOGIC_VECTOR (2 downto 0);
mode_o : out STD_LOGIC
);
end component internoc_interface_type_map;
--Counters
signal next_body_count, current_body_count : unsigned(2 downto 0) := (others=>'0');
signal next_timeout_count, current_timeout_count : integer range 0 to C_TIMEOUT_PERIOD := 0;
--Buffers
signal next_packet, current_packet : std_logic_vector(C_PACKET_WIDTH-1 downto 0) := (others=>'0');
signal next_head, current_head : unsigned(C_IF00_DATA_WIDTH-1 downto 0) := (others=>'0');
signal next_body, current_body : unsigned(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
signal next_axi_data, current_axi_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
--Control signals
signal current_interface_mode : std_logic := '0';
signal current_interface_type : std_logic_vector(2 downto 0) := (others=>'0');
signal next_if00_load, current_if00_load : std_logic := '0';
signal next_init_axi_tx, current_init_axi_tx : std_logic := '0';
signal next_init_axi_rx, current_init_axi_rx : std_logic := '0';
type protocol_state is
(
ST_IDLE,
ST_RX_HEAD,
ST_RX_BODY,
ST_PACK,
ST_AXI_INIT,
ST_AXI_RESP,
ST_TX_DATA,
ST_TX_WAIT,
ST_RESET
);
signal current_state, next_state : protocol_state;
--AXI
signal axi_read_done : std_logic := '0';
signal axi_write_done : std_logic := '0';
signal axi_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
--Aliases
alias header_access : unsigned(0 downto 0) is current_head(C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-1 downto C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-1);
alias header_bytes : unsigned(C_PACKET_CTRL_WIDTH-2 downto 0) is current_head(C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-2 downto C_PACKET_ADDR_WIDTH);
alias packet_access : std_logic is current_packet(C_PACKET_WIDTH-1);
alias packet_bytes : std_logic_vector(C_PACKET_CTRL_WIDTH-2 downto 0) is current_packet(C_PACKET_WIDTH-2 downto C_PACKET_ADDR_WIDTH+C_PACKET_DATA_WIDTH);
alias packet_address : std_logic_vector is current_packet(C_PACKET_WIDTH-C_PACKET_CTRL_WIDTH-1 downto C_PACKET_DATA_WIDTH);
alias packet_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) is current_packet(C_PACKET_DATA_WIDTH-1 downto 0);
begin
-- User logic
seq_logic: process(m00_axi_aclk)
begin
if rising_edge(m00_axi_aclk) then
if (m00_axi_aresetn='0') then
current_state <= ST_RESET;
else
-- Register control signals
current_state <= next_state;
current_init_axi_rx <= next_init_axi_rx;
current_init_axi_tx <= next_init_axi_tx;
current_axi_data <= next_axi_data;
current_packet <= next_packet;
current_body_count <= next_body_count;
current_head <= next_head;
current_body <= next_body;
current_timeout_count <= next_timeout_count;
-- Register interface load pulse
next_if00_load <= if00_load_in;
current_if00_load <= next_if00_load;
end if;
end if;
end process;
comb_logic: process(m00_axi_aclk)
begin
-- Avoid latches
next_state <= current_state;
next_init_axi_rx <= current_init_axi_rx;
next_init_axi_tx <= current_init_axi_tx;
next_axi_data <= current_axi_data;
next_packet <= current_packet;
next_body_count <= current_body_count;
next_head <= current_head;
next_body <= current_body;
next_timeout_count <= current_timeout_count;
if00_load_out <= '0';
-- Drive FSM
case current_state is
when ST_IDLE=>
if00_load_out <= '0';
if00_data_out <= (others=>'0');
if (current_if00_load='0' and next_if00_load='1') then --TODO:check for valid address
next_head <= unsigned(if00_data_in);
next_state <= ST_RX_HEAD;
end if;
when ST_RX_HEAD=>
next_body_count <= resize(header_bytes, 3)+1;
next_state <= ST_RX_BODY;
when ST_RX_BODY=>
if (current_body_count=0) then
next_state <= ST_PACK;
else
if (current_if00_load='0' and next_if00_load='1') then
next_timeout_count <= 0;
case current_body_count is
when "001"=>
next_body(7 downto 0) <= unsigned(if00_data_in);
when "010"=>
next_body(15 downto 8) <= unsigned(if00_data_in);
when "011"=>
next_body(23 downto 16) <= unsigned(if00_data_in);
when "100"=>
next_body(31 downto 24) <= unsigned(if00_data_in);
when others=>
next_state <= ST_RESET;
end case;
next_body_count <= current_body_count - 1;
else
if (current_timeout_count = C_TIMEOUT_PERIOD-1) then
next_timeout_count <= 0;
next_state <= ST_RESET;
else
next_timeout_count <= current_timeout_count + 1;
end if;
end if;
end if;
when ST_PACK=>
next_packet <= std_logic_vector(current_head) & std_logic_vector(current_body);
next_state <= ST_AXI_INIT;
when ST_AXI_INIT=>
if (packet_access='1') then
next_init_axi_rx <= '1';
else
next_init_axi_tx <= '1';
end if;
if (current_init_axi_rx='1') then
next_init_axi_rx <= '0';
next_state <= ST_AXI_RESP;
end if;
if (current_init_axi_tx='1') then
next_init_axi_tx <= '0';
next_state <= ST_AXI_RESP;
end if;
when ST_AXI_RESP=>
if (axi_write_done='1') then
next_state <= ST_IDLE;
next_head <= (others=>'0');
next_body <= (others=>'0');
next_packet <= (others=>'0');
end if;
if (axi_read_done='1') then
next_state <= ST_TX_DATA;
next_body_count <= resize(unsigned(packet_bytes), 3)+1;
next_axi_data <= axi_data;
end if;
when ST_TX_DATA=>
if (current_body_count=0) then
next_state <= ST_IDLE;
next_head <= (others=>'0');
next_body <= (others=>'0');
next_packet <= (others=>'0');
else
if (if00_send_busy='0' and if00_send_done='0') then
if00_load_out <= '1';
case current_body_count is
when "001"=>
if00_data_out <= current_axi_data(7 downto 0);
when "010"=>
if00_data_out <= current_axi_data(15 downto 8);
when "011"=>
if00_data_out <= current_axi_data(23 downto 16);
when "100"=>
if00_data_out <= current_axi_data(31 downto 24);
when others=>
if00_data_out <= (others=>'0');
end case;
next_body_count <= current_body_count - 1;
next_state <= ST_TX_WAIT;
end if;
end if;
when ST_TX_WAIT=>
if (if00_send_busy='0') then
if00_load_out <= '1';
end if;
if (if00_send_done='1') then
next_state <= ST_TX_DATA;
end if;
when ST_RESET=>
if00_data_out <= (others=>'0');
next_init_axi_rx <= '0';
next_init_axi_tx <= '0';
next_axi_data <= (others=>'0');
next_packet <= (others=>'0');
next_body_count <= (others=>'0');
next_head <= (others=>'0');
next_body <= (others=>'0');
next_timeout_count <= 0;
next_state <= ST_IDLE;
end case;
end process;
-- Instantiations
internoc_interface_type_map_inst: internoc_interface_type_map
port map (
clk_i => m00_axi_aclk,
addr_i => packet_address,
type_o => current_interface_type,
mode_o => current_interface_mode
);
internoc_ni_axi_master_v1_0_M00_AXI_inst : internoc_ni_axi_master_v1_0_M00_AXI
generic map (
C_IF00_DATA_WIDTH => C_IF00_DATA_WIDTH,
C_PACKET_WIDTH => C_PACKET_WIDTH,
C_PACKET_ADDR_WIDTH => C_PACKET_ADDR_WIDTH,
C_PACKET_DATA_WIDTH => C_PACKET_DATA_WIDTH,
C_PACKET_CTRL_WIDTH => C_PACKET_CTRL_WIDTH,
C_AXI_PACKET_ADDR_OFFSET => C_AXI_PACKET_ADDR_OFFSET,
C_M_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_PACKET_DATA_WIDTH
)
port map (
PACKET_TX => current_packet,
RXN_DATA => axi_data,
SLV_TYPE => current_interface_type,
INIT_AXI_RXN => current_init_axi_rx,
INIT_AXI_TXN => current_init_axi_tx,
TXN_DONE => axi_write_done,
RXN_DONE => axi_read_done,
M_AXI_ACLK => m00_axi_aclk,
M_AXI_ARESETN => m00_axi_aresetn,
M_AXI_AWADDR => m00_axi_awaddr,
M_AXI_AWPROT => m00_axi_awprot,
M_AXI_AWVALID => m00_axi_awvalid,
M_AXI_AWREADY => m00_axi_awready,
M_AXI_WDATA => m00_axi_wdata,
M_AXI_WSTRB => m00_axi_wstrb,
M_AXI_WVALID => m00_axi_wvalid,
M_AXI_WREADY => m00_axi_wready,
M_AXI_BRESP => m00_axi_bresp,
M_AXI_BVALID => m00_axi_bvalid,
M_AXI_BREADY => m00_axi_bready,
M_AXI_ARADDR => m00_axi_araddr,
M_AXI_ARPROT => m00_axi_arprot,
M_AXI_ARVALID => m00_axi_arvalid,
M_AXI_ARREADY => m00_axi_arready,
M_AXI_RDATA => m00_axi_rdata,
M_AXI_RRESP => m00_axi_rresp,
M_AXI_RVALID => m00_axi_rvalid,
M_AXI_RREADY => m00_axi_rready
);
end arch_imp;
|
mit
|
egk696/InterNoC
|
InterNoC.ip_user_files/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_1_0/sim/DemoInterconnect_axi_spi_master_1_0.vhd
|
2
|
10931
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
mit
|
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_uart_transceiver_0_0/sim/DemoInterconnect_uart_transceiver_0_0.vhd
|
2
|
4296
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
mit
|
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/serial2parallel.vhd
|
3
|
2755
|
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity byte2word is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end byte2word;
architecture behave of byte2word is
signal shift_count : integer range 0 to 7 := 0;
signal rx_done : std_logic := '0';
signal shift_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of shift_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
else
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end if;
end process;
shift_in: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_data <= (others=>'0');
else
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(DATA_WIDTH-8-1 downto 0) & shift_i;
end if;
end if;
end if;
end process;
count_shift: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
rx_done <= '0';
else
if rx_en = '1' and rx_done='0' then
if shift_count = to_integer(unsigned(shift_cnt_i))-1 then
rx_done <= '1';
shift_count <= 0;
else
shift_count <= shift_count + 1;
end if;
else
rx_done <= '0';
end if;
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ;
|
mit
|
tjyrz/vhdl_fft
|
counter.vhd
|
3
|
1144
|
----------------------------------------------------
-- VHDL code for n-bit counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0) := (others => '0');
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= (Pre_Q'range => '0');
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
-----------------------------------------------------
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_rsftpipe32_sv.vhd
|
20
|
4318
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/dp_addpipe.vhd
|
10
|
2509
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - CORE LEVEL ***
--*** ***
--*** DP_ADDPIPE.VHD ***
--*** ***
--*** Function: Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_addpipe;
ARCHITECTURE syn of dp_addpipe IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_expm1_s5.vhd
|
10
|
553434
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_expm1_s5
-- VHDL created on Wed Apr 17 13:39:27 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_expm1_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_expm1_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid8_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstZeroWE_uid11_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstZeroWEP1_uid12_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal cstBiasPWE_uid13_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid15_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid16_fpExpEM1Test_q : std_logic_vector (5 downto 0);
signal cstAllOWE_uid17_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid18_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal cstFPLogZpf_uid35_fpExpEM1Test_q : std_logic_vector (31 downto 0);
signal onesCmpFxpInX_uid42_fpExpEM1Test_a : std_logic_vector(24 downto 0);
signal onesCmpFxpInX_uid42_fpExpEM1Test_b : std_logic_vector(24 downto 0);
signal onesCmpFxpInX_uid42_fpExpEM1Test_q_i : std_logic_vector(24 downto 0);
signal onesCmpFxpInX_uid42_fpExpEM1Test_q : std_logic_vector(24 downto 0);
signal onesCmpFxpIn_uid57_fpExpEM1Test_a : std_logic_vector(33 downto 0);
signal onesCmpFxpIn_uid57_fpExpEM1Test_b : std_logic_vector(33 downto 0);
signal onesCmpFxpIn_uid57_fpExpEM1Test_q_i : std_logic_vector(33 downto 0);
signal onesCmpFxpIn_uid57_fpExpEM1Test_q : std_logic_vector(33 downto 0);
signal zY_uid68_fpExpEM1Test_q : std_logic_vector (25 downto 0);
signal expRPostBiasPreExc0_uid77_fpExpEM1Test_a : std_logic_vector(12 downto 0);
signal expRPostBiasPreExc0_uid77_fpExpEM1Test_b : std_logic_vector(12 downto 0);
signal expRPostBiasPreExc0_uid77_fpExpEM1Test_o : std_logic_vector (12 downto 0);
signal expRPostBiasPreExc0_uid77_fpExpEM1Test_q : std_logic_vector (11 downto 0);
signal expUnderflow_uid83_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal expUnderflow_uid83_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal expUnderflow_uid83_fpExpEM1Test_c : std_logic_vector(0 downto 0);
signal expUnderflow_uid83_fpExpEM1Test_q_i : std_logic_vector(0 downto 0);
signal expUnderflow_uid83_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expUndeflowCondition_uid85_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal expUndeflowCondition_uid85_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal expUndeflowCondition_uid85_fpExpEM1Test_q_i : std_logic_vector(0 downto 0);
signal expUndeflowCondition_uid85_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal cstTabWidth_uid90_fpExpEM1Test_q : std_logic_vector (4 downto 0);
signal addrDecTable_uid93_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal addrDecTable_uid93_fpExpEM1Test_q : std_logic_vector (4 downto 0);
signal normFracRPosPost_uid105_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal normFracRPosPost_uid105_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal invUdfBitSubPos_uid106_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal invUdfBitSubPos_uid106_fpExpEM1Test_q_i : std_logic_vector(0 downto 0);
signal invUdfBitSubPos_uid106_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal negBranchFrac_uid123_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal negBranchFrac_uid123_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal negBranchExp_uid124_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal negBranchExp_uid124_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal prod2_uid132_fpExpEM1Test_a : std_logic_vector (23 downto 0);
signal prod2_uid132_fpExpEM1Test_b : std_logic_vector (25 downto 0);
signal prod2_uid132_fpExpEM1Test_s1 : std_logic_vector (49 downto 0);
signal prod2_uid132_fpExpEM1Test_pr : UNSIGNED (49 downto 0);
signal prod2_uid132_fpExpEM1Test_q : std_logic_vector (49 downto 0);
signal branchSelEnc_uid152_fpExpEM1Test_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid164_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal p4_uid179_constMult_q : std_logic_vector(31 downto 0);
signal p2_uid181_constMult_q : std_logic_vector(24 downto 0);
signal lev1_a0_uid184_constMult_a : std_logic_vector(33 downto 0);
signal lev1_a0_uid184_constMult_b : std_logic_vector(33 downto 0);
signal lev1_a0_uid184_constMult_o : std_logic_vector (33 downto 0);
signal lev1_a0_uid184_constMult_q : std_logic_vector (32 downto 0);
signal lev2_a0_uid186_constMult_a : std_logic_vector(34 downto 0);
signal lev2_a0_uid186_constMult_b : std_logic_vector(34 downto 0);
signal lev2_a0_uid186_constMult_o : std_logic_vector (34 downto 0);
signal lev2_a0_uid186_constMult_q : std_logic_vector (33 downto 0);
signal z_uid191_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (15 downto 0);
signal z_uid195_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid199_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(36 downto 0);
signal rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(36 downto 0);
signal rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(36 downto 0);
signal rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(36 downto 0);
signal z_uid203_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(7 downto 0);
signal z_uid211_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (11 downto 0);
signal rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(11 downto 0);
signal rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal z_uid221_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(1 downto 0);
signal z_uid225_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (2 downto 0);
signal rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q_i : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(2 downto 0);
signal p1_uid234_constMult_q : std_logic_vector(44 downto 0);
signal rightShiftStage0Idx3_uid248_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(33 downto 0);
signal rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(33 downto 0);
signal rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(33 downto 0);
signal rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(33 downto 0);
signal rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(11 downto 0);
signal rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(2 downto 0);
signal memoryC0_uid281_exp10TabGen_q : std_logic_vector(28 downto 0);
signal memoryC1_uid283_exp10TabGen_q : std_logic_vector(21 downto 0);
signal memoryC2_uid285_exp10TabGen_q : std_logic_vector(13 downto 0);
signal rightShiftStage0Idx3Pad24_uid308_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid319_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal prodXY_uid348_pT1_uid288_exp10PolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid348_pT1_uid288_exp10PolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid348_pT1_uid288_exp10PolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid348_pT1_uid288_exp10PolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid348_pT1_uid288_exp10PolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid351_pT2_uid294_exp10PolyEval_a : std_logic_vector (18 downto 0);
signal prodXY_uid351_pT2_uid294_exp10PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid351_pT2_uid294_exp10PolyEval_s1 : std_logic_vector (42 downto 0);
signal prodXY_uid351_pT2_uid294_exp10PolyEval_pr : SIGNED (43 downto 0);
signal prodXY_uid351_pT2_uid294_exp10PolyEval_q : std_logic_vector (42 downto 0);
signal prodXY_uid354_pT1_uid336_expm1PE2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid354_pT1_uid336_expm1PE2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid354_pT1_uid336_expm1PE2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid354_pT1_uid336_expm1PE2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid354_pT1_uid336_expm1PE2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid357_pT2_uid342_expm1PE2PolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid357_pT2_uid342_expm1PE2PolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid357_pT2_uid342_expm1PE2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid357_pT2_uid342_expm1PE2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid357_pT2_uid342_expm1PE2PolyEval_q : std_logic_vector (38 downto 0);
signal memoryC0_uid329_expm1PE2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid329_expm1PE2TabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid329_expm1PE2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid329_expm1PE2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid329_expm1PE2TabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid329_expm1PE2TabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid331_expm1PE2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid331_expm1PE2TabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid331_expm1PE2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid331_expm1PE2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid331_expm1PE2TabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid331_expm1PE2TabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid333_expm1PE2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid333_expm1PE2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid333_expm1PE2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid333_expm1PE2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid333_expm1PE2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid333_expm1PE2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0_q : std_logic_vector (8 downto 0);
signal reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1_q : std_logic_vector (0 downto 0);
signal reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0_q : std_logic_vector (0 downto 0);
signal reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2_q : std_logic_vector (36 downto 0);
signal reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q : std_logic_vector (10 downto 0);
signal reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q : std_logic_vector (33 downto 0);
signal reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3_q : std_logic_vector (33 downto 0);
signal reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4_q : std_logic_vector (33 downto 0);
signal reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q : std_logic_vector (33 downto 0);
signal reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q : std_logic_vector (33 downto 0);
signal reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0_q : std_logic_vector (4 downto 0);
signal reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0_q : std_logic_vector (41 downto 0);
signal reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1_q : std_logic_vector (42 downto 0);
signal reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1_q : std_logic_vector (0 downto 0);
signal reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_q : std_logic_vector (18 downto 0);
signal reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q : std_logic_vector (12 downto 0);
signal reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q : std_logic_vector (2 downto 0);
signal reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q : std_logic_vector (0 downto 0);
signal reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_q : std_logic_vector (7 downto 0);
signal reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_q : std_logic_vector (2 downto 0);
signal reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0_q : std_logic_vector (8 downto 0);
signal reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0_q : std_logic_vector (24 downto 0);
signal reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1_q : std_logic_vector (23 downto 0);
signal reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0_q : std_logic_vector (24 downto 0);
signal reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_q : std_logic_vector (23 downto 0);
signal reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1_q : std_logic_vector (25 downto 0);
signal reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q : std_logic_vector (7 downto 0);
signal reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2_q : std_logic_vector (7 downto 0);
signal reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_q : std_logic_vector (7 downto 0);
signal reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid23_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_InvFracXIsZero_uid27_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_InvExpXIsZero_uid31_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_I_uid30_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_q : std_logic_vector (7 downto 0);
signal ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c_q : std_logic_vector (5 downto 0);
signal ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_yRedPostMux_uid70_fpExpEM1Test_q_to_yPPolyEval_uid73_fpExpEM1Test_a_q : std_logic_vector (25 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c_q : std_logic_vector (0 downto 0);
signal ld_reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q_to_regInAndUndeflowExp_uid84_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_expUnderflow_uid83_fpExpEM1Test_q_to_expUndeflowCondition_uid85_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_tableAddrPos_uid92_fpExpEM1Test_b_to_addrDecTable_uid93_fpExpEM1Test_c_q : std_logic_vector (4 downto 0);
signal ld_fracR_uid79_fpExpEM1Test_b_to_zOFracRExp_uid97_fpExpEM1Test_a_q : std_logic_vector (22 downto 0);
signal ld_lowRangeB_uid98_fpExpEM1Test_b_to_zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q_to_expRPosPost_uid107_fpExpEM1Test_a_q : std_logic_vector (7 downto 0);
signal ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c_q : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_addrPE2FusedClose_uid128_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_q : std_logic_vector (23 downto 0);
signal ld_InvSignX_uid144_fpExpEM1Test_q_to_posFarBranch_uid145_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_posCloseBranch0_uid148_fpExpEM1Test_n_to_posCloseBranch_uid150_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_posCloseBranch_uid150_fpExpEM1Test_q_to_concBranch_uid151_fpExpEM1Test_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f_q : std_logic_vector (7 downto 0);
signal ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c_q : std_logic_vector (22 downto 0);
signal ld_expOvfInitial_uid49_fpExpEM1Test_b_to_InvExpOvfInitial_uid157_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid32_fpExpEM1Test_q_to_regInAndOvf_uid158_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid26_fpExpEM1Test_q_to_posInf_uid160_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid160_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid28_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_c_q : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a_q : std_logic_vector (2 downto 0);
signal ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_a_q : std_logic_vector (32 downto 0);
signal ld_RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_a_q : std_logic_vector (28 downto 0);
signal ld_RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_a_q : std_logic_vector (24 downto 0);
signal ld_rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_a_q : std_logic_vector (34 downto 0);
signal ld_RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_a_q : std_logic_vector (33 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d_q : std_logic_vector (36 downto 0);
signal ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q : std_logic_vector (29 downto 0);
signal ld_RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q : std_logic_vector (25 downto 0);
signal ld_RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q : std_logic_vector (21 downto 0);
signal ld_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q : std_logic_vector (31 downto 0);
signal ld_RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q : std_logic_vector (30 downto 0);
signal ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d_q : std_logic_vector (33 downto 0);
signal ld_reg_addr_uid72_fpExpEM1Test_0_to_memoryC1_uid283_exp10TabGen_0_q_to_memoryC1_uid283_exp10TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q : std_logic_vector (18 downto 0);
signal ld_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC1_uid331_expm1PE2TabGen_lutmem_0_q_to_memoryC1_uid331_expm1PE2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_xv2_uid176_constMult_b_to_reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_expR_uid87_fpExpEM1Test_b_to_reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_a_q : std_logic_vector (7 downto 0);
signal ld_concBranch_uid151_fpExpEM1Test_q_to_reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_a_q : std_logic_vector (2 downto 0);
signal ld_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q : std_logic_vector (0 downto 0);
signal ld_expBranchClosePos_uid139_fpExpEM1Test_b_to_reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_a_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q : signal is true;
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_inputreg_q : std_logic_vector (10 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_eq : std_logic;
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_eq : std_logic;
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_eq : std_logic;
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_reset0 : std_logic;
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q : signal is true;
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_eq : std_logic;
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q : signal is true;
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_reset0 : std_logic;
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_eq : std_logic;
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_mem_top_q : std_logic_vector (5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_inputreg_q : std_logic_vector (18 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_inputreg_q : std_logic_vector (16 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ia : std_logic_vector (16 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_iq : std_logic_vector (16 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_q : std_logic_vector (16 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid50_fpExpEM1Test_a : std_logic_vector(11 downto 0);
signal shiftUdf_uid50_fpExpEM1Test_b : std_logic_vector(11 downto 0);
signal shiftUdf_uid50_fpExpEM1Test_o : std_logic_vector (11 downto 0);
signal shiftUdf_uid50_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid50_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid80_fpExpEM1Test_a : std_logic_vector(15 downto 0);
signal expUdf_uid80_fpExpEM1Test_b : std_logic_vector(15 downto 0);
signal expUdf_uid80_fpExpEM1Test_o : std_logic_vector (15 downto 0);
signal expUdf_uid80_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid80_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid82_fpExpEM1Test_a : std_logic_vector(15 downto 0);
signal expOvf_uid82_fpExpEM1Test_b : std_logic_vector(15 downto 0);
signal expOvf_uid82_fpExpEM1Test_o : std_logic_vector (15 downto 0);
signal expOvf_uid82_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid82_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal expSatValue_uid91_fpExpEM1Test_a : std_logic_vector(11 downto 0);
signal expSatValue_uid91_fpExpEM1Test_b : std_logic_vector(11 downto 0);
signal expSatValue_uid91_fpExpEM1Test_o : std_logic_vector (11 downto 0);
signal expSatValue_uid91_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal expSatValue_uid91_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal negShiftValueSaturate0_uid112_fpExpEM1Test_a : std_logic_vector(11 downto 0);
signal negShiftValueSaturate0_uid112_fpExpEM1Test_b : std_logic_vector(11 downto 0);
signal negShiftValueSaturate0_uid112_fpExpEM1Test_o : std_logic_vector (11 downto 0);
signal negShiftValueSaturate0_uid112_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal negShiftValueSaturate0_uid112_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal pad_o_uid9_uid118_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal oFracXZwE_uid56_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal zOFracRExp_uid97_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal InvSignX_uid144_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid144_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid157_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid157_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal expX_uid6_fpExpEM1Test_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpExpEM1Test_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpExpEM1Test_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal frac_uid24_fpExpEM1Test_in : std_logic_vector (22 downto 0);
signal frac_uid24_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid21_fpExpEM1Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid21_fpExpEM1Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid21_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid23_fpExpEM1Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid23_fpExpEM1Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid23_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid25_fpExpEM1Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid25_fpExpEM1Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid25_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid26_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid26_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid26_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal exc_N_uid28_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid28_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid28_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal fxpInExtX_uid43_fpExpEM1Test_a : std_logic_vector(26 downto 0);
signal fxpInExtX_uid43_fpExpEM1Test_b : std_logic_vector(26 downto 0);
signal fxpInExtX_uid43_fpExpEM1Test_o : std_logic_vector (26 downto 0);
signal fxpInExtX_uid43_fpExpEM1Test_q : std_logic_vector (25 downto 0);
signal shiftValuePreSat_uid48_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid48_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid48_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal shiftValuePreSat_uid48_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal shiftVal_uid52_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid52_fpExpEM1Test_q : std_logic_vector (5 downto 0);
signal fxpInExt_uid58_fpExpEM1Test_a : std_logic_vector(35 downto 0);
signal fxpInExt_uid58_fpExpEM1Test_b : std_logic_vector(35 downto 0);
signal fxpInExt_uid58_fpExpEM1Test_o : std_logic_vector (35 downto 0);
signal fxpInExt_uid58_fpExpEM1Test_q : std_logic_vector (34 downto 0);
signal yExt_uid65_fpExpEM1Test_a : std_logic_vector(43 downto 0);
signal yExt_uid65_fpExpEM1Test_b : std_logic_vector(43 downto 0);
signal yExt_uid65_fpExpEM1Test_o : std_logic_vector (43 downto 0);
signal yExt_uid65_fpExpEM1Test_q : std_logic_vector (43 downto 0);
signal yRedPostMux_uid70_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal yRedPostMux_uid70_fpExpEM1Test_q : std_logic_vector (25 downto 0);
signal expRPostBiasPreExc_uid78_fpExpEM1Test_a : std_logic_vector(13 downto 0);
signal expRPostBiasPreExc_uid78_fpExpEM1Test_b : std_logic_vector(13 downto 0);
signal expRPostBiasPreExc_uid78_fpExpEM1Test_o : std_logic_vector (13 downto 0);
signal expRPostBiasPreExc_uid78_fpExpEM1Test_q : std_logic_vector (12 downto 0);
signal regInAndUndeflowExp_uid84_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal regInAndUndeflowExp_uid84_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal regInAndUndeflowExp_uid84_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expR_uid88_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal expR_uid88_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal tableAddrPosExt_uid89_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal tableAddrPosExt_uid89_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal tableAddrPosExt_uid89_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal tableAddrPosExt_uid89_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal subDecrementMask_uid94_fpExpEM1Test_q : std_logic_vector(19 downto 0);
signal subDecrementMask_uid95_fpExpEM1Test_q : std_logic_vector(4 downto 0);
signal sumAHighB_uid100_fpExpEM1Test_a : std_logic_vector(25 downto 0);
signal sumAHighB_uid100_fpExpEM1Test_b : std_logic_vector(25 downto 0);
signal sumAHighB_uid100_fpExpEM1Test_o : std_logic_vector (25 downto 0);
signal sumAHighB_uid100_fpExpEM1Test_q : std_logic_vector (25 downto 0);
signal expRPosPost_uid107_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal expRPosPost_uid107_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal expRPosPost_uid107_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal expRPosPost_uid107_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal shiftAddrPreSaturate_uid110_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal shiftAddrPreSaturate_uid110_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal shiftAddrPreSaturate_uid110_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal shiftAddrPreSaturate_uid110_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal negInf_uid113_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal negInf_uid113_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal negInf_uid113_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal negShiftValueSaturate_uid114_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal negShiftValueSaturate_uid114_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal negShiftValueSaturate_uid114_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal negShiftValAddr_uid116_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal negShiftValAddr_uid116_fpExpEM1Test_q : std_logic_vector (4 downto 0);
signal negBranchFracNotNorm_uid118_fpExpEM1Test_a : std_logic_vector(25 downto 0);
signal negBranchFracNotNorm_uid118_fpExpEM1Test_b : std_logic_vector(25 downto 0);
signal negBranchFracNotNorm_uid118_fpExpEM1Test_o : std_logic_vector (25 downto 0);
signal negBranchFracNotNorm_uid118_fpExpEM1Test_q : std_logic_vector (25 downto 0);
signal posFarBranch0_uid143_fpExpEM1Test_a : std_logic_vector(10 downto 0);
signal posFarBranch0_uid143_fpExpEM1Test_b : std_logic_vector(10 downto 0);
signal posFarBranch0_uid143_fpExpEM1Test_o : std_logic_vector (10 downto 0);
signal posFarBranch0_uid143_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal posFarBranch0_uid143_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal posFarBranch_uid145_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal posFarBranch_uid145_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal posFarBranch_uid145_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal negFarBranch0_uid146_fpExpEM1Test_a : std_logic_vector(10 downto 0);
signal negFarBranch0_uid146_fpExpEM1Test_b : std_logic_vector(10 downto 0);
signal negFarBranch0_uid146_fpExpEM1Test_o : std_logic_vector (10 downto 0);
signal negFarBranch0_uid146_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal negFarBranch0_uid146_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal negFarBranch_uid147_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal negFarBranch_uid147_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal negFarBranch_uid147_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal posCloseBranch0_uid148_fpExpEM1Test_a : std_logic_vector(10 downto 0);
signal posCloseBranch0_uid148_fpExpEM1Test_b : std_logic_vector(10 downto 0);
signal posCloseBranch0_uid148_fpExpEM1Test_o : std_logic_vector (10 downto 0);
signal posCloseBranch0_uid148_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal posCloseBranch0_uid148_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal posCloseBranch_uid150_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal posCloseBranch_uid150_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal posCloseBranch_uid150_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expPostBranchSel_uid153_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal expPostBranchSel_uid153_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal fracPostBranchSel_uid154_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal fracPostBranchSel_uid154_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal regInAndOvf_uid158_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid158_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid158_fpExpEM1Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid158_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal posInf_uid160_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal posInf_uid160_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal posInf_uid160_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid161_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid161_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid161_fpExpEM1Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid161_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid163_fpExpEM1Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid167_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid167_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid171_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid171_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal p3_uid180_constMult_q : std_logic_vector(30 downto 0);
signal p1_uid182_constMult_q : std_logic_vector(18 downto 0);
signal p0_uid183_constMult_q : std_logic_vector(12 downto 0);
signal lev1_a1_uid185_constMult_a : std_logic_vector(25 downto 0);
signal lev1_a1_uid185_constMult_b : std_logic_vector(25 downto 0);
signal lev1_a1_uid185_constMult_o : std_logic_vector (25 downto 0);
signal lev1_a1_uid185_constMult_q : std_logic_vector (25 downto 0);
signal lev3_a0_uid187_constMult_a : std_logic_vector(35 downto 0);
signal lev3_a0_uid187_constMult_b : std_logic_vector(35 downto 0);
signal lev3_a0_uid187_constMult_o : std_logic_vector (35 downto 0);
signal lev3_a0_uid187_constMult_q : std_logic_vector (34 downto 0);
signal rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal p0_uid235_constMult_q : std_logic_vector(39 downto 0);
signal lev1_a0_uid236_constMult_a : std_logic_vector(46 downto 0);
signal lev1_a0_uid236_constMult_b : std_logic_vector(46 downto 0);
signal lev1_a0_uid236_constMult_o : std_logic_vector (46 downto 0);
signal lev1_a0_uid236_constMult_q : std_logic_vector (45 downto 0);
signal rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal expFracCstLogZ5_uid37_fpExpEM1Test_in : std_logic_vector (30 downto 0);
signal expFracCstLogZ5_uid37_fpExpEM1Test_b : std_logic_vector (30 downto 0);
signal normBit2_uid133_fpExpEM1Test_in : std_logic_vector (48 downto 0);
signal normBit2_uid133_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal fracBranchClosePosHigh_uid135_fpExpEM1Test_in : std_logic_vector (47 downto 0);
signal fracBranchClosePosHigh_uid135_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal fracBranchClosePosLow_uid136_fpExpEM1Test_in : std_logic_vector (46 downto 0);
signal fracBranchClosePosLow_uid136_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_in : std_logic_vector (42 downto 0);
signal prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_b : std_logic_vector (22 downto 0);
signal rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal yPPolyEval_uid73_fpExpEM1Test_in : std_logic_vector (18 downto 0);
signal yPPolyEval_uid73_fpExpEM1Test_b : std_logic_vector (18 downto 0);
signal zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_q : std_logic_vector (26 downto 0);
signal yPPolyEval2_uid129_fpExpEM1Test_in : std_logic_vector (16 downto 0);
signal yPPolyEval2_uid129_fpExpEM1Test_b : std_logic_vector (16 downto 0);
signal concBranch_uid151_fpExpEM1Test_q : std_logic_vector (2 downto 0);
signal concExc_uid162_fpExpEM1Test_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid79_fpExpEM1Test_in : std_logic_vector (22 downto 0);
signal fracR_uid79_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal expBranchClosePosExt_uid138_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal expBranchClosePosExt_uid138_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal expBranchClosePosExt_uid138_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal expBranchClosePosExt_uid138_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_q : std_logic_vector(0 downto 0);
signal RExpE_uid172_fpExpEM1Test_q : std_logic_vector (31 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_a : std_logic_vector(5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_b : std_logic_vector(5 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_q : std_logic_vector(0 downto 0);
signal expFracX_uid36_fpExpEM1Test_q : std_logic_vector (30 downto 0);
signal oFracX_uid34_uid34_fpExpEM1Test_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid31_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid31_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid27_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid27_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid30_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid30_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid29_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid29_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal fxpInPreAlign_uid44_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal fxpInPreAlign_uid44_fpExpEM1Test_b : std_logic_vector (24 downto 0);
signal expOvfInitial_uid49_fpExpEM1Test_in : std_logic_vector (8 downto 0);
signal expOvfInitial_uid49_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid51_fpExpEM1Test_in : std_logic_vector (5 downto 0);
signal shiftValuePreSatRed_uid51_fpExpEM1Test_b : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal fxpInPreAlign_uid59_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal fxpInPreAlign_uid59_fpExpEM1Test_b : std_logic_vector (33 downto 0);
signal YExt43_uid67_fpExpEM1Test_in : std_logic_vector (43 downto 0);
signal YExt43_uid67_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal yRed_uid69_fpExpEM1Test_in : std_logic_vector (31 downto 0);
signal yRed_uid69_fpExpEM1Test_b : std_logic_vector (25 downto 0);
signal addr_uid72_fpExpEM1Test_in : std_logic_vector (25 downto 0);
signal addr_uid72_fpExpEM1Test_b : std_logic_vector (6 downto 0);
signal expR_uid87_fpExpEM1Test_in : std_logic_vector (7 downto 0);
signal expR_uid87_fpExpEM1Test_b : std_logic_vector (7 downto 0);
signal tableAddrPos_uid92_fpExpEM1Test_in : std_logic_vector (4 downto 0);
signal tableAddrPos_uid92_fpExpEM1Test_b : std_logic_vector (4 downto 0);
signal os_uid96_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal expRPosPostRange_uid108_fpExpEM1Test_in : std_logic_vector (7 downto 0);
signal expRPosPostRange_uid108_fpExpEM1Test_b : std_logic_vector (7 downto 0);
signal shiftAddrPreSaturateShort_uid115_fpExpEM1Test_in : std_logic_vector (4 downto 0);
signal shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal expNegBranchIsZero_uid120_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal expNegBranchIsZero_uid120_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal negBranchFracNotNormHigh_uid121_fpExpEM1Test_in : std_logic_vector (23 downto 0);
signal negBranchFracNotNormHigh_uid121_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal negBranchFracNotNormLow_uid122_fpExpEM1Test_in : std_logic_vector (22 downto 0);
signal negBranchFracNotNormLow_uid122_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal sR_uid188_constMult_in : std_logic_vector (31 downto 0);
signal sR_uid188_constMult_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (24 downto 0);
signal sR_uid237_constMult_in : std_logic_vector (44 downto 0);
signal sR_uid237_constMult_b : std_logic_vector (42 downto 0);
signal RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (29 downto 0);
signal RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (25 downto 0);
signal RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (21 downto 0);
signal RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (18 downto 0);
signal inCloseBranch_uid38_fpExpEM1Test_a : std_logic_vector(33 downto 0);
signal inCloseBranch_uid38_fpExpEM1Test_b : std_logic_vector(33 downto 0);
signal inCloseBranch_uid38_fpExpEM1Test_o : std_logic_vector (33 downto 0);
signal inCloseBranch_uid38_fpExpEM1Test_cin : std_logic_vector (0 downto 0);
signal inCloseBranch_uid38_fpExpEM1Test_n : std_logic_vector (0 downto 0);
signal fracBranchClosePos_uid137_fpExpEM1Test_s : std_logic_vector (0 downto 0);
signal fracBranchClosePos_uid137_fpExpEM1Test_q : std_logic_vector (22 downto 0);
signal InvNormBit2_uid140_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvNormBit2_uid140_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal lowRangeB_uid289_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid289_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid290_exp10PolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid290_exp10PolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid295_exp10PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid295_exp10PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid296_exp10PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid296_exp10PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid337_expm1PE2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid337_expm1PE2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid338_expm1PE2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid338_expm1PE2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid343_expm1PE2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid343_expm1PE2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid344_expm1PE2PolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid344_expm1PE2PolyEval_b : std_logic_vector (20 downto 0);
signal RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (33 downto 0);
signal ePreRnd_uid54_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal ePreRnd_uid54_fpExpEM1Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (32 downto 0);
signal RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (31 downto 0);
signal RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (30 downto 0);
signal pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_q : std_logic_vector (41 downto 0);
signal yBranchClose_uid125_fpExpEM1Test_in : std_logic_vector (23 downto 0);
signal yBranchClose_uid125_fpExpEM1Test_b : std_logic_vector (23 downto 0);
signal RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (23 downto 0);
signal yT1_uid287_exp10PolyEval_in : std_logic_vector (18 downto 0);
signal yT1_uid287_exp10PolyEval_b : std_logic_vector (13 downto 0);
signal udfBitSubPos_uid102_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal udfBitSubPos_uid102_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal udfBitSubPosHigh_uid103_fpExpEM1Test_in : std_logic_vector (23 downto 0);
signal udfBitSubPosHigh_uid103_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal udfBitSubPosLow_uid104_fpExpEM1Test_in : std_logic_vector (22 downto 0);
signal udfBitSubPosLow_uid104_fpExpEM1Test_b : std_logic_vector (22 downto 0);
signal yT1_uid335_expm1PE2PolyEval_in : std_logic_vector (16 downto 0);
signal yT1_uid335_expm1PE2PolyEval_b : std_logic_vector (11 downto 0);
signal oFracEXZ_uid109_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal expBranchClosePos_uid139_fpExpEM1Test_in : std_logic_vector (7 downto 0);
signal expBranchClosePos_uid139_fpExpEM1Test_b : std_logic_vector (7 downto 0);
signal oFracX_uid41_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal exc_R_uid32_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid32_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid32_fpExpEM1Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid32_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal xv0_uid174_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid174_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid175_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid175_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid176_constMult_in : std_logic_vector (17 downto 0);
signal xv2_uid176_constMult_b : std_logic_vector (5 downto 0);
signal xv3_uid177_constMult_in : std_logic_vector (23 downto 0);
signal xv3_uid177_constMult_b : std_logic_vector (5 downto 0);
signal xv4_uid178_constMult_in : std_logic_vector (24 downto 0);
signal xv4_uid178_constMult_b : std_logic_vector (0 downto 0);
signal regXAndExpOverflowAndPos_uid156_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid156_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid156_fpExpEM1Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (17 downto 0);
signal X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_in : std_logic_vector (33 downto 0);
signal X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector (1 downto 0);
signal lowRangeB_uid98_fpExpEM1Test_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid98_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal highBBits_uid99_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal highBBits_uid99_fpExpEM1Test_b : std_logic_vector (23 downto 0);
signal oFracXZwE_uid47_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal InvInCloseBranch_uid39_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal InvInCloseBranch_uid39_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expBranchCloseNegExt_uid141_fpExpEM1Test_a : std_logic_vector(8 downto 0);
signal expBranchCloseNegExt_uid141_fpExpEM1Test_b : std_logic_vector(8 downto 0);
signal expBranchCloseNegExt_uid141_fpExpEM1Test_o : std_logic_vector (8 downto 0);
signal expBranchCloseNegExt_uid141_fpExpEM1Test_q : std_logic_vector (8 downto 0);
signal sumAHighB_uid291_exp10PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid291_exp10PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid291_exp10PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid291_exp10PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid297_exp10PolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid297_exp10PolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid297_exp10PolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid297_exp10PolyEval_q : std_logic_vector (29 downto 0);
signal sumAHighB_uid339_expm1PE2PolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid339_expm1PE2PolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid339_expm1PE2PolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid339_expm1PE2PolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid345_expm1PE2PolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid345_expm1PE2PolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid345_expm1PE2PolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid345_expm1PE2PolyEval_q : std_logic_vector (29 downto 0);
signal rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal xv0_uid232_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid232_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid233_constMult_in : std_logic_vector (10 downto 0);
signal xv1_uid233_constMult_b : std_logic_vector (4 downto 0);
signal rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal addrPE2_uid127_fpExpEM1Test_in : std_logic_vector (23 downto 0);
signal addrPE2_uid127_fpExpEM1Test_b : std_logic_vector (6 downto 0);
signal rightShiftStage2Idx1_uid325_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (16 downto 0);
signal X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (8 downto 0);
signal X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_in : std_logic_vector (24 downto 0);
signal X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_q : std_logic_vector (33 downto 0);
signal msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (20 downto 0);
signal X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_in : std_logic_vector (36 downto 0);
signal X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector (4 downto 0);
signal oneSComplementOption_uid40_fpExpEM1Test_a : std_logic_vector(0 downto 0);
signal oneSComplementOption_uid40_fpExpEM1Test_b : std_logic_vector(0 downto 0);
signal oneSComplementOption_uid40_fpExpEM1Test_q : std_logic_vector(0 downto 0);
signal expBranchCloseNeg_uid142_fpExpEM1Test_in : std_logic_vector (7 downto 0);
signal expBranchCloseNeg_uid142_fpExpEM1Test_b : std_logic_vector (7 downto 0);
signal s1_uid289_uid292_exp10PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid295_uid298_exp10PolyEval_q : std_logic_vector (31 downto 0);
signal s1_uid337_uid340_expm1PE2PolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid343_uid346_expm1PE2PolyEval_q : std_logic_vector (31 downto 0);
signal addrPE2FusedClose_uid128_fpExpEM1Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_q : std_logic_vector (36 downto 0);
signal peOR_uid75_fpExpEM1Test_in : std_logic_vector (28 downto 0);
signal peOR_uid75_fpExpEM1Test_b : std_logic_vector (23 downto 0);
signal peORExpInc_uid76_fpExpEM1Test_in : std_logic_vector (29 downto 0);
signal peORExpInc_uid76_fpExpEM1Test_b : std_logic_vector (0 downto 0);
signal pe2OR_uid131_fpExpEM1Test_in : std_logic_vector (29 downto 0);
signal pe2OR_uid131_fpExpEM1Test_b : std_logic_vector (25 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable(LOGICAL,903)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_a <= en;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q <= not ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_a;
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor(LOGICAL,1005)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_b <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_q <= not (ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_a or ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_b);
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_mem_top(CONSTANT,1001)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_mem_top_q <= "011010";
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp(LOGICAL,1002)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_a <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_mem_top_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q);
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_q <= "1" when ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_a = ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_b else "0";
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg(REG,1003)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena(REG,1006)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_nor_q = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd(LOGICAL,1007)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_a <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_sticky_ena_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_b <= en;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_a and ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_b;
--signX_uid7_fpExpEM1Test(BITSELECT,6)@0
signX_uid7_fpExpEM1Test_in <= a;
signX_uid7_fpExpEM1Test_b <= signX_uid7_fpExpEM1Test_in(31 downto 31);
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg(DELAY,958)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExpEM1Test_b, xout => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt(COUNTER,997)
-- every=1, low=0, high=26, step=1, init=1
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i = 25 THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_eq <= '1';
ELSE
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_eq = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i - 26;
ELSE
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_i,5));
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg(REG,998)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux(MUX,999)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_s <= en;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux: PROCESS (ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_s, ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q, ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_q)
BEGIN
CASE ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_s IS
WHEN "0" => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q;
WHEN "1" => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem(DUALMEM,996)
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ia <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_aa <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdreg_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ab <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_rdmux_q;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 27,
width_b => 1,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_iq,
address_a => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_aa,
data_a => ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_ia
);
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_reset0 <= areset;
ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_iq(0 downto 0);
--cstAllOWE_uid17_fpExpEM1Test(CONSTANT,16)
cstAllOWE_uid17_fpExpEM1Test_q <= "11111111";
--ld_signX_uid7_fpExpEM1Test_b_to_addrPE2FusedClose_uid128_fpExpEM1Test_b(DELAY,555)@0
ld_signX_uid7_fpExpEM1Test_b_to_addrPE2FusedClose_uid128_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => signX_uid7_fpExpEM1Test_b, xout => ld_signX_uid7_fpExpEM1Test_b_to_addrPE2FusedClose_uid128_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--expX_uid6_fpExpEM1Test(BITSELECT,5)@0
expX_uid6_fpExpEM1Test_in <= a(30 downto 0);
expX_uid6_fpExpEM1Test_b <= expX_uid6_fpExpEM1Test_in(30 downto 23);
--frac_uid24_fpExpEM1Test(BITSELECT,23)@0
frac_uid24_fpExpEM1Test_in <= a(22 downto 0);
frac_uid24_fpExpEM1Test_b <= frac_uid24_fpExpEM1Test_in(22 downto 0);
--expFracX_uid36_fpExpEM1Test(BITJOIN,35)@0
expFracX_uid36_fpExpEM1Test_q <= expX_uid6_fpExpEM1Test_b & frac_uid24_fpExpEM1Test_b;
--cstFPLogZpf_uid35_fpExpEM1Test(CONSTANT,34)
cstFPLogZpf_uid35_fpExpEM1Test_q <= "00111111001100010111001000011000";
--expFracCstLogZ5_uid37_fpExpEM1Test(BITSELECT,36)@0
expFracCstLogZ5_uid37_fpExpEM1Test_in <= cstFPLogZpf_uid35_fpExpEM1Test_q(30 downto 0);
expFracCstLogZ5_uid37_fpExpEM1Test_b <= expFracCstLogZ5_uid37_fpExpEM1Test_in(30 downto 0);
--inCloseBranch_uid38_fpExpEM1Test(COMPARE,37)@0
inCloseBranch_uid38_fpExpEM1Test_cin <= GND_q;
inCloseBranch_uid38_fpExpEM1Test_a <= STD_LOGIC_VECTOR("00" & expFracCstLogZ5_uid37_fpExpEM1Test_b) & '0';
inCloseBranch_uid38_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00" & expFracX_uid36_fpExpEM1Test_q) & inCloseBranch_uid38_fpExpEM1Test_cin(0);
inCloseBranch_uid38_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(inCloseBranch_uid38_fpExpEM1Test_a) - UNSIGNED(inCloseBranch_uid38_fpExpEM1Test_b));
inCloseBranch_uid38_fpExpEM1Test_n(0) <= not inCloseBranch_uid38_fpExpEM1Test_o(33);
--InvInCloseBranch_uid39_fpExpEM1Test(LOGICAL,38)@0
InvInCloseBranch_uid39_fpExpEM1Test_a <= inCloseBranch_uid38_fpExpEM1Test_n;
InvInCloseBranch_uid39_fpExpEM1Test_q <= not InvInCloseBranch_uid39_fpExpEM1Test_a;
--oneSComplementOption_uid40_fpExpEM1Test(LOGICAL,39)@0
oneSComplementOption_uid40_fpExpEM1Test_a <= signX_uid7_fpExpEM1Test_b;
oneSComplementOption_uid40_fpExpEM1Test_b <= InvInCloseBranch_uid39_fpExpEM1Test_q;
oneSComplementOption_uid40_fpExpEM1Test_q <= oneSComplementOption_uid40_fpExpEM1Test_a and oneSComplementOption_uid40_fpExpEM1Test_b;
--ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b(DELAY,476)@0
ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => oneSComplementOption_uid40_fpExpEM1Test_q, xout => ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1(REG,378)@6
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1_q <= ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor(LOGICAL,904)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_b <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_q <= not (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_a or ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_b);
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_mem_top(CONSTANT,900)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_mem_top_q <= "011";
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp(LOGICAL,901)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_mem_top_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q);
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_q <= "1" when ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_a = ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_b else "0";
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg(REG,902)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena(REG,905)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_nor_q = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd(LOGICAL,906)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_sticky_ena_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_b <= en;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_a and ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_b;
--oFracX_uid34_uid34_fpExpEM1Test(BITJOIN,33)@0
oFracX_uid34_uid34_fpExpEM1Test_q <= VCC_q & frac_uid24_fpExpEM1Test_b;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg(DELAY,894)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid34_uid34_fpExpEM1Test_q, xout => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt(COUNTER,896)
-- every=1, low=0, high=3, step=1, init=1
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_i <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_i,2));
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg(REG,897)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux(MUX,898)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_s <= en;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux: PROCESS (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_s, ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q, ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem(DUALMEM,895)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ia <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_aa <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdreg_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ab <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_rdmux_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 4,
width_b => 24,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_iq,
address_a => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_aa,
data_a => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_ia
);
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_reset0 <= areset;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_iq(23 downto 0);
--cstZeroWEP1_uid12_fpExpEM1Test(CONSTANT,11)
cstZeroWEP1_uid12_fpExpEM1Test_q <= "000000000";
--oFracXZwE_uid56_fpExpEM1Test(BITJOIN,55)@6
oFracXZwE_uid56_fpExpEM1Test_q <= GND_q & ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_replace_mem_q & cstZeroWEP1_uid12_fpExpEM1Test_q;
--onesCmpFxpIn_uid57_fpExpEM1Test(LOGICAL,56)@6
onesCmpFxpIn_uid57_fpExpEM1Test_a <= oFracXZwE_uid56_fpExpEM1Test_q;
onesCmpFxpIn_uid57_fpExpEM1Test_b <= STD_LOGIC_VECTOR((33 downto 1 => ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b_q(0)) & ld_oneSComplementOption_uid40_fpExpEM1Test_q_to_onesCmpFxpIn_uid57_fpExpEM1Test_b_q);
onesCmpFxpIn_uid57_fpExpEM1Test_q_i <= onesCmpFxpIn_uid57_fpExpEM1Test_a xor onesCmpFxpIn_uid57_fpExpEM1Test_b;
onesCmpFxpIn_uid57_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 34, depth => 1)
PORT MAP (xout => onesCmpFxpIn_uid57_fpExpEM1Test_q, xin => onesCmpFxpIn_uid57_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--fxpInExt_uid58_fpExpEM1Test(ADD,57)@7
fxpInExt_uid58_fpExpEM1Test_a <= STD_LOGIC_VECTOR((35 downto 34 => onesCmpFxpIn_uid57_fpExpEM1Test_q(33)) & onesCmpFxpIn_uid57_fpExpEM1Test_q);
fxpInExt_uid58_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000000000" & reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExt_uid58_fpExpEM1Test_1_q);
fxpInExt_uid58_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid58_fpExpEM1Test_a) + SIGNED(fxpInExt_uid58_fpExpEM1Test_b));
fxpInExt_uid58_fpExpEM1Test_q <= fxpInExt_uid58_fpExpEM1Test_o(34 downto 0);
--fxpInPreAlign_uid59_fpExpEM1Test(BITSELECT,58)@7
fxpInPreAlign_uid59_fpExpEM1Test_in <= fxpInExt_uid58_fpExpEM1Test_q(33 downto 0);
fxpInPreAlign_uid59_fpExpEM1Test_b <= fxpInPreAlign_uid59_fpExpEM1Test_in(33 downto 0);
--msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,238)@7
msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= fxpInPreAlign_uid59_fpExpEM1Test_b;
msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 33);
--ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b(DELAY,734)@7
ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid225_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,224)
z_uid225_fxpInPostAlign_uid53_fpExpEM1Test_q <= "000";
--rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,274)@9
rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid225_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((2 downto 1 => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q(0)) & ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q);
rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 3, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b(DELAY,713)@7
ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid211_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,210)
z_uid211_fxpInPostAlign_uid53_fpExpEM1Test_q <= "000000000000";
--rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,260)@8
rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid211_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((11 downto 1 => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q(0)) & ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q);
rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 12, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid248_fxpInPostAlign_X_uid64_fpExpEM1Test(CONSTANT,247)
rightShiftStage0Idx3_uid248_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= "0000000000000000000000000000000000";
--rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,248)@7
rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= rightShiftStage0Idx3_uid248_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((33 downto 1 => msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b(0)) & msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b);
rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 34, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid195_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,194)
z_uid195_fxpInPostAlign_uid53_fpExpEM1Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,244)@7
rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid195_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b(0)) & msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b);
rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
--X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,245)@7
X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= fxpInPreAlign_uid59_fpExpEM1Test_b;
X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 32);
--rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,246)@7
rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage0Idx2Pad32_uid245_fxpInPostAlign_X_uid64_fpExpEM1Test_q & X33dto32_uid246_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
--reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4(REG,382)@7
reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4_q <= rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--z_uid191_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,190)
z_uid191_fxpInPostAlign_uid53_fpExpEM1Test_q <= "0000000000000000";
--rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,240)@7
rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid191_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((15 downto 1 => msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b(0)) & msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b);
rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
--X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,241)@7
X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= fxpInPreAlign_uid59_fpExpEM1Test_b;
X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 16);
--rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,242)@7
rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage0Idx1Pad16_uid241_fxpInPostAlign_X_uid64_fpExpEM1Test_q & X33dto16_uid242_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
--reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3(REG,381)@7
reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3_q <= rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2(REG,380)@7
reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= fxpInPreAlign_uid59_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid16_fpExpEM1Test(CONSTANT,15)
cstBiasPWE_uid16_fpExpEM1Test_q <= "100001";
--ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg(DELAY,893)
ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpExpEM1Test_b, xout => ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b(DELAY,467)@0
ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg_q, xout => ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPWE_uid13_fpExpEM1Test(CONSTANT,12)
cstBiasPWE_uid13_fpExpEM1Test_q <= "10000111";
--shiftValuePreSat_uid48_fpExpEM1Test(SUB,47)@4
shiftValuePreSat_uid48_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid13_fpExpEM1Test_q);
shiftValuePreSat_uid48_fpExpEM1Test_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_q);
shiftValuePreSat_uid48_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid48_fpExpEM1Test_a) - UNSIGNED(shiftValuePreSat_uid48_fpExpEM1Test_b));
shiftValuePreSat_uid48_fpExpEM1Test_q <= shiftValuePreSat_uid48_fpExpEM1Test_o(8 downto 0);
--shiftValuePreSatRed_uid51_fpExpEM1Test(BITSELECT,50)@4
shiftValuePreSatRed_uid51_fpExpEM1Test_in <= shiftValuePreSat_uid48_fpExpEM1Test_q(5 downto 0);
shiftValuePreSatRed_uid51_fpExpEM1Test_b <= shiftValuePreSatRed_uid51_fpExpEM1Test_in(5 downto 0);
--ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c(DELAY,472)@4
ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid51_fpExpEM1Test_b, xout => ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0(REG,362)@4
reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0_q <= shiftValuePreSat_uid48_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid50_fpExpEM1Test(COMPARE,49)@5
shiftUdf_uid50_fpExpEM1Test_cin <= GND_q;
shiftUdf_uid50_fpExpEM1Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0_q(8)) & reg_shiftValuePreSat_uid48_fpExpEM1Test_0_to_shiftUdf_uid50_fpExpEM1Test_0_q) & '0';
shiftUdf_uid50_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBiasPWE_uid16_fpExpEM1Test_q) & shiftUdf_uid50_fpExpEM1Test_cin(0);
shiftUdf_uid50_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid50_fpExpEM1Test_a) - SIGNED(shiftUdf_uid50_fpExpEM1Test_b));
shiftUdf_uid50_fpExpEM1Test_n(0) <= not shiftUdf_uid50_fpExpEM1Test_o(11);
--shiftVal_uid52_fpExpEM1Test(MUX,51)@5
shiftVal_uid52_fpExpEM1Test_s <= shiftUdf_uid50_fpExpEM1Test_n;
shiftVal_uid52_fpExpEM1Test: PROCESS (shiftVal_uid52_fpExpEM1Test_s, en, ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c_q, cstBiasPWE_uid16_fpExpEM1Test_q)
BEGIN
CASE shiftVal_uid52_fpExpEM1Test_s IS
WHEN "0" => shiftVal_uid52_fpExpEM1Test_q <= ld_shiftValuePreSatRed_uid51_fpExpEM1Test_b_to_shiftVal_uid52_fpExpEM1Test_c_q;
WHEN "1" => shiftVal_uid52_fpExpEM1Test_q <= cstBiasPWE_uid16_fpExpEM1Test_q;
WHEN OTHERS => shiftVal_uid52_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,200)@5
rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_in <= shiftVal_uid52_fpExpEM1Test_q;
rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b <= rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_in(5 downto 4);
--ld_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a(DELAY,838)@5
ld_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1(REG,379)@7
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= ld_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test(MUX,250)@8
rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_s <= reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q;
rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test: PROCESS (rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_s, en, reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q, reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3_q, reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4_q, rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= reg_fxpInPreAlign_uid59_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= reg_rightShiftStage0Idx1_uid243_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_3_q;
WHEN "10" => rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= reg_rightShiftStage0Idx2_uid247_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_4_q;
WHEN "11" => rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage0Idx3_uid249_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,261)@8
RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 12);
--ld_RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_a(DELAY,723)@8
ld_RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 22, depth => 1 )
PORT MAP ( xin => RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,262)@9
rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx3Pad12_uid261_fxpInPostAlign_X_uid64_fpExpEM1Test_q & ld_RightShiftStage033dto12_uid262_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q;
--rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,256)@8
rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= cstZeroWE_uid11_fpExpEM1Test_q;
rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q(0)) & ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q);
rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,257)@8
RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 8);
--ld_RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_a(DELAY,719)@8
ld_RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,258)@9
rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx2Pad8_uid257_fxpInPostAlign_X_uid64_fpExpEM1Test_q & ld_RightShiftStage033dto8_uid258_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q;
--z_uid203_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,202)
z_uid203_fxpInPostAlign_uid53_fpExpEM1Test_q <= "0000";
--rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,252)@8
rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid203_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q(0)) & ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q);
rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,253)@8
RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 4);
--ld_RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_a(DELAY,715)@8
ld_RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,254)@9
rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx1Pad4_uid253_fxpInPostAlign_X_uid64_fpExpEM1Test_q & ld_RightShiftStage033dto4_uid254_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q;
--reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2(REG,384)@8
reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,214)@5
rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_in <= shiftVal_uid52_fpExpEM1Test_q(3 downto 0);
rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b <= rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1(REG,383)@5
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_b(DELAY,725)@6
ld_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 3 )
PORT MAP ( xin => reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q, xout => ld_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test(MUX,264)@9
rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_s <= ld_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q;
rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test: PROCESS (rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_s, en, reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q, rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_q, rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_q, rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= reg_rightShiftStage0_uid251_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx1_uid255_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN "10" => rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx2_uid259_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN "11" => rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage1Idx3_uid263_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,275)@9
RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 3);
--ld_RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_a(DELAY,740)@9
ld_RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,276)@10
rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage2Idx3Pad3_uid275_fxpInPostAlign_X_uid64_fpExpEM1Test_q & ld_RightShiftStage133dto3_uid276_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q;
--z_uid221_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,220)
z_uid221_fxpInPostAlign_uid53_fpExpEM1Test_q <= "00";
--rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,270)@9
rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= z_uid221_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q(0)) & ld_msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q);
rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,271)@9
RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 2);
--ld_RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_a(DELAY,736)@9
ld_RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b, xout => ld_RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,272)@10
rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage2Idx2Pad2_uid271_fxpInPostAlign_X_uid64_fpExpEM1Test_q & ld_RightShiftStage133dto2_uid272_fxpInPostAlign_X_uid64_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_a_q;
--rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test(LOGICAL,266)@7
rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_a <= GND_q;
rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= msbx_uid239_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i <= rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_a or rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xin => rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_b(DELAY,733)@8
ld_rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xout => ld_rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test(BITSELECT,267)@9
RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_in <= rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_b <= RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_in(33 downto 1);
--rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test(BITJOIN,268)@9
rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= ld_rightShiftStage2Idx1Pad1_uid267_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_b_q & RightShiftStage133dto1_uid268_fxpInPostAlign_X_uid64_fpExpEM1Test_b;
--ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d(DELAY,744)@9
ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q, xout => ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2(REG,386)@9
reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q <= rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,228)@5
rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_in <= shiftVal_uid52_fpExpEM1Test_q(1 downto 0);
rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b <= rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_in(1 downto 0);
--ld_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a(DELAY,844)@5
ld_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 4 )
PORT MAP ( xin => rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1(REG,385)@9
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q <= ld_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test(MUX,278)@10
rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_s <= reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_1_q;
rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test: PROCESS (rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_s, en, reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q, ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d_q, rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_q, rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= reg_rightShiftStage1_uid265_fxpInPostAlign_X_uid64_fpExpEM1Test_0_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= ld_rightShiftStage2Idx1_uid269_fxpInPostAlign_X_uid64_fpExpEM1Test_q_to_rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_d_q;
WHEN "10" => rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage2Idx2_uid273_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN "11" => rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= rightShiftStage2Idx3_uid277_fxpInPostAlign_X_uid64_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--yBranchClose_uid125_fpExpEM1Test(BITSELECT,124)@10
yBranchClose_uid125_fpExpEM1Test_in <= rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q(23 downto 0);
yBranchClose_uid125_fpExpEM1Test_b <= yBranchClose_uid125_fpExpEM1Test_in(23 downto 0);
--addrPE2_uid127_fpExpEM1Test(BITSELECT,126)@10
addrPE2_uid127_fpExpEM1Test_in <= yBranchClose_uid125_fpExpEM1Test_b;
addrPE2_uid127_fpExpEM1Test_b <= addrPE2_uid127_fpExpEM1Test_in(23 downto 17);
--addrPE2FusedClose_uid128_fpExpEM1Test(BITJOIN,127)@10
addrPE2FusedClose_uid128_fpExpEM1Test_q <= ld_signX_uid7_fpExpEM1Test_b_to_addrPE2FusedClose_uid128_fpExpEM1Test_b_q & addrPE2_uid127_fpExpEM1Test_b;
--reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0(REG,419)@10
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0_q <= addrPE2FusedClose_uid128_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid333_expm1PE2TabGen_lutmem(DUALMEM,361)@11
memoryC2_uid333_expm1PE2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid333_expm1PE2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid333_expm1PE2TabGen_lutmem_ab <= reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0_q;
memoryC2_uid333_expm1PE2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_expm1_s5_memoryC2_uid333_expm1PE2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid333_expm1PE2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid333_expm1PE2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid333_expm1PE2TabGen_lutmem_iq,
address_a => memoryC2_uid333_expm1PE2TabGen_lutmem_aa,
data_a => memoryC2_uid333_expm1PE2TabGen_lutmem_ia
);
memoryC2_uid333_expm1PE2TabGen_lutmem_reset0 <= areset;
memoryC2_uid333_expm1PE2TabGen_lutmem_q <= memoryC2_uid333_expm1PE2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1(REG,421)@13
reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1_q <= memoryC2_uid333_expm1PE2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_inputreg(DELAY,944)
ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => yBranchClose_uid125_fpExpEM1Test_b, xout => ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a(DELAY,556)@10
ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_inputreg_q, xout => ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval2_uid129_fpExpEM1Test(BITSELECT,128)@13
yPPolyEval2_uid129_fpExpEM1Test_in <= ld_yBranchClose_uid125_fpExpEM1Test_b_to_yPPolyEval2_uid129_fpExpEM1Test_a_q(16 downto 0);
yPPolyEval2_uid129_fpExpEM1Test_b <= yPPolyEval2_uid129_fpExpEM1Test_in(16 downto 0);
--yT1_uid335_expm1PE2PolyEval(BITSELECT,334)@13
yT1_uid335_expm1PE2PolyEval_in <= yPPolyEval2_uid129_fpExpEM1Test_b;
yT1_uid335_expm1PE2PolyEval_b <= yT1_uid335_expm1PE2PolyEval_in(16 downto 5);
--reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0(REG,420)@13
reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0_q <= yT1_uid335_expm1PE2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid354_pT1_uid336_expm1PE2PolyEval(MULT,353)@14
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid354_pT1_uid336_expm1PE2PolyEval_a),13)) * SIGNED(prodXY_uid354_pT1_uid336_expm1PE2PolyEval_b);
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_a <= (others => '0');
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_b <= (others => '0');
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_a <= reg_yT1_uid335_expm1PE2PolyEval_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_0_q;
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_b <= reg_memoryC2_uid333_expm1PE2TabGen_lutmem_0_to_prodXY_uid354_pT1_uid336_expm1PE2PolyEval_1_q;
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid354_pT1_uid336_expm1PE2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid354_pT1_uid336_expm1PE2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid354_pT1_uid336_expm1PE2PolyEval_q <= prodXY_uid354_pT1_uid336_expm1PE2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval(BITSELECT,354)@17
prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_in <= prodXY_uid354_pT1_uid336_expm1PE2PolyEval_q;
prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_b <= prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_in(23 downto 11);
--highBBits_uid338_expm1PE2PolyEval(BITSELECT,337)@17
highBBits_uid338_expm1PE2PolyEval_in <= prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_b;
highBBits_uid338_expm1PE2PolyEval_b <= highBBits_uid338_expm1PE2PolyEval_in(12 downto 1);
--ld_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC1_uid331_expm1PE2TabGen_lutmem_0_q_to_memoryC1_uid331_expm1PE2TabGen_lutmem_a(DELAY,819)@11
ld_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC1_uid331_expm1PE2TabGen_lutmem_0_q_to_memoryC1_uid331_expm1PE2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC2_uid333_expm1PE2TabGen_lutmem_0_q, xout => ld_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC1_uid331_expm1PE2TabGen_lutmem_0_q_to_memoryC1_uid331_expm1PE2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid331_expm1PE2TabGen_lutmem(DUALMEM,360)@14
memoryC1_uid331_expm1PE2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid331_expm1PE2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid331_expm1PE2TabGen_lutmem_ab <= ld_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC1_uid331_expm1PE2TabGen_lutmem_0_q_to_memoryC1_uid331_expm1PE2TabGen_lutmem_a_q;
memoryC1_uid331_expm1PE2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_expm1_s5_memoryC1_uid331_expm1PE2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid331_expm1PE2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid331_expm1PE2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid331_expm1PE2TabGen_lutmem_iq,
address_a => memoryC1_uid331_expm1PE2TabGen_lutmem_aa,
data_a => memoryC1_uid331_expm1PE2TabGen_lutmem_ia
);
memoryC1_uid331_expm1PE2TabGen_lutmem_reset0 <= areset;
memoryC1_uid331_expm1PE2TabGen_lutmem_q <= memoryC1_uid331_expm1PE2TabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0(REG,423)@16
reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0_q <= memoryC1_uid331_expm1PE2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid339_expm1PE2PolyEval(ADD,338)@17
sumAHighB_uid339_expm1PE2PolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0_q(19)) & reg_memoryC1_uid331_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid339_expm1PE2PolyEval_0_q);
sumAHighB_uid339_expm1PE2PolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid338_expm1PE2PolyEval_b(11)) & highBBits_uid338_expm1PE2PolyEval_b);
sumAHighB_uid339_expm1PE2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid339_expm1PE2PolyEval_a) + SIGNED(sumAHighB_uid339_expm1PE2PolyEval_b));
sumAHighB_uid339_expm1PE2PolyEval_q <= sumAHighB_uid339_expm1PE2PolyEval_o(20 downto 0);
--lowRangeB_uid337_expm1PE2PolyEval(BITSELECT,336)@17
lowRangeB_uid337_expm1PE2PolyEval_in <= prodXYTruncFR_uid355_pT1_uid336_expm1PE2PolyEval_b(0 downto 0);
lowRangeB_uid337_expm1PE2PolyEval_b <= lowRangeB_uid337_expm1PE2PolyEval_in(0 downto 0);
--s1_uid337_uid340_expm1PE2PolyEval(BITJOIN,339)@17
s1_uid337_uid340_expm1PE2PolyEval_q <= sumAHighB_uid339_expm1PE2PolyEval_q & lowRangeB_uid337_expm1PE2PolyEval_b;
--reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1(REG,425)@17
reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1_q <= s1_uid337_uid340_expm1PE2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor(LOGICAL,1040)
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_b <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_q <= not (ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_a or ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_b);
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg(REG,926)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena(REG,1041)
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd(LOGICAL,1042)
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_a <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_sticky_ena_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_q <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_a and ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_b;
--ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_inputreg(DELAY,1032)
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 17, depth => 1 )
PORT MAP ( xin => yPPolyEval2_uid129_fpExpEM1Test_b, xout => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt(COUNTER,922)
-- every=1, low=0, high=1, step=1, init=1
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_i <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_i,1));
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg(REG,923)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux(MUX,924)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_s <= en;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux: PROCESS (ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_s, ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q, ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_q)
BEGIN
CASE ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_s IS
WHEN "0" => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q;
WHEN "1" => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem(DUALMEM,1033)
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ia <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_inputreg_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_aa <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ab <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 1,
numwords_a => 2,
width_b => 17,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_q <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_iq(16 downto 0);
--reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0(REG,424)@17
reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_q <= ld_yPPolyEval2_uid129_fpExpEM1Test_b_to_reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid357_pT2_uid342_expm1PE2PolyEval(MULT,356)@18
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid357_pT2_uid342_expm1PE2PolyEval_a),18)) * SIGNED(prodXY_uid357_pT2_uid342_expm1PE2PolyEval_b);
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_a <= (others => '0');
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_b <= (others => '0');
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_a <= reg_yPPolyEval2_uid129_fpExpEM1Test_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_0_q;
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_b <= reg_s1_uid337_uid340_expm1PE2PolyEval_0_to_prodXY_uid357_pT2_uid342_expm1PE2PolyEval_1_q;
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid357_pT2_uid342_expm1PE2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid357_pT2_uid342_expm1PE2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid357_pT2_uid342_expm1PE2PolyEval_q <= prodXY_uid357_pT2_uid342_expm1PE2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval(BITSELECT,357)@21
prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_in <= prodXY_uid357_pT2_uid342_expm1PE2PolyEval_q;
prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_b <= prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_in(38 downto 16);
--highBBits_uid344_expm1PE2PolyEval(BITSELECT,343)@21
highBBits_uid344_expm1PE2PolyEval_in <= prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_b;
highBBits_uid344_expm1PE2PolyEval_b <= highBBits_uid344_expm1PE2PolyEval_in(22 downto 2);
--ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor(LOGICAL,1053)
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_b <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_q <= not (ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_a or ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_b);
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_mem_top(CONSTANT,1025)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_mem_top_q <= "0100";
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp(LOGICAL,1026)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_a <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_mem_top_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q);
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_q <= "1" when ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_a = ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_b else "0";
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg(REG,1027)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena(REG,1054)
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd(LOGICAL,1055)
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_a <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_sticky_ena_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_q <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_a and ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_b;
--ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_inputreg(DELAY,1043)
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrPE2FusedClose_uid128_fpExpEM1Test_q, xout => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=4, step=1, init=1
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i = 3 THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i - 4;
ELSE
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_i,3));
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg(REG,1022)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux(MUX,1023)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_s, ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q, ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem(DUALMEM,1044)
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ia <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_inputreg_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_aa <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ab <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_ia
);
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_q <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0(REG,426)@17
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_q <= ld_addrPE2FusedClose_uid128_fpExpEM1Test_q_to_reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid329_expm1PE2TabGen_lutmem(DUALMEM,359)@18
memoryC0_uid329_expm1PE2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid329_expm1PE2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid329_expm1PE2TabGen_lutmem_ab <= reg_addrPE2FusedClose_uid128_fpExpEM1Test_0_to_memoryC0_uid329_expm1PE2TabGen_lutmem_0_q;
memoryC0_uid329_expm1PE2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_expm1_s5_memoryC0_uid329_expm1PE2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid329_expm1PE2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid329_expm1PE2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid329_expm1PE2TabGen_lutmem_iq,
address_a => memoryC0_uid329_expm1PE2TabGen_lutmem_aa,
data_a => memoryC0_uid329_expm1PE2TabGen_lutmem_ia
);
memoryC0_uid329_expm1PE2TabGen_lutmem_reset0 <= areset;
memoryC0_uid329_expm1PE2TabGen_lutmem_q <= memoryC0_uid329_expm1PE2TabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0(REG,427)@20
reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0_q <= memoryC0_uid329_expm1PE2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid345_expm1PE2PolyEval(ADD,344)@21
sumAHighB_uid345_expm1PE2PolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0_q(28)) & reg_memoryC0_uid329_expm1PE2TabGen_lutmem_0_to_sumAHighB_uid345_expm1PE2PolyEval_0_q);
sumAHighB_uid345_expm1PE2PolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid344_expm1PE2PolyEval_b(20)) & highBBits_uid344_expm1PE2PolyEval_b);
sumAHighB_uid345_expm1PE2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid345_expm1PE2PolyEval_a) + SIGNED(sumAHighB_uid345_expm1PE2PolyEval_b));
sumAHighB_uid345_expm1PE2PolyEval_q <= sumAHighB_uid345_expm1PE2PolyEval_o(29 downto 0);
--lowRangeB_uid343_expm1PE2PolyEval(BITSELECT,342)@21
lowRangeB_uid343_expm1PE2PolyEval_in <= prodXYTruncFR_uid358_pT2_uid342_expm1PE2PolyEval_b(1 downto 0);
lowRangeB_uid343_expm1PE2PolyEval_b <= lowRangeB_uid343_expm1PE2PolyEval_in(1 downto 0);
--s2_uid343_uid346_expm1PE2PolyEval(BITJOIN,345)@21
s2_uid343_uid346_expm1PE2PolyEval_q <= sumAHighB_uid345_expm1PE2PolyEval_q & lowRangeB_uid343_expm1PE2PolyEval_b;
--pe2OR_uid131_fpExpEM1Test(BITSELECT,130)@21
pe2OR_uid131_fpExpEM1Test_in <= s2_uid343_uid346_expm1PE2PolyEval_q(29 downto 0);
pe2OR_uid131_fpExpEM1Test_b <= pe2OR_uid131_fpExpEM1Test_in(29 downto 4);
--reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1(REG,429)@21
reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1_q <= pe2OR_uid131_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor(LOGICAL,1066)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_b <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_q <= not (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_a or ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_b);
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_mem_top(CONSTANT,1062)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_mem_top_q <= "010010";
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp(LOGICAL,1063)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_mem_top_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q);
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_q <= "1" when ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_a = ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_b else "0";
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg(REG,1064)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena(REG,1067)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_nor_q = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd(LOGICAL,1068)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_sticky_ena_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_b <= en;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_a and ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_b;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt(COUNTER,1058)
-- every=1, low=0, high=18, step=1, init=1
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i = 17 THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i - 18;
ELSE
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_i,5));
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg(REG,1059)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux(MUX,1060)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_s <= en;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux: PROCESS (ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_s, ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q, ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem(DUALMEM,1057)
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ia <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_inputreg_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_aa <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdreg_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ab <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_rdmux_q;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 5,
numwords_a => 19,
width_b => 24,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_iq,
address_a => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_aa,
data_a => ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_ia
);
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_reset0 <= areset;
ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_iq(23 downto 0);
--reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0(REG,428)@21
reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_q <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prod2_uid132_fpExpEM1Test(MULT,131)@22
prod2_uid132_fpExpEM1Test_pr <= UNSIGNED(prod2_uid132_fpExpEM1Test_a) * UNSIGNED(prod2_uid132_fpExpEM1Test_b);
prod2_uid132_fpExpEM1Test_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod2_uid132_fpExpEM1Test_a <= (others => '0');
prod2_uid132_fpExpEM1Test_b <= (others => '0');
prod2_uid132_fpExpEM1Test_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod2_uid132_fpExpEM1Test_a <= reg_oFracX_uid34_uid34_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_0_q;
prod2_uid132_fpExpEM1Test_b <= reg_pe2OR_uid131_fpExpEM1Test_0_to_prod2_uid132_fpExpEM1Test_1_q;
prod2_uid132_fpExpEM1Test_s1 <= STD_LOGIC_VECTOR(prod2_uid132_fpExpEM1Test_pr);
END IF;
END IF;
END PROCESS;
prod2_uid132_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod2_uid132_fpExpEM1Test_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod2_uid132_fpExpEM1Test_q <= prod2_uid132_fpExpEM1Test_s1;
END IF;
END IF;
END PROCESS;
--normBit2_uid133_fpExpEM1Test(BITSELECT,132)@25
normBit2_uid133_fpExpEM1Test_in <= prod2_uid132_fpExpEM1Test_q(48 downto 0);
normBit2_uid133_fpExpEM1Test_b <= normBit2_uid133_fpExpEM1Test_in(48 downto 48);
--InvNormBit2_uid140_fpExpEM1Test(LOGICAL,139)@25
InvNormBit2_uid140_fpExpEM1Test_a <= normBit2_uid133_fpExpEM1Test_b;
InvNormBit2_uid140_fpExpEM1Test_q <= not InvNormBit2_uid140_fpExpEM1Test_a;
--ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor(LOGICAL,955)
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_b <= ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_q <= not (ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_a or ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_b);
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_mem_top(CONSTANT,937)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_mem_top_q <= "010110";
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp(LOGICAL,938)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_a <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_mem_top_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q);
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_q <= "1" when ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_a = ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_b else "0";
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg(REG,939)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena(REG,956)
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_nor_q = "1") THEN
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd(LOGICAL,957)
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_a <= ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_sticky_ena_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_b <= en;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_q <= ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_a and ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_b;
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt(COUNTER,933)
-- every=1, low=0, high=22, step=1, init=1
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i = 21 THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_eq = '1') THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i - 22;
ELSE
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_i,5));
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg(REG,934)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux(MUX,935)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_s <= en;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux: PROCESS (ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_s, ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q, ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_q)
BEGIN
CASE ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_s IS
WHEN "0" => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q;
WHEN "1" => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem(DUALMEM,946)
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ia <= ld_expX_uid6_fpExpEM1Test_b_to_shiftValuePreSat_uid48_fpExpEM1Test_b_inputreg_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_aa <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ab <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 23,
width_b => 8,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_ia
);
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_q <= ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_iq(7 downto 0);
--expBranchCloseNegExt_uid141_fpExpEM1Test(SUB,140)@25
expBranchCloseNegExt_uid141_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_q);
expBranchCloseNegExt_uid141_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit2_uid140_fpExpEM1Test_q);
expBranchCloseNegExt_uid141_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expBranchCloseNegExt_uid141_fpExpEM1Test_a) - UNSIGNED(expBranchCloseNegExt_uid141_fpExpEM1Test_b));
expBranchCloseNegExt_uid141_fpExpEM1Test_q <= expBranchCloseNegExt_uid141_fpExpEM1Test_o(8 downto 0);
--expBranchCloseNeg_uid142_fpExpEM1Test(BITSELECT,141)@25
expBranchCloseNeg_uid142_fpExpEM1Test_in <= expBranchCloseNegExt_uid141_fpExpEM1Test_q(7 downto 0);
expBranchCloseNeg_uid142_fpExpEM1Test_b <= expBranchCloseNeg_uid142_fpExpEM1Test_in(7 downto 0);
--reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5(REG,433)@25
reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q <= expBranchCloseNeg_uid142_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f(DELAY,591)@26
ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q, xout => ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f_q, ena => en(0), clk => clk, aclr => areset );
--expBranchClosePosExt_uid138_fpExpEM1Test(ADD,137)@25
expBranchClosePosExt_uid138_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpExpEM1Test_b_to_expBranchClosePosExt_uid138_fpExpEM1Test_a_replace_mem_q);
expBranchClosePosExt_uid138_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00000000" & normBit2_uid133_fpExpEM1Test_b);
expBranchClosePosExt_uid138_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expBranchClosePosExt_uid138_fpExpEM1Test_a) + UNSIGNED(expBranchClosePosExt_uid138_fpExpEM1Test_b));
expBranchClosePosExt_uid138_fpExpEM1Test_q <= expBranchClosePosExt_uid138_fpExpEM1Test_o(8 downto 0);
--expBranchClosePos_uid139_fpExpEM1Test(BITSELECT,138)@25
expBranchClosePos_uid139_fpExpEM1Test_in <= expBranchClosePosExt_uid138_fpExpEM1Test_q(7 downto 0);
expBranchClosePos_uid139_fpExpEM1Test_b <= expBranchClosePos_uid139_fpExpEM1Test_in(7 downto 0);
--ld_expBranchClosePos_uid139_fpExpEM1Test_b_to_reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_a(DELAY,891)@25
ld_expBranchClosePos_uid139_fpExpEM1Test_b_to_reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => expBranchClosePos_uid139_fpExpEM1Test_b, xout => ld_expBranchClosePos_uid139_fpExpEM1Test_b_to_reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4(REG,432)@28
reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_q <= ld_expBranchClosePos_uid139_fpExpEM1Test_b_to_reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_a_q;
END IF;
END IF;
END PROCESS;
--cstBias_uid8_fpExpEM1Test(CONSTANT,7)
cstBias_uid8_fpExpEM1Test_q <= "01111111";
--cstBiasM1_uid14_fpExpEM1Test(CONSTANT,13)
cstBiasM1_uid14_fpExpEM1Test_q <= "01111110";
--RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,322)@27
RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 1);
--rightShiftStage2Idx1_uid325_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,324)@27
rightShiftStage2Idx1_uid325_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= GND_q & RightShiftStage124dto1_uid323_shiftedFracForNegBranch_uid117_fpExpEM1Test_b;
--rightShiftStage1Idx3Pad6_uid319_shiftedFracForNegBranch_uid117_fpExpEM1Test(CONSTANT,318)
rightShiftStage1Idx3Pad6_uid319_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= "000000";
--rightShiftStage0Idx3Pad24_uid308_shiftedFracForNegBranch_uid117_fpExpEM1Test(CONSTANT,307)
rightShiftStage0Idx3Pad24_uid308_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= "000000000000000000000000";
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor(LOGICAL,928)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_b <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_q <= not (ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_a or ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_b);
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena(REG,929)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_nor_q = "1") THEN
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd(LOGICAL,930)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_a <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_sticky_ena_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_b <= en;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_a and ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_b;
--zY_uid68_fpExpEM1Test(CONSTANT,67)
zY_uid68_fpExpEM1Test_q <= "00000000000000000000000000";
--reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1(REG,363)@0
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1_q <= oneSComplementOption_uid40_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--oFracX_uid41_fpExpEM1Test(BITJOIN,40)@0
oFracX_uid41_fpExpEM1Test_q <= GND_q & oFracX_uid34_uid34_fpExpEM1Test_q;
--onesCmpFxpInX_uid42_fpExpEM1Test(LOGICAL,41)@0
onesCmpFxpInX_uid42_fpExpEM1Test_a <= oFracX_uid41_fpExpEM1Test_q;
onesCmpFxpInX_uid42_fpExpEM1Test_b <= STD_LOGIC_VECTOR((24 downto 1 => oneSComplementOption_uid40_fpExpEM1Test_q(0)) & oneSComplementOption_uid40_fpExpEM1Test_q);
onesCmpFxpInX_uid42_fpExpEM1Test_q_i <= onesCmpFxpInX_uid42_fpExpEM1Test_a xor onesCmpFxpInX_uid42_fpExpEM1Test_b;
onesCmpFxpInX_uid42_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 25, depth => 1)
PORT MAP (xout => onesCmpFxpInX_uid42_fpExpEM1Test_q, xin => onesCmpFxpInX_uid42_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--fxpInExtX_uid43_fpExpEM1Test(ADD,42)@1
fxpInExtX_uid43_fpExpEM1Test_a <= STD_LOGIC_VECTOR((26 downto 25 => onesCmpFxpInX_uid42_fpExpEM1Test_q(24)) & onesCmpFxpInX_uid42_fpExpEM1Test_q);
fxpInExtX_uid43_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000" & reg_oneSComplementOption_uid40_fpExpEM1Test_0_to_fxpInExtX_uid43_fpExpEM1Test_1_q);
fxpInExtX_uid43_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExtX_uid43_fpExpEM1Test_a) + SIGNED(fxpInExtX_uid43_fpExpEM1Test_b));
fxpInExtX_uid43_fpExpEM1Test_q <= fxpInExtX_uid43_fpExpEM1Test_o(25 downto 0);
--fxpInPreAlign_uid44_fpExpEM1Test(BITSELECT,43)@1
fxpInPreAlign_uid44_fpExpEM1Test_in <= fxpInExtX_uid43_fpExpEM1Test_q(24 downto 0);
fxpInPreAlign_uid44_fpExpEM1Test_b <= fxpInPreAlign_uid44_fpExpEM1Test_in(24 downto 0);
--xv0_uid174_constMult(BITSELECT,173)@1
xv0_uid174_constMult_in <= fxpInPreAlign_uid44_fpExpEM1Test_b(5 downto 0);
xv0_uid174_constMult_b <= xv0_uid174_constMult_in(5 downto 0);
--reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0(REG,368)@1
reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q <= xv0_uid174_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a(DELAY,629)@2
ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 3 )
PORT MAP ( xin => reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q, xout => ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid183_constMult(LOOKUP,182)@5
p0_uid183_constMult: PROCESS (ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid174_constMult_0_to_p0_uid183_constMult_0_q_to_p0_uid183_constMult_a_q) IS
WHEN "000000" => p0_uid183_constMult_q <= "0000000000000";
WHEN "000001" => p0_uid183_constMult_q <= "0000001011100";
WHEN "000010" => p0_uid183_constMult_q <= "0000010111001";
WHEN "000011" => p0_uid183_constMult_q <= "0000100010101";
WHEN "000100" => p0_uid183_constMult_q <= "0000101110001";
WHEN "000101" => p0_uid183_constMult_q <= "0000111001110";
WHEN "000110" => p0_uid183_constMult_q <= "0001000101010";
WHEN "000111" => p0_uid183_constMult_q <= "0001010000110";
WHEN "001000" => p0_uid183_constMult_q <= "0001011100011";
WHEN "001001" => p0_uid183_constMult_q <= "0001100111111";
WHEN "001010" => p0_uid183_constMult_q <= "0001110011011";
WHEN "001011" => p0_uid183_constMult_q <= "0001111111000";
WHEN "001100" => p0_uid183_constMult_q <= "0010001010100";
WHEN "001101" => p0_uid183_constMult_q <= "0010010110000";
WHEN "001110" => p0_uid183_constMult_q <= "0010100001101";
WHEN "001111" => p0_uid183_constMult_q <= "0010101101001";
WHEN "010000" => p0_uid183_constMult_q <= "0010111000101";
WHEN "010001" => p0_uid183_constMult_q <= "0011000100010";
WHEN "010010" => p0_uid183_constMult_q <= "0011001111110";
WHEN "010011" => p0_uid183_constMult_q <= "0011011011010";
WHEN "010100" => p0_uid183_constMult_q <= "0011100110111";
WHEN "010101" => p0_uid183_constMult_q <= "0011110010011";
WHEN "010110" => p0_uid183_constMult_q <= "0011111101111";
WHEN "010111" => p0_uid183_constMult_q <= "0100001001100";
WHEN "011000" => p0_uid183_constMult_q <= "0100010101000";
WHEN "011001" => p0_uid183_constMult_q <= "0100100000100";
WHEN "011010" => p0_uid183_constMult_q <= "0100101100001";
WHEN "011011" => p0_uid183_constMult_q <= "0100110111101";
WHEN "011100" => p0_uid183_constMult_q <= "0101000011001";
WHEN "011101" => p0_uid183_constMult_q <= "0101001110110";
WHEN "011110" => p0_uid183_constMult_q <= "0101011010010";
WHEN "011111" => p0_uid183_constMult_q <= "0101100101110";
WHEN "100000" => p0_uid183_constMult_q <= "0101110001011";
WHEN "100001" => p0_uid183_constMult_q <= "0101111100111";
WHEN "100010" => p0_uid183_constMult_q <= "0110001000011";
WHEN "100011" => p0_uid183_constMult_q <= "0110010100000";
WHEN "100100" => p0_uid183_constMult_q <= "0110011111100";
WHEN "100101" => p0_uid183_constMult_q <= "0110101011000";
WHEN "100110" => p0_uid183_constMult_q <= "0110110110101";
WHEN "100111" => p0_uid183_constMult_q <= "0111000010001";
WHEN "101000" => p0_uid183_constMult_q <= "0111001101101";
WHEN "101001" => p0_uid183_constMult_q <= "0111011001010";
WHEN "101010" => p0_uid183_constMult_q <= "0111100100110";
WHEN "101011" => p0_uid183_constMult_q <= "0111110000010";
WHEN "101100" => p0_uid183_constMult_q <= "0111111011111";
WHEN "101101" => p0_uid183_constMult_q <= "1000000111011";
WHEN "101110" => p0_uid183_constMult_q <= "1000010010111";
WHEN "101111" => p0_uid183_constMult_q <= "1000011110100";
WHEN "110000" => p0_uid183_constMult_q <= "1000101010000";
WHEN "110001" => p0_uid183_constMult_q <= "1000110101100";
WHEN "110010" => p0_uid183_constMult_q <= "1001000001001";
WHEN "110011" => p0_uid183_constMult_q <= "1001001100101";
WHEN "110100" => p0_uid183_constMult_q <= "1001011000001";
WHEN "110101" => p0_uid183_constMult_q <= "1001100011110";
WHEN "110110" => p0_uid183_constMult_q <= "1001101111010";
WHEN "110111" => p0_uid183_constMult_q <= "1001111010110";
WHEN "111000" => p0_uid183_constMult_q <= "1010000110011";
WHEN "111001" => p0_uid183_constMult_q <= "1010010001111";
WHEN "111010" => p0_uid183_constMult_q <= "1010011101011";
WHEN "111011" => p0_uid183_constMult_q <= "1010101001000";
WHEN "111100" => p0_uid183_constMult_q <= "1010110100100";
WHEN "111101" => p0_uid183_constMult_q <= "1011000000000";
WHEN "111110" => p0_uid183_constMult_q <= "1011001011101";
WHEN "111111" => p0_uid183_constMult_q <= "1011010111001";
WHEN OTHERS =>
p0_uid183_constMult_q <= "0000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid175_constMult(BITSELECT,174)@1
xv1_uid175_constMult_in <= fxpInPreAlign_uid44_fpExpEM1Test_b(11 downto 0);
xv1_uid175_constMult_b <= xv1_uid175_constMult_in(11 downto 6);
--reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0(REG,367)@1
reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q <= xv1_uid175_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a(DELAY,628)@2
ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q, xout => ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p1_uid182_constMult(LOOKUP,181)@4
p1_uid182_constMult: PROCESS (ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv1_uid175_constMult_0_to_p1_uid182_constMult_0_q_to_p1_uid182_constMult_a_q) IS
WHEN "000000" => p1_uid182_constMult_q <= "0000000000000000000";
WHEN "000001" => p1_uid182_constMult_q <= "0000001011100010101";
WHEN "000010" => p1_uid182_constMult_q <= "0000010111000101011";
WHEN "000011" => p1_uid182_constMult_q <= "0000100010101000000";
WHEN "000100" => p1_uid182_constMult_q <= "0000101110001010101";
WHEN "000101" => p1_uid182_constMult_q <= "0000111001101101010";
WHEN "000110" => p1_uid182_constMult_q <= "0001000101010000000";
WHEN "000111" => p1_uid182_constMult_q <= "0001010000110010101";
WHEN "001000" => p1_uid182_constMult_q <= "0001011100010101010";
WHEN "001001" => p1_uid182_constMult_q <= "0001100111111000000";
WHEN "001010" => p1_uid182_constMult_q <= "0001110011011010101";
WHEN "001011" => p1_uid182_constMult_q <= "0001111110111101010";
WHEN "001100" => p1_uid182_constMult_q <= "0010001010011111111";
WHEN "001101" => p1_uid182_constMult_q <= "0010010110000010101";
WHEN "001110" => p1_uid182_constMult_q <= "0010100001100101010";
WHEN "001111" => p1_uid182_constMult_q <= "0010101101000111111";
WHEN "010000" => p1_uid182_constMult_q <= "0010111000101010100";
WHEN "010001" => p1_uid182_constMult_q <= "0011000100001101010";
WHEN "010010" => p1_uid182_constMult_q <= "0011001111101111111";
WHEN "010011" => p1_uid182_constMult_q <= "0011011011010010100";
WHEN "010100" => p1_uid182_constMult_q <= "0011100110110101010";
WHEN "010101" => p1_uid182_constMult_q <= "0011110010010111111";
WHEN "010110" => p1_uid182_constMult_q <= "0011111101111010100";
WHEN "010111" => p1_uid182_constMult_q <= "0100001001011101001";
WHEN "011000" => p1_uid182_constMult_q <= "0100010100111111111";
WHEN "011001" => p1_uid182_constMult_q <= "0100100000100010100";
WHEN "011010" => p1_uid182_constMult_q <= "0100101100000101001";
WHEN "011011" => p1_uid182_constMult_q <= "0100110111100111111";
WHEN "011100" => p1_uid182_constMult_q <= "0101000011001010100";
WHEN "011101" => p1_uid182_constMult_q <= "0101001110101101001";
WHEN "011110" => p1_uid182_constMult_q <= "0101011010001111110";
WHEN "011111" => p1_uid182_constMult_q <= "0101100101110010100";
WHEN "100000" => p1_uid182_constMult_q <= "0101110001010101001";
WHEN "100001" => p1_uid182_constMult_q <= "0101111100110111110";
WHEN "100010" => p1_uid182_constMult_q <= "0110001000011010011";
WHEN "100011" => p1_uid182_constMult_q <= "0110010011111101001";
WHEN "100100" => p1_uid182_constMult_q <= "0110011111011111110";
WHEN "100101" => p1_uid182_constMult_q <= "0110101011000010011";
WHEN "100110" => p1_uid182_constMult_q <= "0110110110100101001";
WHEN "100111" => p1_uid182_constMult_q <= "0111000010000111110";
WHEN "101000" => p1_uid182_constMult_q <= "0111001101101010011";
WHEN "101001" => p1_uid182_constMult_q <= "0111011001001101000";
WHEN "101010" => p1_uid182_constMult_q <= "0111100100101111110";
WHEN "101011" => p1_uid182_constMult_q <= "0111110000010010011";
WHEN "101100" => p1_uid182_constMult_q <= "0111111011110101000";
WHEN "101101" => p1_uid182_constMult_q <= "1000000111010111110";
WHEN "101110" => p1_uid182_constMult_q <= "1000010010111010011";
WHEN "101111" => p1_uid182_constMult_q <= "1000011110011101000";
WHEN "110000" => p1_uid182_constMult_q <= "1000101001111111101";
WHEN "110001" => p1_uid182_constMult_q <= "1000110101100010011";
WHEN "110010" => p1_uid182_constMult_q <= "1001000001000101000";
WHEN "110011" => p1_uid182_constMult_q <= "1001001100100111101";
WHEN "110100" => p1_uid182_constMult_q <= "1001011000001010011";
WHEN "110101" => p1_uid182_constMult_q <= "1001100011101101000";
WHEN "110110" => p1_uid182_constMult_q <= "1001101111001111101";
WHEN "110111" => p1_uid182_constMult_q <= "1001111010110010010";
WHEN "111000" => p1_uid182_constMult_q <= "1010000110010101000";
WHEN "111001" => p1_uid182_constMult_q <= "1010010001110111101";
WHEN "111010" => p1_uid182_constMult_q <= "1010011101011010010";
WHEN "111011" => p1_uid182_constMult_q <= "1010101000111100111";
WHEN "111100" => p1_uid182_constMult_q <= "1010110100011111101";
WHEN "111101" => p1_uid182_constMult_q <= "1011000000000010010";
WHEN "111110" => p1_uid182_constMult_q <= "1011001011100100111";
WHEN "111111" => p1_uid182_constMult_q <= "1011010111000111101";
WHEN OTHERS =>
p1_uid182_constMult_q <= "0000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid176_constMult(BITSELECT,175)@1
xv2_uid176_constMult_in <= fxpInPreAlign_uid44_fpExpEM1Test_b(17 downto 0);
xv2_uid176_constMult_b <= xv2_uid176_constMult_in(17 downto 12);
--ld_xv2_uid176_constMult_b_to_reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_a(DELAY,825)@1
ld_xv2_uid176_constMult_b_to_reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv2_uid176_constMult_b, xout => ld_xv2_uid176_constMult_b_to_reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0(REG,366)@2
reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_q <= ld_xv2_uid176_constMult_b_to_reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p2_uid181_constMult(LOOKUP,180)@3
p2_uid181_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid181_constMult_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid176_constMult_0_to_p2_uid181_constMult_0_q) IS
WHEN "000000" => p2_uid181_constMult_q <= "0000000000000000000000000";
WHEN "000001" => p2_uid181_constMult_q <= "0000001011100010101010010";
WHEN "000010" => p2_uid181_constMult_q <= "0000010111000101010100100";
WHEN "000011" => p2_uid181_constMult_q <= "0000100010100111111110110";
WHEN "000100" => p2_uid181_constMult_q <= "0000101110001010101000111";
WHEN "000101" => p2_uid181_constMult_q <= "0000111001101101010011001";
WHEN "000110" => p2_uid181_constMult_q <= "0001000101001111111101011";
WHEN "000111" => p2_uid181_constMult_q <= "0001010000110010100111101";
WHEN "001000" => p2_uid181_constMult_q <= "0001011100010101010001111";
WHEN "001001" => p2_uid181_constMult_q <= "0001100111110111111100001";
WHEN "001010" => p2_uid181_constMult_q <= "0001110011011010100110010";
WHEN "001011" => p2_uid181_constMult_q <= "0001111110111101010000100";
WHEN "001100" => p2_uid181_constMult_q <= "0010001010011111111010110";
WHEN "001101" => p2_uid181_constMult_q <= "0010010110000010100101000";
WHEN "001110" => p2_uid181_constMult_q <= "0010100001100101001111010";
WHEN "001111" => p2_uid181_constMult_q <= "0010101101000111111001100";
WHEN "010000" => p2_uid181_constMult_q <= "0010111000101010100011110";
WHEN "010001" => p2_uid181_constMult_q <= "0011000100001101001101111";
WHEN "010010" => p2_uid181_constMult_q <= "0011001111101111111000001";
WHEN "010011" => p2_uid181_constMult_q <= "0011011011010010100010011";
WHEN "010100" => p2_uid181_constMult_q <= "0011100110110101001100101";
WHEN "010101" => p2_uid181_constMult_q <= "0011110010010111110110111";
WHEN "010110" => p2_uid181_constMult_q <= "0011111101111010100001001";
WHEN "010111" => p2_uid181_constMult_q <= "0100001001011101001011011";
WHEN "011000" => p2_uid181_constMult_q <= "0100010100111111110101100";
WHEN "011001" => p2_uid181_constMult_q <= "0100100000100010011111110";
WHEN "011010" => p2_uid181_constMult_q <= "0100101100000101001010000";
WHEN "011011" => p2_uid181_constMult_q <= "0100110111100111110100010";
WHEN "011100" => p2_uid181_constMult_q <= "0101000011001010011110100";
WHEN "011101" => p2_uid181_constMult_q <= "0101001110101101001000110";
WHEN "011110" => p2_uid181_constMult_q <= "0101011010001111110010111";
WHEN "011111" => p2_uid181_constMult_q <= "0101100101110010011101001";
WHEN "100000" => p2_uid181_constMult_q <= "0101110001010101000111011";
WHEN "100001" => p2_uid181_constMult_q <= "0101111100110111110001101";
WHEN "100010" => p2_uid181_constMult_q <= "0110001000011010011011111";
WHEN "100011" => p2_uid181_constMult_q <= "0110010011111101000110001";
WHEN "100100" => p2_uid181_constMult_q <= "0110011111011111110000011";
WHEN "100101" => p2_uid181_constMult_q <= "0110101011000010011010100";
WHEN "100110" => p2_uid181_constMult_q <= "0110110110100101000100110";
WHEN "100111" => p2_uid181_constMult_q <= "0111000010000111101111000";
WHEN "101000" => p2_uid181_constMult_q <= "0111001101101010011001010";
WHEN "101001" => p2_uid181_constMult_q <= "0111011001001101000011100";
WHEN "101010" => p2_uid181_constMult_q <= "0111100100101111101101110";
WHEN "101011" => p2_uid181_constMult_q <= "0111110000010010010111111";
WHEN "101100" => p2_uid181_constMult_q <= "0111111011110101000010001";
WHEN "101101" => p2_uid181_constMult_q <= "1000000111010111101100011";
WHEN "101110" => p2_uid181_constMult_q <= "1000010010111010010110101";
WHEN "101111" => p2_uid181_constMult_q <= "1000011110011101000000111";
WHEN "110000" => p2_uid181_constMult_q <= "1000101001111111101011001";
WHEN "110001" => p2_uid181_constMult_q <= "1000110101100010010101011";
WHEN "110010" => p2_uid181_constMult_q <= "1001000001000100111111100";
WHEN "110011" => p2_uid181_constMult_q <= "1001001100100111101001110";
WHEN "110100" => p2_uid181_constMult_q <= "1001011000001010010100000";
WHEN "110101" => p2_uid181_constMult_q <= "1001100011101100111110010";
WHEN "110110" => p2_uid181_constMult_q <= "1001101111001111101000100";
WHEN "110111" => p2_uid181_constMult_q <= "1001111010110010010010110";
WHEN "111000" => p2_uid181_constMult_q <= "1010000110010100111101000";
WHEN "111001" => p2_uid181_constMult_q <= "1010010001110111100111001";
WHEN "111010" => p2_uid181_constMult_q <= "1010011101011010010001011";
WHEN "111011" => p2_uid181_constMult_q <= "1010101000111100111011101";
WHEN "111100" => p2_uid181_constMult_q <= "1010110100011111100101111";
WHEN "111101" => p2_uid181_constMult_q <= "1011000000000010010000001";
WHEN "111110" => p2_uid181_constMult_q <= "1011001011100100111010011";
WHEN "111111" => p2_uid181_constMult_q <= "1011010111000111100100100";
WHEN OTHERS =>
p2_uid181_constMult_q <= "0000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a1_uid185_constMult(ADD,184)@4
lev1_a1_uid185_constMult_a <= STD_LOGIC_VECTOR("0" & p2_uid181_constMult_q);
lev1_a1_uid185_constMult_b <= STD_LOGIC_VECTOR("0000000" & p1_uid182_constMult_q);
lev1_a1_uid185_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1_uid185_constMult_a) + UNSIGNED(lev1_a1_uid185_constMult_b));
lev1_a1_uid185_constMult_q <= lev1_a1_uid185_constMult_o(25 downto 0);
--xv3_uid177_constMult(BITSELECT,176)@1
xv3_uid177_constMult_in <= fxpInPreAlign_uid44_fpExpEM1Test_b(23 downto 0);
xv3_uid177_constMult_b <= xv3_uid177_constMult_in(23 downto 18);
--reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0(REG,365)@1
reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q <= xv3_uid177_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a(DELAY,626)@2
ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q, xout => ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p3_uid180_constMult(LOOKUP,179)@3
p3_uid180_constMult: PROCESS (ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv3_uid177_constMult_0_to_p3_uid180_constMult_0_q_to_p3_uid180_constMult_a_q) IS
WHEN "000000" => p3_uid180_constMult_q <= "0000000000000000000000000000000";
WHEN "000001" => p3_uid180_constMult_q <= "0000001011100010101010001110110";
WHEN "000010" => p3_uid180_constMult_q <= "0000010111000101010100011101101";
WHEN "000011" => p3_uid180_constMult_q <= "0000100010100111111110101100011";
WHEN "000100" => p3_uid180_constMult_q <= "0000101110001010101000111011001";
WHEN "000101" => p3_uid180_constMult_q <= "0000111001101101010011001010000";
WHEN "000110" => p3_uid180_constMult_q <= "0001000101001111111101011000110";
WHEN "000111" => p3_uid180_constMult_q <= "0001010000110010100111100111100";
WHEN "001000" => p3_uid180_constMult_q <= "0001011100010101010001110110010";
WHEN "001001" => p3_uid180_constMult_q <= "0001100111110111111100000101001";
WHEN "001010" => p3_uid180_constMult_q <= "0001110011011010100110010011111";
WHEN "001011" => p3_uid180_constMult_q <= "0001111110111101010000100010101";
WHEN "001100" => p3_uid180_constMult_q <= "0010001010011111111010110001100";
WHEN "001101" => p3_uid180_constMult_q <= "0010010110000010100101000000010";
WHEN "001110" => p3_uid180_constMult_q <= "0010100001100101001111001111000";
WHEN "001111" => p3_uid180_constMult_q <= "0010101101000111111001011101111";
WHEN "010000" => p3_uid180_constMult_q <= "0010111000101010100011101100101";
WHEN "010001" => p3_uid180_constMult_q <= "0011000100001101001101111011011";
WHEN "010010" => p3_uid180_constMult_q <= "0011001111101111111000001010010";
WHEN "010011" => p3_uid180_constMult_q <= "0011011011010010100010011001000";
WHEN "010100" => p3_uid180_constMult_q <= "0011100110110101001100100111110";
WHEN "010101" => p3_uid180_constMult_q <= "0011110010010111110110110110101";
WHEN "010110" => p3_uid180_constMult_q <= "0011111101111010100001000101011";
WHEN "010111" => p3_uid180_constMult_q <= "0100001001011101001011010100001";
WHEN "011000" => p3_uid180_constMult_q <= "0100010100111111110101100011000";
WHEN "011001" => p3_uid180_constMult_q <= "0100100000100010011111110001110";
WHEN "011010" => p3_uid180_constMult_q <= "0100101100000101001010000000100";
WHEN "011011" => p3_uid180_constMult_q <= "0100110111100111110100001111010";
WHEN "011100" => p3_uid180_constMult_q <= "0101000011001010011110011110001";
WHEN "011101" => p3_uid180_constMult_q <= "0101001110101101001000101100111";
WHEN "011110" => p3_uid180_constMult_q <= "0101011010001111110010111011101";
WHEN "011111" => p3_uid180_constMult_q <= "0101100101110010011101001010100";
WHEN "100000" => p3_uid180_constMult_q <= "0101110001010101000111011001010";
WHEN "100001" => p3_uid180_constMult_q <= "0101111100110111110001101000000";
WHEN "100010" => p3_uid180_constMult_q <= "0110001000011010011011110110111";
WHEN "100011" => p3_uid180_constMult_q <= "0110010011111101000110000101101";
WHEN "100100" => p3_uid180_constMult_q <= "0110011111011111110000010100011";
WHEN "100101" => p3_uid180_constMult_q <= "0110101011000010011010100011010";
WHEN "100110" => p3_uid180_constMult_q <= "0110110110100101000100110010000";
WHEN "100111" => p3_uid180_constMult_q <= "0111000010000111101111000000110";
WHEN "101000" => p3_uid180_constMult_q <= "0111001101101010011001001111100";
WHEN "101001" => p3_uid180_constMult_q <= "0111011001001101000011011110011";
WHEN "101010" => p3_uid180_constMult_q <= "0111100100101111101101101101001";
WHEN "101011" => p3_uid180_constMult_q <= "0111110000010010010111111011111";
WHEN "101100" => p3_uid180_constMult_q <= "0111111011110101000010001010110";
WHEN "101101" => p3_uid180_constMult_q <= "1000000111010111101100011001100";
WHEN "101110" => p3_uid180_constMult_q <= "1000010010111010010110101000010";
WHEN "101111" => p3_uid180_constMult_q <= "1000011110011101000000110111001";
WHEN "110000" => p3_uid180_constMult_q <= "1000101001111111101011000101111";
WHEN "110001" => p3_uid180_constMult_q <= "1000110101100010010101010100101";
WHEN "110010" => p3_uid180_constMult_q <= "1001000001000100111111100011100";
WHEN "110011" => p3_uid180_constMult_q <= "1001001100100111101001110010010";
WHEN "110100" => p3_uid180_constMult_q <= "1001011000001010010100000001000";
WHEN "110101" => p3_uid180_constMult_q <= "1001100011101100111110001111111";
WHEN "110110" => p3_uid180_constMult_q <= "1001101111001111101000011110101";
WHEN "110111" => p3_uid180_constMult_q <= "1001111010110010010010101101011";
WHEN "111000" => p3_uid180_constMult_q <= "1010000110010100111100111100010";
WHEN "111001" => p3_uid180_constMult_q <= "1010010001110111100111001011000";
WHEN "111010" => p3_uid180_constMult_q <= "1010011101011010010001011001110";
WHEN "111011" => p3_uid180_constMult_q <= "1010101000111100111011101000100";
WHEN "111100" => p3_uid180_constMult_q <= "1010110100011111100101110111011";
WHEN "111101" => p3_uid180_constMult_q <= "1011000000000010010000000110001";
WHEN "111110" => p3_uid180_constMult_q <= "1011001011100100111010010100111";
WHEN "111111" => p3_uid180_constMult_q <= "1011010111000111100100100011110";
WHEN OTHERS =>
p3_uid180_constMult_q <= "0000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv4_uid178_constMult(BITSELECT,177)@1
xv4_uid178_constMult_in <= fxpInPreAlign_uid44_fpExpEM1Test_b;
xv4_uid178_constMult_b <= xv4_uid178_constMult_in(24 downto 24);
--reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0(REG,364)@1
reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0_q <= xv4_uid178_constMult_b;
END IF;
END IF;
END PROCESS;
--p4_uid179_constMult(LOOKUP,178)@2
p4_uid179_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p4_uid179_constMult_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv4_uid178_constMult_0_to_p4_uid179_constMult_0_q) IS
WHEN "0" => p4_uid179_constMult_q <= "00000000000000000000000000000000";
WHEN "1" => p4_uid179_constMult_q <= "10100011101010101110001001101100";
WHEN OTHERS =>
p4_uid179_constMult_q <= "00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid184_constMult(ADD,183)@3
lev1_a0_uid184_constMult_a <= STD_LOGIC_VECTOR((33 downto 32 => p4_uid179_constMult_q(31)) & p4_uid179_constMult_q);
lev1_a0_uid184_constMult_b <= STD_LOGIC_VECTOR('0' & "00" & p3_uid180_constMult_q);
lev1_a0_uid184_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid184_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid184_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid184_constMult_a) + SIGNED(lev1_a0_uid184_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid184_constMult_q <= lev1_a0_uid184_constMult_o(32 downto 0);
--lev2_a0_uid186_constMult(ADD,185)@4
lev2_a0_uid186_constMult_a <= STD_LOGIC_VECTOR((34 downto 33 => lev1_a0_uid184_constMult_q(32)) & lev1_a0_uid184_constMult_q);
lev2_a0_uid186_constMult_b <= STD_LOGIC_VECTOR('0' & "00000000" & lev1_a1_uid185_constMult_q);
lev2_a0_uid186_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev2_a0_uid186_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev2_a0_uid186_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid186_constMult_a) + SIGNED(lev2_a0_uid186_constMult_b));
END IF;
END IF;
END PROCESS;
lev2_a0_uid186_constMult_q <= lev2_a0_uid186_constMult_o(33 downto 0);
--lev3_a0_uid187_constMult(ADD,186)@5
lev3_a0_uid187_constMult_a <= STD_LOGIC_VECTOR((35 downto 34 => lev2_a0_uid186_constMult_q(33)) & lev2_a0_uid186_constMult_q);
lev3_a0_uid187_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000" & p0_uid183_constMult_q);
lev3_a0_uid187_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev3_a0_uid187_constMult_a) + SIGNED(lev3_a0_uid187_constMult_b));
lev3_a0_uid187_constMult_q <= lev3_a0_uid187_constMult_o(34 downto 0);
--sR_uid188_constMult(BITSELECT,187)@5
sR_uid188_constMult_in <= lev3_a0_uid187_constMult_q(31 downto 0);
sR_uid188_constMult_b <= sR_uid188_constMult_in(31 downto 3);
--oFracXZwE_uid47_fpExpEM1Test(BITJOIN,46)@5
oFracXZwE_uid47_fpExpEM1Test_q <= sR_uid188_constMult_b & cstZeroWE_uid11_fpExpEM1Test_q;
--msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,189)@5
msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_in <= oFracXZwE_uid47_fpExpEM1Test_q;
msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b <= msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 36);
--ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b(DELAY,677)@5
ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,225)@7
rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid225_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((2 downto 1 => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q(0)) & ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q);
rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 3, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b(DELAY,655)@5
ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,211)@6
rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid211_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((11 downto 1 => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q(0)) & ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q);
rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 12, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid199_fxpInPostAlign_uid53_fpExpEM1Test(CONSTANT,198)
rightShiftStage0Idx3_uid199_fxpInPostAlign_uid53_fpExpEM1Test_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,199)@5
rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_a <= rightShiftStage0Idx3_uid199_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((36 downto 1 => msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b(0)) & msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b);
rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,195)@5
rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid195_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b(0)) & msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b);
rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_b;
--X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,196)@5
X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_in <= oFracXZwE_uid47_fpExpEM1Test_q;
X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_b <= X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 32);
--rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,197)@5
rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage0Idx2Pad32_uid196_fxpInPostAlign_uid53_fpExpEM1Test_q & X36dto32_uid197_fxpInPostAlign_uid53_fpExpEM1Test_b;
--reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4(REG,372)@5
reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4_q <= rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,191)@5
rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid191_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((15 downto 1 => msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b(0)) & msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b);
rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_b;
--X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,192)@5
X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_in <= oFracXZwE_uid47_fpExpEM1Test_q;
X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_b <= X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 16);
--rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,193)@5
rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage0Idx1Pad16_uid192_fxpInPostAlign_uid53_fpExpEM1Test_q & X36dto16_uid193_fxpInPostAlign_uid53_fpExpEM1Test_b;
--reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3(REG,371)@5
reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3_q <= rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2(REG,370)@5
reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= oFracXZwE_uid47_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1(REG,369)@5
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test(MUX,201)@6
rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_s <= reg_rightShiftStageSel5Dto4_uid201_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_1_q;
rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test: PROCESS (rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_s, en, reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2_q, reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3_q, reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4_q, rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q <= reg_oFracXZwE_uid47_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q <= reg_rightShiftStage0Idx1_uid194_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_3_q;
WHEN "10" => rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q <= reg_rightShiftStage0Idx2_uid198_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_4_q;
WHEN "11" => rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage0Idx3_uid200_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,212)@6
RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 12);
--ld_RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_a(DELAY,665)@6
ld_RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,213)@7
rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx3Pad12_uid212_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage036dto12_uid213_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_a_q;
--rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,207)@6
rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_a <= cstZeroWE_uid11_fpExpEM1Test_q;
rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q(0)) & ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q);
rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,208)@6
RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 8);
--ld_RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_a(DELAY,661)@6
ld_RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,209)@7
rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx2Pad8_uid208_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage036dto8_uid209_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_a_q;
--rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,203)@6
rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid203_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q(0)) & ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b_q);
rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,204)@6
RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 4);
--ld_RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_a(DELAY,657)@6
ld_RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,205)@7
rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx1Pad4_uid204_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage036dto4_uid205_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_a_q;
--reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2(REG,374)@6
reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_a(DELAY,832)@5
ld_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1(REG,373)@6
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= ld_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_b_to_reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test(MUX,215)@7
rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_s <= reg_rightShiftStageSel3Dto2_uid215_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_1_q;
rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test: PROCESS (rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_s, en, reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2_q, rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_q, rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_q, rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q <= reg_rightShiftStage0_uid202_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx1_uid206_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN "10" => rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx2_uid210_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN "11" => rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage1Idx3_uid214_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,226)@7
RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 3);
--ld_RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_a(DELAY,683)@7
ld_RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,227)@8
rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage2Idx3Pad3_uid226_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage136dto3_uid227_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_a_q;
--rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,221)@7
rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_a <= z_uid221_fxpInPostAlign_uid53_fpExpEM1Test_q;
rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q(0)) & ld_msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b_q);
rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,222)@7
RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 2);
--ld_RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_a(DELAY,679)@7
ld_RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b, xout => ld_RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,223)@8
rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage2Idx2Pad2_uid222_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage136dto2_uid223_fxpInPostAlign_uid53_fpExpEM1Test_b_to_rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_a_q;
--rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test(LOGICAL,217)@5
rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_a <= GND_q;
rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_b <= msbx_uid190_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_i <= rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_a or rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_b;
rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q, xin => rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_b(DELAY,676)@6
ld_rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q, xout => ld_rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test(BITSELECT,218)@7
RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_in <= rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q;
RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_b <= RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_in(36 downto 1);
--rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test(BITJOIN,219)@7
rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q <= ld_rightShiftStage2Idx1Pad1_uid218_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_b_q & RightShiftStage136dto1_uid219_fxpInPostAlign_uid53_fpExpEM1Test_b;
--ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d(DELAY,688)@7
ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d : dspba_delay
GENERIC MAP ( width => 37, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q, xout => ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2(REG,376)@7
reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2_q <= rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1(REG,375)@5
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q <= rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_b(DELAY,686)@6
ld_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test(MUX,229)@8
rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_s <= ld_reg_rightShiftStageSel1Dto0_uid229_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_1_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_b_q;
rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test: PROCESS (rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_s, en, reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2_q, ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d_q, rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_q, rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q <= reg_rightShiftStage1_uid216_fxpInPostAlign_uid53_fpExpEM1Test_0_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q <= ld_rightShiftStage2Idx1_uid220_fxpInPostAlign_uid53_fpExpEM1Test_q_to_rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_d_q;
WHEN "10" => rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage2Idx2_uid224_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN "11" => rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q <= rightShiftStage2Idx3_uid228_fxpInPostAlign_uid53_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePreRnd_uid54_fpExpEM1Test(BITSELECT,53)@8
ePreRnd_uid54_fpExpEM1Test_in <= rightShiftStage2_uid230_fxpInPostAlign_uid53_fpExpEM1Test_q;
ePreRnd_uid54_fpExpEM1Test_b <= ePreRnd_uid54_fpExpEM1Test_in(36 downto 26);
--xv0_uid232_constMult(BITSELECT,231)@8
xv0_uid232_constMult_in <= ePreRnd_uid54_fpExpEM1Test_b(5 downto 0);
xv0_uid232_constMult_b <= xv0_uid232_constMult_in(5 downto 0);
--reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0(REG,388)@8
reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q <= xv0_uid232_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a(DELAY,694)@9
ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q, xout => ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid235_constMult(LOOKUP,234)@10
p0_uid235_constMult: PROCESS (ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid232_constMult_0_to_p0_uid235_constMult_0_q_to_p0_uid235_constMult_a_q) IS
WHEN "000000" => p0_uid235_constMult_q <= "0000000000000000000000000000000000000000";
WHEN "000001" => p0_uid235_constMult_q <= "0000001011000101110010000101111111011111";
WHEN "000010" => p0_uid235_constMult_q <= "0000010110001011100100001011111110111110";
WHEN "000011" => p0_uid235_constMult_q <= "0000100001010001010110010001111110011101";
WHEN "000100" => p0_uid235_constMult_q <= "0000101100010111001000010111111101111100";
WHEN "000101" => p0_uid235_constMult_q <= "0000110111011100111010011101111101011011";
WHEN "000110" => p0_uid235_constMult_q <= "0001000010100010101100100011111100111010";
WHEN "000111" => p0_uid235_constMult_q <= "0001001101101000011110101001111100011001";
WHEN "001000" => p0_uid235_constMult_q <= "0001011000101110010000101111111011111000";
WHEN "001001" => p0_uid235_constMult_q <= "0001100011110100000010110101111011010111";
WHEN "001010" => p0_uid235_constMult_q <= "0001101110111001110100111011111010110110";
WHEN "001011" => p0_uid235_constMult_q <= "0001111001111111100111000001111010010101";
WHEN "001100" => p0_uid235_constMult_q <= "0010000101000101011001000111111001110100";
WHEN "001101" => p0_uid235_constMult_q <= "0010010000001011001011001101111001010011";
WHEN "001110" => p0_uid235_constMult_q <= "0010011011010000111101010011111000110010";
WHEN "001111" => p0_uid235_constMult_q <= "0010100110010110101111011001111000010001";
WHEN "010000" => p0_uid235_constMult_q <= "0010110001011100100001011111110111110000";
WHEN "010001" => p0_uid235_constMult_q <= "0010111100100010010011100101110111001111";
WHEN "010010" => p0_uid235_constMult_q <= "0011000111101000000101101011110110101110";
WHEN "010011" => p0_uid235_constMult_q <= "0011010010101101110111110001110110001101";
WHEN "010100" => p0_uid235_constMult_q <= "0011011101110011101001110111110101101100";
WHEN "010101" => p0_uid235_constMult_q <= "0011101000111001011011111101110101001011";
WHEN "010110" => p0_uid235_constMult_q <= "0011110011111111001110000011110100101010";
WHEN "010111" => p0_uid235_constMult_q <= "0011111111000101000000001001110100001001";
WHEN "011000" => p0_uid235_constMult_q <= "0100001010001010110010001111110011101000";
WHEN "011001" => p0_uid235_constMult_q <= "0100010101010000100100010101110011000111";
WHEN "011010" => p0_uid235_constMult_q <= "0100100000010110010110011011110010100110";
WHEN "011011" => p0_uid235_constMult_q <= "0100101011011100001000100001110010000101";
WHEN "011100" => p0_uid235_constMult_q <= "0100110110100001111010100111110001100100";
WHEN "011101" => p0_uid235_constMult_q <= "0101000001100111101100101101110001000011";
WHEN "011110" => p0_uid235_constMult_q <= "0101001100101101011110110011110000100010";
WHEN "011111" => p0_uid235_constMult_q <= "0101010111110011010000111001110000000001";
WHEN "100000" => p0_uid235_constMult_q <= "0101100010111001000010111111101111100000";
WHEN "100001" => p0_uid235_constMult_q <= "0101101101111110110101000101101110111111";
WHEN "100010" => p0_uid235_constMult_q <= "0101111001000100100111001011101110011110";
WHEN "100011" => p0_uid235_constMult_q <= "0110000100001010011001010001101101111101";
WHEN "100100" => p0_uid235_constMult_q <= "0110001111010000001011010111101101011100";
WHEN "100101" => p0_uid235_constMult_q <= "0110011010010101111101011101101100111011";
WHEN "100110" => p0_uid235_constMult_q <= "0110100101011011101111100011101100011010";
WHEN "100111" => p0_uid235_constMult_q <= "0110110000100001100001101001101011111001";
WHEN "101000" => p0_uid235_constMult_q <= "0110111011100111010011101111101011011000";
WHEN "101001" => p0_uid235_constMult_q <= "0111000110101101000101110101101010110111";
WHEN "101010" => p0_uid235_constMult_q <= "0111010001110010110111111011101010010110";
WHEN "101011" => p0_uid235_constMult_q <= "0111011100111000101010000001101001110101";
WHEN "101100" => p0_uid235_constMult_q <= "0111100111111110011100000111101001010100";
WHEN "101101" => p0_uid235_constMult_q <= "0111110011000100001110001101101000110011";
WHEN "101110" => p0_uid235_constMult_q <= "0111111110001010000000010011101000010010";
WHEN "101111" => p0_uid235_constMult_q <= "1000001001001111110010011001100111110001";
WHEN "110000" => p0_uid235_constMult_q <= "1000010100010101100100011111100111010000";
WHEN "110001" => p0_uid235_constMult_q <= "1000011111011011010110100101100110101111";
WHEN "110010" => p0_uid235_constMult_q <= "1000101010100001001000101011100110001110";
WHEN "110011" => p0_uid235_constMult_q <= "1000110101100110111010110001100101101101";
WHEN "110100" => p0_uid235_constMult_q <= "1001000000101100101100110111100101001100";
WHEN "110101" => p0_uid235_constMult_q <= "1001001011110010011110111101100100101011";
WHEN "110110" => p0_uid235_constMult_q <= "1001010110111000010001000011100100001010";
WHEN "110111" => p0_uid235_constMult_q <= "1001100001111110000011001001100011101001";
WHEN "111000" => p0_uid235_constMult_q <= "1001101101000011110101001111100011001000";
WHEN "111001" => p0_uid235_constMult_q <= "1001111000001001100111010101100010100111";
WHEN "111010" => p0_uid235_constMult_q <= "1010000011001111011001011011100010000110";
WHEN "111011" => p0_uid235_constMult_q <= "1010001110010101001011100001100001100101";
WHEN "111100" => p0_uid235_constMult_q <= "1010011001011010111101100111100001000100";
WHEN "111101" => p0_uid235_constMult_q <= "1010100100100000101111101101100000100011";
WHEN "111110" => p0_uid235_constMult_q <= "1010101111100110100001110011100000000010";
WHEN "111111" => p0_uid235_constMult_q <= "1010111010101100010011111001011111100001";
WHEN OTHERS =>
p0_uid235_constMult_q <= "0000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid233_constMult(BITSELECT,232)@8
xv1_uid233_constMult_in <= ePreRnd_uid54_fpExpEM1Test_b;
xv1_uid233_constMult_b <= xv1_uid233_constMult_in(10 downto 6);
--reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0(REG,387)@8
reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0_q <= xv1_uid233_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid234_constMult(LOOKUP,233)@9
p1_uid234_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid234_constMult_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid233_constMult_0_to_p1_uid234_constMult_0_q) IS
WHEN "00000" => p1_uid234_constMult_q <= "000000000000000000000000000000000000000000000";
WHEN "00001" => p1_uid234_constMult_q <= "000001011000101110010000101111111011111000000";
WHEN "00010" => p1_uid234_constMult_q <= "000010110001011100100001011111110111110000000";
WHEN "00011" => p1_uid234_constMult_q <= "000100001010001010110010001111110011101000000";
WHEN "00100" => p1_uid234_constMult_q <= "000101100010111001000010111111101111100000000";
WHEN "00101" => p1_uid234_constMult_q <= "000110111011100111010011101111101011011000000";
WHEN "00110" => p1_uid234_constMult_q <= "001000010100010101100100011111100111010000000";
WHEN "00111" => p1_uid234_constMult_q <= "001001101101000011110101001111100011001000000";
WHEN "01000" => p1_uid234_constMult_q <= "001011000101110010000101111111011111000000000";
WHEN "01001" => p1_uid234_constMult_q <= "001100011110100000010110101111011010111000000";
WHEN "01010" => p1_uid234_constMult_q <= "001101110111001110100111011111010110110000000";
WHEN "01011" => p1_uid234_constMult_q <= "001111001111111100111000001111010010101000000";
WHEN "01100" => p1_uid234_constMult_q <= "010000101000101011001000111111001110100000000";
WHEN "01101" => p1_uid234_constMult_q <= "010010000001011001011001101111001010011000000";
WHEN "01110" => p1_uid234_constMult_q <= "010011011010000111101010011111000110010000000";
WHEN "01111" => p1_uid234_constMult_q <= "010100110010110101111011001111000010001000000";
WHEN "10000" => p1_uid234_constMult_q <= "101001110100011011110100000001000010000000000";
WHEN "10001" => p1_uid234_constMult_q <= "101011001101001010000100110000111101111000000";
WHEN "10010" => p1_uid234_constMult_q <= "101100100101111000010101100000111001110000000";
WHEN "10011" => p1_uid234_constMult_q <= "101101111110100110100110010000110101101000000";
WHEN "10100" => p1_uid234_constMult_q <= "101111010111010100110111000000110001100000000";
WHEN "10101" => p1_uid234_constMult_q <= "110000110000000011000111110000101101011000000";
WHEN "10110" => p1_uid234_constMult_q <= "110010001000110001011000100000101001010000000";
WHEN "10111" => p1_uid234_constMult_q <= "110011100001011111101001010000100101001000000";
WHEN "11000" => p1_uid234_constMult_q <= "110100111010001101111010000000100001000000000";
WHEN "11001" => p1_uid234_constMult_q <= "110110010010111100001010110000011100111000000";
WHEN "11010" => p1_uid234_constMult_q <= "110111101011101010011011100000011000110000000";
WHEN "11011" => p1_uid234_constMult_q <= "111001000100011000101100010000010100101000000";
WHEN "11100" => p1_uid234_constMult_q <= "111010011101000110111101000000010000100000000";
WHEN "11101" => p1_uid234_constMult_q <= "111011110101110101001101110000001100011000000";
WHEN "11110" => p1_uid234_constMult_q <= "111101001110100011011110100000001000010000000";
WHEN "11111" => p1_uid234_constMult_q <= "111110100111010001101111010000000100001000000";
WHEN OTHERS =>
p1_uid234_constMult_q <= "000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid236_constMult(ADD,235)@10
lev1_a0_uid236_constMult_a <= STD_LOGIC_VECTOR((46 downto 45 => p1_uid234_constMult_q(44)) & p1_uid234_constMult_q);
lev1_a0_uid236_constMult_b <= STD_LOGIC_VECTOR('0' & "000000" & p0_uid235_constMult_q);
lev1_a0_uid236_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid236_constMult_a) + SIGNED(lev1_a0_uid236_constMult_b));
lev1_a0_uid236_constMult_q <= lev1_a0_uid236_constMult_o(45 downto 0);
--sR_uid237_constMult(BITSELECT,236)@10
sR_uid237_constMult_in <= lev1_a0_uid236_constMult_q(44 downto 0);
sR_uid237_constMult_b <= sR_uid237_constMult_in(44 downto 2);
--reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1(REG,390)@10
reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1_q <= "0000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1_q <= sR_uid237_constMult_b;
END IF;
END IF;
END PROCESS;
--pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test(BITJOIN,64)@10
pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_q <= rightShiftStage2_uid279_fxpInPostAlign_X_uid64_fpExpEM1Test_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0(REG,389)@10
reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0_q <= "000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0_q <= pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--yExt_uid65_fpExpEM1Test(SUB,65)@11
yExt_uid65_fpExpEM1Test_a <= STD_LOGIC_VECTOR((43 downto 42 => reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0_q(41)) & reg_pad_fxpInPostAlignR_X_uid65_uid65_fpExpEM1Test_0_to_yExt_uid65_fpExpEM1Test_0_q);
yExt_uid65_fpExpEM1Test_b <= STD_LOGIC_VECTOR((43 downto 43 => reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1_q(42)) & reg_sR_uid237_constMult_0_to_yExt_uid65_fpExpEM1Test_1_q);
yExt_uid65_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(yExt_uid65_fpExpEM1Test_a) - SIGNED(yExt_uid65_fpExpEM1Test_b));
yExt_uid65_fpExpEM1Test_q <= yExt_uid65_fpExpEM1Test_o(43 downto 0);
--yRed_uid69_fpExpEM1Test(BITSELECT,68)@11
yRed_uid69_fpExpEM1Test_in <= yExt_uid65_fpExpEM1Test_q(31 downto 0);
yRed_uid69_fpExpEM1Test_b <= yRed_uid69_fpExpEM1Test_in(31 downto 6);
--reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2(REG,392)@11
reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2_q <= yRed_uid69_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--YExt43_uid67_fpExpEM1Test(BITSELECT,66)@11
YExt43_uid67_fpExpEM1Test_in <= yExt_uid65_fpExpEM1Test_q;
YExt43_uid67_fpExpEM1Test_b <= YExt43_uid67_fpExpEM1Test_in(43 downto 43);
--reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1(REG,391)@11
reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1_q <= YExt43_uid67_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--yRedPostMux_uid70_fpExpEM1Test(MUX,69)@12
yRedPostMux_uid70_fpExpEM1Test_s <= reg_YExt43_uid67_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_1_q;
yRedPostMux_uid70_fpExpEM1Test: PROCESS (yRedPostMux_uid70_fpExpEM1Test_s, en, reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2_q, zY_uid68_fpExpEM1Test_q)
BEGIN
CASE yRedPostMux_uid70_fpExpEM1Test_s IS
WHEN "0" => yRedPostMux_uid70_fpExpEM1Test_q <= reg_yRed_uid69_fpExpEM1Test_0_to_yRedPostMux_uid70_fpExpEM1Test_2_q;
WHEN "1" => yRedPostMux_uid70_fpExpEM1Test_q <= zY_uid68_fpExpEM1Test_q;
WHEN OTHERS => yRedPostMux_uid70_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid72_fpExpEM1Test(BITSELECT,71)@12
addr_uid72_fpExpEM1Test_in <= yRedPostMux_uid70_fpExpEM1Test_q;
addr_uid72_fpExpEM1Test_b <= addr_uid72_fpExpEM1Test_in(25 downto 19);
--reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0(REG,393)@12
reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0_q <= addr_uid72_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid285_exp10TabGen(LOOKUP,284)@13
memoryC2_uid285_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid285_exp10TabGen_q <= "00100000000111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid285_exp10TabGen_q <= "00100000000111";
WHEN "0000001" => memoryC2_uid285_exp10TabGen_q <= "00100000011010";
WHEN "0000010" => memoryC2_uid285_exp10TabGen_q <= "00100000101001";
WHEN "0000011" => memoryC2_uid285_exp10TabGen_q <= "00100000111001";
WHEN "0000100" => memoryC2_uid285_exp10TabGen_q <= "00100001001001";
WHEN "0000101" => memoryC2_uid285_exp10TabGen_q <= "00100001011000";
WHEN "0000110" => memoryC2_uid285_exp10TabGen_q <= "00100001101010";
WHEN "0000111" => memoryC2_uid285_exp10TabGen_q <= "00100001111101";
WHEN "0001000" => memoryC2_uid285_exp10TabGen_q <= "00100010001100";
WHEN "0001001" => memoryC2_uid285_exp10TabGen_q <= "00100010011101";
WHEN "0001010" => memoryC2_uid285_exp10TabGen_q <= "00100010101111";
WHEN "0001011" => memoryC2_uid285_exp10TabGen_q <= "00100011000001";
WHEN "0001100" => memoryC2_uid285_exp10TabGen_q <= "00100011010010";
WHEN "0001101" => memoryC2_uid285_exp10TabGen_q <= "00100011100100";
WHEN "0001110" => memoryC2_uid285_exp10TabGen_q <= "00100011110110";
WHEN "0001111" => memoryC2_uid285_exp10TabGen_q <= "00100100000111";
WHEN "0010000" => memoryC2_uid285_exp10TabGen_q <= "00100100011010";
WHEN "0010001" => memoryC2_uid285_exp10TabGen_q <= "00100100101011";
WHEN "0010010" => memoryC2_uid285_exp10TabGen_q <= "00100100111110";
WHEN "0010011" => memoryC2_uid285_exp10TabGen_q <= "00100101010001";
WHEN "0010100" => memoryC2_uid285_exp10TabGen_q <= "00100101100100";
WHEN "0010101" => memoryC2_uid285_exp10TabGen_q <= "00100101110111";
WHEN "0010110" => memoryC2_uid285_exp10TabGen_q <= "00100110001000";
WHEN "0010111" => memoryC2_uid285_exp10TabGen_q <= "00100110011110";
WHEN "0011000" => memoryC2_uid285_exp10TabGen_q <= "00100110101111";
WHEN "0011001" => memoryC2_uid285_exp10TabGen_q <= "00100111000101";
WHEN "0011010" => memoryC2_uid285_exp10TabGen_q <= "00100111011000";
WHEN "0011011" => memoryC2_uid285_exp10TabGen_q <= "00100111101001";
WHEN "0011100" => memoryC2_uid285_exp10TabGen_q <= "00101000000000";
WHEN "0011101" => memoryC2_uid285_exp10TabGen_q <= "00101000010011";
WHEN "0011110" => memoryC2_uid285_exp10TabGen_q <= "00101000101000";
WHEN "0011111" => memoryC2_uid285_exp10TabGen_q <= "00101000111100";
WHEN "0100000" => memoryC2_uid285_exp10TabGen_q <= "00101001001110";
WHEN "0100001" => memoryC2_uid285_exp10TabGen_q <= "00101001100101";
WHEN "0100010" => memoryC2_uid285_exp10TabGen_q <= "00101001111000";
WHEN "0100011" => memoryC2_uid285_exp10TabGen_q <= "00101010001111";
WHEN "0100100" => memoryC2_uid285_exp10TabGen_q <= "00101010100011";
WHEN "0100101" => memoryC2_uid285_exp10TabGen_q <= "00101010111000";
WHEN "0100110" => memoryC2_uid285_exp10TabGen_q <= "00101011001100";
WHEN "0100111" => memoryC2_uid285_exp10TabGen_q <= "00101011100100";
WHEN "0101000" => memoryC2_uid285_exp10TabGen_q <= "00101011111100";
WHEN "0101001" => memoryC2_uid285_exp10TabGen_q <= "00101100001111";
WHEN "0101010" => memoryC2_uid285_exp10TabGen_q <= "00101100100111";
WHEN "0101011" => memoryC2_uid285_exp10TabGen_q <= "00101100111100";
WHEN "0101100" => memoryC2_uid285_exp10TabGen_q <= "00101101010010";
WHEN "0101101" => memoryC2_uid285_exp10TabGen_q <= "00101101101011";
WHEN "0101110" => memoryC2_uid285_exp10TabGen_q <= "00101110000010";
WHEN "0101111" => memoryC2_uid285_exp10TabGen_q <= "00101110011010";
WHEN "0110000" => memoryC2_uid285_exp10TabGen_q <= "00101110101111";
WHEN "0110001" => memoryC2_uid285_exp10TabGen_q <= "00101111000101";
WHEN "0110010" => memoryC2_uid285_exp10TabGen_q <= "00101111100000";
WHEN "0110011" => memoryC2_uid285_exp10TabGen_q <= "00101111111000";
WHEN "0110100" => memoryC2_uid285_exp10TabGen_q <= "00110000001101";
WHEN "0110101" => memoryC2_uid285_exp10TabGen_q <= "00110000101000";
WHEN "0110110" => memoryC2_uid285_exp10TabGen_q <= "00110000111110";
WHEN "0110111" => memoryC2_uid285_exp10TabGen_q <= "00110001011001";
WHEN "0111000" => memoryC2_uid285_exp10TabGen_q <= "00110001110000";
WHEN "0111001" => memoryC2_uid285_exp10TabGen_q <= "00110010001010";
WHEN "0111010" => memoryC2_uid285_exp10TabGen_q <= "00110010100010";
WHEN "0111011" => memoryC2_uid285_exp10TabGen_q <= "00110010111100";
WHEN "0111100" => memoryC2_uid285_exp10TabGen_q <= "00110011010110";
WHEN "0111101" => memoryC2_uid285_exp10TabGen_q <= "00110011110000";
WHEN "0111110" => memoryC2_uid285_exp10TabGen_q <= "00110100000111";
WHEN "0111111" => memoryC2_uid285_exp10TabGen_q <= "00110100100011";
WHEN "1000000" => memoryC2_uid285_exp10TabGen_q <= "00110100111101";
WHEN "1000001" => memoryC2_uid285_exp10TabGen_q <= "00110101011001";
WHEN "1000010" => memoryC2_uid285_exp10TabGen_q <= "00110101110011";
WHEN "1000011" => memoryC2_uid285_exp10TabGen_q <= "00110110001110";
WHEN "1000100" => memoryC2_uid285_exp10TabGen_q <= "00110110101001";
WHEN "1000101" => memoryC2_uid285_exp10TabGen_q <= "00110111000101";
WHEN "1000110" => memoryC2_uid285_exp10TabGen_q <= "00110111100000";
WHEN "1000111" => memoryC2_uid285_exp10TabGen_q <= "00110111111011";
WHEN "1001000" => memoryC2_uid285_exp10TabGen_q <= "00111000011010";
WHEN "1001001" => memoryC2_uid285_exp10TabGen_q <= "00111000110100";
WHEN "1001010" => memoryC2_uid285_exp10TabGen_q <= "00111001010001";
WHEN "1001011" => memoryC2_uid285_exp10TabGen_q <= "00111001101110";
WHEN "1001100" => memoryC2_uid285_exp10TabGen_q <= "00111010001010";
WHEN "1001101" => memoryC2_uid285_exp10TabGen_q <= "00111010100111";
WHEN "1001110" => memoryC2_uid285_exp10TabGen_q <= "00111011000111";
WHEN "1001111" => memoryC2_uid285_exp10TabGen_q <= "00111011100000";
WHEN "1010000" => memoryC2_uid285_exp10TabGen_q <= "00111100000010";
WHEN "1010001" => memoryC2_uid285_exp10TabGen_q <= "00111100011110";
WHEN "1010010" => memoryC2_uid285_exp10TabGen_q <= "00111101000000";
WHEN "1010011" => memoryC2_uid285_exp10TabGen_q <= "00111101011101";
WHEN "1010100" => memoryC2_uid285_exp10TabGen_q <= "00111101111010";
WHEN "1010101" => memoryC2_uid285_exp10TabGen_q <= "00111110011011";
WHEN "1010110" => memoryC2_uid285_exp10TabGen_q <= "00111110111010";
WHEN "1010111" => memoryC2_uid285_exp10TabGen_q <= "00111111011001";
WHEN "1011000" => memoryC2_uid285_exp10TabGen_q <= "00111111111010";
WHEN "1011001" => memoryC2_uid285_exp10TabGen_q <= "01000000010111";
WHEN "1011010" => memoryC2_uid285_exp10TabGen_q <= "01000000111001";
WHEN "1011011" => memoryC2_uid285_exp10TabGen_q <= "01000001011011";
WHEN "1011100" => memoryC2_uid285_exp10TabGen_q <= "01000001111011";
WHEN "1011101" => memoryC2_uid285_exp10TabGen_q <= "01000010011100";
WHEN "1011110" => memoryC2_uid285_exp10TabGen_q <= "01000010111111";
WHEN "1011111" => memoryC2_uid285_exp10TabGen_q <= "01000011011111";
WHEN "1100000" => memoryC2_uid285_exp10TabGen_q <= "01000100000011";
WHEN "1100001" => memoryC2_uid285_exp10TabGen_q <= "01000100100001";
WHEN "1100010" => memoryC2_uid285_exp10TabGen_q <= "01000101000100";
WHEN "1100011" => memoryC2_uid285_exp10TabGen_q <= "01000101101001";
WHEN "1100100" => memoryC2_uid285_exp10TabGen_q <= "01000110001100";
WHEN "1100101" => memoryC2_uid285_exp10TabGen_q <= "01000110101111";
WHEN "1100110" => memoryC2_uid285_exp10TabGen_q <= "01000111010010";
WHEN "1100111" => memoryC2_uid285_exp10TabGen_q <= "01000111110101";
WHEN "1101000" => memoryC2_uid285_exp10TabGen_q <= "01001000011010";
WHEN "1101001" => memoryC2_uid285_exp10TabGen_q <= "01001000111100";
WHEN "1101010" => memoryC2_uid285_exp10TabGen_q <= "01001001100100";
WHEN "1101011" => memoryC2_uid285_exp10TabGen_q <= "01001010000110";
WHEN "1101100" => memoryC2_uid285_exp10TabGen_q <= "01001010101110";
WHEN "1101101" => memoryC2_uid285_exp10TabGen_q <= "01001011010001";
WHEN "1101110" => memoryC2_uid285_exp10TabGen_q <= "01001011111000";
WHEN "1101111" => memoryC2_uid285_exp10TabGen_q <= "01001100011101";
WHEN "1110000" => memoryC2_uid285_exp10TabGen_q <= "01001101000100";
WHEN "1110001" => memoryC2_uid285_exp10TabGen_q <= "01001101101101";
WHEN "1110010" => memoryC2_uid285_exp10TabGen_q <= "01001110010100";
WHEN "1110011" => memoryC2_uid285_exp10TabGen_q <= "01001110111000";
WHEN "1110100" => memoryC2_uid285_exp10TabGen_q <= "01001111100010";
WHEN "1110101" => memoryC2_uid285_exp10TabGen_q <= "01010000000111";
WHEN "1110110" => memoryC2_uid285_exp10TabGen_q <= "01010000110001";
WHEN "1110111" => memoryC2_uid285_exp10TabGen_q <= "01010001011001";
WHEN "1111000" => memoryC2_uid285_exp10TabGen_q <= "01010010000010";
WHEN "1111001" => memoryC2_uid285_exp10TabGen_q <= "01010010101011";
WHEN "1111010" => memoryC2_uid285_exp10TabGen_q <= "01010011010101";
WHEN "1111011" => memoryC2_uid285_exp10TabGen_q <= "01010100000000";
WHEN "1111100" => memoryC2_uid285_exp10TabGen_q <= "01010100101010";
WHEN "1111101" => memoryC2_uid285_exp10TabGen_q <= "01010101010101";
WHEN "1111110" => memoryC2_uid285_exp10TabGen_q <= "01010101111111";
WHEN "1111111" => memoryC2_uid285_exp10TabGen_q <= "01010110101001";
WHEN OTHERS =>
memoryC2_uid285_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_yRedPostMux_uid70_fpExpEM1Test_q_to_yPPolyEval_uid73_fpExpEM1Test_a(DELAY,488)@12
ld_yRedPostMux_uid70_fpExpEM1Test_q_to_yPPolyEval_uid73_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yRedPostMux_uid70_fpExpEM1Test_q, xout => ld_yRedPostMux_uid70_fpExpEM1Test_q_to_yPPolyEval_uid73_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid73_fpExpEM1Test(BITSELECT,72)@13
yPPolyEval_uid73_fpExpEM1Test_in <= ld_yRedPostMux_uid70_fpExpEM1Test_q_to_yPPolyEval_uid73_fpExpEM1Test_a_q(18 downto 0);
yPPolyEval_uid73_fpExpEM1Test_b <= yPPolyEval_uid73_fpExpEM1Test_in(18 downto 0);
--yT1_uid287_exp10PolyEval(BITSELECT,286)@13
yT1_uid287_exp10PolyEval_in <= yPPolyEval_uid73_fpExpEM1Test_b;
yT1_uid287_exp10PolyEval_b <= yT1_uid287_exp10PolyEval_in(18 downto 5);
--reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0(REG,394)@13
reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0_q <= yT1_uid287_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid348_pT1_uid288_exp10PolyEval(MULT,347)@14
prodXY_uid348_pT1_uid288_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid348_pT1_uid288_exp10PolyEval_a),15)) * SIGNED(prodXY_uid348_pT1_uid288_exp10PolyEval_b);
prodXY_uid348_pT1_uid288_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid348_pT1_uid288_exp10PolyEval_a <= (others => '0');
prodXY_uid348_pT1_uid288_exp10PolyEval_b <= (others => '0');
prodXY_uid348_pT1_uid288_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid348_pT1_uid288_exp10PolyEval_a <= reg_yT1_uid287_exp10PolyEval_0_to_prodXY_uid348_pT1_uid288_exp10PolyEval_0_q;
prodXY_uid348_pT1_uid288_exp10PolyEval_b <= memoryC2_uid285_exp10TabGen_q;
prodXY_uid348_pT1_uid288_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid348_pT1_uid288_exp10PolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid348_pT1_uid288_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid348_pT1_uid288_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid348_pT1_uid288_exp10PolyEval_q <= prodXY_uid348_pT1_uid288_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval(BITSELECT,348)@17
prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_in <= prodXY_uid348_pT1_uid288_exp10PolyEval_q;
prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_b <= prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_in(27 downto 13);
--highBBits_uid290_exp10PolyEval(BITSELECT,289)@17
highBBits_uid290_exp10PolyEval_in <= prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_b;
highBBits_uid290_exp10PolyEval_b <= highBBits_uid290_exp10PolyEval_in(14 downto 1);
--ld_reg_addr_uid72_fpExpEM1Test_0_to_memoryC1_uid283_exp10TabGen_0_q_to_memoryC1_uid283_exp10TabGen_a(DELAY,748)@13
ld_reg_addr_uid72_fpExpEM1Test_0_to_memoryC1_uid283_exp10TabGen_0_q_to_memoryC1_uid283_exp10TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid72_fpExpEM1Test_0_to_memoryC2_uid285_exp10TabGen_0_q, xout => ld_reg_addr_uid72_fpExpEM1Test_0_to_memoryC1_uid283_exp10TabGen_0_q_to_memoryC1_uid283_exp10TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid283_exp10TabGen(LOOKUP,282)@16
memoryC1_uid283_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid283_exp10TabGen_q <= "0001111111111111111110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid72_fpExpEM1Test_0_to_memoryC1_uid283_exp10TabGen_0_q_to_memoryC1_uid283_exp10TabGen_a_q) IS
WHEN "0000000" => memoryC1_uid283_exp10TabGen_q <= "0001111111111111111110";
WHEN "0000001" => memoryC1_uid283_exp10TabGen_q <= "0010000001000000001011";
WHEN "0000010" => memoryC1_uid283_exp10TabGen_q <= "0010000010000000111101";
WHEN "0000011" => memoryC1_uid283_exp10TabGen_q <= "0010000011000010001110";
WHEN "0000100" => memoryC1_uid283_exp10TabGen_q <= "0010000100000100000000";
WHEN "0000101" => memoryC1_uid283_exp10TabGen_q <= "0010000101000110010100";
WHEN "0000110" => memoryC1_uid283_exp10TabGen_q <= "0010000110001001000110";
WHEN "0000111" => memoryC1_uid283_exp10TabGen_q <= "0010000111001100011010";
WHEN "0001000" => memoryC1_uid283_exp10TabGen_q <= "0010001000010000010011";
WHEN "0001001" => memoryC1_uid283_exp10TabGen_q <= "0010001001010100101101";
WHEN "0001010" => memoryC1_uid283_exp10TabGen_q <= "0010001010011001101000";
WHEN "0001011" => memoryC1_uid283_exp10TabGen_q <= "0010001011011111000101";
WHEN "0001100" => memoryC1_uid283_exp10TabGen_q <= "0010001100100101000111";
WHEN "0001101" => memoryC1_uid283_exp10TabGen_q <= "0010001101101011101011";
WHEN "0001110" => memoryC1_uid283_exp10TabGen_q <= "0010001110110010110010";
WHEN "0001111" => memoryC1_uid283_exp10TabGen_q <= "0010001111111010011110";
WHEN "0010000" => memoryC1_uid283_exp10TabGen_q <= "0010010001000010101100";
WHEN "0010001" => memoryC1_uid283_exp10TabGen_q <= "0010010010001011100010";
WHEN "0010010" => memoryC1_uid283_exp10TabGen_q <= "0010010011010100111001";
WHEN "0010011" => memoryC1_uid283_exp10TabGen_q <= "0010010100011110110110";
WHEN "0010100" => memoryC1_uid283_exp10TabGen_q <= "0010010101101001010111";
WHEN "0010101" => memoryC1_uid283_exp10TabGen_q <= "0010010110110100011111";
WHEN "0010110" => memoryC1_uid283_exp10TabGen_q <= "0010011000000000001101";
WHEN "0010111" => memoryC1_uid283_exp10TabGen_q <= "0010011001001100011110";
WHEN "0011000" => memoryC1_uid283_exp10TabGen_q <= "0010011010011001011001";
WHEN "0011001" => memoryC1_uid283_exp10TabGen_q <= "0010011011100110110111";
WHEN "0011010" => memoryC1_uid283_exp10TabGen_q <= "0010011100110100111111";
WHEN "0011011" => memoryC1_uid283_exp10TabGen_q <= "0010011110000011101111";
WHEN "0011100" => memoryC1_uid283_exp10TabGen_q <= "0010011111010011000010";
WHEN "0011101" => memoryC1_uid283_exp10TabGen_q <= "0010100000100011000001";
WHEN "0011110" => memoryC1_uid283_exp10TabGen_q <= "0010100001110011100110";
WHEN "0011111" => memoryC1_uid283_exp10TabGen_q <= "0010100011000100110100";
WHEN "0100000" => memoryC1_uid283_exp10TabGen_q <= "0010100100010110101101";
WHEN "0100001" => memoryC1_uid283_exp10TabGen_q <= "0010100101101001001011";
WHEN "0100010" => memoryC1_uid283_exp10TabGen_q <= "0010100110111100010110";
WHEN "0100011" => memoryC1_uid283_exp10TabGen_q <= "0010101000010000000111";
WHEN "0100100" => memoryC1_uid283_exp10TabGen_q <= "0010101001100100100110";
WHEN "0100101" => memoryC1_uid283_exp10TabGen_q <= "0010101010111001101110";
WHEN "0100110" => memoryC1_uid283_exp10TabGen_q <= "0010101100001111100001";
WHEN "0100111" => memoryC1_uid283_exp10TabGen_q <= "0010101101100101111100";
WHEN "0101000" => memoryC1_uid283_exp10TabGen_q <= "0010101110111101000011";
WHEN "0101001" => memoryC1_uid283_exp10TabGen_q <= "0010110000010100111010";
WHEN "0101010" => memoryC1_uid283_exp10TabGen_q <= "0010110001101101011001";
WHEN "0101011" => memoryC1_uid283_exp10TabGen_q <= "0010110011000110101000";
WHEN "0101100" => memoryC1_uid283_exp10TabGen_q <= "0010110100100000100010";
WHEN "0101101" => memoryC1_uid283_exp10TabGen_q <= "0010110101111011000110";
WHEN "0101110" => memoryC1_uid283_exp10TabGen_q <= "0010110111010110011010";
WHEN "0101111" => memoryC1_uid283_exp10TabGen_q <= "0010111000110010011100";
WHEN "0110000" => memoryC1_uid283_exp10TabGen_q <= "0010111010001111001111";
WHEN "0110001" => memoryC1_uid283_exp10TabGen_q <= "0010111011101100101111";
WHEN "0110010" => memoryC1_uid283_exp10TabGen_q <= "0010111101001010111010";
WHEN "0110011" => memoryC1_uid283_exp10TabGen_q <= "0010111110101001110111";
WHEN "0110100" => memoryC1_uid283_exp10TabGen_q <= "0011000000001001100110";
WHEN "0110101" => memoryC1_uid283_exp10TabGen_q <= "0011000001101010000001";
WHEN "0110110" => memoryC1_uid283_exp10TabGen_q <= "0011000011001011010000";
WHEN "0110111" => memoryC1_uid283_exp10TabGen_q <= "0011000100101101001100";
WHEN "0111000" => memoryC1_uid283_exp10TabGen_q <= "0011000110001111111101";
WHEN "0111001" => memoryC1_uid283_exp10TabGen_q <= "0011000111110011011100";
WHEN "0111010" => memoryC1_uid283_exp10TabGen_q <= "0011001001010111110000";
WHEN "0111011" => memoryC1_uid283_exp10TabGen_q <= "0011001010111100110101";
WHEN "0111100" => memoryC1_uid283_exp10TabGen_q <= "0011001100100010101100";
WHEN "0111101" => memoryC1_uid283_exp10TabGen_q <= "0011001110001001010111";
WHEN "0111110" => memoryC1_uid283_exp10TabGen_q <= "0011001111110000111001";
WHEN "0111111" => memoryC1_uid283_exp10TabGen_q <= "0011010001011001001001";
WHEN "1000000" => memoryC1_uid283_exp10TabGen_q <= "0011010011000010010000";
WHEN "1000001" => memoryC1_uid283_exp10TabGen_q <= "0011010100101100001011";
WHEN "1000010" => memoryC1_uid283_exp10TabGen_q <= "0011010110010110111101";
WHEN "1000011" => memoryC1_uid283_exp10TabGen_q <= "0011011000000010100011";
WHEN "1000100" => memoryC1_uid283_exp10TabGen_q <= "0011011001101111000000";
WHEN "1000101" => memoryC1_uid283_exp10TabGen_q <= "0011011011011100010010";
WHEN "1000110" => memoryC1_uid283_exp10TabGen_q <= "0011011101001010011100";
WHEN "1000111" => memoryC1_uid283_exp10TabGen_q <= "0011011110111001011110";
WHEN "1001000" => memoryC1_uid283_exp10TabGen_q <= "0011100000101001010011";
WHEN "1001001" => memoryC1_uid283_exp10TabGen_q <= "0011100010011010000111";
WHEN "1001010" => memoryC1_uid283_exp10TabGen_q <= "0011100100001011110000";
WHEN "1001011" => memoryC1_uid283_exp10TabGen_q <= "0011100101111110010010";
WHEN "1001100" => memoryC1_uid283_exp10TabGen_q <= "0011100111110001101111";
WHEN "1001101" => memoryC1_uid283_exp10TabGen_q <= "0011101001100110000101";
WHEN "1001110" => memoryC1_uid283_exp10TabGen_q <= "0011101011011011010010";
WHEN "1001111" => memoryC1_uid283_exp10TabGen_q <= "0011101101010001100010";
WHEN "1010000" => memoryC1_uid283_exp10TabGen_q <= "0011101111001000100101";
WHEN "1010001" => memoryC1_uid283_exp10TabGen_q <= "0011110001000000101001";
WHEN "1010010" => memoryC1_uid283_exp10TabGen_q <= "0011110010111001100100";
WHEN "1010011" => memoryC1_uid283_exp10TabGen_q <= "0011110100110011100001";
WHEN "1010100" => memoryC1_uid283_exp10TabGen_q <= "0011110110101110011011";
WHEN "1010101" => memoryC1_uid283_exp10TabGen_q <= "0011111000101010001111";
WHEN "1010110" => memoryC1_uid283_exp10TabGen_q <= "0011111010100111000011";
WHEN "1010111" => memoryC1_uid283_exp10TabGen_q <= "0011111100100100110111";
WHEN "1011000" => memoryC1_uid283_exp10TabGen_q <= "0011111110100011101000";
WHEN "1011001" => memoryC1_uid283_exp10TabGen_q <= "0100000000100011011101";
WHEN "1011010" => memoryC1_uid283_exp10TabGen_q <= "0100000010100100001101";
WHEN "1011011" => memoryC1_uid283_exp10TabGen_q <= "0100000100100101111110";
WHEN "1011100" => memoryC1_uid283_exp10TabGen_q <= "0100000110101000110010";
WHEN "1011101" => memoryC1_uid283_exp10TabGen_q <= "0100001000101100101000";
WHEN "1011110" => memoryC1_uid283_exp10TabGen_q <= "0100001010110001011110";
WHEN "1011111" => memoryC1_uid283_exp10TabGen_q <= "0100001100110111011010";
WHEN "1100000" => memoryC1_uid283_exp10TabGen_q <= "0100001110111110010101";
WHEN "1100001" => memoryC1_uid283_exp10TabGen_q <= "0100010001000110011010";
WHEN "1100010" => memoryC1_uid283_exp10TabGen_q <= "0100010011001111011111";
WHEN "1100011" => memoryC1_uid283_exp10TabGen_q <= "0100010101011001100111";
WHEN "1100100" => memoryC1_uid283_exp10TabGen_q <= "0100010111100100110110";
WHEN "1100101" => memoryC1_uid283_exp10TabGen_q <= "0100011001110001001100";
WHEN "1100110" => memoryC1_uid283_exp10TabGen_q <= "0100011011111110101000";
WHEN "1100111" => memoryC1_uid283_exp10TabGen_q <= "0100011110001101001100";
WHEN "1101000" => memoryC1_uid283_exp10TabGen_q <= "0100100000011100110110";
WHEN "1101001" => memoryC1_uid283_exp10TabGen_q <= "0100100010101101101011";
WHEN "1101010" => memoryC1_uid283_exp10TabGen_q <= "0100100100111111100011";
WHEN "1101011" => memoryC1_uid283_exp10TabGen_q <= "0100100111010010101010";
WHEN "1101100" => memoryC1_uid283_exp10TabGen_q <= "0100101001100110110110";
WHEN "1101101" => memoryC1_uid283_exp10TabGen_q <= "0100101011111100010001";
WHEN "1101110" => memoryC1_uid283_exp10TabGen_q <= "0100101110010010110011";
WHEN "1101111" => memoryC1_uid283_exp10TabGen_q <= "0100110000101010100011";
WHEN "1110000" => memoryC1_uid283_exp10TabGen_q <= "0100110011000011011111";
WHEN "1110001" => memoryC1_uid283_exp10TabGen_q <= "0100110101011101100100";
WHEN "1110010" => memoryC1_uid283_exp10TabGen_q <= "0100110111111000111010";
WHEN "1110011" => memoryC1_uid283_exp10TabGen_q <= "0100111010010101100001";
WHEN "1110100" => memoryC1_uid283_exp10TabGen_q <= "0100111100110011010001";
WHEN "1110101" => memoryC1_uid283_exp10TabGen_q <= "0100111111010010010101";
WHEN "1110110" => memoryC1_uid283_exp10TabGen_q <= "0101000001110010100100";
WHEN "1110111" => memoryC1_uid283_exp10TabGen_q <= "0101000100010100000110";
WHEN "1111000" => memoryC1_uid283_exp10TabGen_q <= "0101000110110110111001";
WHEN "1111001" => memoryC1_uid283_exp10TabGen_q <= "0101001001011010111101";
WHEN "1111010" => memoryC1_uid283_exp10TabGen_q <= "0101001100000000010100";
WHEN "1111011" => memoryC1_uid283_exp10TabGen_q <= "0101001110100110111100";
WHEN "1111100" => memoryC1_uid283_exp10TabGen_q <= "0101010001001110111010";
WHEN "1111101" => memoryC1_uid283_exp10TabGen_q <= "0101010011111000001011";
WHEN "1111110" => memoryC1_uid283_exp10TabGen_q <= "0101010110100010110010";
WHEN "1111111" => memoryC1_uid283_exp10TabGen_q <= "0101011001001110110000";
WHEN OTHERS =>
memoryC1_uid283_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid291_exp10PolyEval(ADD,290)@17
sumAHighB_uid291_exp10PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid283_exp10TabGen_q(21)) & memoryC1_uid283_exp10TabGen_q);
sumAHighB_uid291_exp10PolyEval_b <= STD_LOGIC_VECTOR((22 downto 14 => highBBits_uid290_exp10PolyEval_b(13)) & highBBits_uid290_exp10PolyEval_b);
sumAHighB_uid291_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid291_exp10PolyEval_a) + SIGNED(sumAHighB_uid291_exp10PolyEval_b));
sumAHighB_uid291_exp10PolyEval_q <= sumAHighB_uid291_exp10PolyEval_o(22 downto 0);
--lowRangeB_uid289_exp10PolyEval(BITSELECT,288)@17
lowRangeB_uid289_exp10PolyEval_in <= prodXYTruncFR_uid349_pT1_uid288_exp10PolyEval_b(0 downto 0);
lowRangeB_uid289_exp10PolyEval_b <= lowRangeB_uid289_exp10PolyEval_in(0 downto 0);
--s1_uid289_uid292_exp10PolyEval(BITJOIN,291)@17
s1_uid289_uid292_exp10PolyEval_q <= sumAHighB_uid291_exp10PolyEval_q & lowRangeB_uid289_exp10PolyEval_b;
--reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1(REG,397)@17
reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1_q <= s1_uid289_uid292_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor(LOGICAL,1016)
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_b <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_a or ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_b);
--ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena(REG,1017)
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd(LOGICAL,1018)
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_inputreg(DELAY,1008)
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid73_fpExpEM1Test_b, xout => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem(DUALMEM,1009)
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_aa <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ab <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_iq(18 downto 0);
--reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0(REG,396)@17
reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_q <= "0000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_q <= ld_yPPolyEval_uid73_fpExpEM1Test_b_to_reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid351_pT2_uid294_exp10PolyEval(MULT,350)@18
prodXY_uid351_pT2_uid294_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid351_pT2_uid294_exp10PolyEval_a),20)) * SIGNED(prodXY_uid351_pT2_uid294_exp10PolyEval_b);
prodXY_uid351_pT2_uid294_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid351_pT2_uid294_exp10PolyEval_a <= (others => '0');
prodXY_uid351_pT2_uid294_exp10PolyEval_b <= (others => '0');
prodXY_uid351_pT2_uid294_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid351_pT2_uid294_exp10PolyEval_a <= reg_yPPolyEval_uid73_fpExpEM1Test_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_0_q;
prodXY_uid351_pT2_uid294_exp10PolyEval_b <= reg_s1_uid289_uid292_exp10PolyEval_0_to_prodXY_uid351_pT2_uid294_exp10PolyEval_1_q;
prodXY_uid351_pT2_uid294_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid351_pT2_uid294_exp10PolyEval_pr,43));
END IF;
END IF;
END PROCESS;
prodXY_uid351_pT2_uid294_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid351_pT2_uid294_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid351_pT2_uid294_exp10PolyEval_q <= prodXY_uid351_pT2_uid294_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval(BITSELECT,351)@21
prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_in <= prodXY_uid351_pT2_uid294_exp10PolyEval_q;
prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_b <= prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_in(42 downto 18);
--highBBits_uid296_exp10PolyEval(BITSELECT,295)@21
highBBits_uid296_exp10PolyEval_in <= prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_b;
highBBits_uid296_exp10PolyEval_b <= highBBits_uid296_exp10PolyEval_in(24 downto 2);
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor(LOGICAL,1029)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_b <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_q <= not (ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_a or ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_b);
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena(REG,1030)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd(LOGICAL,1031)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_a and ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_inputreg(DELAY,1019)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid72_fpExpEM1Test_b, xout => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem(DUALMEM,1020)
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_inputreg_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_aa <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdreg_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ab <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_rdmux_q;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0(REG,398)@19
reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_q <= ld_addr_uid72_fpExpEM1Test_b_to_reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid281_exp10TabGen(LOOKUP,280)@20
memoryC0_uid281_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid281_exp10TabGen_q <= "00100000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid72_fpExpEM1Test_0_to_memoryC0_uid281_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid281_exp10TabGen_q <= "00100000000000000000000000100";
WHEN "0000001" => memoryC0_uid281_exp10TabGen_q <= "00100000010000000100000001010";
WHEN "0000010" => memoryC0_uid281_exp10TabGen_q <= "00100000100000010000000101111";
WHEN "0000011" => memoryC0_uid281_exp10TabGen_q <= "00100000110000100100010010101";
WHEN "0000100" => memoryC0_uid281_exp10TabGen_q <= "00100001000001000000101011100";
WHEN "0000101" => memoryC0_uid281_exp10TabGen_q <= "00100001010001100101010100101";
WHEN "0000110" => memoryC0_uid281_exp10TabGen_q <= "00100001100010010010010010010";
WHEN "0000111" => memoryC0_uid281_exp10TabGen_q <= "00100001110011000111101000011";
WHEN "0001000" => memoryC0_uid281_exp10TabGen_q <= "00100010000100000101011011010";
WHEN "0001001" => memoryC0_uid281_exp10TabGen_q <= "00100010010101001011101111001";
WHEN "0001010" => memoryC0_uid281_exp10TabGen_q <= "00100010100110011010101000011";
WHEN "0001011" => memoryC0_uid281_exp10TabGen_q <= "00100010110111110010001011010";
WHEN "0001100" => memoryC0_uid281_exp10TabGen_q <= "00100011001001010010011100000";
WHEN "0001101" => memoryC0_uid281_exp10TabGen_q <= "00100011011010111011011111001";
WHEN "0001110" => memoryC0_uid281_exp10TabGen_q <= "00100011101100101101011001000";
WHEN "0001111" => memoryC0_uid281_exp10TabGen_q <= "00100011111110101000001110000";
WHEN "0010000" => memoryC0_uid281_exp10TabGen_q <= "00100100010000101100000010110";
WHEN "0010001" => memoryC0_uid281_exp10TabGen_q <= "00100100100010111000111011100";
WHEN "0010010" => memoryC0_uid281_exp10TabGen_q <= "00100100110101001110111101001";
WHEN "0010011" => memoryC0_uid281_exp10TabGen_q <= "00100101000111101110001100000";
WHEN "0010100" => memoryC0_uid281_exp10TabGen_q <= "00100101011010010110101100111";
WHEN "0010101" => memoryC0_uid281_exp10TabGen_q <= "00100101101101001000100100010";
WHEN "0010110" => memoryC0_uid281_exp10TabGen_q <= "00100110000000000011110111000";
WHEN "0010111" => memoryC0_uid281_exp10TabGen_q <= "00100110010011001000101001110";
WHEN "0011000" => memoryC0_uid281_exp10TabGen_q <= "00100110100110010111000001010";
WHEN "0011001" => memoryC0_uid281_exp10TabGen_q <= "00100110111001101111000010011";
WHEN "0011010" => memoryC0_uid281_exp10TabGen_q <= "00100111001101010000110001111";
WHEN "0011011" => memoryC0_uid281_exp10TabGen_q <= "00100111100000111100010100110";
WHEN "0011100" => memoryC0_uid281_exp10TabGen_q <= "00100111110100110001101111111";
WHEN "0011101" => memoryC0_uid281_exp10TabGen_q <= "00101000001000110001001000001";
WHEN "0011110" => memoryC0_uid281_exp10TabGen_q <= "00101000011100111010100010101";
WHEN "0011111" => memoryC0_uid281_exp10TabGen_q <= "00101000110001001110000100011";
WHEN "0100000" => memoryC0_uid281_exp10TabGen_q <= "00101001000101101011110010011";
WHEN "0100001" => memoryC0_uid281_exp10TabGen_q <= "00101001011010010011110001111";
WHEN "0100010" => memoryC0_uid281_exp10TabGen_q <= "00101001101111000110000111111";
WHEN "0100011" => memoryC0_uid281_exp10TabGen_q <= "00101010000100000010111001110";
WHEN "0100100" => memoryC0_uid281_exp10TabGen_q <= "00101010011001001010001100100";
WHEN "0100101" => memoryC0_uid281_exp10TabGen_q <= "00101010101110011100000101101";
WHEN "0100110" => memoryC0_uid281_exp10TabGen_q <= "00101011000011111000101010011";
WHEN "0100111" => memoryC0_uid281_exp10TabGen_q <= "00101011011001100000000000001";
WHEN "0101000" => memoryC0_uid281_exp10TabGen_q <= "00101011101111010010001100010";
WHEN "0101001" => memoryC0_uid281_exp10TabGen_q <= "00101100000101001111010100001";
WHEN "0101010" => memoryC0_uid281_exp10TabGen_q <= "00101100011011010111011101011";
WHEN "0101011" => memoryC0_uid281_exp10TabGen_q <= "00101100110001101010101101011";
WHEN "0101100" => memoryC0_uid281_exp10TabGen_q <= "00101101001000001001001001111";
WHEN "0101101" => memoryC0_uid281_exp10TabGen_q <= "00101101011110110010111000100";
WHEN "0101110" => memoryC0_uid281_exp10TabGen_q <= "00101101110101100111111110110";
WHEN "0101111" => memoryC0_uid281_exp10TabGen_q <= "00101110001100101000100010011";
WHEN "0110000" => memoryC0_uid281_exp10TabGen_q <= "00101110100011110100101001001";
WHEN "0110001" => memoryC0_uid281_exp10TabGen_q <= "00101110111011001100011000111";
WHEN "0110010" => memoryC0_uid281_exp10TabGen_q <= "00101111010010101111110111100";
WHEN "0110011" => memoryC0_uid281_exp10TabGen_q <= "00101111101010011111001010110";
WHEN "0110100" => memoryC0_uid281_exp10TabGen_q <= "00110000000010011010011000101";
WHEN "0110101" => memoryC0_uid281_exp10TabGen_q <= "00110000011010100001100111001";
WHEN "0110110" => memoryC0_uid281_exp10TabGen_q <= "00110000110010110100111100010";
WHEN "0110111" => memoryC0_uid281_exp10TabGen_q <= "00110001001011010100011110001";
WHEN "0111000" => memoryC0_uid281_exp10TabGen_q <= "00110001100100000000010010110";
WHEN "0111001" => memoryC0_uid281_exp10TabGen_q <= "00110001111100111000100000100";
WHEN "0111010" => memoryC0_uid281_exp10TabGen_q <= "00110010010101111101001101011";
WHEN "0111011" => memoryC0_uid281_exp10TabGen_q <= "00110010101111001110011111110";
WHEN "0111100" => memoryC0_uid281_exp10TabGen_q <= "00110011001000101100011110000";
WHEN "0111101" => memoryC0_uid281_exp10TabGen_q <= "00110011100010010111001110011";
WHEN "0111110" => memoryC0_uid281_exp10TabGen_q <= "00110011111100001110110111010";
WHEN "0111111" => memoryC0_uid281_exp10TabGen_q <= "00110100010110010011011111011";
WHEN "1000000" => memoryC0_uid281_exp10TabGen_q <= "00110100110000100101001101000";
WHEN "1000001" => memoryC0_uid281_exp10TabGen_q <= "00110101001011000100000110110";
WHEN "1000010" => memoryC0_uid281_exp10TabGen_q <= "00110101100101110000010011010";
WHEN "1000011" => memoryC0_uid281_exp10TabGen_q <= "00110110000000101001111001010";
WHEN "1000100" => memoryC0_uid281_exp10TabGen_q <= "00110110011011110000111111011";
WHEN "1000101" => memoryC0_uid281_exp10TabGen_q <= "00110110110111000101101100100";
WHEN "1000110" => memoryC0_uid281_exp10TabGen_q <= "00110111010010101000000111011";
WHEN "1000111" => memoryC0_uid281_exp10TabGen_q <= "00110111101110011000010110111";
WHEN "1001000" => memoryC0_uid281_exp10TabGen_q <= "00111000001010010110100010001";
WHEN "1001001" => memoryC0_uid281_exp10TabGen_q <= "00111000100110100010101111110";
WHEN "1001010" => memoryC0_uid281_exp10TabGen_q <= "00111001000010111101000111001";
WHEN "1001011" => memoryC0_uid281_exp10TabGen_q <= "00111001011111100101101111010";
WHEN "1001100" => memoryC0_uid281_exp10TabGen_q <= "00111001111100011100101111010";
WHEN "1001101" => memoryC0_uid281_exp10TabGen_q <= "00111010011001100010001110011";
WHEN "1001110" => memoryC0_uid281_exp10TabGen_q <= "00111010110110110110010100000";
WHEN "1001111" => memoryC0_uid281_exp10TabGen_q <= "00111011010100011001000111001";
WHEN "1010000" => memoryC0_uid281_exp10TabGen_q <= "00111011110010001010101111100";
WHEN "1010001" => memoryC0_uid281_exp10TabGen_q <= "00111100010000001011010100011";
WHEN "1010010" => memoryC0_uid281_exp10TabGen_q <= "00111100101110011010111101011";
WHEN "1010011" => memoryC0_uid281_exp10TabGen_q <= "00111101001100111001110001111";
WHEN "1010100" => memoryC0_uid281_exp10TabGen_q <= "00111101101011100111111001101";
WHEN "1010101" => memoryC0_uid281_exp10TabGen_q <= "00111110001010100101011100011";
WHEN "1010110" => memoryC0_uid281_exp10TabGen_q <= "00111110101001110010100001110";
WHEN "1010111" => memoryC0_uid281_exp10TabGen_q <= "00111111001001001111010001100";
WHEN "1011000" => memoryC0_uid281_exp10TabGen_q <= "00111111101000111011110011101";
WHEN "1011001" => memoryC0_uid281_exp10TabGen_q <= "01000000001000111000001111111";
WHEN "1011010" => memoryC0_uid281_exp10TabGen_q <= "01000000101001000100101110100";
WHEN "1011011" => memoryC0_uid281_exp10TabGen_q <= "01000001001001100001010111011";
WHEN "1011100" => memoryC0_uid281_exp10TabGen_q <= "01000001101010001110010010101";
WHEN "1011101" => memoryC0_uid281_exp10TabGen_q <= "01000010001011001011101000011";
WHEN "1011110" => memoryC0_uid281_exp10TabGen_q <= "01000010101100011001100001000";
WHEN "1011111" => memoryC0_uid281_exp10TabGen_q <= "01000011001101111000000100101";
WHEN "1100000" => memoryC0_uid281_exp10TabGen_q <= "01000011101111100111011011111";
WHEN "1100001" => memoryC0_uid281_exp10TabGen_q <= "01000100010001100111101110111";
WHEN "1100010" => memoryC0_uid281_exp10TabGen_q <= "01000100110011111001000110011";
WHEN "1100011" => memoryC0_uid281_exp10TabGen_q <= "01000101010110011011101010111";
WHEN "1100100" => memoryC0_uid281_exp10TabGen_q <= "01000101111001001111100101000";
WHEN "1100101" => memoryC0_uid281_exp10TabGen_q <= "01000110011100010100111101011";
WHEN "1100110" => memoryC0_uid281_exp10TabGen_q <= "01000110111111101011111100111";
WHEN "1100111" => memoryC0_uid281_exp10TabGen_q <= "01000111100011010100101100010";
WHEN "1101000" => memoryC0_uid281_exp10TabGen_q <= "01001000000111001111010100100";
WHEN "1101001" => memoryC0_uid281_exp10TabGen_q <= "01001000101011011011111110100";
WHEN "1101010" => memoryC0_uid281_exp10TabGen_q <= "01001001001111111010110011100";
WHEN "1101011" => memoryC0_uid281_exp10TabGen_q <= "01001001110100101011111100011";
WHEN "1101100" => memoryC0_uid281_exp10TabGen_q <= "01001010011001101111100010100";
WHEN "1101101" => memoryC0_uid281_exp10TabGen_q <= "01001010111111000101101111000";
WHEN "1101110" => memoryC0_uid281_exp10TabGen_q <= "01001011100100101110101011011";
WHEN "1101111" => memoryC0_uid281_exp10TabGen_q <= "01001100001010101010100000111";
WHEN "1110000" => memoryC0_uid281_exp10TabGen_q <= "01001100110000111001011001000";
WHEN "1110001" => memoryC0_uid281_exp10TabGen_q <= "01001101010111011011011101100";
WHEN "1110010" => memoryC0_uid281_exp10TabGen_q <= "01001101111110010000110111110";
WHEN "1110011" => memoryC0_uid281_exp10TabGen_q <= "01001110100101011001110001100";
WHEN "1110100" => memoryC0_uid281_exp10TabGen_q <= "01001111001100110110010100110";
WHEN "1110101" => memoryC0_uid281_exp10TabGen_q <= "01001111110100100110101011001";
WHEN "1110110" => memoryC0_uid281_exp10TabGen_q <= "01010000011100101010111110110";
WHEN "1110111" => memoryC0_uid281_exp10TabGen_q <= "01010001000101000011011001100";
WHEN "1111000" => memoryC0_uid281_exp10TabGen_q <= "01010001101101110000000101100";
WHEN "1111001" => memoryC0_uid281_exp10TabGen_q <= "01010010010110110001001101000";
WHEN "1111010" => memoryC0_uid281_exp10TabGen_q <= "01010011000000000110111010001";
WHEN "1111011" => memoryC0_uid281_exp10TabGen_q <= "01010011101001110001010111011";
WHEN "1111100" => memoryC0_uid281_exp10TabGen_q <= "01010100010011110000101111000";
WHEN "1111101" => memoryC0_uid281_exp10TabGen_q <= "01010100111110000101001011101";
WHEN "1111110" => memoryC0_uid281_exp10TabGen_q <= "01010101101000101110110111110";
WHEN "1111111" => memoryC0_uid281_exp10TabGen_q <= "01010110010011101101111110000";
WHEN OTHERS =>
memoryC0_uid281_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid297_exp10PolyEval(ADD,296)@21
sumAHighB_uid297_exp10PolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid281_exp10TabGen_q(28)) & memoryC0_uid281_exp10TabGen_q);
sumAHighB_uid297_exp10PolyEval_b <= STD_LOGIC_VECTOR((29 downto 23 => highBBits_uid296_exp10PolyEval_b(22)) & highBBits_uid296_exp10PolyEval_b);
sumAHighB_uid297_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid297_exp10PolyEval_a) + SIGNED(sumAHighB_uid297_exp10PolyEval_b));
sumAHighB_uid297_exp10PolyEval_q <= sumAHighB_uid297_exp10PolyEval_o(29 downto 0);
--lowRangeB_uid295_exp10PolyEval(BITSELECT,294)@21
lowRangeB_uid295_exp10PolyEval_in <= prodXYTruncFR_uid352_pT2_uid294_exp10PolyEval_b(1 downto 0);
lowRangeB_uid295_exp10PolyEval_b <= lowRangeB_uid295_exp10PolyEval_in(1 downto 0);
--s2_uid295_uid298_exp10PolyEval(BITJOIN,297)@21
s2_uid295_uid298_exp10PolyEval_q <= sumAHighB_uid297_exp10PolyEval_q & lowRangeB_uid295_exp10PolyEval_b;
--peOR_uid75_fpExpEM1Test(BITSELECT,74)@21
peOR_uid75_fpExpEM1Test_in <= s2_uid295_uid298_exp10PolyEval_q(28 downto 0);
peOR_uid75_fpExpEM1Test_b <= peOR_uid75_fpExpEM1Test_in(28 downto 5);
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_inputreg(DELAY,920)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => peOR_uid75_fpExpEM1Test_b, xout => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem(DUALMEM,921)
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ia <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_inputreg_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_aa <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ab <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_ia
);
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_iq(23 downto 0);
--fracR_uid79_fpExpEM1Test(BITSELECT,78)@25
fracR_uid79_fpExpEM1Test_in <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_mem_q(22 downto 0);
fracR_uid79_fpExpEM1Test_b <= fracR_uid79_fpExpEM1Test_in(22 downto 0);
--oFracEXZ_uid109_fpExpEM1Test(BITJOIN,108)@25
oFracEXZ_uid109_fpExpEM1Test_q <= VCC_q & fracR_uid79_fpExpEM1Test_b & GND_q;
--X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,306)@25
X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= oFracEXZ_uid109_fpExpEM1Test_q;
X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 24);
--rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,308)@25
rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage0Idx3Pad24_uid308_shiftedFracForNegBranch_uid117_fpExpEM1Test_q & X24dto24_uid307_shiftedFracForNegBranch_uid117_fpExpEM1Test_b;
--reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5(REG,414)@25
reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5_q <= rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,303)@25
X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= oFracEXZ_uid109_fpExpEM1Test_q;
X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 16);
--rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,305)@25
rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= z_uid191_fxpInPostAlign_uid53_fpExpEM1Test_q & X24dto16_uid304_shiftedFracForNegBranch_uid117_fpExpEM1Test_b;
--reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4(REG,413)@25
reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4_q <= rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,300)@25
X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= oFracEXZ_uid109_fpExpEM1Test_q;
X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 8);
--rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,302)@25
rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= cstZeroWE_uid11_fpExpEM1Test_q & X24dto8_uid301_shiftedFracForNegBranch_uid117_fpExpEM1Test_b;
--reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3(REG,412)@25
reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3_q <= rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2(REG,411)@25
reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q <= oFracEXZ_uid109_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--cstTabWidth_uid90_fpExpEM1Test(CONSTANT,89)
cstTabWidth_uid90_fpExpEM1Test_q <= "11001";
--peORExpInc_uid76_fpExpEM1Test(BITSELECT,75)@21
peORExpInc_uid76_fpExpEM1Test_in <= s2_uid295_uid298_exp10PolyEval_q(29 downto 0);
peORExpInc_uid76_fpExpEM1Test_b <= peORExpInc_uid76_fpExpEM1Test_in(29 downto 29);
--reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1(REG,399)@21
reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1_q <= peORExpInc_uid76_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor(LOGICAL,917)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_b <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_q <= not (ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_a or ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_b);
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_mem_top(CONSTANT,913)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_mem_top_q <= "01001";
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp(LOGICAL,914)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_a <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_mem_top_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q);
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_q <= "1" when ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_a = ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_b else "0";
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg(REG,915)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena(REG,918)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_nor_q = "1") THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd(LOGICAL,919)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_a <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_sticky_ena_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_b <= en;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_a and ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_b;
--reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0(REG,377)@8
reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q <= ePreRnd_uid54_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_inputreg(DELAY,907)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q, xout => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt(COUNTER,909)
-- every=1, low=0, high=9, step=1, init=1
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i = 8 THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_eq = '1') THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i - 9;
ELSE
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_i,4));
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg(REG,910)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux(MUX,911)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_s <= en;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux: PROCESS (ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_s, ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q, ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_s IS
WHEN "0" => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q;
WHEN "1" => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem(DUALMEM,908)
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ia <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_inputreg_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_aa <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdreg_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ab <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_rdmux_q;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 4,
numwords_a => 10,
width_b => 11,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_ia
);
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_q <= ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_iq(10 downto 0);
--expRPostBiasPreExc0_uid77_fpExpEM1Test(ADD,76)@21
expRPostBiasPreExc0_uid77_fpExpEM1Test_a <= STD_LOGIC_VECTOR((12 downto 11 => ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_q(10)) & ld_reg_ePreRnd_uid54_fpExpEM1Test_0_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_0_q_to_expRPostBiasPreExc0_uid77_fpExpEM1Test_a_replace_mem_q);
expRPostBiasPreExc0_uid77_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBias_uid8_fpExpEM1Test_q);
expRPostBiasPreExc0_uid77_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostBiasPreExc0_uid77_fpExpEM1Test_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRPostBiasPreExc0_uid77_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc0_uid77_fpExpEM1Test_a) + SIGNED(expRPostBiasPreExc0_uid77_fpExpEM1Test_b));
END IF;
END IF;
END PROCESS;
expRPostBiasPreExc0_uid77_fpExpEM1Test_q <= expRPostBiasPreExc0_uid77_fpExpEM1Test_o(11 downto 0);
--expRPostBiasPreExc_uid78_fpExpEM1Test(ADD,77)@22
expRPostBiasPreExc_uid78_fpExpEM1Test_a <= STD_LOGIC_VECTOR((13 downto 12 => expRPostBiasPreExc0_uid77_fpExpEM1Test_q(11)) & expRPostBiasPreExc0_uid77_fpExpEM1Test_q);
expRPostBiasPreExc_uid78_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "000000000000" & reg_peORExpInc_uid76_fpExpEM1Test_0_to_expRPostBiasPreExc_uid78_fpExpEM1Test_1_q);
expRPostBiasPreExc_uid78_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid78_fpExpEM1Test_a) + SIGNED(expRPostBiasPreExc_uid78_fpExpEM1Test_b));
expRPostBiasPreExc_uid78_fpExpEM1Test_q <= expRPostBiasPreExc_uid78_fpExpEM1Test_o(12 downto 0);
--expR_uid87_fpExpEM1Test(BITSELECT,86)@22
expR_uid87_fpExpEM1Test_in <= expRPostBiasPreExc_uid78_fpExpEM1Test_q(7 downto 0);
expR_uid87_fpExpEM1Test_b <= expR_uid87_fpExpEM1Test_in(7 downto 0);
--ld_expR_uid87_fpExpEM1Test_b_to_reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_a(DELAY,863)@22
ld_expR_uid87_fpExpEM1Test_b_to_reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_a : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expR_uid87_fpExpEM1Test_b, xout => ld_expR_uid87_fpExpEM1Test_b_to_reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2(REG,404)@23
reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_q <= ld_expR_uid87_fpExpEM1Test_b_to_reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c(DELAY,499)@0
ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => signX_uid7_fpExpEM1Test_b, xout => ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid18_fpExpEM1Test(CONSTANT,17)
cstAllZWF_uid18_fpExpEM1Test_q <= "00000000000000000000000";
--fracXIsZero_uid25_fpExpEM1Test(LOGICAL,24)@0
fracXIsZero_uid25_fpExpEM1Test_a <= frac_uid24_fpExpEM1Test_b;
fracXIsZero_uid25_fpExpEM1Test_b <= cstAllZWF_uid18_fpExpEM1Test_q;
fracXIsZero_uid25_fpExpEM1Test_q <= "1" when fracXIsZero_uid25_fpExpEM1Test_a = fracXIsZero_uid25_fpExpEM1Test_b else "0";
--InvFracXIsZero_uid27_fpExpEM1Test(LOGICAL,26)@0
InvFracXIsZero_uid27_fpExpEM1Test_a <= fracXIsZero_uid25_fpExpEM1Test_q;
InvFracXIsZero_uid27_fpExpEM1Test_q <= not InvFracXIsZero_uid27_fpExpEM1Test_a;
--ld_InvFracXIsZero_uid27_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_b(DELAY,445)@0
ld_InvFracXIsZero_uid27_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => InvFracXIsZero_uid27_fpExpEM1Test_q, xout => ld_InvFracXIsZero_uid27_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid23_fpExpEM1Test(LOGICAL,22)@0
expXIsMax_uid23_fpExpEM1Test_a <= expX_uid6_fpExpEM1Test_b;
expXIsMax_uid23_fpExpEM1Test_b <= cstAllOWE_uid17_fpExpEM1Test_q;
expXIsMax_uid23_fpExpEM1Test_q <= "1" when expXIsMax_uid23_fpExpEM1Test_a = expXIsMax_uid23_fpExpEM1Test_b else "0";
--ld_expXIsMax_uid23_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_a(DELAY,444)@0
ld_expXIsMax_uid23_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => expXIsMax_uid23_fpExpEM1Test_q, xout => ld_expXIsMax_uid23_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_N_uid28_fpExpEM1Test(LOGICAL,27)@4
exc_N_uid28_fpExpEM1Test_a <= ld_expXIsMax_uid23_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_a_q;
exc_N_uid28_fpExpEM1Test_b <= ld_InvFracXIsZero_uid27_fpExpEM1Test_q_to_exc_N_uid28_fpExpEM1Test_b_q;
exc_N_uid28_fpExpEM1Test_q <= exc_N_uid28_fpExpEM1Test_a and exc_N_uid28_fpExpEM1Test_b;
--InvExc_N_uid29_fpExpEM1Test(LOGICAL,28)@4
InvExc_N_uid29_fpExpEM1Test_a <= exc_N_uid28_fpExpEM1Test_q;
InvExc_N_uid29_fpExpEM1Test_q <= not InvExc_N_uid29_fpExpEM1Test_a;
--exc_I_uid26_fpExpEM1Test(LOGICAL,25)@0
exc_I_uid26_fpExpEM1Test_a <= expXIsMax_uid23_fpExpEM1Test_q;
exc_I_uid26_fpExpEM1Test_b <= fracXIsZero_uid25_fpExpEM1Test_q;
exc_I_uid26_fpExpEM1Test_q <= exc_I_uid26_fpExpEM1Test_a and exc_I_uid26_fpExpEM1Test_b;
--InvExc_I_uid30_fpExpEM1Test(LOGICAL,29)@0
InvExc_I_uid30_fpExpEM1Test_a <= exc_I_uid26_fpExpEM1Test_q;
InvExc_I_uid30_fpExpEM1Test_q <= not InvExc_I_uid30_fpExpEM1Test_a;
--ld_InvExc_I_uid30_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_b(DELAY,450)@0
ld_InvExc_I_uid30_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => InvExc_I_uid30_fpExpEM1Test_q, xout => ld_InvExc_I_uid30_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsZero_uid21_fpExpEM1Test(LOGICAL,20)@0
expXIsZero_uid21_fpExpEM1Test_a <= expX_uid6_fpExpEM1Test_b;
expXIsZero_uid21_fpExpEM1Test_b <= cstZeroWE_uid11_fpExpEM1Test_q;
expXIsZero_uid21_fpExpEM1Test_q <= "1" when expXIsZero_uid21_fpExpEM1Test_a = expXIsZero_uid21_fpExpEM1Test_b else "0";
--InvExpXIsZero_uid31_fpExpEM1Test(LOGICAL,30)@0
InvExpXIsZero_uid31_fpExpEM1Test_a <= expXIsZero_uid21_fpExpEM1Test_q;
InvExpXIsZero_uid31_fpExpEM1Test_q <= not InvExpXIsZero_uid31_fpExpEM1Test_a;
--ld_InvExpXIsZero_uid31_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_a(DELAY,449)@0
ld_InvExpXIsZero_uid31_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => InvExpXIsZero_uid31_fpExpEM1Test_q, xout => ld_InvExpXIsZero_uid31_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_R_uid32_fpExpEM1Test(LOGICAL,31)@4
exc_R_uid32_fpExpEM1Test_a <= ld_InvExpXIsZero_uid31_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_a_q;
exc_R_uid32_fpExpEM1Test_b <= ld_InvExc_I_uid30_fpExpEM1Test_q_to_exc_R_uid32_fpExpEM1Test_b_q;
exc_R_uid32_fpExpEM1Test_c <= InvExc_N_uid29_fpExpEM1Test_q;
exc_R_uid32_fpExpEM1Test_q <= exc_R_uid32_fpExpEM1Test_a and exc_R_uid32_fpExpEM1Test_b and exc_R_uid32_fpExpEM1Test_c;
--expOvfInitial_uid49_fpExpEM1Test(BITSELECT,48)@4
expOvfInitial_uid49_fpExpEM1Test_in <= shiftValuePreSat_uid48_fpExpEM1Test_q;
expOvfInitial_uid49_fpExpEM1Test_b <= expOvfInitial_uid49_fpExpEM1Test_in(8 downto 8);
--expUnderflow_uid83_fpExpEM1Test(LOGICAL,82)@4
expUnderflow_uid83_fpExpEM1Test_a <= expOvfInitial_uid49_fpExpEM1Test_b;
expUnderflow_uid83_fpExpEM1Test_b <= exc_R_uid32_fpExpEM1Test_q;
expUnderflow_uid83_fpExpEM1Test_c <= ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c_q;
expUnderflow_uid83_fpExpEM1Test_q_i <= expUnderflow_uid83_fpExpEM1Test_a and expUnderflow_uid83_fpExpEM1Test_b and expUnderflow_uid83_fpExpEM1Test_c;
expUnderflow_uid83_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => expUnderflow_uid83_fpExpEM1Test_q, xin => expUnderflow_uid83_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_expUnderflow_uid83_fpExpEM1Test_q_to_expUndeflowCondition_uid85_fpExpEM1Test_b(DELAY,503)@5
ld_expUnderflow_uid83_fpExpEM1Test_q_to_expUndeflowCondition_uid85_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => expUnderflow_uid83_fpExpEM1Test_q, xout => ld_expUnderflow_uid83_fpExpEM1Test_q_to_expUndeflowCondition_uid85_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2(REG,403)@4
reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q <= exc_R_uid32_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q_to_regInAndUndeflowExp_uid84_fpExpEM1Test_b(DELAY,501)@5
ld_reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q_to_regInAndUndeflowExp_uid84_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q, xout => ld_reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q_to_regInAndUndeflowExp_uid84_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0(REG,400)@22
reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q <= expRPostBiasPreExc_uid78_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--expUdf_uid80_fpExpEM1Test(COMPARE,79)@23
expUdf_uid80_fpExpEM1Test_cin <= GND_q;
expUdf_uid80_fpExpEM1Test_a <= STD_LOGIC_VECTOR('0' & "0000000000000" & GND_q) & '0';
expUdf_uid80_fpExpEM1Test_b <= STD_LOGIC_VECTOR((14 downto 13 => reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q(12)) & reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q) & expUdf_uid80_fpExpEM1Test_cin(0);
expUdf_uid80_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid80_fpExpEM1Test_a) - SIGNED(expUdf_uid80_fpExpEM1Test_b));
expUdf_uid80_fpExpEM1Test_n(0) <= not expUdf_uid80_fpExpEM1Test_o(15);
--regInAndUndeflowExp_uid84_fpExpEM1Test(LOGICAL,83)@23
regInAndUndeflowExp_uid84_fpExpEM1Test_a <= expUdf_uid80_fpExpEM1Test_n;
regInAndUndeflowExp_uid84_fpExpEM1Test_b <= ld_reg_exc_R_uid32_fpExpEM1Test_0_to_regInAndUndeflowExp_uid84_fpExpEM1Test_2_q_to_regInAndUndeflowExp_uid84_fpExpEM1Test_b_q;
regInAndUndeflowExp_uid84_fpExpEM1Test_q <= regInAndUndeflowExp_uid84_fpExpEM1Test_a and regInAndUndeflowExp_uid84_fpExpEM1Test_b;
--expUndeflowCondition_uid85_fpExpEM1Test(LOGICAL,84)@23
expUndeflowCondition_uid85_fpExpEM1Test_a <= regInAndUndeflowExp_uid84_fpExpEM1Test_q;
expUndeflowCondition_uid85_fpExpEM1Test_b <= ld_expUnderflow_uid83_fpExpEM1Test_q_to_expUndeflowCondition_uid85_fpExpEM1Test_b_q;
expUndeflowCondition_uid85_fpExpEM1Test_q_i <= expUndeflowCondition_uid85_fpExpEM1Test_a or expUndeflowCondition_uid85_fpExpEM1Test_b;
expUndeflowCondition_uid85_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => expUndeflowCondition_uid85_fpExpEM1Test_q, xin => expUndeflowCondition_uid85_fpExpEM1Test_q_i, clk => clk, ena => en(0), aclr => areset);
--expR_uid88_fpExpEM1Test(MUX,87)@24
expR_uid88_fpExpEM1Test_s <= expUndeflowCondition_uid85_fpExpEM1Test_q;
expR_uid88_fpExpEM1Test: PROCESS (expR_uid88_fpExpEM1Test_s, en, reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_q, cstZeroWE_uid11_fpExpEM1Test_q)
BEGIN
CASE expR_uid88_fpExpEM1Test_s IS
WHEN "0" => expR_uid88_fpExpEM1Test_q <= reg_expR_uid87_fpExpEM1Test_0_to_expR_uid88_fpExpEM1Test_2_q;
WHEN "1" => expR_uid88_fpExpEM1Test_q <= cstZeroWE_uid11_fpExpEM1Test_q;
WHEN OTHERS => expR_uid88_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--shiftAddrPreSaturate_uid110_fpExpEM1Test(SUB,109)@24
shiftAddrPreSaturate_uid110_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & cstBias_uid8_fpExpEM1Test_q);
shiftAddrPreSaturate_uid110_fpExpEM1Test_b <= STD_LOGIC_VECTOR("0" & expR_uid88_fpExpEM1Test_q);
shiftAddrPreSaturate_uid110_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftAddrPreSaturate_uid110_fpExpEM1Test_a) - UNSIGNED(shiftAddrPreSaturate_uid110_fpExpEM1Test_b));
shiftAddrPreSaturate_uid110_fpExpEM1Test_q <= shiftAddrPreSaturate_uid110_fpExpEM1Test_o(8 downto 0);
--shiftAddrPreSaturateShort_uid115_fpExpEM1Test(BITSELECT,114)@24
shiftAddrPreSaturateShort_uid115_fpExpEM1Test_in <= shiftAddrPreSaturate_uid110_fpExpEM1Test_q(4 downto 0);
shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b <= shiftAddrPreSaturateShort_uid115_fpExpEM1Test_in(4 downto 0);
--ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c(DELAY,542)@24
ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 5, depth => 1 )
PORT MAP ( xin => shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b, xout => ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0(REG,409)@24
reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0_q <= shiftAddrPreSaturate_uid110_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--negShiftValueSaturate0_uid112_fpExpEM1Test(COMPARE,111)@25
negShiftValueSaturate0_uid112_fpExpEM1Test_cin <= GND_q;
negShiftValueSaturate0_uid112_fpExpEM1Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0_q(8)) & reg_shiftAddrPreSaturate_uid110_fpExpEM1Test_0_to_negShiftValueSaturate0_uid112_fpExpEM1Test_0_q) & '0';
negShiftValueSaturate0_uid112_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "00000" & cstTabWidth_uid90_fpExpEM1Test_q) & negShiftValueSaturate0_uid112_fpExpEM1Test_cin(0);
negShiftValueSaturate0_uid112_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(negShiftValueSaturate0_uid112_fpExpEM1Test_a) - SIGNED(negShiftValueSaturate0_uid112_fpExpEM1Test_b));
negShiftValueSaturate0_uid112_fpExpEM1Test_n(0) <= not negShiftValueSaturate0_uid112_fpExpEM1Test_o(11);
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor(LOGICAL,941)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_b <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_q <= not (ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_a or ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_b);
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena(REG,942)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_nor_q = "1") THEN
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd(LOGICAL,943)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_a <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_sticky_ena_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_b <= en;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_a and ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_b;
--negInf_uid113_fpExpEM1Test(LOGICAL,112)@0
negInf_uid113_fpExpEM1Test_a <= exc_I_uid26_fpExpEM1Test_q;
negInf_uid113_fpExpEM1Test_b <= signX_uid7_fpExpEM1Test_b;
negInf_uid113_fpExpEM1Test_q <= negInf_uid113_fpExpEM1Test_a and negInf_uid113_fpExpEM1Test_b;
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_inputreg(DELAY,931)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negInf_uid113_fpExpEM1Test_q, xout => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem(DUALMEM,932)
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ia <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_inputreg_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_aa <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdreg_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ab <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_rdmux_q;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 23,
width_b => 1,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_ia
);
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_q <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_iq(0 downto 0);
--negShiftValueSaturate_uid114_fpExpEM1Test(LOGICAL,113)@25
negShiftValueSaturate_uid114_fpExpEM1Test_a <= ld_negInf_uid113_fpExpEM1Test_q_to_negShiftValueSaturate_uid114_fpExpEM1Test_a_replace_mem_q;
negShiftValueSaturate_uid114_fpExpEM1Test_b <= negShiftValueSaturate0_uid112_fpExpEM1Test_n;
negShiftValueSaturate_uid114_fpExpEM1Test_q <= negShiftValueSaturate_uid114_fpExpEM1Test_a or negShiftValueSaturate_uid114_fpExpEM1Test_b;
--negShiftValAddr_uid116_fpExpEM1Test(MUX,115)@25
negShiftValAddr_uid116_fpExpEM1Test_s <= negShiftValueSaturate_uid114_fpExpEM1Test_q;
negShiftValAddr_uid116_fpExpEM1Test: PROCESS (negShiftValAddr_uid116_fpExpEM1Test_s, en, ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c_q, cstTabWidth_uid90_fpExpEM1Test_q)
BEGIN
CASE negShiftValAddr_uid116_fpExpEM1Test_s IS
WHEN "0" => negShiftValAddr_uid116_fpExpEM1Test_q <= ld_shiftAddrPreSaturateShort_uid115_fpExpEM1Test_b_to_negShiftValAddr_uid116_fpExpEM1Test_c_q;
WHEN "1" => negShiftValAddr_uid116_fpExpEM1Test_q <= cstTabWidth_uid90_fpExpEM1Test_q;
WHEN OTHERS => negShiftValAddr_uid116_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,309)@25
rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= negShiftValAddr_uid116_fpExpEM1Test_q;
rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1(REG,410)@25
reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test(MUX,310)@26
rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_s <= reg_rightShiftStageSel4Dto3_uid310_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q;
rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test: PROCESS (rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_s, en, reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q, reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3_q, reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4_q, reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5_q)
BEGIN
CASE rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= reg_oFracEXZ_uid109_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= reg_rightShiftStage0Idx1_uid303_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_3_q;
WHEN "10" => rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= reg_rightShiftStage0Idx2_uid306_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_4_q;
WHEN "11" => rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= reg_rightShiftStage0Idx3_uid309_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_5_q;
WHEN OTHERS => rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,317)@26
RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 6);
--ld_RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_a(DELAY,780)@26
ld_RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b, xout => ld_RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,319)@27
rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage1Idx3Pad6_uid319_shiftedFracForNegBranch_uid117_fpExpEM1Test_q & ld_RightShiftStage024dto6_uid318_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q;
--RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,314)@26
RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 4);
--ld_RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_a(DELAY,778)@26
ld_RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b, xout => ld_RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,316)@27
rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= z_uid203_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage024dto4_uid315_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q;
--RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,311)@26
RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(24 downto 2);
--ld_RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_a(DELAY,776)@26
ld_RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b, xout => ld_RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITJOIN,313)@27
rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= z_uid221_fxpInPostAlign_uid53_fpExpEM1Test_q & ld_RightShiftStage024dto2_uid312_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_a_q;
--reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2(REG,416)@26
reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q <= rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,320)@25
rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= negShiftValAddr_uid116_fpExpEM1Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a(DELAY,874)@25
ld_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b, xout => ld_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1(REG,415)@26
reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= ld_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test(MUX,321)@27
rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_s <= reg_rightShiftStageSel2Dto1_uid321_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q;
rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test: PROCESS (rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_s, en, reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q, rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_q, rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_q, rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_q)
BEGIN
CASE rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_s IS
WHEN "00" => rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= reg_rightShiftStage0_uid311_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_2_q;
WHEN "01" => rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage1Idx1_uid314_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
WHEN "10" => rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage1Idx2_uid317_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
WHEN "11" => rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage1Idx3_uid320_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test(BITSELECT,325)@25
rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_in <= negShiftValAddr_uid116_fpExpEM1Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b <= rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a(DELAY,876)@25
ld_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b, xout => ld_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1(REG,417)@26
reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q <= ld_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_b_to_reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test(MUX,326)@27
rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_s <= reg_rightShiftStageSel0Dto0_uid326_shiftedFracForNegBranch_uid117_fpExpEM1Test_0_to_rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_1_q;
rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_s IS
WHEN "0" => rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage1_uid322_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
WHEN "1" => rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= rightShiftStage2Idx1_uid325_shiftedFracForNegBranch_uid117_fpExpEM1Test_q;
WHEN OTHERS => rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_o_uid9_uid118_fpExpEM1Test(BITJOIN,117)@27
pad_o_uid9_uid118_fpExpEM1Test_q <= VCC_q & STD_LOGIC_VECTOR((23 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0(REG,418)@27
reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0_q <= pad_o_uid9_uid118_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--negBranchFracNotNorm_uid118_fpExpEM1Test(SUB,118)@28
negBranchFracNotNorm_uid118_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid9_uid118_fpExpEM1Test_0_to_negBranchFracNotNorm_uid118_fpExpEM1Test_0_q);
negBranchFracNotNorm_uid118_fpExpEM1Test_b <= STD_LOGIC_VECTOR("0" & rightShiftStage2_uid327_shiftedFracForNegBranch_uid117_fpExpEM1Test_q);
negBranchFracNotNorm_uid118_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(negBranchFracNotNorm_uid118_fpExpEM1Test_a) - UNSIGNED(negBranchFracNotNorm_uid118_fpExpEM1Test_b));
negBranchFracNotNorm_uid118_fpExpEM1Test_q <= negBranchFracNotNorm_uid118_fpExpEM1Test_o(25 downto 0);
--expNegBranchIsZero_uid120_fpExpEM1Test(BITSELECT,119)@28
expNegBranchIsZero_uid120_fpExpEM1Test_in <= negBranchFracNotNorm_uid118_fpExpEM1Test_q(24 downto 0);
expNegBranchIsZero_uid120_fpExpEM1Test_b <= expNegBranchIsZero_uid120_fpExpEM1Test_in(24 downto 24);
--negBranchExp_uid124_fpExpEM1Test(MUX,123)@28
negBranchExp_uid124_fpExpEM1Test_s <= expNegBranchIsZero_uid120_fpExpEM1Test_b;
negBranchExp_uid124_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negBranchExp_uid124_fpExpEM1Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE negBranchExp_uid124_fpExpEM1Test_s IS
WHEN "0" => negBranchExp_uid124_fpExpEM1Test_q <= cstBiasM1_uid14_fpExpEM1Test_q;
WHEN "1" => negBranchExp_uid124_fpExpEM1Test_q <= cstBias_uid8_fpExpEM1Test_q;
WHEN OTHERS => negBranchExp_uid124_fpExpEM1Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--tableAddrPosExt_uid89_fpExpEM1Test(SUB,88)@24
tableAddrPosExt_uid89_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & expR_uid88_fpExpEM1Test_q);
tableAddrPosExt_uid89_fpExpEM1Test_b <= STD_LOGIC_VECTOR("0" & cstBias_uid8_fpExpEM1Test_q);
tableAddrPosExt_uid89_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(tableAddrPosExt_uid89_fpExpEM1Test_a) - UNSIGNED(tableAddrPosExt_uid89_fpExpEM1Test_b));
tableAddrPosExt_uid89_fpExpEM1Test_q <= tableAddrPosExt_uid89_fpExpEM1Test_o(8 downto 0);
--tableAddrPos_uid92_fpExpEM1Test(BITSELECT,91)@24
tableAddrPos_uid92_fpExpEM1Test_in <= tableAddrPosExt_uid89_fpExpEM1Test_q(4 downto 0);
tableAddrPos_uid92_fpExpEM1Test_b <= tableAddrPos_uid92_fpExpEM1Test_in(4 downto 0);
--ld_tableAddrPos_uid92_fpExpEM1Test_b_to_addrDecTable_uid93_fpExpEM1Test_c(DELAY,511)@24
ld_tableAddrPos_uid92_fpExpEM1Test_b_to_addrDecTable_uid93_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 5, depth => 1 )
PORT MAP ( xin => tableAddrPos_uid92_fpExpEM1Test_b, xout => ld_tableAddrPos_uid92_fpExpEM1Test_b_to_addrDecTable_uid93_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0(REG,406)@24
reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0_q <= tableAddrPosExt_uid89_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--expSatValue_uid91_fpExpEM1Test(COMPARE,90)@25
expSatValue_uid91_fpExpEM1Test_cin <= GND_q;
expSatValue_uid91_fpExpEM1Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0_q(8)) & reg_tableAddrPosExt_uid89_fpExpEM1Test_0_to_expSatValue_uid91_fpExpEM1Test_0_q) & '0';
expSatValue_uid91_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "00000" & cstTabWidth_uid90_fpExpEM1Test_q) & expSatValue_uid91_fpExpEM1Test_cin(0);
expSatValue_uid91_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(expSatValue_uid91_fpExpEM1Test_a) - SIGNED(expSatValue_uid91_fpExpEM1Test_b));
expSatValue_uid91_fpExpEM1Test_n(0) <= not expSatValue_uid91_fpExpEM1Test_o(11);
--addrDecTable_uid93_fpExpEM1Test(MUX,92)@25
addrDecTable_uid93_fpExpEM1Test_s <= expSatValue_uid91_fpExpEM1Test_n;
addrDecTable_uid93_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addrDecTable_uid93_fpExpEM1Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addrDecTable_uid93_fpExpEM1Test_s IS
WHEN "0" => addrDecTable_uid93_fpExpEM1Test_q <= ld_tableAddrPos_uid92_fpExpEM1Test_b_to_addrDecTable_uid93_fpExpEM1Test_c_q;
WHEN "1" => addrDecTable_uid93_fpExpEM1Test_q <= cstTabWidth_uid90_fpExpEM1Test_q;
WHEN OTHERS => addrDecTable_uid93_fpExpEM1Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--subDecrementMask_uid95_fpExpEM1Test(LOOKUP,94)@26
subDecrementMask_uid95_fpExpEM1Test: PROCESS (addrDecTable_uid93_fpExpEM1Test_q)
BEGIN
-- Begin reserved scope level
CASE (addrDecTable_uid93_fpExpEM1Test_q) IS
WHEN "00000" => subDecrementMask_uid95_fpExpEM1Test_q <= "10000";
WHEN "00001" => subDecrementMask_uid95_fpExpEM1Test_q <= "11000";
WHEN "00010" => subDecrementMask_uid95_fpExpEM1Test_q <= "11100";
WHEN "00011" => subDecrementMask_uid95_fpExpEM1Test_q <= "11110";
WHEN "00100" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "00101" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "00110" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "00111" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01000" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01001" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01010" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01011" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01100" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01101" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01110" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "01111" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10000" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10001" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10010" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10011" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10100" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10101" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10110" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "10111" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "11000" => subDecrementMask_uid95_fpExpEM1Test_q <= "11111";
WHEN "11001" => subDecrementMask_uid95_fpExpEM1Test_q <= "00000";
WHEN OTHERS =>
subDecrementMask_uid95_fpExpEM1Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--subDecrementMask_uid94_fpExpEM1Test(LOOKUP,93)@26
subDecrementMask_uid94_fpExpEM1Test: PROCESS (addrDecTable_uid93_fpExpEM1Test_q)
BEGIN
-- Begin reserved scope level
CASE (addrDecTable_uid93_fpExpEM1Test_q) IS
WHEN "00000" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN "00001" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN "00010" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN "00011" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN "00100" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN "00101" => subDecrementMask_uid94_fpExpEM1Test_q <= "10000000000000000000";
WHEN "00110" => subDecrementMask_uid94_fpExpEM1Test_q <= "11000000000000000000";
WHEN "00111" => subDecrementMask_uid94_fpExpEM1Test_q <= "11100000000000000000";
WHEN "01000" => subDecrementMask_uid94_fpExpEM1Test_q <= "11110000000000000000";
WHEN "01001" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111000000000000000";
WHEN "01010" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111100000000000000";
WHEN "01011" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111110000000000000";
WHEN "01100" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111000000000000";
WHEN "01101" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111100000000000";
WHEN "01110" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111110000000000";
WHEN "01111" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111000000000";
WHEN "10000" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111100000000";
WHEN "10001" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111110000000";
WHEN "10010" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111000000";
WHEN "10011" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111100000";
WHEN "10100" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111110000";
WHEN "10101" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111111000";
WHEN "10110" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111111100";
WHEN "10111" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111111110";
WHEN "11000" => subDecrementMask_uid94_fpExpEM1Test_q <= "11111111111111111111";
WHEN "11001" => subDecrementMask_uid94_fpExpEM1Test_q <= "00000000000000000000";
WHEN OTHERS =>
subDecrementMask_uid94_fpExpEM1Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid96_fpExpEM1Test(BITJOIN,95)@26
os_uid96_fpExpEM1Test_q <= subDecrementMask_uid95_fpExpEM1Test_q & subDecrementMask_uid94_fpExpEM1Test_q;
--highBBits_uid99_fpExpEM1Test(BITSELECT,98)@26
highBBits_uid99_fpExpEM1Test_in <= os_uid96_fpExpEM1Test_q;
highBBits_uid99_fpExpEM1Test_b <= highBBits_uid99_fpExpEM1Test_in(24 downto 1);
--reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1(REG,408)@26
reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1_q <= highBBits_uid99_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--ld_fracR_uid79_fpExpEM1Test_b_to_zOFracRExp_uid97_fpExpEM1Test_a(DELAY,516)@25
ld_fracR_uid79_fpExpEM1Test_b_to_zOFracRExp_uid97_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracR_uid79_fpExpEM1Test_b, xout => ld_fracR_uid79_fpExpEM1Test_b_to_zOFracRExp_uid97_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--zOFracRExp_uid97_fpExpEM1Test(BITJOIN,96)@26
zOFracRExp_uid97_fpExpEM1Test_q <= GND_q & VCC_q & ld_fracR_uid79_fpExpEM1Test_b_to_zOFracRExp_uid97_fpExpEM1Test_a_q;
--reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0(REG,407)@26
reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0_q <= zOFracRExp_uid97_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid100_fpExpEM1Test(ADD,99)@27
sumAHighB_uid100_fpExpEM1Test_a <= STD_LOGIC_VECTOR((25 downto 25 => reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0_q(24)) & reg_zOFracRExp_uid97_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_0_q);
sumAHighB_uid100_fpExpEM1Test_b <= STD_LOGIC_VECTOR((25 downto 24 => reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1_q(23)) & reg_highBBits_uid99_fpExpEM1Test_0_to_sumAHighB_uid100_fpExpEM1Test_1_q);
sumAHighB_uid100_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid100_fpExpEM1Test_a) + SIGNED(sumAHighB_uid100_fpExpEM1Test_b));
sumAHighB_uid100_fpExpEM1Test_q <= sumAHighB_uid100_fpExpEM1Test_o(25 downto 0);
--lowRangeB_uid98_fpExpEM1Test(BITSELECT,97)@26
lowRangeB_uid98_fpExpEM1Test_in <= os_uid96_fpExpEM1Test_q(0 downto 0);
lowRangeB_uid98_fpExpEM1Test_b <= lowRangeB_uid98_fpExpEM1Test_in(0 downto 0);
--ld_lowRangeB_uid98_fpExpEM1Test_b_to_zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_a(DELAY,521)@26
ld_lowRangeB_uid98_fpExpEM1Test_b_to_zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid98_fpExpEM1Test_b, xout => ld_lowRangeB_uid98_fpExpEM1Test_b_to_zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--zoFracRPosPostSub_uid98_uid101_fpExpEM1Test(BITJOIN,100)@27
zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_q <= sumAHighB_uid100_fpExpEM1Test_q & ld_lowRangeB_uid98_fpExpEM1Test_b_to_zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_a_q;
--udfBitSubPos_uid102_fpExpEM1Test(BITSELECT,101)@27
udfBitSubPos_uid102_fpExpEM1Test_in <= zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_q(24 downto 0);
udfBitSubPos_uid102_fpExpEM1Test_b <= udfBitSubPos_uid102_fpExpEM1Test_in(24 downto 24);
--invUdfBitSubPos_uid106_fpExpEM1Test(LOGICAL,105)@27
invUdfBitSubPos_uid106_fpExpEM1Test_a <= udfBitSubPos_uid102_fpExpEM1Test_b;
invUdfBitSubPos_uid106_fpExpEM1Test_q_i <= not invUdfBitSubPos_uid106_fpExpEM1Test_a;
invUdfBitSubPos_uid106_fpExpEM1Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => invUdfBitSubPos_uid106_fpExpEM1Test_q, xin => invUdfBitSubPos_uid106_fpExpEM1Test_q_i, clk => clk, aclr => areset);
--reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0(REG,430)@24
reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q <= expR_uid88_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q_to_expRPosPost_uid107_fpExpEM1Test_a(DELAY,530)@25
ld_reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q_to_expRPosPost_uid107_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q, xout => ld_reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q_to_expRPosPost_uid107_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--expRPosPost_uid107_fpExpEM1Test(SUB,106)@28
expRPosPost_uid107_fpExpEM1Test_a <= STD_LOGIC_VECTOR("0" & ld_reg_expR_uid88_fpExpEM1Test_0_to_expRPosPost_uid107_fpExpEM1Test_0_q_to_expRPosPost_uid107_fpExpEM1Test_a_q);
expRPosPost_uid107_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00000000" & invUdfBitSubPos_uid106_fpExpEM1Test_q);
expRPosPost_uid107_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPosPost_uid107_fpExpEM1Test_a) - UNSIGNED(expRPosPost_uid107_fpExpEM1Test_b));
expRPosPost_uid107_fpExpEM1Test_q <= expRPosPost_uid107_fpExpEM1Test_o(8 downto 0);
--expRPosPostRange_uid108_fpExpEM1Test(BITSELECT,107)@28
expRPosPostRange_uid108_fpExpEM1Test_in <= expRPosPost_uid107_fpExpEM1Test_q(7 downto 0);
expRPosPostRange_uid108_fpExpEM1Test_b <= expRPosPostRange_uid108_fpExpEM1Test_in(7 downto 0);
--reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2(REG,431)@28
reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2_q <= expRPosPostRange_uid108_fpExpEM1Test_b;
END IF;
END IF;
END PROCESS;
--posCloseBranch0_uid148_fpExpEM1Test(COMPARE,147)@0
posCloseBranch0_uid148_fpExpEM1Test_cin <= GND_q;
posCloseBranch0_uid148_fpExpEM1Test_a <= STD_LOGIC_VECTOR("00" & cstBiasM1_uid14_fpExpEM1Test_q) & '0';
posCloseBranch0_uid148_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpExpEM1Test_b) & posCloseBranch0_uid148_fpExpEM1Test_cin(0);
posCloseBranch0_uid148_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(posCloseBranch0_uid148_fpExpEM1Test_a) - UNSIGNED(posCloseBranch0_uid148_fpExpEM1Test_b));
posCloseBranch0_uid148_fpExpEM1Test_n(0) <= not posCloseBranch0_uid148_fpExpEM1Test_o(10);
--ld_posCloseBranch0_uid148_fpExpEM1Test_n_to_posCloseBranch_uid150_fpExpEM1Test_b(DELAY,582)@0
ld_posCloseBranch0_uid148_fpExpEM1Test_n_to_posCloseBranch_uid150_fpExpEM1Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => posCloseBranch0_uid148_fpExpEM1Test_n, xout => ld_posCloseBranch0_uid148_fpExpEM1Test_n_to_posCloseBranch_uid150_fpExpEM1Test_b_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid144_fpExpEM1Test(LOGICAL,143)@4
InvSignX_uid144_fpExpEM1Test_a <= ld_signX_uid7_fpExpEM1Test_b_to_expUnderflow_uid83_fpExpEM1Test_c_q;
InvSignX_uid144_fpExpEM1Test_q <= not InvSignX_uid144_fpExpEM1Test_a;
--posCloseBranch_uid150_fpExpEM1Test(LOGICAL,149)@4
posCloseBranch_uid150_fpExpEM1Test_a <= InvSignX_uid144_fpExpEM1Test_q;
posCloseBranch_uid150_fpExpEM1Test_b <= ld_posCloseBranch0_uid148_fpExpEM1Test_n_to_posCloseBranch_uid150_fpExpEM1Test_b_q;
posCloseBranch_uid150_fpExpEM1Test_q <= posCloseBranch_uid150_fpExpEM1Test_a and posCloseBranch_uid150_fpExpEM1Test_b;
--ld_posCloseBranch_uid150_fpExpEM1Test_q_to_concBranch_uid151_fpExpEM1Test_c(DELAY,585)@4
ld_posCloseBranch_uid150_fpExpEM1Test_q_to_concBranch_uid151_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => posCloseBranch_uid150_fpExpEM1Test_q, xout => ld_posCloseBranch_uid150_fpExpEM1Test_q_to_concBranch_uid151_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--negFarBranch0_uid146_fpExpEM1Test(COMPARE,145)@24
negFarBranch0_uid146_fpExpEM1Test_cin <= GND_q;
negFarBranch0_uid146_fpExpEM1Test_a <= STD_LOGIC_VECTOR("00" & cstBiasM1_uid14_fpExpEM1Test_q) & '0';
negFarBranch0_uid146_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00" & expR_uid88_fpExpEM1Test_q) & negFarBranch0_uid146_fpExpEM1Test_cin(0);
negFarBranch0_uid146_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(negFarBranch0_uid146_fpExpEM1Test_a) - UNSIGNED(negFarBranch0_uid146_fpExpEM1Test_b));
negFarBranch0_uid146_fpExpEM1Test_n(0) <= not negFarBranch0_uid146_fpExpEM1Test_o(10);
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor(LOGICAL,968)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_b <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_q <= not (ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_a or ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_b);
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_mem_top(CONSTANT,964)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_mem_top_q <= "010101";
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp(LOGICAL,965)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_a <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_mem_top_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q);
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_q <= "1" when ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_a = ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_b else "0";
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg(REG,966)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena(REG,969)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_nor_q = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd(LOGICAL,970)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_a <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_sticky_ena_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_b <= en;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_a and ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_b;
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt(COUNTER,960)
-- every=1, low=0, high=21, step=1, init=1
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i = 20 THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_eq = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i - 21;
ELSE
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_i,5));
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg(REG,961)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux(MUX,962)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_s <= en;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux: PROCESS (ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_s, ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q, ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_q)
BEGIN
CASE ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_s IS
WHEN "0" => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q;
WHEN "1" => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem(DUALMEM,959)
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ia <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_inputreg_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_aa <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdreg_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ab <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_rdmux_q;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_ia
);
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_q <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_iq(0 downto 0);
--negFarBranch_uid147_fpExpEM1Test(LOGICAL,146)@24
negFarBranch_uid147_fpExpEM1Test_a <= ld_signX_uid7_fpExpEM1Test_b_to_negFarBranch_uid147_fpExpEM1Test_a_replace_mem_q;
negFarBranch_uid147_fpExpEM1Test_b <= negFarBranch0_uid146_fpExpEM1Test_n;
negFarBranch_uid147_fpExpEM1Test_q <= negFarBranch_uid147_fpExpEM1Test_a and negFarBranch_uid147_fpExpEM1Test_b;
--cstBiasP1_uid15_fpExpEM1Test(CONSTANT,14)
cstBiasP1_uid15_fpExpEM1Test_q <= "10000000";
--posFarBranch0_uid143_fpExpEM1Test(COMPARE,142)@24
posFarBranch0_uid143_fpExpEM1Test_cin <= GND_q;
posFarBranch0_uid143_fpExpEM1Test_a <= STD_LOGIC_VECTOR("00" & expR_uid88_fpExpEM1Test_q) & '0';
posFarBranch0_uid143_fpExpEM1Test_b <= STD_LOGIC_VECTOR("00" & cstBiasP1_uid15_fpExpEM1Test_q) & posFarBranch0_uid143_fpExpEM1Test_cin(0);
posFarBranch0_uid143_fpExpEM1Test_o <= STD_LOGIC_VECTOR(UNSIGNED(posFarBranch0_uid143_fpExpEM1Test_a) - UNSIGNED(posFarBranch0_uid143_fpExpEM1Test_b));
posFarBranch0_uid143_fpExpEM1Test_n(0) <= not posFarBranch0_uid143_fpExpEM1Test_o(10);
--ld_InvSignX_uid144_fpExpEM1Test_q_to_posFarBranch_uid145_fpExpEM1Test_a(DELAY,575)@4
ld_InvSignX_uid144_fpExpEM1Test_q_to_posFarBranch_uid145_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => InvSignX_uid144_fpExpEM1Test_q, xout => ld_InvSignX_uid144_fpExpEM1Test_q_to_posFarBranch_uid145_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posFarBranch_uid145_fpExpEM1Test(LOGICAL,144)@24
posFarBranch_uid145_fpExpEM1Test_a <= ld_InvSignX_uid144_fpExpEM1Test_q_to_posFarBranch_uid145_fpExpEM1Test_a_q;
posFarBranch_uid145_fpExpEM1Test_b <= posFarBranch0_uid143_fpExpEM1Test_n;
posFarBranch_uid145_fpExpEM1Test_q <= posFarBranch_uid145_fpExpEM1Test_a and posFarBranch_uid145_fpExpEM1Test_b;
--concBranch_uid151_fpExpEM1Test(BITJOIN,150)@24
concBranch_uid151_fpExpEM1Test_q <= ld_posCloseBranch_uid150_fpExpEM1Test_q_to_concBranch_uid151_fpExpEM1Test_c_q & negFarBranch_uid147_fpExpEM1Test_q & posFarBranch_uid145_fpExpEM1Test_q;
--ld_concBranch_uid151_fpExpEM1Test_q_to_reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_a(DELAY,864)@24
ld_concBranch_uid151_fpExpEM1Test_q_to_reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_a : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => concBranch_uid151_fpExpEM1Test_q, xout => ld_concBranch_uid151_fpExpEM1Test_q_to_reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0(REG,405)@27
reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_q <= ld_concBranch_uid151_fpExpEM1Test_q_to_reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_a_q;
END IF;
END IF;
END PROCESS;
--branchSelEnc_uid152_fpExpEM1Test(LOOKUP,151)@28
branchSelEnc_uid152_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branchSelEnc_uid152_fpExpEM1Test_q <= "11";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_concBranch_uid151_fpExpEM1Test_0_to_branchSelEnc_uid152_fpExpEM1Test_0_q) IS
WHEN "000" => branchSelEnc_uid152_fpExpEM1Test_q <= "11";
WHEN "001" => branchSelEnc_uid152_fpExpEM1Test_q <= "00";
WHEN "010" => branchSelEnc_uid152_fpExpEM1Test_q <= "01";
WHEN "011" => branchSelEnc_uid152_fpExpEM1Test_q <= "11";
WHEN "100" => branchSelEnc_uid152_fpExpEM1Test_q <= "10";
WHEN "101" => branchSelEnc_uid152_fpExpEM1Test_q <= "00";
WHEN "110" => branchSelEnc_uid152_fpExpEM1Test_q <= "10";
WHEN "111" => branchSelEnc_uid152_fpExpEM1Test_q <= "10";
WHEN OTHERS =>
branchSelEnc_uid152_fpExpEM1Test_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expPostBranchSel_uid153_fpExpEM1Test(MUX,152)@29
expPostBranchSel_uid153_fpExpEM1Test_s <= branchSelEnc_uid152_fpExpEM1Test_q;
expPostBranchSel_uid153_fpExpEM1Test: PROCESS (expPostBranchSel_uid153_fpExpEM1Test_s, en, reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2_q, negBranchExp_uid124_fpExpEM1Test_q, reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_q, ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f_q)
BEGIN
CASE expPostBranchSel_uid153_fpExpEM1Test_s IS
WHEN "00" => expPostBranchSel_uid153_fpExpEM1Test_q <= reg_expRPosPostRange_uid108_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_2_q;
WHEN "01" => expPostBranchSel_uid153_fpExpEM1Test_q <= negBranchExp_uid124_fpExpEM1Test_q;
WHEN "10" => expPostBranchSel_uid153_fpExpEM1Test_q <= reg_expBranchClosePos_uid139_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_4_q;
WHEN "11" => expPostBranchSel_uid153_fpExpEM1Test_q <= ld_reg_expBranchCloseNeg_uid142_fpExpEM1Test_0_to_expPostBranchSel_uid153_fpExpEM1Test_5_q_to_expPostBranchSel_uid153_fpExpEM1Test_f_q;
WHEN OTHERS => expPostBranchSel_uid153_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--cstZeroWE_uid11_fpExpEM1Test(CONSTANT,10)
cstZeroWE_uid11_fpExpEM1Test_q <= "00000000";
--ld_exc_N_uid28_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_c(DELAY,611)@4
ld_exc_N_uid28_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid28_fpExpEM1Test_q, xout => ld_exc_N_uid28_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndPos_uid156_fpExpEM1Test(LOGICAL,155)@4
regXAndExpOverflowAndPos_uid156_fpExpEM1Test_a <= exc_R_uid32_fpExpEM1Test_q;
regXAndExpOverflowAndPos_uid156_fpExpEM1Test_b <= expOvfInitial_uid49_fpExpEM1Test_b;
regXAndExpOverflowAndPos_uid156_fpExpEM1Test_c <= InvSignX_uid144_fpExpEM1Test_q;
regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q <= regXAndExpOverflowAndPos_uid156_fpExpEM1Test_a and regXAndExpOverflowAndPos_uid156_fpExpEM1Test_b and regXAndExpOverflowAndPos_uid156_fpExpEM1Test_c;
--ld_regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_c(DELAY,608)@4
ld_regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q, xout => ld_regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid49_fpExpEM1Test_b_to_InvExpOvfInitial_uid157_fpExpEM1Test_a(DELAY,600)@4
ld_expOvfInitial_uid49_fpExpEM1Test_b_to_InvExpOvfInitial_uid157_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expOvfInitial_uid49_fpExpEM1Test_b, xout => ld_expOvfInitial_uid49_fpExpEM1Test_b_to_InvExpOvfInitial_uid157_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid157_fpExpEM1Test(LOGICAL,156)@23
InvExpOvfInitial_uid157_fpExpEM1Test_a <= ld_expOvfInitial_uid49_fpExpEM1Test_b_to_InvExpOvfInitial_uid157_fpExpEM1Test_a_q;
InvExpOvfInitial_uid157_fpExpEM1Test_q <= not InvExpOvfInitial_uid157_fpExpEM1Test_a;
--expOvf_uid82_fpExpEM1Test(COMPARE,81)@23
expOvf_uid82_fpExpEM1Test_cin <= GND_q;
expOvf_uid82_fpExpEM1Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q(12)) & reg_expRPostBiasPreExc_uid78_fpExpEM1Test_0_to_expOvf_uid82_fpExpEM1Test_0_q) & '0';
expOvf_uid82_fpExpEM1Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstAllOWE_uid17_fpExpEM1Test_q) & expOvf_uid82_fpExpEM1Test_cin(0);
expOvf_uid82_fpExpEM1Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid82_fpExpEM1Test_a) - SIGNED(expOvf_uid82_fpExpEM1Test_b));
expOvf_uid82_fpExpEM1Test_n(0) <= not expOvf_uid82_fpExpEM1Test_o(15);
--ld_exc_R_uid32_fpExpEM1Test_q_to_regInAndOvf_uid158_fpExpEM1Test_a(DELAY,601)@4
ld_exc_R_uid32_fpExpEM1Test_q_to_regInAndOvf_uid158_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_R_uid32_fpExpEM1Test_q, xout => ld_exc_R_uid32_fpExpEM1Test_q_to_regInAndOvf_uid158_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid158_fpExpEM1Test(LOGICAL,157)@23
regInAndOvf_uid158_fpExpEM1Test_a <= ld_exc_R_uid32_fpExpEM1Test_q_to_regInAndOvf_uid158_fpExpEM1Test_a_q;
regInAndOvf_uid158_fpExpEM1Test_b <= expOvf_uid82_fpExpEM1Test_n;
regInAndOvf_uid158_fpExpEM1Test_c <= InvExpOvfInitial_uid157_fpExpEM1Test_q;
regInAndOvf_uid158_fpExpEM1Test_q <= regInAndOvf_uid158_fpExpEM1Test_a and regInAndOvf_uid158_fpExpEM1Test_b and regInAndOvf_uid158_fpExpEM1Test_c;
--ld_exc_I_uid26_fpExpEM1Test_q_to_posInf_uid160_fpExpEM1Test_a(DELAY,604)@0
ld_exc_I_uid26_fpExpEM1Test_q_to_posInf_uid160_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_I_uid26_fpExpEM1Test_q, xout => ld_exc_I_uid26_fpExpEM1Test_q_to_posInf_uid160_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid160_fpExpEM1Test(LOGICAL,159)@4
posInf_uid160_fpExpEM1Test_a <= ld_exc_I_uid26_fpExpEM1Test_q_to_posInf_uid160_fpExpEM1Test_a_q;
posInf_uid160_fpExpEM1Test_b <= InvSignX_uid144_fpExpEM1Test_q;
posInf_uid160_fpExpEM1Test_q <= posInf_uid160_fpExpEM1Test_a and posInf_uid160_fpExpEM1Test_b;
--ld_posInf_uid160_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_a(DELAY,606)@4
ld_posInf_uid160_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => posInf_uid160_fpExpEM1Test_q, xout => ld_posInf_uid160_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid161_fpExpEM1Test(LOGICAL,160)@23
excRInf_uid161_fpExpEM1Test_a <= ld_posInf_uid160_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_a_q;
excRInf_uid161_fpExpEM1Test_b <= regInAndOvf_uid158_fpExpEM1Test_q;
excRInf_uid161_fpExpEM1Test_c <= ld_regXAndExpOverflowAndPos_uid156_fpExpEM1Test_q_to_excRInf_uid161_fpExpEM1Test_c_q;
excRInf_uid161_fpExpEM1Test_q <= excRInf_uid161_fpExpEM1Test_a or excRInf_uid161_fpExpEM1Test_b or excRInf_uid161_fpExpEM1Test_c;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor(LOGICAL,992)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_b <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_q <= not (ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_a or ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_b);
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_mem_top(CONSTANT,988)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_mem_top_q <= "010100";
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp(LOGICAL,989)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_a <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_mem_top_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q);
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_q <= "1" when ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_a = ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_b else "0";
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg(REG,990)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena(REG,993)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_nor_q = "1") THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd(LOGICAL,994)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_a <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_sticky_ena_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_b <= en;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_a and ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_b;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_inputreg(DELAY,982)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid21_fpExpEM1Test_q, xout => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt(COUNTER,984)
-- every=1, low=0, high=20, step=1, init=1
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i = 19 THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_eq = '1') THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i - 20;
ELSE
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_i,5));
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg(REG,985)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux(MUX,986)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_s <= en;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux: PROCESS (ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_s, ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q, ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_q)
BEGIN
CASE ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_s IS
WHEN "0" => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q;
WHEN "1" => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem(DUALMEM,983)
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ia <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_inputreg_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_aa <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdreg_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ab <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_rdmux_q;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_iq,
address_a => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_aa,
data_a => ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_ia
);
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_q <= ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_iq(0 downto 0);
--concExc_uid162_fpExpEM1Test(BITJOIN,161)@23
concExc_uid162_fpExpEM1Test_q <= ld_exc_N_uid28_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_c_q & excRInf_uid161_fpExpEM1Test_q & ld_expXIsZero_uid21_fpExpEM1Test_q_to_concExc_uid162_fpExpEM1Test_a_replace_mem_q;
--reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0(REG,401)@23
reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q <= concExc_uid162_fpExpEM1Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a(DELAY,612)@24
ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a : dspba_delay
GENERIC MAP ( width => 3, depth => 5 )
PORT MAP ( xin => reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q, xout => ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excREnc_uid163_fpExpEM1Test(LOOKUP,162)@29
excREnc_uid163_fpExpEM1Test: PROCESS (ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_concExc_uid162_fpExpEM1Test_0_to_excREnc_uid163_fpExpEM1Test_0_q_to_excREnc_uid163_fpExpEM1Test_a_q) IS
WHEN "000" => excREnc_uid163_fpExpEM1Test_q <= "01";
WHEN "001" => excREnc_uid163_fpExpEM1Test_q <= "00";
WHEN "010" => excREnc_uid163_fpExpEM1Test_q <= "10";
WHEN "011" => excREnc_uid163_fpExpEM1Test_q <= "00";
WHEN "100" => excREnc_uid163_fpExpEM1Test_q <= "11";
WHEN "101" => excREnc_uid163_fpExpEM1Test_q <= "00";
WHEN "110" => excREnc_uid163_fpExpEM1Test_q <= "00";
WHEN "111" => excREnc_uid163_fpExpEM1Test_q <= "00";
WHEN OTHERS =>
excREnc_uid163_fpExpEM1Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid171_fpExpEM1Test(MUX,170)@29
expRPostExc_uid171_fpExpEM1Test_s <= excREnc_uid163_fpExpEM1Test_q;
expRPostExc_uid171_fpExpEM1Test: PROCESS (expRPostExc_uid171_fpExpEM1Test_s, en, cstZeroWE_uid11_fpExpEM1Test_q, expPostBranchSel_uid153_fpExpEM1Test_q, cstAllOWE_uid17_fpExpEM1Test_q, cstAllOWE_uid17_fpExpEM1Test_q)
BEGIN
CASE expRPostExc_uid171_fpExpEM1Test_s IS
WHEN "00" => expRPostExc_uid171_fpExpEM1Test_q <= cstZeroWE_uid11_fpExpEM1Test_q;
WHEN "01" => expRPostExc_uid171_fpExpEM1Test_q <= expPostBranchSel_uid153_fpExpEM1Test_q;
WHEN "10" => expRPostExc_uid171_fpExpEM1Test_q <= cstAllOWE_uid17_fpExpEM1Test_q;
WHEN "11" => expRPostExc_uid171_fpExpEM1Test_q <= cstAllOWE_uid17_fpExpEM1Test_q;
WHEN OTHERS => expRPostExc_uid171_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid164_fpExpEM1Test(CONSTANT,163)
oneFracRPostExc2_uid164_fpExpEM1Test_q <= "00000000000000000000001";
--ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor(LOGICAL,979)
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_a <= ld_oFracX_uid34_uid34_fpExpEM1Test_q_to_oFracXZwE_uid56_fpExpEM1Test_b_notEnable_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_b <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_q <= not (ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_a or ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_b);
--ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena(REG,980)
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_nor_q = "1") THEN
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd(LOGICAL,981)
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_a <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_sticky_ena_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_b <= en;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_q <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_a and ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_b;
--fracBranchClosePosHigh_uid135_fpExpEM1Test(BITSELECT,134)@25
fracBranchClosePosHigh_uid135_fpExpEM1Test_in <= prod2_uid132_fpExpEM1Test_q(47 downto 0);
fracBranchClosePosHigh_uid135_fpExpEM1Test_b <= fracBranchClosePosHigh_uid135_fpExpEM1Test_in(47 downto 25);
--fracBranchClosePosLow_uid136_fpExpEM1Test(BITSELECT,135)@25
fracBranchClosePosLow_uid136_fpExpEM1Test_in <= prod2_uid132_fpExpEM1Test_q(46 downto 0);
fracBranchClosePosLow_uid136_fpExpEM1Test_b <= fracBranchClosePosLow_uid136_fpExpEM1Test_in(46 downto 24);
--fracBranchClosePos_uid137_fpExpEM1Test(MUX,136)@25
fracBranchClosePos_uid137_fpExpEM1Test_s <= normBit2_uid133_fpExpEM1Test_b;
fracBranchClosePos_uid137_fpExpEM1Test: PROCESS (fracBranchClosePos_uid137_fpExpEM1Test_s, en, fracBranchClosePosLow_uid136_fpExpEM1Test_b, fracBranchClosePosHigh_uid135_fpExpEM1Test_b)
BEGIN
CASE fracBranchClosePos_uid137_fpExpEM1Test_s IS
WHEN "0" => fracBranchClosePos_uid137_fpExpEM1Test_q <= fracBranchClosePosLow_uid136_fpExpEM1Test_b;
WHEN "1" => fracBranchClosePos_uid137_fpExpEM1Test_q <= fracBranchClosePosHigh_uid135_fpExpEM1Test_b;
WHEN OTHERS => fracBranchClosePos_uid137_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_inputreg(DELAY,971)
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracBranchClosePos_uid137_fpExpEM1Test_q, xout => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem(DUALMEM,972)
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ia <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_inputreg_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_aa <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdreg_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ab <= ld_peOR_uid75_fpExpEM1Test_b_to_fracR_uid79_fpExpEM1Test_a_replace_rdmux_q;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_iq,
address_a => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_aa,
data_a => ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_ia
);
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_reset0 <= areset;
ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_iq(22 downto 0);
--negBranchFracNotNormHigh_uid121_fpExpEM1Test(BITSELECT,120)@28
negBranchFracNotNormHigh_uid121_fpExpEM1Test_in <= negBranchFracNotNorm_uid118_fpExpEM1Test_q(23 downto 0);
negBranchFracNotNormHigh_uid121_fpExpEM1Test_b <= negBranchFracNotNormHigh_uid121_fpExpEM1Test_in(23 downto 1);
--negBranchFracNotNormLow_uid122_fpExpEM1Test(BITSELECT,121)@28
negBranchFracNotNormLow_uid122_fpExpEM1Test_in <= negBranchFracNotNorm_uid118_fpExpEM1Test_q(22 downto 0);
negBranchFracNotNormLow_uid122_fpExpEM1Test_b <= negBranchFracNotNormLow_uid122_fpExpEM1Test_in(22 downto 0);
--negBranchFrac_uid123_fpExpEM1Test(MUX,122)@28
negBranchFrac_uid123_fpExpEM1Test_s <= expNegBranchIsZero_uid120_fpExpEM1Test_b;
negBranchFrac_uid123_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negBranchFrac_uid123_fpExpEM1Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE negBranchFrac_uid123_fpExpEM1Test_s IS
WHEN "0" => negBranchFrac_uid123_fpExpEM1Test_q <= negBranchFracNotNormLow_uid122_fpExpEM1Test_b;
WHEN "1" => negBranchFrac_uid123_fpExpEM1Test_q <= negBranchFracNotNormHigh_uid121_fpExpEM1Test_b;
WHEN OTHERS => negBranchFrac_uid123_fpExpEM1Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--udfBitSubPosHigh_uid103_fpExpEM1Test(BITSELECT,102)@27
udfBitSubPosHigh_uid103_fpExpEM1Test_in <= zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_q(23 downto 0);
udfBitSubPosHigh_uid103_fpExpEM1Test_b <= udfBitSubPosHigh_uid103_fpExpEM1Test_in(23 downto 1);
--udfBitSubPosLow_uid104_fpExpEM1Test(BITSELECT,103)@27
udfBitSubPosLow_uid104_fpExpEM1Test_in <= zoFracRPosPostSub_uid98_uid101_fpExpEM1Test_q(22 downto 0);
udfBitSubPosLow_uid104_fpExpEM1Test_b <= udfBitSubPosLow_uid104_fpExpEM1Test_in(22 downto 0);
--normFracRPosPost_uid105_fpExpEM1Test(MUX,104)@27
normFracRPosPost_uid105_fpExpEM1Test_s <= udfBitSubPos_uid102_fpExpEM1Test_b;
normFracRPosPost_uid105_fpExpEM1Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
normFracRPosPost_uid105_fpExpEM1Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE normFracRPosPost_uid105_fpExpEM1Test_s IS
WHEN "0" => normFracRPosPost_uid105_fpExpEM1Test_q <= udfBitSubPosLow_uid104_fpExpEM1Test_b;
WHEN "1" => normFracRPosPost_uid105_fpExpEM1Test_q <= udfBitSubPosHigh_uid103_fpExpEM1Test_b;
WHEN OTHERS => normFracRPosPost_uid105_fpExpEM1Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c(DELAY,593)@28
ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => normFracRPosPost_uid105_fpExpEM1Test_q, xout => ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c_q, ena => en(0), clk => clk, aclr => areset );
--fracPostBranchSel_uid154_fpExpEM1Test(MUX,153)@29
fracPostBranchSel_uid154_fpExpEM1Test_s <= branchSelEnc_uid152_fpExpEM1Test_q;
fracPostBranchSel_uid154_fpExpEM1Test: PROCESS (fracPostBranchSel_uid154_fpExpEM1Test_s, en, ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c_q, negBranchFrac_uid123_fpExpEM1Test_q, ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q, ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q)
BEGIN
CASE fracPostBranchSel_uid154_fpExpEM1Test_s IS
WHEN "00" => fracPostBranchSel_uid154_fpExpEM1Test_q <= ld_normFracRPosPost_uid105_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_c_q;
WHEN "01" => fracPostBranchSel_uid154_fpExpEM1Test_q <= negBranchFrac_uid123_fpExpEM1Test_q;
WHEN "10" => fracPostBranchSel_uid154_fpExpEM1Test_q <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q;
WHEN "11" => fracPostBranchSel_uid154_fpExpEM1Test_q <= ld_fracBranchClosePos_uid137_fpExpEM1Test_q_to_fracPostBranchSel_uid154_fpExpEM1Test_e_replace_mem_q;
WHEN OTHERS => fracPostBranchSel_uid154_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid167_fpExpEM1Test(MUX,166)@29
fracRPostExc_uid167_fpExpEM1Test_s <= excREnc_uid163_fpExpEM1Test_q;
fracRPostExc_uid167_fpExpEM1Test: PROCESS (fracRPostExc_uid167_fpExpEM1Test_s, en, cstAllZWF_uid18_fpExpEM1Test_q, fracPostBranchSel_uid154_fpExpEM1Test_q, cstAllZWF_uid18_fpExpEM1Test_q, oneFracRPostExc2_uid164_fpExpEM1Test_q)
BEGIN
CASE fracRPostExc_uid167_fpExpEM1Test_s IS
WHEN "00" => fracRPostExc_uid167_fpExpEM1Test_q <= cstAllZWF_uid18_fpExpEM1Test_q;
WHEN "01" => fracRPostExc_uid167_fpExpEM1Test_q <= fracPostBranchSel_uid154_fpExpEM1Test_q;
WHEN "10" => fracRPostExc_uid167_fpExpEM1Test_q <= cstAllZWF_uid18_fpExpEM1Test_q;
WHEN "11" => fracRPostExc_uid167_fpExpEM1Test_q <= oneFracRPostExc2_uid164_fpExpEM1Test_q;
WHEN OTHERS => fracRPostExc_uid167_fpExpEM1Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExpE_uid172_fpExpEM1Test(BITJOIN,171)@29
RExpE_uid172_fpExpEM1Test_q <= ld_signX_uid7_fpExpEM1Test_b_to_RExpE_uid172_fpExpEM1Test_c_replace_mem_q & expRPostExc_uid171_fpExpEM1Test_q & fracRPostExc_uid167_fpExpEM1Test_q;
--xOut(GPOUT,4)@29
q <= RExpE_uid172_fpExpEM1Test_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/dp_invsqr.vhd
|
10
|
10246
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ***
--*** ***
--*** DP_INVSQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 32 + 2*Speed ***
--*** Speed = 0 : 32 ***
--*** Speed = 1 : 34 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 31 + Speed ***
--*** Speed = 0 : 31 ***
--*** Speed = 1 : 32 ***
--*** ***
--***************************************************
ENTITY dp_invsqr IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_invsqr;
ARCHITECTURE rtl OF dp_invsqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
constant coredepth : positive := 31+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth+1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth+1 DOWNTO 1);
signal correctff : STD_LOGIC_VECTOR (3 DOWNTO 1); -- SPR 383712
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (54 DOWNTO 1);
--signal invroottest : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (coredepth-2 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinityconditionff, nanconditionff, expzeroff : STD_LOGIC;
signal correct_powers_of_two : STD_LOGIC; -- SPR 383712
component dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
correctff <= "000"; -- SPR 383712
ELSIF (rising_edge(sysclk)) THEN
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signin;
FOR k IN 2 TO coredepth+1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1 + correctff(3);
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(coredepth+1)(k) <= (expff(coredepth)(k) AND zeroexpff(coredepth-2)) OR nanexpff(coredepth-2);
END LOOP;
-- SPR 383712
correctff(1) <= correct_powers_of_two;
correctff(2) <= correctff(1);
correctff(3) <= correctff(2);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (invroot(k+1) AND zeromanff(coredepth-2)) OR nanmanff(coredepth-2);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-1 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-2 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
infinityconditionff <= '0';
nanconditionff <= '0';
expzeroff <= '0';
ELSIF (rising_edge(sysclk)) THEN
infinityconditionff <= manzero AND expmax;
nanconditionff <= signff(1) OR expzero OR (expmax AND manzero);
expzeroff <= expzero;
nanmanff(1) <= nanconditionff; -- level 3
nanexpff(1) <= nanconditionff OR infinityconditionff; -- also max exp when infinity
FOR k IN 2 TO coredepth-1 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= NOT(expzeroff) AND NOT(infinityconditionff); -- level 3
zeroexpff(1) <= NOT(expzeroff); -- level 3
FOR k IN 2 TO coredepth-2 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= '1' & mantissain & '0';
-- sub 1023, so 1023 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: dp_invsqr_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN
-- 2. 0 in, invalid operation, NAN
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '1' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= NOT(expinzero(expwidth)); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= NOT(maninzero(manwidth));
-- 09/03/11 ML
-- if mantissa is 0 and exponent is odd (...123,125,127,129,131...) then dont subtract 1 from offset corrected exponent
-- '1' is subtracted as any value, no matter how small, in the mantissa will reduce the inverse below the mirrored exponent (around 127)
-- if the exponent is odd (with mantissa 0) the value is a power of 2 (...0.25,0.5,1,2,4...) and the mirrored exponent is correct
-- if the exponent is even (with mantissa 0), the inverse square root will have a non zero mantissa and can be handled normally
correct_powers_of_two <= manzero AND expinff(1); -- SPR 383712
--***************
--*** OUTPUTS ***
--***************
signout <= signff(coredepth+1);
exponentout <= expff(coredepth+1)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(coredepth-1);
invalidout <= nanmanff(coredepth-1);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_invsqr.vhd
|
10
|
10246
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ***
--*** ***
--*** DP_INVSQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 32 + 2*Speed ***
--*** Speed = 0 : 32 ***
--*** Speed = 1 : 34 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 31 + Speed ***
--*** Speed = 0 : 31 ***
--*** Speed = 1 : 32 ***
--*** ***
--***************************************************
ENTITY dp_invsqr IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_invsqr;
ARCHITECTURE rtl OF dp_invsqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
constant coredepth : positive := 31+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth+1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth+1 DOWNTO 1);
signal correctff : STD_LOGIC_VECTOR (3 DOWNTO 1); -- SPR 383712
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (54 DOWNTO 1);
--signal invroottest : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (coredepth-2 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinityconditionff, nanconditionff, expzeroff : STD_LOGIC;
signal correct_powers_of_two : STD_LOGIC; -- SPR 383712
component dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
correctff <= "000"; -- SPR 383712
ELSIF (rising_edge(sysclk)) THEN
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signin;
FOR k IN 2 TO coredepth+1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1 + correctff(3);
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(coredepth+1)(k) <= (expff(coredepth)(k) AND zeroexpff(coredepth-2)) OR nanexpff(coredepth-2);
END LOOP;
-- SPR 383712
correctff(1) <= correct_powers_of_two;
correctff(2) <= correctff(1);
correctff(3) <= correctff(2);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (invroot(k+1) AND zeromanff(coredepth-2)) OR nanmanff(coredepth-2);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-1 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-2 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
infinityconditionff <= '0';
nanconditionff <= '0';
expzeroff <= '0';
ELSIF (rising_edge(sysclk)) THEN
infinityconditionff <= manzero AND expmax;
nanconditionff <= signff(1) OR expzero OR (expmax AND manzero);
expzeroff <= expzero;
nanmanff(1) <= nanconditionff; -- level 3
nanexpff(1) <= nanconditionff OR infinityconditionff; -- also max exp when infinity
FOR k IN 2 TO coredepth-1 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= NOT(expzeroff) AND NOT(infinityconditionff); -- level 3
zeroexpff(1) <= NOT(expzeroff); -- level 3
FOR k IN 2 TO coredepth-2 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= '1' & mantissain & '0';
-- sub 1023, so 1023 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: dp_invsqr_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN
-- 2. 0 in, invalid operation, NAN
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '1' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= NOT(expinzero(expwidth)); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= NOT(maninzero(manwidth));
-- 09/03/11 ML
-- if mantissa is 0 and exponent is odd (...123,125,127,129,131...) then dont subtract 1 from offset corrected exponent
-- '1' is subtracted as any value, no matter how small, in the mantissa will reduce the inverse below the mirrored exponent (around 127)
-- if the exponent is odd (with mantissa 0) the value is a power of 2 (...0.25,0.5,1,2,4...) and the mirrored exponent is correct
-- if the exponent is even (with mantissa 0), the inverse square root will have a non zero mantissa and can be handled normally
correct_powers_of_two <= manzero AND expinff(1); -- SPR 383712
--***************
--*** OUTPUTS ***
--***************
signout <= signff(coredepth+1);
exponentout <= expff(coredepth+1)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(coredepth-1);
invalidout <= nanmanff(coredepth-1);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/CosPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_atan2_s5.vhd
|
10
|
652299
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atan2_s5
-- VHDL created on Fri Apr 12 10:15:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atan2_s5 is
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atan2_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal zwEwF_uid40_fpArctan2Test_q : std_logic_vector (30 downto 0);
signal cstNaNWF_uid55_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid56_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstBias_uid57_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid58_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid59_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid60_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstWFP1_uid61_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid62_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal piO2_uid83_fpArctan2Test_q : std_logic_vector (25 downto 0);
signal piO4_uid84_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid93_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid93_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid93_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal arctanIsConst_uid93_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal arctanIsConst_uid93_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid100_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal shiftBias_uid102_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal zS_uid105_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid107_fpArctan2Test_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid117_fpArctan2Test_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid117_fpArctan2Test_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid117_fpArctan2Test_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid117_fpArctan2Test_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid117_fpArctan2Test_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid148_fpArctan2Test_q : std_logic_vector(1 downto 0);
signal cstPi_uid153_fpArctan2Test_q : std_logic_vector (46 downto 0);
signal padConst_uid161_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal xInIsLTEZero_uid171_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal xInIsLTEZero_uid171_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal xInIsLTEZero_uid171_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal xInIsLTEZero_uid171_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excRZero2_uid175_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRZero2_uid175_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRZero2_uid175_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excRZero2_uid175_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal excRZero2_uid175_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXmY_uid232_div_uid49_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal expXmY_uid232_div_uid49_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal expXmY_uid232_div_uid49_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal expXmY_uid232_div_uid49_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal expR_uid233_div_uid49_fpArctan2Test_a : std_logic_vector(10 downto 0);
signal expR_uid233_div_uid49_fpArctan2Test_b : std_logic_vector(10 downto 0);
signal expR_uid233_div_uid49_fpArctan2Test_o : std_logic_vector (10 downto 0);
signal expR_uid233_div_uid49_fpArctan2Test_q : std_logic_vector (9 downto 0);
signal fracYPostZ_uid240_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal fracYPostZ_uid240_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal fracYPostZ_uid240_div_uid49_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal fracYPostZ_uid240_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal z_uid243_div_uid49_fpArctan2Test_q : std_logic_vector (1 downto 0);
signal sRPostExc_uid287_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal sRPostExc_uid287_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal sRPostExc_uid287_div_uid49_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal sRPostExc_uid287_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid297_z_uid95_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid298_z_uid95_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid330_z_uid95_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid330_z_uid95_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRCalc_uid331_z_uid95_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal expRCalc_uid331_z_uid95_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid337_z_uid95_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid337_z_uid95_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal signR_uid339_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal signR_uid339_z_uid95_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal signR_uid339_z_uid95_fpArctan2Test_q_i : std_logic_vector(0 downto 0);
signal signR_uid339_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid349_fxpU_uid110_fpArctan2Test_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx3Pad3_uid360_fxpU_uid110_fpArctan2Test_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid390_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx3Pad6_uid404_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_a : std_logic_vector (25 downto 0);
signal prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_pr : UNSIGNED (49 downto 0);
signal prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_q : std_logic_vector (49 downto 0);
signal prodXY_uid484_pT1_uid373_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid484_pT1_uid373_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid484_pT1_uid373_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid484_pT1_uid373_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid484_pT1_uid373_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid487_pT2_uid379_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid487_pT2_uid379_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid379_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid487_pT2_uid379_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid487_pT2_uid379_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid490_pT1_uid450_invPE_a : std_logic_vector (11 downto 0);
signal prodXY_uid490_pT1_uid450_invPE_b : std_logic_vector (11 downto 0);
signal prodXY_uid490_pT1_uid450_invPE_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid490_pT1_uid450_invPE_pr : SIGNED (24 downto 0);
signal prodXY_uid490_pT1_uid450_invPE_q : std_logic_vector (23 downto 0);
signal prodXY_uid493_pT2_uid456_invPE_a : std_logic_vector (13 downto 0);
signal prodXY_uid493_pT2_uid456_invPE_b : std_logic_vector (22 downto 0);
signal prodXY_uid493_pT2_uid456_invPE_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid493_pT2_uid456_invPE_pr : SIGNED (37 downto 0);
signal prodXY_uid493_pT2_uid456_invPE_q : std_logic_vector (36 downto 0);
signal prodXY_uid496_pT1_uid472_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid496_pT1_uid472_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid496_pT1_uid472_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid496_pT1_uid472_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid496_pT1_uid472_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid499_pT2_uid478_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid499_pT2_uid478_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid499_pT2_uid478_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid499_pT2_uid478_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid499_pT2_uid478_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid366_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid366_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid366_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid366_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid366_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid366_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid368_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid368_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid368_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid368_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid368_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid368_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid370_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid370_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid370_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid370_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid370_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid370_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid443_invTab_lutmem_reset0 : std_logic;
signal memoryC0_uid443_invTab_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid443_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid443_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid443_invTab_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid443_invTab_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid445_invTab_lutmem_reset0 : std_logic;
signal memoryC1_uid445_invTab_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid445_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid445_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid445_invTab_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid445_invTab_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid447_invTab_lutmem_reset0 : std_logic;
signal memoryC2_uid447_invTab_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid447_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid447_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid447_invTab_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid447_invTab_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid465_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid465_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid465_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid465_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid465_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid465_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid467_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid467_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid467_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid467_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid467_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid467_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid469_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid469_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid469_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid469_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid469_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid469_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1_q : std_logic_vector (11 downto 0);
signal reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0_q : std_logic_vector (20 downto 0);
signal reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_q : std_logic_vector (13 downto 0);
signal reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1_q : std_logic_vector (22 downto 0);
signal reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0_q : std_logic_vector (30 downto 0);
signal reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0_q : std_logic_vector (25 downto 0);
signal reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1_q : std_logic_vector (23 downto 0);
signal reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0_q : std_logic_vector (33 downto 0);
signal reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q : std_logic_vector (10 downto 0);
signal reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0_q : std_logic_vector (2 downto 0);
signal reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_q : std_logic_vector (0 downto 0);
signal reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0_q : std_logic_vector (2 downto 0);
signal reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1_q : std_logic_vector (22 downto 0);
signal reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1_q : std_logic_vector (0 downto 0);
signal reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q : std_logic_vector (0 downto 0);
signal reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q : std_logic_vector (31 downto 0);
signal reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1_q : std_logic_vector (7 downto 0);
signal reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0_q : std_logic_vector (31 downto 0);
signal reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0_q : std_logic_vector (31 downto 0);
signal reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2_q : std_logic_vector (31 downto 0);
signal reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3_q : std_logic_vector (31 downto 0);
signal reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5_q : std_logic_vector (22 downto 0);
signal reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5_q : std_logic_vector (7 downto 0);
signal reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0_q : std_logic_vector (7 downto 0);
signal reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2_q : std_logic_vector (47 downto 0);
signal reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q : std_logic_vector (0 downto 0);
signal reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0_q : std_logic_vector (48 downto 0);
signal reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1_q : std_logic_vector (0 downto 0);
signal reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2_q : std_logic_vector (22 downto 0);
signal reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3_q : std_logic_vector (22 downto 0);
signal ld_xyInInf_uid92_fpArctan2Test_q_to_arctanIsConst_uid93_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q_to_u_uid96_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid98_fpArctan2Test_b_to_oFracU_uid99_uid99_fpArctan2Test_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid130_fpArctan2Test_c_to_sValPostSOut_uid132_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid121_fpArctan2Test_q_to_oFracRPath2_uid133_uid133_fpArctan2Test_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid94_fpArctan2Test_n_to_pathSelBits_uid147_fpArctan2Test_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid93_fpArctan2Test_q_to_pathSelBits_uid147_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_oFracRCalc_uid160_uid160_fpArctan2Test_a_q : std_logic_vector (22 downto 0);
signal ld_yInSign_uid38_fpArctan2Test_b_to_InvYInSign_uid177_fpArctan2Test_a_q : std_logic_vector (0 downto 0);
signal ld_InvXInSign_uid174_fpArctan2Test_q_to_excRZero1_uid178_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excRZero2_uid175_fpArctan2Test_q_to_excRZero_uid179_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_fracYZero_uid198_div_uid49_fpArctan2Test_q_to_fracYPostZ_uid240_div_uid49_fpArctan2Test_a_q : std_logic_vector (0 downto 0);
signal ld_fracYPostZ_uid240_div_uid49_fpArctan2Test_q_to_divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_norm_uid247_div_uid49_fpArctan2Test_b_to_rndOp_uid253_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_zeroOverReg_uid263_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excXRYZ_uid268_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_a_q : std_logic_vector (0 downto 0);
signal ld_excXIYZ_uid270_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excXIYR_uid271_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_d_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid275_div_uid49_fpArctan2Test_q_to_concExc_uid276_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d_q : std_logic_vector (22 downto 0);
signal ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d_q : std_logic_vector (7 downto 0);
signal ld_sRPostExc_uid287_div_uid49_fpArctan2Test_q_to_divR_uid288_div_uid49_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid317_z_uid95_fpArctan2Test_q_to_fracRCalc_uid330_z_uid95_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid339_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_b_q : std_logic_vector (33 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_b_q : std_logic_vector (1 downto 0);
signal ld_RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_a_q : std_logic_vector (18 downto 0);
signal ld_RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_a_q : std_logic_vector (45 downto 0);
signal ld_RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_a_q : std_logic_vector (43 downto 0);
signal ld_RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_q : std_logic_vector (11 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_a_q : std_logic_vector (8 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid113_fpArctan2Test_b_to_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_a_q : std_logic_vector (0 downto 0);
signal ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_mem_top_q : std_logic_vector (5 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q : signal is true;
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_eq : std_logic;
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q : signal is true;
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_eq : std_logic;
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_reset0 : std_logic;
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_eq : std_logic;
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q : signal is true;
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_reset0 : std_logic;
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_eq : std_logic;
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q : signal is true;
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_eq : std_logic;
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_reset0 : std_logic;
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_eq : std_logic;
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q : signal is true;
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q : signal is true;
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_reset0 : std_logic;
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_eq : std_logic;
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q : signal is true;
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q : signal is true;
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_reset0 : std_logic;
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q : signal is true;
signal ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_inputreg_q : std_logic_vector (13 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_reset0 : std_logic;
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q : signal is true;
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_eq : std_logic;
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q : signal is true;
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q : signal is true;
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_reset0 : std_logic;
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q : signal is true;
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_reset0 : std_logic;
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q : signal is true;
signal ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_inputreg_q : std_logic_vector (7 downto 0);
signal path2_uid94_fpArctan2Test_a : std_logic_vector(10 downto 0);
signal path2_uid94_fpArctan2Test_b : std_logic_vector(10 downto 0);
signal path2_uid94_fpArctan2Test_o : std_logic_vector (10 downto 0);
signal path2_uid94_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal path2_uid94_fpArctan2Test_n : std_logic_vector (0 downto 0);
signal atanUIsU_uid101_fpArctan2Test_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid101_fpArctan2Test_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid101_fpArctan2Test_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid101_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid101_fpArctan2Test_n : std_logic_vector (0 downto 0);
signal shiftOut_uid130_fpArctan2Test_a : std_logic_vector(10 downto 0);
signal shiftOut_uid130_fpArctan2Test_b : std_logic_vector(10 downto 0);
signal shiftOut_uid130_fpArctan2Test_o : std_logic_vector (10 downto 0);
signal shiftOut_uid130_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid130_fpArctan2Test_c : std_logic_vector (0 downto 0);
signal sOutAlignRes_uid155_fpArctan2Test_a : std_logic_vector(10 downto 0);
signal sOutAlignRes_uid155_fpArctan2Test_b : std_logic_vector(10 downto 0);
signal sOutAlignRes_uid155_fpArctan2Test_o : std_logic_vector (10 downto 0);
signal sOutAlignRes_uid155_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal sOutAlignRes_uid155_fpArctan2Test_c : std_logic_vector (0 downto 0);
signal pad_cstPi_uid153_uid164_fpArctan2Test_q : std_logic_vector (48 downto 0);
signal excSelBits_uid181_fpArctan2Test_q : std_logic_vector (2 downto 0);
signal expUdf_uid259_div_uid49_fpArctan2Test_a : std_logic_vector(13 downto 0);
signal expUdf_uid259_div_uid49_fpArctan2Test_b : std_logic_vector(13 downto 0);
signal expUdf_uid259_div_uid49_fpArctan2Test_o : std_logic_vector (13 downto 0);
signal expUdf_uid259_div_uid49_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid259_div_uid49_fpArctan2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid262_div_uid49_fpArctan2Test_a : std_logic_vector(13 downto 0);
signal expOvf_uid262_div_uid49_fpArctan2Test_b : std_logic_vector(13 downto 0);
signal expOvf_uid262_div_uid49_fpArctan2Test_o : std_logic_vector (13 downto 0);
signal expOvf_uid262_div_uid49_fpArctan2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid262_div_uid49_fpArctan2Test_n : std_logic_vector (0 downto 0);
signal fracXIsZero_uid317_z_uid95_fpArctan2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid317_z_uid95_fpArctan2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid317_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal fracRPath3PostRnd_uid126_fpArctan2Test_a : std_logic_vector(32 downto 0);
signal fracRPath3PostRnd_uid126_fpArctan2Test_b : std_logic_vector(32 downto 0);
signal fracRPath3PostRnd_uid126_fpArctan2Test_o : std_logic_vector (32 downto 0);
signal fracRPath3PostRnd_uid126_fpArctan2Test_q : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid144_fpArctan2Test_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid144_fpArctan2Test_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid144_fpArctan2Test_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid144_fpArctan2Test_q : std_logic_vector (32 downto 0);
signal InvYInSign_uid177_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvYInSign_uid177_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal lOAdded_uid241_div_uid49_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal rndOp_uid253_div_uid49_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal oFracU_uid99_uid99_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid133_uid133_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal oFracRCalc_uid160_uid160_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal exp_uid27_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal exp_uid27_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal frac_uid29_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal frac_uid29_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal yInSign_uid38_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal yInSign_uid38_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal exp_uid11_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal xInSign_uid39_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal xInSign_uid39_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal fracYAddr_uid235_div_uid49_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal fracYAddr_uid235_div_uid49_fpArctan2Test_b : std_logic_vector (8 downto 0);
signal yPE_uid236_div_uid49_fpArctan2Test_in : std_logic_vector (13 downto 0);
signal yPE_uid236_div_uid49_fpArctan2Test_b : std_logic_vector (13 downto 0);
signal expXIsMax_uid12_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpArctan2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpArctan2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid28_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid28_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid28_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid30_fpArctan2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid30_fpArctan2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid30_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid31_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid31_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid31_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid68_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid68_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid68_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid70_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid70_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid70_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid72_fpArctan2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid72_fpArctan2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid72_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid73_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid73_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid73_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid81_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid81_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid81_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal inIsOne_uid82_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal inIsOne_uid82_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal inIsOne_uid82_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal constOut_uid91_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal constOut_uid91_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal xyInInf_uid92_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal xyInInf_uid92_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal xyInInf_uid92_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal shiftValue_uid103_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal shiftValue_uid103_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal shiftValue_uid103_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal shiftValue_uid103_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid129_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal shiftValPath2PreSub_uid129_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal shiftValPath2PreSub_uid129_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid129_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal path2Diff_uid136_fpArctan2Test_a : std_logic_vector(26 downto 0);
signal path2Diff_uid136_fpArctan2Test_b : std_logic_vector(26 downto 0);
signal path2Diff_uid136_fpArctan2Test_o : std_logic_vector (26 downto 0);
signal path2Diff_uid136_fpArctan2Test_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid150_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid150_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRCalc_uid152_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal expRCalc_uid152_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal sValAlignRes_uid154_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal sValAlignRes_uid154_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal sValAlignRes_uid154_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal sValAlignRes_uid154_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal yInZOrsOutAlignRes_uid156_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal yInZOrsOutAlignRes_uid156_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal yInZOrsOutAlignRes_uid156_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal subRes_uid164_fpArctan2Test_a : std_logic_vector(49 downto 0);
signal subRes_uid164_fpArctan2Test_b : std_logic_vector(49 downto 0);
signal subRes_uid164_fpArctan2Test_o : std_logic_vector (49 downto 0);
signal subRes_uid164_fpArctan2Test_q : std_logic_vector (49 downto 0);
signal fracRSub_uid169_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal fracRSub_uid169_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRSub_uid170_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal expRSub_uid170_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal fracRFinal_uid172_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal fracRFinal_uid172_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRFinal_uid173_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal expRFinal_uid173_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal excRZero1_uid178_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRZero1_uid178_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRZero1_uid178_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excRZero1_uid178_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid179_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid179_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid179_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal outMuxSelEnc_uid182_fpArctan2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid183_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid183_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid184_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid184_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal fracYZero_uid198_div_uid49_fpArctan2Test_a : std_logic_vector(22 downto 0);
signal fracYZero_uid198_div_uid49_fpArctan2Test_b : std_logic_vector(22 downto 0);
signal fracYZero_uid198_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid203_div_uid49_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid203_div_uid49_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid203_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid219_div_uid49_fpArctan2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid219_div_uid49_fpArctan2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid219_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal signR_uid231_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal signR_uid231_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal signR_uid231_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid254_div_uid49_fpArctan2Test_a : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid254_div_uid49_fpArctan2Test_b : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid254_div_uid49_fpArctan2Test_o : std_logic_vector (35 downto 0);
signal expFracPostRnd_uid254_div_uid49_fpArctan2Test_q : std_logic_vector (34 downto 0);
signal regOverRegWithUf_uid264_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid264_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid267_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid267_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid267_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid267_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXRYROvf_uid269_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXRYROvf_uid269_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXRYROvf_uid269_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excXRYROvf_uid269_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXIYZ_uid270_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXIYZ_uid270_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXIYZ_uid270_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid272_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid272_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid272_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid272_div_uid49_fpArctan2Test_d : std_logic_vector(0 downto 0);
signal excRInf_uid272_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXZYZ_uid273_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXZYZ_uid273_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXZYZ_uid273_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXIYI_uid274_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXIYI_uid274_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXIYI_uid274_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid277_div_uid49_fpArctan2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid281_div_uid49_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid281_div_uid49_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid285_div_uid49_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid285_div_uid49_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal expRCompExt_uid324_z_uid95_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid324_z_uid95_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid324_z_uid95_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid324_z_uid95_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid336_z_uid95_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid336_z_uid95_fpArctan2Test_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal cstPiO2_uid85_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid85_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid88_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid88_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid108_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal normBit_uid118_fpArctan2Test_in : std_logic_vector (49 downto 0);
signal normBit_uid118_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid119_fpArctan2Test_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid119_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid120_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid120_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal rightPaddedIn_uid162_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal oFracXExt_uid244_div_uid49_fpArctan2Test_q : std_logic_vector (25 downto 0);
signal leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid491_pT1_uid450_invPE_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid491_pT1_uid450_invPE_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid494_pT2_uid456_invPE_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid494_pT2_uid456_invPE_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid497_pT1_uid472_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid497_pT1_uid472_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid500_pT2_uid478_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid500_pT2_uid478_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal pathSelBits_uid147_fpArctan2Test_q : std_logic_vector (2 downto 0);
signal divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q : std_logic_vector (25 downto 0);
signal concExc_uid276_div_uid49_fpArctan2Test_q : std_logic_vector (2 downto 0);
signal divR_uid288_div_uid49_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid321_z_uid95_fpArctan2Test_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid321_z_uid95_fpArctan2Test_b : std_logic_vector (14 downto 0);
signal R_uid340_z_uid95_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid86_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid89_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_a : std_logic_vector(5 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_b : std_logic_vector(5 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid96_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal u_uid96_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid187_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_q : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid127_fpArctan2Test_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid127_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal expRPath3_uid128_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal expRPath3_uid128_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid145_fpArctan2Test_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid145_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal expRPath2_uid146_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal expRPath2_uid146_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (16 downto 0);
signal X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (8 downto 0);
signal X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal join_uid43_fpArctan2Test_q : std_logic_vector (30 downto 0);
signal join_uid47_fpArctan2Test_q : std_logic_vector (30 downto 0);
signal InvXInSign_uid174_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvXInSign_uid174_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal yT1_uid449_invPE_in : std_logic_vector (13 downto 0);
signal yT1_uid449_invPE_b : std_logic_vector (11 downto 0);
signal InvFracXIsZero_uid16_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid228_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid228_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid32_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid32_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid212_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid212_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid314_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid314_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid310_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid310_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid313_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid313_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fracOutCst_uid149_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid149_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal expOutCst_uid151_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal expOutCst_uid151_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal ShiftValue8_uid104_fpArctan2Test_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid104_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid106_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid106_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid131_fpArctan2Test_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid131_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid138_fpArctan2Test_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid138_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid139_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid139_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid140_fpArctan2Test_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid140_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal sValAlignResRange_uid157_fpArctan2Test_in : std_logic_vector (7 downto 0);
signal sValAlignResRange_uid157_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal sValPostSAlignOut_uid158_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal sValPostSAlignOut_uid158_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal subResNormBit_uid166_fpArctan2Test_in : std_logic_vector (48 downto 0);
signal subResNormBit_uid166_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal subResHigh_uid167_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal subResHigh_uid167_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal subResLow_uid168_fpArctan2Test_in : std_logic_vector (46 downto 0);
signal subResLow_uid168_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal InvExpXIsZero_uid213_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid213_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid229_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid229_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid256_div_uid49_fpArctan2Test_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid256_div_uid49_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal excRPreExc_uid257_div_uid49_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal excRPreExc_uid257_div_uid49_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal expRExt_uid258_div_uid49_fpArctan2Test_in : std_logic_vector (34 downto 0);
signal expRExt_uid258_div_uid49_fpArctan2Test_b : std_logic_vector (10 downto 0);
signal expRComp_uid325_z_uid95_fpArctan2Test_in : std_logic_vector (7 downto 0);
signal expRComp_uid325_z_uid95_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal udf_uid326_z_uid95_fpArctan2Test_in : std_logic_vector (9 downto 0);
signal udf_uid326_z_uid95_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid328_z_uid95_fpArctan2Test_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid328_z_uid95_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b : std_logic_vector (33 downto 0);
signal X32dto0_uid344_fxpU_uid110_fpArctan2Test_in : std_logic_vector (32 downto 0);
signal X32dto0_uid344_fxpU_uid110_fpArctan2Test_b : std_logic_vector (32 downto 0);
signal X28dto0_uid347_fxpU_uid110_fpArctan2Test_in : std_logic_vector (28 downto 0);
signal X28dto0_uid347_fxpU_uid110_fpArctan2Test_b : std_logic_vector (28 downto 0);
signal X24dto0_uid350_fxpU_uid110_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal X24dto0_uid350_fxpU_uid110_fpArctan2Test_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid121_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid121_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid122_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid122_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (39 downto 0);
signal X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (31 downto 0);
signal X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid374_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid374_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid375_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid375_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid380_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid380_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid381_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid381_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid451_invPE_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid451_invPE_b : std_logic_vector (0 downto 0);
signal highBBits_uid452_invPE_in : std_logic_vector (12 downto 0);
signal highBBits_uid452_invPE_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid457_invPE_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid457_invPE_b : std_logic_vector (1 downto 0);
signal highBBits_uid458_invPE_in : std_logic_vector (23 downto 0);
signal highBBits_uid458_invPE_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid473_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid473_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid474_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid474_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid479_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid479_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid480_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid480_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid111_fpArctan2Test_in : std_logic_vector (35 downto 0);
signal y_uid111_fpArctan2Test_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (46 downto 0);
signal norm_uid247_div_uid49_fpArctan2Test_in : std_logic_vector (25 downto 0);
signal norm_uid247_div_uid49_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal divValPreNormHigh_uid248_div_uid49_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal divValPreNormHigh_uid248_div_uid49_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid249_div_uid49_fpArctan2Test_in : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid249_div_uid49_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal expX_uid50_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal expX_uid50_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal fracX_uid51_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal fracX_uid51_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal singX_uid52_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal singX_uid52_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal yT1_uid471_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid471_invPolyEval_b : std_logic_vector (11 downto 0);
signal expU_uid97_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal expU_uid97_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal fracU_uid98_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal fracU_uid98_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid388_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid391_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid394_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal yInZero_uid44_fpArctan2Test_a : std_logic_vector(30 downto 0);
signal yInZero_uid44_fpArctan2Test_b : std_logic_vector(30 downto 0);
signal yInZero_uid44_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal xInZero_uid48_fpArctan2Test_a : std_logic_vector(30 downto 0);
signal xInZero_uid48_fpArctan2Test_b : std_logic_vector(30 downto 0);
signal xInZero_uid48_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_N_uid33_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid33_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid33_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_N_uid311_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid311_z_uid95_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid311_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid109_fpArctan2Test_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid109_fpArctan2Test_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid132_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid132_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid141_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid141_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal expRPath2_uid142_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal expRPath2_uid142_fpArctan2Test_q : std_logic_vector (7 downto 0);
signal sValPostSOutRange_uid159_fpArctan2Test_in : std_logic_vector (4 downto 0);
signal sValPostSOutRange_uid159_fpArctan2Test_b : std_logic_vector (4 downto 0);
signal leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid123_fpArctan2Test_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid123_fpArctan2Test_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid123_fpArctan2Test_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid123_fpArctan2Test_q : std_logic_vector (8 downto 0);
signal rightShiftStage0Idx1_uid417_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx2_uid420_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx3_uid423_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal sumAHighB_uid376_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid376_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid376_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid376_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid382_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid382_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid382_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid382_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid453_invPE_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid453_invPE_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid453_invPE_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid453_invPE_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid459_invPE_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid459_invPE_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid459_invPE_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid459_invPE_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid475_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid475_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid475_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid475_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid481_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid481_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid481_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid481_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid113_fpArctan2Test_in : std_logic_vector (34 downto 0);
signal yAddr_uid113_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid114_fpArctan2Test_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid114_fpArctan2Test_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid410_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal rightShiftStage2Idx1_uid439_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal normFracRnd_uid250_div_uid49_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal normFracRnd_uid250_div_uid49_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal oFracX_uid316_uid316_z_uid95_fpArctan2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal excRNaN_uid180_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRNaN_uid180_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRNaN_uid180_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid227_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid227_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excRNaN_uid275_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excRNaN_uid275_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excRNaN_uid275_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal excRNaN_uid275_div_uid49_fpArctan2Test_d : std_logic_vector(0 downto 0);
signal excRNaN_uid275_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid211_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid211_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid312_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid312_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid134_fpArctan2Test_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid134_fpArctan2Test_b : std_logic_vector (4 downto 0);
signal expFracConc_uid143_uid143_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal expRPath3PreRnd_uid124_fpArctan2Test_in : std_logic_vector (7 downto 0);
signal expRPath3PreRnd_uid124_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q : std_logic_vector (47 downto 0);
signal s1_uid374_uid377_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid380_uid383_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid451_uid454_invPE_q : std_logic_vector (22 downto 0);
signal s2_uid457_uid460_invPE_q : std_logic_vector (33 downto 0);
signal s1_uid473_uid476_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid479_uid482_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid372_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid372_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_q : std_logic_vector (24 downto 0);
signal expFracRnd_uid251_div_uid49_fpArctan2Test_q : std_logic_vector (33 downto 0);
signal y_uid318_z_uid95_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal y_uid318_z_uid95_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (18 downto 0);
signal InvExcRNaN_uid185_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid185_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_R_uid230_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid230_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid230_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid230_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid286_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid286_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_R_uid214_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid214_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid214_div_uid49_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid214_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal exc_R_uid315_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid315_z_uid95_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid315_z_uid95_fpArctan2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid315_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_q : std_logic_vector (31 downto 0);
signal RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (45 downto 0);
signal RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (43 downto 0);
signal RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b : std_logic_vector (41 downto 0);
signal fxpAtanXOXRes_uid116_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid116_fpArctan2Test_b : std_logic_vector (26 downto 0);
signal invY_uid238_div_uid49_fpArctan2Test_in : std_logic_vector (30 downto 0);
signal invY_uid238_div_uid49_fpArctan2Test_b : std_logic_vector (25 downto 0);
signal invYO_uid239_div_uid49_fpArctan2Test_in : std_logic_vector (31 downto 0);
signal invYO_uid239_div_uid49_fpArctan2Test_b : std_logic_vector (0 downto 0);
signal fxpInverseRes_uid323_z_uid95_fpArctan2Test_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid323_z_uid95_fpArctan2Test_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_q : std_logic_vector (25 downto 0);
signal yAddr_uid320_z_uid95_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal yAddr_uid320_z_uid95_fpArctan2Test_b : std_logic_vector (7 downto 0);
signal signR_uid186_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal signR_uid186_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal signR_uid186_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal zeroOverReg_uid263_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal zeroOverReg_uid263_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal zeroOverReg_uid263_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXIYR_uid271_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXIYR_uid271_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXIYR_uid271_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal xRegOrZero_uid265_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal xRegOrZero_uid265_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal xRegOrZero_uid265_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excXRYZ_uid268_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal excXRYZ_uid268_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal excXRYZ_uid268_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid332_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid332_z_uid95_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid332_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_b : std_logic_vector (22 downto 0);
signal regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid333_z_uid95_fpArctan2Test_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid333_z_uid95_fpArctan2Test_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid333_z_uid95_fpArctan2Test_q : std_logic_vector(0 downto 0);
signal excSelBits_uid334_z_uid95_fpArctan2Test_q : std_logic_vector (2 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable(LOGICAL,1163)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_a <= en;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q <= not ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_a;
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor(LOGICAL,1305)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_b <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_q <= not (ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_a or ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_b);
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_mem_top(CONSTANT,1301)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_mem_top_q <= "0111000";
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp(LOGICAL,1302)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_a <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_mem_top_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q);
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_q <= "1" when ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_a = ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_b else "0";
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg(REG,1303)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena(REG,1306)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_nor_q = "1") THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd(LOGICAL,1307)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_a <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_sticky_ena_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_b <= en;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_a and ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_b;
--cstAllZWF_uid7_fpArctan2Test(CONSTANT,6)
cstAllZWF_uid7_fpArctan2Test_q <= "00000000000000000000000";
--frac_uid29_fpArctan2Test(BITSELECT,28)@0
frac_uid29_fpArctan2Test_in <= a(22 downto 0);
frac_uid29_fpArctan2Test_b <= frac_uid29_fpArctan2Test_in(22 downto 0);
--fracXIsZero_uid30_fpArctan2Test(LOGICAL,29)@0
fracXIsZero_uid30_fpArctan2Test_a <= frac_uid29_fpArctan2Test_b;
fracXIsZero_uid30_fpArctan2Test_b <= cstAllZWF_uid7_fpArctan2Test_q;
fracXIsZero_uid30_fpArctan2Test_q <= "1" when fracXIsZero_uid30_fpArctan2Test_a = fracXIsZero_uid30_fpArctan2Test_b else "0";
--InvFracXIsZero_uid32_fpArctan2Test(LOGICAL,31)@0
InvFracXIsZero_uid32_fpArctan2Test_a <= fracXIsZero_uid30_fpArctan2Test_q;
InvFracXIsZero_uid32_fpArctan2Test_q <= not InvFracXIsZero_uid32_fpArctan2Test_a;
--cstAllOWE_uid6_fpArctan2Test(CONSTANT,5)
cstAllOWE_uid6_fpArctan2Test_q <= "11111111";
--exp_uid27_fpArctan2Test(BITSELECT,26)@0
exp_uid27_fpArctan2Test_in <= a(30 downto 0);
exp_uid27_fpArctan2Test_b <= exp_uid27_fpArctan2Test_in(30 downto 23);
--expXIsMax_uid28_fpArctan2Test(LOGICAL,27)@0
expXIsMax_uid28_fpArctan2Test_a <= exp_uid27_fpArctan2Test_b;
expXIsMax_uid28_fpArctan2Test_b <= cstAllOWE_uid6_fpArctan2Test_q;
expXIsMax_uid28_fpArctan2Test_q <= "1" when expXIsMax_uid28_fpArctan2Test_a = expXIsMax_uid28_fpArctan2Test_b else "0";
--exc_N_uid33_fpArctan2Test(LOGICAL,32)@0
exc_N_uid33_fpArctan2Test_a <= expXIsMax_uid28_fpArctan2Test_q;
exc_N_uid33_fpArctan2Test_b <= InvFracXIsZero_uid32_fpArctan2Test_q;
exc_N_uid33_fpArctan2Test_q <= exc_N_uid33_fpArctan2Test_a and exc_N_uid33_fpArctan2Test_b;
--frac_uid13_fpArctan2Test(BITSELECT,12)@0
frac_uid13_fpArctan2Test_in <= b(22 downto 0);
frac_uid13_fpArctan2Test_b <= frac_uid13_fpArctan2Test_in(22 downto 0);
--fracXIsZero_uid14_fpArctan2Test(LOGICAL,13)@0
fracXIsZero_uid14_fpArctan2Test_a <= frac_uid13_fpArctan2Test_b;
fracXIsZero_uid14_fpArctan2Test_b <= cstAllZWF_uid7_fpArctan2Test_q;
fracXIsZero_uid14_fpArctan2Test_q <= "1" when fracXIsZero_uid14_fpArctan2Test_a = fracXIsZero_uid14_fpArctan2Test_b else "0";
--InvFracXIsZero_uid16_fpArctan2Test(LOGICAL,15)@0
InvFracXIsZero_uid16_fpArctan2Test_a <= fracXIsZero_uid14_fpArctan2Test_q;
InvFracXIsZero_uid16_fpArctan2Test_q <= not InvFracXIsZero_uid16_fpArctan2Test_a;
--exp_uid11_fpArctan2Test(BITSELECT,10)@0
exp_uid11_fpArctan2Test_in <= b(30 downto 0);
exp_uid11_fpArctan2Test_b <= exp_uid11_fpArctan2Test_in(30 downto 23);
--expXIsMax_uid12_fpArctan2Test(LOGICAL,11)@0
expXIsMax_uid12_fpArctan2Test_a <= exp_uid11_fpArctan2Test_b;
expXIsMax_uid12_fpArctan2Test_b <= cstAllOWE_uid6_fpArctan2Test_q;
expXIsMax_uid12_fpArctan2Test_q <= "1" when expXIsMax_uid12_fpArctan2Test_a = expXIsMax_uid12_fpArctan2Test_b else "0";
--exc_N_uid17_fpArctan2Test(LOGICAL,16)@0
exc_N_uid17_fpArctan2Test_a <= expXIsMax_uid12_fpArctan2Test_q;
exc_N_uid17_fpArctan2Test_b <= InvFracXIsZero_uid16_fpArctan2Test_q;
exc_N_uid17_fpArctan2Test_q <= exc_N_uid17_fpArctan2Test_a and exc_N_uid17_fpArctan2Test_b;
--excRNaN_uid180_fpArctan2Test(LOGICAL,179)@0
excRNaN_uid180_fpArctan2Test_a <= exc_N_uid17_fpArctan2Test_q;
excRNaN_uid180_fpArctan2Test_b <= exc_N_uid33_fpArctan2Test_q;
excRNaN_uid180_fpArctan2Test_q <= excRNaN_uid180_fpArctan2Test_a or excRNaN_uid180_fpArctan2Test_b;
--InvExcRNaN_uid185_fpArctan2Test(LOGICAL,184)@0
InvExcRNaN_uid185_fpArctan2Test_a <= excRNaN_uid180_fpArctan2Test_q;
InvExcRNaN_uid185_fpArctan2Test_q <= not InvExcRNaN_uid185_fpArctan2Test_a;
--yInSign_uid38_fpArctan2Test(BITSELECT,37)@0
yInSign_uid38_fpArctan2Test_in <= a;
yInSign_uid38_fpArctan2Test_b <= yInSign_uid38_fpArctan2Test_in(31 downto 31);
--signR_uid186_fpArctan2Test(LOGICAL,185)@0
signR_uid186_fpArctan2Test_a <= yInSign_uid38_fpArctan2Test_b;
signR_uid186_fpArctan2Test_b <= InvExcRNaN_uid185_fpArctan2Test_q;
signR_uid186_fpArctan2Test_q <= signR_uid186_fpArctan2Test_a and signR_uid186_fpArctan2Test_b;
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_inputreg(DELAY,1295)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid186_fpArctan2Test_q, xout => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt(COUNTER,1297)
-- every=1, low=0, high=56, step=1, init=1
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i = 55 THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i - 56;
ELSE
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_i,6));
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg(REG,1298)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux(MUX,1299)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_s <= en;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux: PROCESS (ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_s, ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q, ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem(DUALMEM,1296)
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ia <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_inputreg_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_aa <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdreg_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ab <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_rdmux_q;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 57,
width_b => 1,
widthad_b => 6,
numwords_b => 57,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_iq,
address_a => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_aa,
data_a => ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_ia
);
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_iq(0 downto 0);
--cstBiasP1_uid60_fpArctan2Test(CONSTANT,59)
cstBiasP1_uid60_fpArctan2Test_q <= "10000000";
--cstBias_uid57_fpArctan2Test(CONSTANT,56)
cstBias_uid57_fpArctan2Test_q <= "01111111";
--GND(CONSTANT,0)
GND_q <= "0";
--RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,436)@57
RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_in <= rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q;
RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_b <= RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 1);
--rightShiftStage2Idx1_uid439_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,438)@57
rightShiftStage2Idx1_uid439_fxpAlignedRes_uid161_fpArctan2Test_q <= GND_q & RightShiftStage147dto1_uid437_fxpAlignedRes_uid161_fpArctan2Test_b;
--rightShiftStage1Idx3Pad6_uid404_fxpOp2Path2_uid135_fpArctan2Test(CONSTANT,403)
rightShiftStage1Idx3Pad6_uid404_fxpOp2Path2_uid135_fpArctan2Test_q <= "000000";
--padConst_uid161_fpArctan2Test(CONSTANT,160)
padConst_uid161_fpArctan2Test_q <= "000000000000000000000000";
--X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,420)@56
X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_in <= rightPaddedIn_uid162_fpArctan2Test_q;
X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_b <= X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 24);
--rightShiftStage0Idx3_uid423_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,422)@56
rightShiftStage0Idx3_uid423_fxpAlignedRes_uid161_fpArctan2Test_q <= padConst_uid161_fpArctan2Test_q & X47dto24_uid421_fxpAlignedRes_uid161_fpArctan2Test_b;
--rightShiftStage0Idx2Pad16_uid390_fxpOp2Path2_uid135_fpArctan2Test(CONSTANT,389)
rightShiftStage0Idx2Pad16_uid390_fxpOp2Path2_uid135_fpArctan2Test_q <= "0000000000000000";
--X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,417)@56
X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_in <= rightPaddedIn_uid162_fpArctan2Test_q;
X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_b <= X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 16);
--rightShiftStage0Idx2_uid420_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,419)@56
rightShiftStage0Idx2_uid420_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage0Idx2Pad16_uid390_fxpOp2Path2_uid135_fpArctan2Test_q & X47dto16_uid418_fxpAlignedRes_uid161_fpArctan2Test_b;
--X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,414)@56
X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_in <= rightPaddedIn_uid162_fpArctan2Test_q;
X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_b <= X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 8);
--rightShiftStage0Idx1_uid417_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,416)@56
rightShiftStage0Idx1_uid417_fxpAlignedRes_uid161_fpArctan2Test_q <= cstAllZWE_uid56_fpArctan2Test_q & X47dto8_uid415_fxpAlignedRes_uid161_fpArctan2Test_b;
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor(LOGICAL,1164)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_b <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_q <= not (ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_a or ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_b);
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_mem_top(CONSTANT,1160)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_mem_top_q <= "011111";
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp(LOGICAL,1161)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_mem_top_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q);
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_q <= "1" when ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_a = ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_b else "0";
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg(REG,1162)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena(REG,1165)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_nor_q = "1") THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd(LOGICAL,1166)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_sticky_ena_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_b <= en;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_a and ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_b;
--exc_I_uid15_fpArctan2Test(LOGICAL,14)@0
exc_I_uid15_fpArctan2Test_a <= expXIsMax_uid12_fpArctan2Test_q;
exc_I_uid15_fpArctan2Test_b <= fracXIsZero_uid14_fpArctan2Test_q;
exc_I_uid15_fpArctan2Test_q <= exc_I_uid15_fpArctan2Test_a and exc_I_uid15_fpArctan2Test_b;
--exc_I_uid31_fpArctan2Test(LOGICAL,30)@0
exc_I_uid31_fpArctan2Test_a <= expXIsMax_uid28_fpArctan2Test_q;
exc_I_uid31_fpArctan2Test_b <= fracXIsZero_uid30_fpArctan2Test_q;
exc_I_uid31_fpArctan2Test_q <= exc_I_uid31_fpArctan2Test_a and exc_I_uid31_fpArctan2Test_b;
--excXIYI_uid274_div_uid49_fpArctan2Test(LOGICAL,273)@0
excXIYI_uid274_div_uid49_fpArctan2Test_a <= exc_I_uid31_fpArctan2Test_q;
excXIYI_uid274_div_uid49_fpArctan2Test_b <= exc_I_uid15_fpArctan2Test_q;
excXIYI_uid274_div_uid49_fpArctan2Test_q <= excXIYI_uid274_div_uid49_fpArctan2Test_a and excXIYI_uid274_div_uid49_fpArctan2Test_b;
--expXIsZero_uid219_div_uid49_fpArctan2Test(LOGICAL,218)@0
expXIsZero_uid219_div_uid49_fpArctan2Test_a <= exp_uid11_fpArctan2Test_b;
expXIsZero_uid219_div_uid49_fpArctan2Test_b <= cstAllZWE_uid56_fpArctan2Test_q;
expXIsZero_uid219_div_uid49_fpArctan2Test_q <= "1" when expXIsZero_uid219_div_uid49_fpArctan2Test_a = expXIsZero_uid219_div_uid49_fpArctan2Test_b else "0";
--expXIsZero_uid203_div_uid49_fpArctan2Test(LOGICAL,202)@0
expXIsZero_uid203_div_uid49_fpArctan2Test_a <= exp_uid27_fpArctan2Test_b;
expXIsZero_uid203_div_uid49_fpArctan2Test_b <= cstAllZWE_uid56_fpArctan2Test_q;
expXIsZero_uid203_div_uid49_fpArctan2Test_q <= "1" when expXIsZero_uid203_div_uid49_fpArctan2Test_a = expXIsZero_uid203_div_uid49_fpArctan2Test_b else "0";
--excXZYZ_uid273_div_uid49_fpArctan2Test(LOGICAL,272)@0
excXZYZ_uid273_div_uid49_fpArctan2Test_a <= expXIsZero_uid203_div_uid49_fpArctan2Test_q;
excXZYZ_uid273_div_uid49_fpArctan2Test_b <= expXIsZero_uid219_div_uid49_fpArctan2Test_q;
excXZYZ_uid273_div_uid49_fpArctan2Test_q <= excXZYZ_uid273_div_uid49_fpArctan2Test_a and excXZYZ_uid273_div_uid49_fpArctan2Test_b;
--excRNaN_uid275_div_uid49_fpArctan2Test(LOGICAL,274)@0
excRNaN_uid275_div_uid49_fpArctan2Test_a <= excXZYZ_uid273_div_uid49_fpArctan2Test_q;
excRNaN_uid275_div_uid49_fpArctan2Test_b <= exc_N_uid33_fpArctan2Test_q;
excRNaN_uid275_div_uid49_fpArctan2Test_c <= exc_N_uid17_fpArctan2Test_q;
excRNaN_uid275_div_uid49_fpArctan2Test_d <= excXIYI_uid274_div_uid49_fpArctan2Test_q;
excRNaN_uid275_div_uid49_fpArctan2Test_q <= excRNaN_uid275_div_uid49_fpArctan2Test_a or excRNaN_uid275_div_uid49_fpArctan2Test_b or excRNaN_uid275_div_uid49_fpArctan2Test_c or excRNaN_uid275_div_uid49_fpArctan2Test_d;
--InvExcRNaN_uid286_div_uid49_fpArctan2Test(LOGICAL,285)@0
InvExcRNaN_uid286_div_uid49_fpArctan2Test_a <= excRNaN_uid275_div_uid49_fpArctan2Test_q;
InvExcRNaN_uid286_div_uid49_fpArctan2Test_q <= not InvExcRNaN_uid286_div_uid49_fpArctan2Test_a;
--xInSign_uid39_fpArctan2Test(BITSELECT,38)@0
xInSign_uid39_fpArctan2Test_in <= b;
xInSign_uid39_fpArctan2Test_b <= xInSign_uid39_fpArctan2Test_in(31 downto 31);
--signR_uid231_div_uid49_fpArctan2Test(LOGICAL,230)@0
signR_uid231_div_uid49_fpArctan2Test_a <= yInSign_uid38_fpArctan2Test_b;
signR_uid231_div_uid49_fpArctan2Test_b <= xInSign_uid39_fpArctan2Test_b;
signR_uid231_div_uid49_fpArctan2Test_q <= signR_uid231_div_uid49_fpArctan2Test_a xor signR_uid231_div_uid49_fpArctan2Test_b;
--sRPostExc_uid287_div_uid49_fpArctan2Test(LOGICAL,286)@0
sRPostExc_uid287_div_uid49_fpArctan2Test_a <= signR_uid231_div_uid49_fpArctan2Test_q;
sRPostExc_uid287_div_uid49_fpArctan2Test_b <= InvExcRNaN_uid286_div_uid49_fpArctan2Test_q;
sRPostExc_uid287_div_uid49_fpArctan2Test_q_i <= sRPostExc_uid287_div_uid49_fpArctan2Test_a and sRPostExc_uid287_div_uid49_fpArctan2Test_b;
sRPostExc_uid287_div_uid49_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => sRPostExc_uid287_div_uid49_fpArctan2Test_q, xin => sRPostExc_uid287_div_uid49_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_sRPostExc_uid287_div_uid49_fpArctan2Test_q_to_divR_uid288_div_uid49_fpArctan2Test_c(DELAY,867)@1
ld_sRPostExc_uid287_div_uid49_fpArctan2Test_q_to_divR_uid288_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => sRPostExc_uid287_div_uid49_fpArctan2Test_q, xout => ld_sRPostExc_uid287_div_uid49_fpArctan2Test_q_to_divR_uid288_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor(LOGICAL,1342)
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_b <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_q <= not (ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_a or ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_b);
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg(REG,1212)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena(REG,1343)
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_nor_q = "1") THEN
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd(LOGICAL,1344)
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_a <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_sticky_ena_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_b <= en;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_q <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_a and ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_b;
--ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor(LOGICAL,1331)
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_b <= ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_q <= not (ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_a or ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_b);
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_mem_top(CONSTANT,1186)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_mem_top_q <= "01000";
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp(LOGICAL,1187)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_a <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_mem_top_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q);
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_q <= "1" when ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_a = ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_b else "0";
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg(REG,1188)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena(REG,1332)
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_nor_q = "1") THEN
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd(LOGICAL,1333)
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_a <= ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_sticky_ena_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_b <= en;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_q <= ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_a and ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_b;
--ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_inputreg(DELAY,1321)
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid29_fpArctan2Test_b, xout => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt(COUNTER,1182)
-- every=1, low=0, high=8, step=1, init=1
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i = 7 THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_eq <= '1';
ELSE
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_eq = '1') THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i - 8;
ELSE
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_i,4));
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg(REG,1183)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux(MUX,1184)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_s <= en;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux: PROCESS (ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_s, ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q, ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_q)
BEGIN
CASE ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_s IS
WHEN "0" => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q;
WHEN "1" => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem(DUALMEM,1322)
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ia <= ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_inputreg_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_aa <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ab <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_iq,
address_a => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_aa,
data_a => ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_ia
);
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_reset0 <= areset;
ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_q <= ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_iq(22 downto 0);
--lOAdded_uid241_div_uid49_fpArctan2Test(BITJOIN,240)@11
lOAdded_uid241_div_uid49_fpArctan2Test_q <= VCC_q & ld_frac_uid29_fpArctan2Test_b_to_lOAdded_uid241_div_uid49_fpArctan2Test_a_replace_mem_q;
--ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_inputreg(DELAY,1334)
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => lOAdded_uid241_div_uid49_fpArctan2Test_q, xout => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt(COUNTER,1208)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg(REG,1209)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux(MUX,1210)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_s, ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q, ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem(DUALMEM,1335)
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ia <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_inputreg_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_aa <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ab <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_iq,
address_a => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_aa,
data_a => ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_ia
);
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_reset0 <= areset;
ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_q <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_iq(23 downto 0);
--z_uid243_div_uid49_fpArctan2Test(CONSTANT,242)
z_uid243_div_uid49_fpArctan2Test_q <= "00";
--oFracXExt_uid244_div_uid49_fpArctan2Test(BITJOIN,243)@15
oFracXExt_uid244_div_uid49_fpArctan2Test_q <= ld_lOAdded_uid241_div_uid49_fpArctan2Test_q_to_oFracXExt_uid244_div_uid49_fpArctan2Test_b_replace_mem_q & z_uid243_div_uid49_fpArctan2Test_q;
--reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1(REG,520)@11
reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1_q <= lOAdded_uid241_div_uid49_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--fracYAddr_uid235_div_uid49_fpArctan2Test(BITSELECT,234)@0
fracYAddr_uid235_div_uid49_fpArctan2Test_in <= b(22 downto 0);
fracYAddr_uid235_div_uid49_fpArctan2Test_b <= fracYAddr_uid235_div_uid49_fpArctan2Test_in(22 downto 14);
--reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0(REG,510)@0
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0_q <= fracYAddr_uid235_div_uid49_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid447_invTab_lutmem(DUALMEM,506)@1
memoryC2_uid447_invTab_lutmem_ia <= (others => '0');
memoryC2_uid447_invTab_lutmem_aa <= (others => '0');
memoryC2_uid447_invTab_lutmem_ab <= reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC2_uid447_invTab_lutmem_0_q;
memoryC2_uid447_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC2_uid447_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid447_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid447_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid447_invTab_lutmem_iq,
address_a => memoryC2_uid447_invTab_lutmem_aa,
data_a => memoryC2_uid447_invTab_lutmem_ia
);
memoryC2_uid447_invTab_lutmem_reset0 <= areset;
memoryC2_uid447_invTab_lutmem_q <= memoryC2_uid447_invTab_lutmem_iq(11 downto 0);
--reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1(REG,512)@3
reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1_q <= memoryC2_uid447_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPE_uid236_div_uid49_fpArctan2Test(BITSELECT,235)@0
yPE_uid236_div_uid49_fpArctan2Test_in <= b(13 downto 0);
yPE_uid236_div_uid49_fpArctan2Test_b <= yPE_uid236_div_uid49_fpArctan2Test_in(13 downto 0);
--yT1_uid449_invPE(BITSELECT,448)@0
yT1_uid449_invPE_in <= yPE_uid236_div_uid49_fpArctan2Test_b;
yT1_uid449_invPE_b <= yT1_uid449_invPE_in(13 downto 2);
--reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0(REG,511)@0
reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q <= yT1_uid449_invPE_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_inputreg(DELAY,1373)
ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q, xout => ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a(DELAY,1043)@1
ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_inputreg_q, xout => ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid490_pT1_uid450_invPE(MULT,489)@4
prodXY_uid490_pT1_uid450_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid490_pT1_uid450_invPE_a),13)) * SIGNED(prodXY_uid490_pT1_uid450_invPE_b);
prodXY_uid490_pT1_uid450_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid490_pT1_uid450_invPE_a <= (others => '0');
prodXY_uid490_pT1_uid450_invPE_b <= (others => '0');
prodXY_uid490_pT1_uid450_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid490_pT1_uid450_invPE_a <= ld_reg_yT1_uid449_invPE_0_to_prodXY_uid490_pT1_uid450_invPE_0_q_to_prodXY_uid490_pT1_uid450_invPE_a_q;
prodXY_uid490_pT1_uid450_invPE_b <= reg_memoryC2_uid447_invTab_lutmem_0_to_prodXY_uid490_pT1_uid450_invPE_1_q;
prodXY_uid490_pT1_uid450_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid490_pT1_uid450_invPE_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid490_pT1_uid450_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid490_pT1_uid450_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid490_pT1_uid450_invPE_q <= prodXY_uid490_pT1_uid450_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid491_pT1_uid450_invPE(BITSELECT,490)@7
prodXYTruncFR_uid491_pT1_uid450_invPE_in <= prodXY_uid490_pT1_uid450_invPE_q;
prodXYTruncFR_uid491_pT1_uid450_invPE_b <= prodXYTruncFR_uid491_pT1_uid450_invPE_in(23 downto 11);
--highBBits_uid452_invPE(BITSELECT,451)@7
highBBits_uid452_invPE_in <= prodXYTruncFR_uid491_pT1_uid450_invPE_b;
highBBits_uid452_invPE_b <= highBBits_uid452_invPE_in(12 downto 1);
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_a(DELAY,1067)@0
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => fracYAddr_uid235_div_uid49_fpArctan2Test_b, xout => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0(REG,513)@3
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_q <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid445_invTab_lutmem(DUALMEM,505)@4
memoryC1_uid445_invTab_lutmem_ia <= (others => '0');
memoryC1_uid445_invTab_lutmem_aa <= (others => '0');
memoryC1_uid445_invTab_lutmem_ab <= reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC1_uid445_invTab_lutmem_0_q;
memoryC1_uid445_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC1_uid445_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid445_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid445_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid445_invTab_lutmem_iq,
address_a => memoryC1_uid445_invTab_lutmem_aa,
data_a => memoryC1_uid445_invTab_lutmem_ia
);
memoryC1_uid445_invTab_lutmem_reset0 <= areset;
memoryC1_uid445_invTab_lutmem_q <= memoryC1_uid445_invTab_lutmem_iq(20 downto 0);
--reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0(REG,514)@6
reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0_q <= memoryC1_uid445_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid453_invPE(ADD,452)@7
sumAHighB_uid453_invPE_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0_q(20)) & reg_memoryC1_uid445_invTab_lutmem_0_to_sumAHighB_uid453_invPE_0_q);
sumAHighB_uid453_invPE_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid452_invPE_b(11)) & highBBits_uid452_invPE_b);
sumAHighB_uid453_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_invPE_a) + SIGNED(sumAHighB_uid453_invPE_b));
sumAHighB_uid453_invPE_q <= sumAHighB_uid453_invPE_o(21 downto 0);
--lowRangeB_uid451_invPE(BITSELECT,450)@7
lowRangeB_uid451_invPE_in <= prodXYTruncFR_uid491_pT1_uid450_invPE_b(0 downto 0);
lowRangeB_uid451_invPE_b <= lowRangeB_uid451_invPE_in(0 downto 0);
--s1_uid451_uid454_invPE(BITJOIN,453)@7
s1_uid451_uid454_invPE_q <= sumAHighB_uid453_invPE_q & lowRangeB_uid451_invPE_b;
--reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1(REG,516)@7
reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1_q <= s1_uid451_uid454_invPE_q;
END IF;
END IF;
END PROCESS;
--ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor(LOGICAL,1408)
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_b <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_q <= not (ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_a or ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_b);
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_mem_top(CONSTANT,1366)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp(LOGICAL,1367)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg(REG,1368)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena(REG,1409)
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_nor_q = "1") THEN
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd(LOGICAL,1410)
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_a <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_sticky_ena_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_b <= en;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_q <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_a and ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_b;
--ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_inputreg(DELAY,1398)
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yPE_uid236_div_uid49_fpArctan2Test_b, xout => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg(REG,1363)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux(MUX,1364)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem(DUALMEM,1399)
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ia <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_inputreg_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 3,
numwords_a => 5,
width_b => 14,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_iq,
address_a => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_aa,
data_a => ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_ia
);
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_reset0 <= areset;
ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_q <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_iq(13 downto 0);
--reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0(REG,515)@7
reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_q <= ld_yPE_uid236_div_uid49_fpArctan2Test_b_to_reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid493_pT2_uid456_invPE(MULT,492)@8
prodXY_uid493_pT2_uid456_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid493_pT2_uid456_invPE_a),15)) * SIGNED(prodXY_uid493_pT2_uid456_invPE_b);
prodXY_uid493_pT2_uid456_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid493_pT2_uid456_invPE_a <= (others => '0');
prodXY_uid493_pT2_uid456_invPE_b <= (others => '0');
prodXY_uid493_pT2_uid456_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid493_pT2_uid456_invPE_a <= reg_yPE_uid236_div_uid49_fpArctan2Test_0_to_prodXY_uid493_pT2_uid456_invPE_0_q;
prodXY_uid493_pT2_uid456_invPE_b <= reg_s1_uid451_uid454_invPE_0_to_prodXY_uid493_pT2_uid456_invPE_1_q;
prodXY_uid493_pT2_uid456_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid493_pT2_uid456_invPE_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid493_pT2_uid456_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid493_pT2_uid456_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid493_pT2_uid456_invPE_q <= prodXY_uid493_pT2_uid456_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid494_pT2_uid456_invPE(BITSELECT,493)@11
prodXYTruncFR_uid494_pT2_uid456_invPE_in <= prodXY_uid493_pT2_uid456_invPE_q;
prodXYTruncFR_uid494_pT2_uid456_invPE_b <= prodXYTruncFR_uid494_pT2_uid456_invPE_in(36 downto 13);
--highBBits_uid458_invPE(BITSELECT,457)@11
highBBits_uid458_invPE_in <= prodXYTruncFR_uid494_pT2_uid456_invPE_b;
highBBits_uid458_invPE_b <= highBBits_uid458_invPE_in(23 downto 2);
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor(LOGICAL,1421)
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_b <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_q <= not (ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_a or ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_b);
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena(REG,1422)
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_nor_q = "1") THEN
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd(LOGICAL,1423)
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_a <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_sticky_ena_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_b <= en;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_q <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_a and ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_b;
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_inputreg(DELAY,1411)
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => fracYAddr_uid235_div_uid49_fpArctan2Test_b, xout => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem(DUALMEM,1412)
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ia <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_inputreg_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_iq,
address_a => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_aa,
data_a => ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_ia
);
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_reset0 <= areset;
ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_q <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_iq(8 downto 0);
--reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0(REG,517)@7
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_q <= ld_fracYAddr_uid235_div_uid49_fpArctan2Test_b_to_reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid443_invTab_lutmem(DUALMEM,504)@8
memoryC0_uid443_invTab_lutmem_ia <= (others => '0');
memoryC0_uid443_invTab_lutmem_aa <= (others => '0');
memoryC0_uid443_invTab_lutmem_ab <= reg_fracYAddr_uid235_div_uid49_fpArctan2Test_0_to_memoryC0_uid443_invTab_lutmem_0_q;
memoryC0_uid443_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC0_uid443_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid443_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid443_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid443_invTab_lutmem_iq,
address_a => memoryC0_uid443_invTab_lutmem_aa,
data_a => memoryC0_uid443_invTab_lutmem_ia
);
memoryC0_uid443_invTab_lutmem_reset0 <= areset;
memoryC0_uid443_invTab_lutmem_q <= memoryC0_uid443_invTab_lutmem_iq(30 downto 0);
--reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0(REG,518)@10
reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0_q <= memoryC0_uid443_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid459_invPE(ADD,458)@11
sumAHighB_uid459_invPE_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0_q(30)) & reg_memoryC0_uid443_invTab_lutmem_0_to_sumAHighB_uid459_invPE_0_q);
sumAHighB_uid459_invPE_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid458_invPE_b(21)) & highBBits_uid458_invPE_b);
sumAHighB_uid459_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid459_invPE_a) + SIGNED(sumAHighB_uid459_invPE_b));
sumAHighB_uid459_invPE_q <= sumAHighB_uid459_invPE_o(31 downto 0);
--lowRangeB_uid457_invPE(BITSELECT,456)@11
lowRangeB_uid457_invPE_in <= prodXYTruncFR_uid494_pT2_uid456_invPE_b(1 downto 0);
lowRangeB_uid457_invPE_b <= lowRangeB_uid457_invPE_in(1 downto 0);
--s2_uid457_uid460_invPE(BITJOIN,459)@11
s2_uid457_uid460_invPE_q <= sumAHighB_uid459_invPE_q & lowRangeB_uid457_invPE_b;
--invY_uid238_div_uid49_fpArctan2Test(BITSELECT,237)@11
invY_uid238_div_uid49_fpArctan2Test_in <= s2_uid457_uid460_invPE_q(30 downto 0);
invY_uid238_div_uid49_fpArctan2Test_b <= invY_uid238_div_uid49_fpArctan2Test_in(30 downto 5);
--reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0(REG,519)@11
reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0_q <= invY_uid238_div_uid49_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test(MULT,461)@12
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_pr <= UNSIGNED(prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_a) * UNSIGNED(prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b);
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_a <= (others => '0');
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b <= (others => '0');
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_a <= reg_invY_uid238_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_0_q;
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b <= reg_lOAdded_uid241_div_uid49_fpArctan2Test_0_to_prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_1_q;
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_s1 <= STD_LOGIC_VECTOR(prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_q <= prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test(BITSELECT,462)@15
prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_in <= prodXY_uid462_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_q;
prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b <= prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_in(49 downto 24);
--invYO_uid239_div_uid49_fpArctan2Test(BITSELECT,238)@11
invYO_uid239_div_uid49_fpArctan2Test_in <= s2_uid457_uid460_invPE_q(31 downto 0);
invYO_uid239_div_uid49_fpArctan2Test_b <= invYO_uid239_div_uid49_fpArctan2Test_in(31 downto 31);
--fracYZero_uid198_div_uid49_fpArctan2Test(LOGICAL,197)@0
fracYZero_uid198_div_uid49_fpArctan2Test_a <= frac_uid13_fpArctan2Test_b;
fracYZero_uid198_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracYZero_uid198_div_uid49_fpArctan2Test_q <= "1" when fracYZero_uid198_div_uid49_fpArctan2Test_a = fracYZero_uid198_div_uid49_fpArctan2Test_b else "0";
--ld_fracYZero_uid198_div_uid49_fpArctan2Test_q_to_fracYPostZ_uid240_div_uid49_fpArctan2Test_a(DELAY,798)@0
ld_fracYZero_uid198_div_uid49_fpArctan2Test_q_to_fracYPostZ_uid240_div_uid49_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracYZero_uid198_div_uid49_fpArctan2Test_q, xout => ld_fracYZero_uid198_div_uid49_fpArctan2Test_q_to_fracYPostZ_uid240_div_uid49_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--fracYPostZ_uid240_div_uid49_fpArctan2Test(LOGICAL,239)@11
fracYPostZ_uid240_div_uid49_fpArctan2Test_a <= ld_fracYZero_uid198_div_uid49_fpArctan2Test_q_to_fracYPostZ_uid240_div_uid49_fpArctan2Test_a_q;
fracYPostZ_uid240_div_uid49_fpArctan2Test_b <= invYO_uid239_div_uid49_fpArctan2Test_b;
fracYPostZ_uid240_div_uid49_fpArctan2Test_q_i <= fracYPostZ_uid240_div_uid49_fpArctan2Test_a or fracYPostZ_uid240_div_uid49_fpArctan2Test_b;
fracYPostZ_uid240_div_uid49_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => fracYPostZ_uid240_div_uid49_fpArctan2Test_q, xin => fracYPostZ_uid240_div_uid49_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_fracYPostZ_uid240_div_uid49_fpArctan2Test_q_to_divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_b(DELAY,802)@12
ld_fracYPostZ_uid240_div_uid49_fpArctan2Test_q_to_divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => fracYPostZ_uid240_div_uid49_fpArctan2Test_q, xout => ld_fracYPostZ_uid240_div_uid49_fpArctan2Test_q_to_divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--divValPreNormTrunc_uid246_div_uid49_fpArctan2Test(MUX,245)@15
divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_s <= ld_fracYPostZ_uid240_div_uid49_fpArctan2Test_q_to_divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_b_q;
divValPreNormTrunc_uid246_div_uid49_fpArctan2Test: PROCESS (divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_s, en, prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b, oFracXExt_uid244_div_uid49_fpArctan2Test_q)
BEGIN
CASE divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_s IS
WHEN "0" => divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q <= prodXYTruncFR_uid463_prodDivPreNormProd_uid242_div_uid49_fpArctan2Test_b;
WHEN "1" => divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q <= oFracXExt_uid244_div_uid49_fpArctan2Test_q;
WHEN OTHERS => divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--norm_uid247_div_uid49_fpArctan2Test(BITSELECT,246)@15
norm_uid247_div_uid49_fpArctan2Test_in <= divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q;
norm_uid247_div_uid49_fpArctan2Test_b <= norm_uid247_div_uid49_fpArctan2Test_in(25 downto 25);
--ld_norm_uid247_div_uid49_fpArctan2Test_b_to_rndOp_uid253_div_uid49_fpArctan2Test_c(DELAY,813)@15
ld_norm_uid247_div_uid49_fpArctan2Test_b_to_rndOp_uid253_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => norm_uid247_div_uid49_fpArctan2Test_b, xout => ld_norm_uid247_div_uid49_fpArctan2Test_b_to_rndOp_uid253_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--rndOp_uid253_div_uid49_fpArctan2Test(BITJOIN,252)@16
rndOp_uid253_div_uid49_fpArctan2Test_q <= ld_norm_uid247_div_uid49_fpArctan2Test_b_to_rndOp_uid253_div_uid49_fpArctan2Test_c_q & cstAllZWF_uid7_fpArctan2Test_q & VCC_q;
--cstBiasM1_uid58_fpArctan2Test(CONSTANT,57)
cstBiasM1_uid58_fpArctan2Test_q <= "01111110";
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor(LOGICAL,1318)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_b <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_q <= not (ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_a or ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_b);
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_mem_top(CONSTANT,1314)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_mem_top_q <= "01010";
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp(LOGICAL,1315)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_a <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_mem_top_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q);
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_q <= "1" when ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_a = ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_b else "0";
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg(REG,1316)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena(REG,1319)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_nor_q = "1") THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd(LOGICAL,1320)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_a <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_sticky_ena_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_b <= en;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_a and ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_b;
--expXmY_uid232_div_uid49_fpArctan2Test(SUB,231)@0
expXmY_uid232_div_uid49_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & exp_uid27_fpArctan2Test_b);
expXmY_uid232_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & exp_uid11_fpArctan2Test_b);
expXmY_uid232_div_uid49_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid232_div_uid49_fpArctan2Test_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expXmY_uid232_div_uid49_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid232_div_uid49_fpArctan2Test_a) - UNSIGNED(expXmY_uid232_div_uid49_fpArctan2Test_b));
END IF;
END IF;
END PROCESS;
expXmY_uid232_div_uid49_fpArctan2Test_q <= expXmY_uid232_div_uid49_fpArctan2Test_o(8 downto 0);
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_inputreg(DELAY,1308)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expXmY_uid232_div_uid49_fpArctan2Test_q, xout => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt(COUNTER,1310)
-- every=1, low=0, high=10, step=1, init=1
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i = 9 THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_eq = '1') THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i - 10;
ELSE
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_i,4));
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg(REG,1311)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux(MUX,1312)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_s <= en;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux: PROCESS (ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_s, ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q, ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_q)
BEGIN
CASE ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_s IS
WHEN "0" => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q;
WHEN "1" => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem(DUALMEM,1309)
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ia <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_inputreg_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_aa <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ab <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 4,
numwords_a => 11,
width_b => 9,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_iq,
address_a => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_aa,
data_a => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_ia
);
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_reset0 <= areset;
ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_iq(8 downto 0);
--expR_uid233_div_uid49_fpArctan2Test(ADD,232)@14
expR_uid233_div_uid49_fpArctan2Test_a <= STD_LOGIC_VECTOR((10 downto 9 => ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_q(8)) & ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_mem_q);
expR_uid233_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasM1_uid58_fpArctan2Test_q);
expR_uid233_div_uid49_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expR_uid233_div_uid49_fpArctan2Test_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expR_uid233_div_uid49_fpArctan2Test_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid233_div_uid49_fpArctan2Test_a) + SIGNED(expR_uid233_div_uid49_fpArctan2Test_b));
END IF;
END IF;
END PROCESS;
expR_uid233_div_uid49_fpArctan2Test_q <= expR_uid233_div_uid49_fpArctan2Test_o(9 downto 0);
--divValPreNormHigh_uid248_div_uid49_fpArctan2Test(BITSELECT,247)@15
divValPreNormHigh_uid248_div_uid49_fpArctan2Test_in <= divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q(24 downto 0);
divValPreNormHigh_uid248_div_uid49_fpArctan2Test_b <= divValPreNormHigh_uid248_div_uid49_fpArctan2Test_in(24 downto 1);
--divValPreNormLow_uid249_div_uid49_fpArctan2Test(BITSELECT,248)@15
divValPreNormLow_uid249_div_uid49_fpArctan2Test_in <= divValPreNormTrunc_uid246_div_uid49_fpArctan2Test_q(23 downto 0);
divValPreNormLow_uid249_div_uid49_fpArctan2Test_b <= divValPreNormLow_uid249_div_uid49_fpArctan2Test_in(23 downto 0);
--normFracRnd_uid250_div_uid49_fpArctan2Test(MUX,249)@15
normFracRnd_uid250_div_uid49_fpArctan2Test_s <= norm_uid247_div_uid49_fpArctan2Test_b;
normFracRnd_uid250_div_uid49_fpArctan2Test: PROCESS (normFracRnd_uid250_div_uid49_fpArctan2Test_s, en, divValPreNormLow_uid249_div_uid49_fpArctan2Test_b, divValPreNormHigh_uid248_div_uid49_fpArctan2Test_b)
BEGIN
CASE normFracRnd_uid250_div_uid49_fpArctan2Test_s IS
WHEN "0" => normFracRnd_uid250_div_uid49_fpArctan2Test_q <= divValPreNormLow_uid249_div_uid49_fpArctan2Test_b;
WHEN "1" => normFracRnd_uid250_div_uid49_fpArctan2Test_q <= divValPreNormHigh_uid248_div_uid49_fpArctan2Test_b;
WHEN OTHERS => normFracRnd_uid250_div_uid49_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRnd_uid251_div_uid49_fpArctan2Test(BITJOIN,250)@15
expFracRnd_uid251_div_uid49_fpArctan2Test_q <= expR_uid233_div_uid49_fpArctan2Test_q & normFracRnd_uid250_div_uid49_fpArctan2Test_q;
--reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0(REG,521)@15
reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0_q <= expFracRnd_uid251_div_uid49_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid254_div_uid49_fpArctan2Test(ADD,253)@16
expFracPostRnd_uid254_div_uid49_fpArctan2Test_a <= STD_LOGIC_VECTOR((35 downto 34 => reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0_q(33)) & reg_expFracRnd_uid251_div_uid49_fpArctan2Test_0_to_expFracPostRnd_uid254_div_uid49_fpArctan2Test_0_q);
expFracPostRnd_uid254_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR('0' & "0000000000" & rndOp_uid253_div_uid49_fpArctan2Test_q);
expFracPostRnd_uid254_div_uid49_fpArctan2Test_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid254_div_uid49_fpArctan2Test_a) + SIGNED(expFracPostRnd_uid254_div_uid49_fpArctan2Test_b));
expFracPostRnd_uid254_div_uid49_fpArctan2Test_q <= expFracPostRnd_uid254_div_uid49_fpArctan2Test_o(34 downto 0);
--excRPreExc_uid257_div_uid49_fpArctan2Test(BITSELECT,256)@16
excRPreExc_uid257_div_uid49_fpArctan2Test_in <= expFracPostRnd_uid254_div_uid49_fpArctan2Test_q(31 downto 0);
excRPreExc_uid257_div_uid49_fpArctan2Test_b <= excRPreExc_uid257_div_uid49_fpArctan2Test_in(31 downto 24);
--ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d(DELAY,861)@16
ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => excRPreExc_uid257_div_uid49_fpArctan2Test_b, xout => ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid275_div_uid49_fpArctan2Test_q_to_concExc_uid276_div_uid49_fpArctan2Test_c(DELAY,856)@0
ld_excRNaN_uid275_div_uid49_fpArctan2Test_q_to_concExc_uid276_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid275_div_uid49_fpArctan2Test_q, xout => ld_excRNaN_uid275_div_uid49_fpArctan2Test_q_to_concExc_uid276_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid227_div_uid49_fpArctan2Test(LOGICAL,226)@0
InvExc_N_uid227_div_uid49_fpArctan2Test_a <= exc_N_uid17_fpArctan2Test_q;
InvExc_N_uid227_div_uid49_fpArctan2Test_q <= not InvExc_N_uid227_div_uid49_fpArctan2Test_a;
--InvExc_I_uid228_div_uid49_fpArctan2Test(LOGICAL,227)@0
InvExc_I_uid228_div_uid49_fpArctan2Test_a <= exc_I_uid15_fpArctan2Test_q;
InvExc_I_uid228_div_uid49_fpArctan2Test_q <= not InvExc_I_uid228_div_uid49_fpArctan2Test_a;
--InvExpXIsZero_uid229_div_uid49_fpArctan2Test(LOGICAL,228)@0
InvExpXIsZero_uid229_div_uid49_fpArctan2Test_a <= expXIsZero_uid219_div_uid49_fpArctan2Test_q;
InvExpXIsZero_uid229_div_uid49_fpArctan2Test_q <= not InvExpXIsZero_uid229_div_uid49_fpArctan2Test_a;
--exc_R_uid230_div_uid49_fpArctan2Test(LOGICAL,229)@0
exc_R_uid230_div_uid49_fpArctan2Test_a <= InvExpXIsZero_uid229_div_uid49_fpArctan2Test_q;
exc_R_uid230_div_uid49_fpArctan2Test_b <= InvExc_I_uid228_div_uid49_fpArctan2Test_q;
exc_R_uid230_div_uid49_fpArctan2Test_c <= InvExc_N_uid227_div_uid49_fpArctan2Test_q;
exc_R_uid230_div_uid49_fpArctan2Test_q <= exc_R_uid230_div_uid49_fpArctan2Test_a and exc_R_uid230_div_uid49_fpArctan2Test_b and exc_R_uid230_div_uid49_fpArctan2Test_c;
--excXIYR_uid271_div_uid49_fpArctan2Test(LOGICAL,270)@0
excXIYR_uid271_div_uid49_fpArctan2Test_a <= exc_I_uid31_fpArctan2Test_q;
excXIYR_uid271_div_uid49_fpArctan2Test_b <= exc_R_uid230_div_uid49_fpArctan2Test_q;
excXIYR_uid271_div_uid49_fpArctan2Test_q <= excXIYR_uid271_div_uid49_fpArctan2Test_a and excXIYR_uid271_div_uid49_fpArctan2Test_b;
--ld_excXIYR_uid271_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_d(DELAY,845)@0
ld_excXIYR_uid271_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_d : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excXIYR_uid271_div_uid49_fpArctan2Test_q, xout => ld_excXIYR_uid271_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--excXIYZ_uid270_div_uid49_fpArctan2Test(LOGICAL,269)@0
excXIYZ_uid270_div_uid49_fpArctan2Test_a <= exc_I_uid31_fpArctan2Test_q;
excXIYZ_uid270_div_uid49_fpArctan2Test_b <= expXIsZero_uid219_div_uid49_fpArctan2Test_q;
excXIYZ_uid270_div_uid49_fpArctan2Test_q <= excXIYZ_uid270_div_uid49_fpArctan2Test_a and excXIYZ_uid270_div_uid49_fpArctan2Test_b;
--ld_excXIYZ_uid270_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_c(DELAY,844)@0
ld_excXIYZ_uid270_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excXIYZ_uid270_div_uid49_fpArctan2Test_q, xout => ld_excXIYZ_uid270_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid258_div_uid49_fpArctan2Test(BITSELECT,257)@16
expRExt_uid258_div_uid49_fpArctan2Test_in <= expFracPostRnd_uid254_div_uid49_fpArctan2Test_q;
expRExt_uid258_div_uid49_fpArctan2Test_b <= expRExt_uid258_div_uid49_fpArctan2Test_in(34 downto 24);
--reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1(REG,522)@16
reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q <= expRExt_uid258_div_uid49_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid262_div_uid49_fpArctan2Test(COMPARE,261)@17
expOvf_uid262_div_uid49_fpArctan2Test_cin <= GND_q;
expOvf_uid262_div_uid49_fpArctan2Test_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q(10)) & reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q) & '0';
expOvf_uid262_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid6_fpArctan2Test_q) & expOvf_uid262_div_uid49_fpArctan2Test_cin(0);
expOvf_uid262_div_uid49_fpArctan2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid262_div_uid49_fpArctan2Test_a) - SIGNED(expOvf_uid262_div_uid49_fpArctan2Test_b));
expOvf_uid262_div_uid49_fpArctan2Test_n(0) <= not expOvf_uid262_div_uid49_fpArctan2Test_o(13);
--ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c(DELAY,825)@0
ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => exc_R_uid230_div_uid49_fpArctan2Test_q, xout => ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid211_div_uid49_fpArctan2Test(LOGICAL,210)@0
InvExc_N_uid211_div_uid49_fpArctan2Test_a <= exc_N_uid33_fpArctan2Test_q;
InvExc_N_uid211_div_uid49_fpArctan2Test_q <= not InvExc_N_uid211_div_uid49_fpArctan2Test_a;
--InvExc_I_uid212_div_uid49_fpArctan2Test(LOGICAL,211)@0
InvExc_I_uid212_div_uid49_fpArctan2Test_a <= exc_I_uid31_fpArctan2Test_q;
InvExc_I_uid212_div_uid49_fpArctan2Test_q <= not InvExc_I_uid212_div_uid49_fpArctan2Test_a;
--InvExpXIsZero_uid213_div_uid49_fpArctan2Test(LOGICAL,212)@0
InvExpXIsZero_uid213_div_uid49_fpArctan2Test_a <= expXIsZero_uid203_div_uid49_fpArctan2Test_q;
InvExpXIsZero_uid213_div_uid49_fpArctan2Test_q <= not InvExpXIsZero_uid213_div_uid49_fpArctan2Test_a;
--exc_R_uid214_div_uid49_fpArctan2Test(LOGICAL,213)@0
exc_R_uid214_div_uid49_fpArctan2Test_a <= InvExpXIsZero_uid213_div_uid49_fpArctan2Test_q;
exc_R_uid214_div_uid49_fpArctan2Test_b <= InvExc_I_uid212_div_uid49_fpArctan2Test_q;
exc_R_uid214_div_uid49_fpArctan2Test_c <= InvExc_N_uid211_div_uid49_fpArctan2Test_q;
exc_R_uid214_div_uid49_fpArctan2Test_q <= exc_R_uid214_div_uid49_fpArctan2Test_a and exc_R_uid214_div_uid49_fpArctan2Test_b and exc_R_uid214_div_uid49_fpArctan2Test_c;
--ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b(DELAY,824)@0
ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => exc_R_uid214_div_uid49_fpArctan2Test_q, xout => ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--excXRYROvf_uid269_div_uid49_fpArctan2Test(LOGICAL,268)@17
excXRYROvf_uid269_div_uid49_fpArctan2Test_a <= ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b_q;
excXRYROvf_uid269_div_uid49_fpArctan2Test_b <= ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c_q;
excXRYROvf_uid269_div_uid49_fpArctan2Test_c <= expOvf_uid262_div_uid49_fpArctan2Test_n;
excXRYROvf_uid269_div_uid49_fpArctan2Test_q <= excXRYROvf_uid269_div_uid49_fpArctan2Test_a and excXRYROvf_uid269_div_uid49_fpArctan2Test_b and excXRYROvf_uid269_div_uid49_fpArctan2Test_c;
--excXRYZ_uid268_div_uid49_fpArctan2Test(LOGICAL,267)@0
excXRYZ_uid268_div_uid49_fpArctan2Test_a <= exc_R_uid214_div_uid49_fpArctan2Test_q;
excXRYZ_uid268_div_uid49_fpArctan2Test_b <= expXIsZero_uid219_div_uid49_fpArctan2Test_q;
excXRYZ_uid268_div_uid49_fpArctan2Test_q <= excXRYZ_uid268_div_uid49_fpArctan2Test_a and excXRYZ_uid268_div_uid49_fpArctan2Test_b;
--ld_excXRYZ_uid268_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_a(DELAY,842)@0
ld_excXRYZ_uid268_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excXRYZ_uid268_div_uid49_fpArctan2Test_q, xout => ld_excXRYZ_uid268_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid272_div_uid49_fpArctan2Test(LOGICAL,271)@17
excRInf_uid272_div_uid49_fpArctan2Test_a <= ld_excXRYZ_uid268_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_a_q;
excRInf_uid272_div_uid49_fpArctan2Test_b <= excXRYROvf_uid269_div_uid49_fpArctan2Test_q;
excRInf_uid272_div_uid49_fpArctan2Test_c <= ld_excXIYZ_uid270_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_c_q;
excRInf_uid272_div_uid49_fpArctan2Test_d <= ld_excXIYR_uid271_div_uid49_fpArctan2Test_q_to_excRInf_uid272_div_uid49_fpArctan2Test_d_q;
excRInf_uid272_div_uid49_fpArctan2Test_q <= excRInf_uid272_div_uid49_fpArctan2Test_a or excRInf_uid272_div_uid49_fpArctan2Test_b or excRInf_uid272_div_uid49_fpArctan2Test_c or excRInf_uid272_div_uid49_fpArctan2Test_d;
--xRegOrZero_uid265_div_uid49_fpArctan2Test(LOGICAL,264)@0
xRegOrZero_uid265_div_uid49_fpArctan2Test_a <= exc_R_uid214_div_uid49_fpArctan2Test_q;
xRegOrZero_uid265_div_uid49_fpArctan2Test_b <= expXIsZero_uid203_div_uid49_fpArctan2Test_q;
xRegOrZero_uid265_div_uid49_fpArctan2Test_q <= xRegOrZero_uid265_div_uid49_fpArctan2Test_a or xRegOrZero_uid265_div_uid49_fpArctan2Test_b;
--regOrZeroOverInf_uid266_div_uid49_fpArctan2Test(LOGICAL,265)@0
regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_a <= xRegOrZero_uid265_div_uid49_fpArctan2Test_q;
regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_b <= exc_I_uid15_fpArctan2Test_q;
regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q <= regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_a and regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_b;
--ld_regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_c(DELAY,832)@0
ld_regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q, xout => ld_regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid259_div_uid49_fpArctan2Test(COMPARE,258)@17
expUdf_uid259_div_uid49_fpArctan2Test_cin <= GND_q;
expUdf_uid259_div_uid49_fpArctan2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid259_div_uid49_fpArctan2Test_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q(10)) & reg_expRExt_uid258_div_uid49_fpArctan2Test_0_to_expUdf_uid259_div_uid49_fpArctan2Test_1_q) & expUdf_uid259_div_uid49_fpArctan2Test_cin(0);
expUdf_uid259_div_uid49_fpArctan2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid259_div_uid49_fpArctan2Test_a) - SIGNED(expUdf_uid259_div_uid49_fpArctan2Test_b));
expUdf_uid259_div_uid49_fpArctan2Test_n(0) <= not expUdf_uid259_div_uid49_fpArctan2Test_o(13);
--regOverRegWithUf_uid264_div_uid49_fpArctan2Test(LOGICAL,263)@17
regOverRegWithUf_uid264_div_uid49_fpArctan2Test_a <= expUdf_uid259_div_uid49_fpArctan2Test_n;
regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b <= ld_exc_R_uid214_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b_q;
regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c <= ld_exc_R_uid230_div_uid49_fpArctan2Test_q_to_regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c_q;
regOverRegWithUf_uid264_div_uid49_fpArctan2Test_q <= regOverRegWithUf_uid264_div_uid49_fpArctan2Test_a and regOverRegWithUf_uid264_div_uid49_fpArctan2Test_b and regOverRegWithUf_uid264_div_uid49_fpArctan2Test_c;
--zeroOverReg_uid263_div_uid49_fpArctan2Test(LOGICAL,262)@0
zeroOverReg_uid263_div_uid49_fpArctan2Test_a <= expXIsZero_uid203_div_uid49_fpArctan2Test_q;
zeroOverReg_uid263_div_uid49_fpArctan2Test_b <= exc_R_uid230_div_uid49_fpArctan2Test_q;
zeroOverReg_uid263_div_uid49_fpArctan2Test_q <= zeroOverReg_uid263_div_uid49_fpArctan2Test_a and zeroOverReg_uid263_div_uid49_fpArctan2Test_b;
--ld_zeroOverReg_uid263_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_a(DELAY,830)@0
ld_zeroOverReg_uid263_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => zeroOverReg_uid263_div_uid49_fpArctan2Test_q, xout => ld_zeroOverReg_uid263_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid267_div_uid49_fpArctan2Test(LOGICAL,266)@17
excRZero_uid267_div_uid49_fpArctan2Test_a <= ld_zeroOverReg_uid263_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_a_q;
excRZero_uid267_div_uid49_fpArctan2Test_b <= regOverRegWithUf_uid264_div_uid49_fpArctan2Test_q;
excRZero_uid267_div_uid49_fpArctan2Test_c <= ld_regOrZeroOverInf_uid266_div_uid49_fpArctan2Test_q_to_excRZero_uid267_div_uid49_fpArctan2Test_c_q;
excRZero_uid267_div_uid49_fpArctan2Test_q <= excRZero_uid267_div_uid49_fpArctan2Test_a or excRZero_uid267_div_uid49_fpArctan2Test_b or excRZero_uid267_div_uid49_fpArctan2Test_c;
--concExc_uid276_div_uid49_fpArctan2Test(BITJOIN,275)@17
concExc_uid276_div_uid49_fpArctan2Test_q <= ld_excRNaN_uid275_div_uid49_fpArctan2Test_q_to_concExc_uid276_div_uid49_fpArctan2Test_c_q & excRInf_uid272_div_uid49_fpArctan2Test_q & excRZero_uid267_div_uid49_fpArctan2Test_q;
--reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0(REG,524)@17
reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0_q <= concExc_uid276_div_uid49_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid277_div_uid49_fpArctan2Test(LOOKUP,276)@18
excREnc_uid277_div_uid49_fpArctan2Test: PROCESS (reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid276_div_uid49_fpArctan2Test_0_to_excREnc_uid277_div_uid49_fpArctan2Test_0_q) IS
WHEN "000" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "01";
WHEN "001" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "00";
WHEN "010" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "10";
WHEN "011" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "00";
WHEN "100" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "11";
WHEN "101" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "00";
WHEN "110" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "00";
WHEN "111" => excREnc_uid277_div_uid49_fpArctan2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid277_div_uid49_fpArctan2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid285_div_uid49_fpArctan2Test(MUX,284)@18
expRPostExc_uid285_div_uid49_fpArctan2Test_s <= excREnc_uid277_div_uid49_fpArctan2Test_q;
expRPostExc_uid285_div_uid49_fpArctan2Test: PROCESS (expRPostExc_uid285_div_uid49_fpArctan2Test_s, en, cstAllZWE_uid56_fpArctan2Test_q, ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d_q, cstAllOWE_uid6_fpArctan2Test_q, cstAllOWE_uid6_fpArctan2Test_q)
BEGIN
CASE expRPostExc_uid285_div_uid49_fpArctan2Test_s IS
WHEN "00" => expRPostExc_uid285_div_uid49_fpArctan2Test_q <= cstAllZWE_uid56_fpArctan2Test_q;
WHEN "01" => expRPostExc_uid285_div_uid49_fpArctan2Test_q <= ld_excRPreExc_uid257_div_uid49_fpArctan2Test_b_to_expRPostExc_uid285_div_uid49_fpArctan2Test_d_q;
WHEN "10" => expRPostExc_uid285_div_uid49_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN "11" => expRPostExc_uid285_div_uid49_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN OTHERS => expRPostExc_uid285_div_uid49_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNWF_uid55_fpArctan2Test(CONSTANT,54)
cstNaNWF_uid55_fpArctan2Test_q <= "00000000000000000000001";
--fracRPreExc_uid256_div_uid49_fpArctan2Test(BITSELECT,255)@16
fracRPreExc_uid256_div_uid49_fpArctan2Test_in <= expFracPostRnd_uid254_div_uid49_fpArctan2Test_q(23 downto 0);
fracRPreExc_uid256_div_uid49_fpArctan2Test_b <= fracRPreExc_uid256_div_uid49_fpArctan2Test_in(23 downto 1);
--ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d(DELAY,859)@16
ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid256_div_uid49_fpArctan2Test_b, xout => ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid281_div_uid49_fpArctan2Test(MUX,280)@18
fracRPostExc_uid281_div_uid49_fpArctan2Test_s <= excREnc_uid277_div_uid49_fpArctan2Test_q;
fracRPostExc_uid281_div_uid49_fpArctan2Test: PROCESS (fracRPostExc_uid281_div_uid49_fpArctan2Test_s, en, cstAllZWF_uid7_fpArctan2Test_q, ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d_q, cstAllZWF_uid7_fpArctan2Test_q, cstNaNWF_uid55_fpArctan2Test_q)
BEGIN
CASE fracRPostExc_uid281_div_uid49_fpArctan2Test_s IS
WHEN "00" => fracRPostExc_uid281_div_uid49_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "01" => fracRPostExc_uid281_div_uid49_fpArctan2Test_q <= ld_fracRPreExc_uid256_div_uid49_fpArctan2Test_b_to_fracRPostExc_uid281_div_uid49_fpArctan2Test_d_q;
WHEN "10" => fracRPostExc_uid281_div_uid49_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "11" => fracRPostExc_uid281_div_uid49_fpArctan2Test_q <= cstNaNWF_uid55_fpArctan2Test_q;
WHEN OTHERS => fracRPostExc_uid281_div_uid49_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--divR_uid288_div_uid49_fpArctan2Test(BITJOIN,287)@18
divR_uid288_div_uid49_fpArctan2Test_q <= ld_sRPostExc_uid287_div_uid49_fpArctan2Test_q_to_divR_uid288_div_uid49_fpArctan2Test_c_q & expRPostExc_uid285_div_uid49_fpArctan2Test_q & fracRPostExc_uid281_div_uid49_fpArctan2Test_q;
--singX_uid52_fpArctan2Test(BITSELECT,51)@18
singX_uid52_fpArctan2Test_in <= divR_uid288_div_uid49_fpArctan2Test_q;
singX_uid52_fpArctan2Test_b <= singX_uid52_fpArctan2Test_in(31 downto 31);
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_inputreg(DELAY,1154)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid52_fpArctan2Test_b, xout => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt(COUNTER,1156)
-- every=1, low=0, high=31, step=1, init=1
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_i <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_i,5));
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg(REG,1157)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux(MUX,1158)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_s <= en;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux: PROCESS (ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_s, ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q, ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem(DUALMEM,1155)
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ia <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_inputreg_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_aa <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ab <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_iq,
address_a => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_aa,
data_a => ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_ia
);
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_iq(0 downto 0);
--piO2_uid83_fpArctan2Test(CONSTANT,82)
piO2_uid83_fpArctan2Test_q <= "11001001000011111101101011";
--cstPiO2_uid85_fpArctan2Test(BITSELECT,84)@52
cstPiO2_uid85_fpArctan2Test_in <= piO2_uid83_fpArctan2Test_q(24 downto 0);
cstPiO2_uid85_fpArctan2Test_b <= cstPiO2_uid85_fpArctan2Test_in(24 downto 2);
--fpPiO2C_uid86_fpArctan2Test(BITJOIN,85)@52
fpPiO2C_uid86_fpArctan2Test_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_q & cstBias_uid57_fpArctan2Test_q & cstPiO2_uid85_fpArctan2Test_b;
--reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3(REG,580)@52
reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3_q <= fpPiO2C_uid86_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--piO4_uid84_fpArctan2Test(CONSTANT,83)
piO4_uid84_fpArctan2Test_q <= "110010010000111111011011";
--cstPiO4_uid88_fpArctan2Test(BITSELECT,87)@52
cstPiO4_uid88_fpArctan2Test_in <= piO4_uid84_fpArctan2Test_q(22 downto 0);
cstPiO4_uid88_fpArctan2Test_b <= cstPiO4_uid88_fpArctan2Test_in(22 downto 0);
--fpPiO4C_uid89_fpArctan2Test(BITJOIN,88)@52
fpPiO4C_uid89_fpArctan2Test_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_mem_q & cstBiasM1_uid58_fpArctan2Test_q & cstPiO4_uid88_fpArctan2Test_b;
--reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2(REG,579)@52
reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2_q <= fpPiO4C_uid89_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor(LOGICAL,1177)
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_b <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_q <= not (ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_a or ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_b);
--ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena(REG,1178)
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_nor_q = "1") THEN
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd(LOGICAL,1179)
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_a <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_sticky_ena_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_b <= en;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_q <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_a and ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_b;
--fracX_uid51_fpArctan2Test(BITSELECT,50)@18
fracX_uid51_fpArctan2Test_in <= divR_uid288_div_uid49_fpArctan2Test_q(22 downto 0);
fracX_uid51_fpArctan2Test_b <= fracX_uid51_fpArctan2Test_in(22 downto 0);
--reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1(REG,530)@18
reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1_q <= fracX_uid51_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid72_fpArctan2Test(LOGICAL,71)@19
fracXIsZero_uid72_fpArctan2Test_a <= reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1_q;
fracXIsZero_uid72_fpArctan2Test_b <= cstAllZWF_uid7_fpArctan2Test_q;
fracXIsZero_uid72_fpArctan2Test_q <= "1" when fracXIsZero_uid72_fpArctan2Test_a = fracXIsZero_uid72_fpArctan2Test_b else "0";
--expX_uid50_fpArctan2Test(BITSELECT,49)@18
expX_uid50_fpArctan2Test_in <= divR_uid288_div_uid49_fpArctan2Test_q(30 downto 0);
expX_uid50_fpArctan2Test_b <= expX_uid50_fpArctan2Test_in(30 downto 23);
--reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1(REG,525)@18
reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q <= expX_uid50_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid70_fpArctan2Test(LOGICAL,69)@19
expXIsMax_uid70_fpArctan2Test_a <= reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q;
expXIsMax_uid70_fpArctan2Test_b <= cstAllOWE_uid6_fpArctan2Test_q;
expXIsMax_uid70_fpArctan2Test_q <= "1" when expXIsMax_uid70_fpArctan2Test_a = expXIsMax_uid70_fpArctan2Test_b else "0";
--exc_I_uid73_fpArctan2Test(LOGICAL,72)@19
exc_I_uid73_fpArctan2Test_a <= expXIsMax_uid70_fpArctan2Test_q;
exc_I_uid73_fpArctan2Test_b <= fracXIsZero_uid72_fpArctan2Test_q;
exc_I_uid73_fpArctan2Test_q <= exc_I_uid73_fpArctan2Test_a and exc_I_uid73_fpArctan2Test_b;
--ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_inputreg(DELAY,1167)
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid73_fpArctan2Test_q, xout => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem(DUALMEM,1168)
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ia <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_inputreg_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_aa <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdreg_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ab <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_replace_rdmux_q;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_iq,
address_a => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_aa,
data_a => ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_ia
);
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_reset0 <= areset;
ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_q <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_iq(0 downto 0);
--constOut_uid91_fpArctan2Test(MUX,90)@53
constOut_uid91_fpArctan2Test_s <= ld_exc_I_uid73_fpArctan2Test_q_to_constOut_uid91_fpArctan2Test_b_replace_mem_q;
constOut_uid91_fpArctan2Test: PROCESS (constOut_uid91_fpArctan2Test_s, en, reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2_q, reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3_q)
BEGIN
CASE constOut_uid91_fpArctan2Test_s IS
WHEN "0" => constOut_uid91_fpArctan2Test_q <= reg_fpPiO4C_uid89_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_2_q;
WHEN "1" => constOut_uid91_fpArctan2Test_q <= reg_fpPiO2C_uid86_fpArctan2Test_0_to_constOut_uid91_fpArctan2Test_3_q;
WHEN OTHERS => constOut_uid91_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid149_fpArctan2Test(BITSELECT,148)@53
fracOutCst_uid149_fpArctan2Test_in <= constOut_uid91_fpArctan2Test_q(22 downto 0);
fracOutCst_uid149_fpArctan2Test_b <= fracOutCst_uid149_fpArctan2Test_in(22 downto 0);
--reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5(REG,584)@53
reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5_q <= fracOutCst_uid149_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor(LOGICAL,1214)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_b <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_q <= not (ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_a or ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_b);
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena(REG,1215)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd(LOGICAL,1216)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_a <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_sticky_ena_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_a and ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_b;
--cst01pWShift_uid107_fpArctan2Test(CONSTANT,106)
cst01pWShift_uid107_fpArctan2Test_q <= "0000000000000";
--InvFracXIsZero_uid310_z_uid95_fpArctan2Test(LOGICAL,309)@19
InvFracXIsZero_uid310_z_uid95_fpArctan2Test_a <= fracXIsZero_uid72_fpArctan2Test_q;
InvFracXIsZero_uid310_z_uid95_fpArctan2Test_q <= not InvFracXIsZero_uid310_z_uid95_fpArctan2Test_a;
--exc_N_uid311_z_uid95_fpArctan2Test(LOGICAL,310)@19
exc_N_uid311_z_uid95_fpArctan2Test_a <= expXIsMax_uid70_fpArctan2Test_q;
exc_N_uid311_z_uid95_fpArctan2Test_b <= InvFracXIsZero_uid310_z_uid95_fpArctan2Test_q;
exc_N_uid311_z_uid95_fpArctan2Test_q <= exc_N_uid311_z_uid95_fpArctan2Test_a and exc_N_uid311_z_uid95_fpArctan2Test_b;
--InvExc_N_uid312_z_uid95_fpArctan2Test(LOGICAL,311)@19
InvExc_N_uid312_z_uid95_fpArctan2Test_a <= exc_N_uid311_z_uid95_fpArctan2Test_q;
InvExc_N_uid312_z_uid95_fpArctan2Test_q <= not InvExc_N_uid312_z_uid95_fpArctan2Test_a;
--reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1(REG,545)@18
reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1_q <= singX_uid52_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--signR_uid339_z_uid95_fpArctan2Test(LOGICAL,338)@19
signR_uid339_z_uid95_fpArctan2Test_a <= reg_singX_uid52_fpArctan2Test_0_to_signR_uid339_z_uid95_fpArctan2Test_1_q;
signR_uid339_z_uid95_fpArctan2Test_b <= InvExc_N_uid312_z_uid95_fpArctan2Test_q;
signR_uid339_z_uid95_fpArctan2Test_q_i <= signR_uid339_z_uid95_fpArctan2Test_a and signR_uid339_z_uid95_fpArctan2Test_b;
signR_uid339_z_uid95_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signR_uid339_z_uid95_fpArctan2Test_q, xin => signR_uid339_z_uid95_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signR_uid339_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_c(DELAY,910)@20
ld_signR_uid339_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => signR_uid339_z_uid95_fpArctan2Test_q, xout => ld_signR_uid339_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor(LOGICAL,1356)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_b <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_q <= not (ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_a or ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_b);
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_mem_top(CONSTANT,1352)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_mem_top_q <= "0110";
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp(LOGICAL,1353)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_a <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_mem_top_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q);
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_q <= "1" when ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_a = ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_b else "0";
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg(REG,1354)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena(REG,1357)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd(LOGICAL,1358)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_a <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_sticky_ena_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_a and ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_b;
--cst2Bias_uid298_z_uid95_fpArctan2Test(CONSTANT,297)
cst2Bias_uid298_z_uid95_fpArctan2Test_q <= "11111110";
--expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test(SUB,326)@19
expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid298_z_uid95_fpArctan2Test_q);
expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q);
expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_a) - UNSIGNED(expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_b));
expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_q <= expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_o(8 downto 0);
--expRCompYIsOne_uid328_z_uid95_fpArctan2Test(BITSELECT,327)@19
expRCompYIsOne_uid328_z_uid95_fpArctan2Test_in <= expRCompYIsOneExt_uid327_z_uid95_fpArctan2Test_q(7 downto 0);
expRCompYIsOne_uid328_z_uid95_fpArctan2Test_b <= expRCompYIsOne_uid328_z_uid95_fpArctan2Test_in(7 downto 0);
--cst2BiasM1_uid297_z_uid95_fpArctan2Test(CONSTANT,296)
cst2BiasM1_uid297_z_uid95_fpArctan2Test_q <= "11111101";
--expRCompExt_uid324_z_uid95_fpArctan2Test(SUB,323)@19
expRCompExt_uid324_z_uid95_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid297_z_uid95_fpArctan2Test_q);
expRCompExt_uid324_z_uid95_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q);
expRCompExt_uid324_z_uid95_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid324_z_uid95_fpArctan2Test_a) - UNSIGNED(expRCompExt_uid324_z_uid95_fpArctan2Test_b));
expRCompExt_uid324_z_uid95_fpArctan2Test_q <= expRCompExt_uid324_z_uid95_fpArctan2Test_o(8 downto 0);
--expRComp_uid325_z_uid95_fpArctan2Test(BITSELECT,324)@19
expRComp_uid325_z_uid95_fpArctan2Test_in <= expRCompExt_uid324_z_uid95_fpArctan2Test_q(7 downto 0);
expRComp_uid325_z_uid95_fpArctan2Test_b <= expRComp_uid325_z_uid95_fpArctan2Test_in(7 downto 0);
--fracXIsZero_uid317_z_uid95_fpArctan2Test(LOGICAL,316)@19
fracXIsZero_uid317_z_uid95_fpArctan2Test_a <= reg_fracX_uid51_fpArctan2Test_0_to_fracXIsZero_uid72_fpArctan2Test_1_q;
fracXIsZero_uid317_z_uid95_fpArctan2Test_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid317_z_uid95_fpArctan2Test_q <= "1" when fracXIsZero_uid317_z_uid95_fpArctan2Test_a = fracXIsZero_uid317_z_uid95_fpArctan2Test_b else "0";
--expRCalc_uid331_z_uid95_fpArctan2Test(MUX,330)@19
expRCalc_uid331_z_uid95_fpArctan2Test_s <= fracXIsZero_uid317_z_uid95_fpArctan2Test_q;
expRCalc_uid331_z_uid95_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid331_z_uid95_fpArctan2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid331_z_uid95_fpArctan2Test_s IS
WHEN "0" => expRCalc_uid331_z_uid95_fpArctan2Test_q <= expRComp_uid325_z_uid95_fpArctan2Test_b;
WHEN "1" => expRCalc_uid331_z_uid95_fpArctan2Test_q <= expRCompYIsOne_uid328_z_uid95_fpArctan2Test_b;
WHEN OTHERS => expRCalc_uid331_z_uid95_fpArctan2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid68_fpArctan2Test(LOGICAL,67)@19
expXIsZero_uid68_fpArctan2Test_a <= reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q;
expXIsZero_uid68_fpArctan2Test_b <= cstAllZWE_uid56_fpArctan2Test_q;
expXIsZero_uid68_fpArctan2Test_q <= "1" when expXIsZero_uid68_fpArctan2Test_a = expXIsZero_uid68_fpArctan2Test_b else "0";
--udf_uid326_z_uid95_fpArctan2Test(BITSELECT,325)@19
udf_uid326_z_uid95_fpArctan2Test_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid324_z_uid95_fpArctan2Test_q(8)) & expRCompExt_uid324_z_uid95_fpArctan2Test_q);
udf_uid326_z_uid95_fpArctan2Test_b <= udf_uid326_z_uid95_fpArctan2Test_in(9 downto 9);
--InvExc_I_uid313_z_uid95_fpArctan2Test(LOGICAL,312)@19
InvExc_I_uid313_z_uid95_fpArctan2Test_a <= exc_I_uid73_fpArctan2Test_q;
InvExc_I_uid313_z_uid95_fpArctan2Test_q <= not InvExc_I_uid313_z_uid95_fpArctan2Test_a;
--InvExpXIsZero_uid314_z_uid95_fpArctan2Test(LOGICAL,313)@19
InvExpXIsZero_uid314_z_uid95_fpArctan2Test_a <= expXIsZero_uid68_fpArctan2Test_q;
InvExpXIsZero_uid314_z_uid95_fpArctan2Test_q <= not InvExpXIsZero_uid314_z_uid95_fpArctan2Test_a;
--exc_R_uid315_z_uid95_fpArctan2Test(LOGICAL,314)@19
exc_R_uid315_z_uid95_fpArctan2Test_a <= InvExpXIsZero_uid314_z_uid95_fpArctan2Test_q;
exc_R_uid315_z_uid95_fpArctan2Test_b <= InvExc_I_uid313_z_uid95_fpArctan2Test_q;
exc_R_uid315_z_uid95_fpArctan2Test_c <= InvExc_N_uid312_z_uid95_fpArctan2Test_q;
exc_R_uid315_z_uid95_fpArctan2Test_q <= exc_R_uid315_z_uid95_fpArctan2Test_a and exc_R_uid315_z_uid95_fpArctan2Test_b and exc_R_uid315_z_uid95_fpArctan2Test_c;
--xRegAndUdf_uid332_z_uid95_fpArctan2Test(LOGICAL,331)@19
xRegAndUdf_uid332_z_uid95_fpArctan2Test_a <= exc_R_uid315_z_uid95_fpArctan2Test_q;
xRegAndUdf_uid332_z_uid95_fpArctan2Test_b <= udf_uid326_z_uid95_fpArctan2Test_b;
xRegAndUdf_uid332_z_uid95_fpArctan2Test_q <= xRegAndUdf_uid332_z_uid95_fpArctan2Test_a and xRegAndUdf_uid332_z_uid95_fpArctan2Test_b;
--xIOrXRUdf_uid333_z_uid95_fpArctan2Test(LOGICAL,332)@19
xIOrXRUdf_uid333_z_uid95_fpArctan2Test_a <= exc_I_uid73_fpArctan2Test_q;
xIOrXRUdf_uid333_z_uid95_fpArctan2Test_b <= xRegAndUdf_uid332_z_uid95_fpArctan2Test_q;
xIOrXRUdf_uid333_z_uid95_fpArctan2Test_q <= xIOrXRUdf_uid333_z_uid95_fpArctan2Test_a or xIOrXRUdf_uid333_z_uid95_fpArctan2Test_b;
--excSelBits_uid334_z_uid95_fpArctan2Test(BITJOIN,333)@19
excSelBits_uid334_z_uid95_fpArctan2Test_q <= exc_N_uid311_z_uid95_fpArctan2Test_q & expXIsZero_uid68_fpArctan2Test_q & xIOrXRUdf_uid333_z_uid95_fpArctan2Test_q;
--reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0(REG,532)@19
reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_q <= excSelBits_uid334_z_uid95_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid335_z_uid95_fpArctan2Test(LOOKUP,334)@20
outMuxSelEnc_uid335_z_uid95_fpArctan2Test: PROCESS (reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid334_z_uid95_fpArctan2Test_0_to_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_q) IS
WHEN "000" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "01";
WHEN "001" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "00";
WHEN "010" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "10";
WHEN "011" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "01";
WHEN "100" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "11";
WHEN "101" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "01";
WHEN "110" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "01";
WHEN "111" => outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid337_z_uid95_fpArctan2Test(MUX,336)@20
expRPostExc_uid337_z_uid95_fpArctan2Test_s <= outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q;
expRPostExc_uid337_z_uid95_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid337_z_uid95_fpArctan2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid337_z_uid95_fpArctan2Test_s IS
WHEN "00" => expRPostExc_uid337_z_uid95_fpArctan2Test_q <= cstAllZWE_uid56_fpArctan2Test_q;
WHEN "01" => expRPostExc_uid337_z_uid95_fpArctan2Test_q <= expRCalc_uid331_z_uid95_fpArctan2Test_q;
WHEN "10" => expRPostExc_uid337_z_uid95_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN "11" => expRPostExc_uid337_z_uid95_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN OTHERS => expRPostExc_uid337_z_uid95_fpArctan2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_inputreg(DELAY,1346)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid337_z_uid95_fpArctan2Test_q, xout => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt(COUNTER,1348)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg(REG,1349)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux(MUX,1350)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_s <= en;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux: PROCESS (ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_s, ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q, ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem(DUALMEM,1347)
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ia <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_inputreg_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_aa <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdreg_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ab <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_rdmux_q;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_ia
);
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_q <= ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_iq(7 downto 0);
--oFracX_uid316_uid316_z_uid95_fpArctan2Test(BITJOIN,315)@18
oFracX_uid316_uid316_z_uid95_fpArctan2Test_q <= VCC_q & fracX_uid51_fpArctan2Test_b;
--y_uid318_z_uid95_fpArctan2Test(BITSELECT,317)@18
y_uid318_z_uid95_fpArctan2Test_in <= oFracX_uid316_uid316_z_uid95_fpArctan2Test_q(22 downto 0);
y_uid318_z_uid95_fpArctan2Test_b <= y_uid318_z_uid95_fpArctan2Test_in(22 downto 0);
--yAddr_uid320_z_uid95_fpArctan2Test(BITSELECT,319)@18
yAddr_uid320_z_uid95_fpArctan2Test_in <= y_uid318_z_uid95_fpArctan2Test_b;
yAddr_uid320_z_uid95_fpArctan2Test_b <= yAddr_uid320_z_uid95_fpArctan2Test_in(22 downto 15);
--reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0(REG,534)@18
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0_q <= yAddr_uid320_z_uid95_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid469_invTabGen_lutmem(DUALMEM,509)@19
memoryC2_uid469_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid469_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid469_invTabGen_lutmem_ab <= reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC2_uid469_invTabGen_lutmem_0_q;
memoryC2_uid469_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC2_uid469_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid469_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid469_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid469_invTabGen_lutmem_iq,
address_a => memoryC2_uid469_invTabGen_lutmem_aa,
data_a => memoryC2_uid469_invTabGen_lutmem_ia
);
memoryC2_uid469_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid469_invTabGen_lutmem_q <= memoryC2_uid469_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1(REG,536)@21
reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1_q <= memoryC2_uid469_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_inputreg(DELAY,1345)
ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid318_z_uid95_fpArctan2Test_b, xout => ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a(DELAY,881)@18
ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_inputreg_q, xout => ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid321_z_uid95_fpArctan2Test(BITSELECT,320)@21
yPPolyEval_uid321_z_uid95_fpArctan2Test_in <= ld_y_uid318_z_uid95_fpArctan2Test_b_to_yPPolyEval_uid321_z_uid95_fpArctan2Test_a_q(14 downto 0);
yPPolyEval_uid321_z_uid95_fpArctan2Test_b <= yPPolyEval_uid321_z_uid95_fpArctan2Test_in(14 downto 0);
--yT1_uid471_invPolyEval(BITSELECT,470)@21
yT1_uid471_invPolyEval_in <= yPPolyEval_uid321_z_uid95_fpArctan2Test_b;
yT1_uid471_invPolyEval_b <= yT1_uid471_invPolyEval_in(14 downto 3);
--reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0(REG,535)@21
reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0_q <= yT1_uid471_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid496_pT1_uid472_invPolyEval(MULT,495)@22
prodXY_uid496_pT1_uid472_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid496_pT1_uid472_invPolyEval_a),13)) * SIGNED(prodXY_uid496_pT1_uid472_invPolyEval_b);
prodXY_uid496_pT1_uid472_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid496_pT1_uid472_invPolyEval_a <= (others => '0');
prodXY_uid496_pT1_uid472_invPolyEval_b <= (others => '0');
prodXY_uid496_pT1_uid472_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid496_pT1_uid472_invPolyEval_a <= reg_yT1_uid471_invPolyEval_0_to_prodXY_uid496_pT1_uid472_invPolyEval_0_q;
prodXY_uid496_pT1_uid472_invPolyEval_b <= reg_memoryC2_uid469_invTabGen_lutmem_0_to_prodXY_uid496_pT1_uid472_invPolyEval_1_q;
prodXY_uid496_pT1_uid472_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid496_pT1_uid472_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid496_pT1_uid472_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid496_pT1_uid472_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid496_pT1_uid472_invPolyEval_q <= prodXY_uid496_pT1_uid472_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid497_pT1_uid472_invPolyEval(BITSELECT,496)@25
prodXYTruncFR_uid497_pT1_uid472_invPolyEval_in <= prodXY_uid496_pT1_uid472_invPolyEval_q;
prodXYTruncFR_uid497_pT1_uid472_invPolyEval_b <= prodXYTruncFR_uid497_pT1_uid472_invPolyEval_in(23 downto 11);
--highBBits_uid474_invPolyEval(BITSELECT,473)@25
highBBits_uid474_invPolyEval_in <= prodXYTruncFR_uid497_pT1_uid472_invPolyEval_b;
highBBits_uid474_invPolyEval_b <= highBBits_uid474_invPolyEval_in(12 downto 1);
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_a(DELAY,1091)@18
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid320_z_uid95_fpArctan2Test_b, xout => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0(REG,537)@21
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_q <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid467_invTabGen_lutmem(DUALMEM,508)@22
memoryC1_uid467_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid467_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid467_invTabGen_lutmem_ab <= reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC1_uid467_invTabGen_lutmem_0_q;
memoryC1_uid467_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC1_uid467_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid467_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid467_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid467_invTabGen_lutmem_iq,
address_a => memoryC1_uid467_invTabGen_lutmem_aa,
data_a => memoryC1_uid467_invTabGen_lutmem_ia
);
memoryC1_uid467_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid467_invTabGen_lutmem_q <= memoryC1_uid467_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0(REG,538)@24
reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0_q <= memoryC1_uid467_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid475_invPolyEval(ADD,474)@25
sumAHighB_uid475_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0_q(19)) & reg_memoryC1_uid467_invTabGen_lutmem_0_to_sumAHighB_uid475_invPolyEval_0_q);
sumAHighB_uid475_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid474_invPolyEval_b(11)) & highBBits_uid474_invPolyEval_b);
sumAHighB_uid475_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid475_invPolyEval_a) + SIGNED(sumAHighB_uid475_invPolyEval_b));
sumAHighB_uid475_invPolyEval_q <= sumAHighB_uid475_invPolyEval_o(20 downto 0);
--lowRangeB_uid473_invPolyEval(BITSELECT,472)@25
lowRangeB_uid473_invPolyEval_in <= prodXYTruncFR_uid497_pT1_uid472_invPolyEval_b(0 downto 0);
lowRangeB_uid473_invPolyEval_b <= lowRangeB_uid473_invPolyEval_in(0 downto 0);
--s1_uid473_uid476_invPolyEval(BITJOIN,475)@25
s1_uid473_uid476_invPolyEval_q <= sumAHighB_uid475_invPolyEval_q & lowRangeB_uid473_invPolyEval_b;
--reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1(REG,540)@25
reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1_q <= s1_uid473_uid476_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor(LOGICAL,1382)
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_a or ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena(REG,1383)
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd(LOGICAL,1384)
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0(REG,539)@21
reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q <= yPPolyEval_uid321_z_uid95_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_inputreg(DELAY,1374)
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q, xout => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem(DUALMEM,1375)
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_aa <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ab <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_iq(14 downto 0);
--prodXY_uid499_pT2_uid478_invPolyEval(MULT,498)@26
prodXY_uid499_pT2_uid478_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid499_pT2_uid478_invPolyEval_a),16)) * SIGNED(prodXY_uid499_pT2_uid478_invPolyEval_b);
prodXY_uid499_pT2_uid478_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid499_pT2_uid478_invPolyEval_a <= (others => '0');
prodXY_uid499_pT2_uid478_invPolyEval_b <= (others => '0');
prodXY_uid499_pT2_uid478_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid499_pT2_uid478_invPolyEval_a <= ld_reg_yPPolyEval_uid321_z_uid95_fpArctan2Test_0_to_prodXY_uid499_pT2_uid478_invPolyEval_0_q_to_prodXY_uid499_pT2_uid478_invPolyEval_a_replace_mem_q;
prodXY_uid499_pT2_uid478_invPolyEval_b <= reg_s1_uid473_uid476_invPolyEval_0_to_prodXY_uid499_pT2_uid478_invPolyEval_1_q;
prodXY_uid499_pT2_uid478_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid499_pT2_uid478_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid499_pT2_uid478_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid499_pT2_uid478_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid499_pT2_uid478_invPolyEval_q <= prodXY_uid499_pT2_uid478_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid500_pT2_uid478_invPolyEval(BITSELECT,499)@29
prodXYTruncFR_uid500_pT2_uid478_invPolyEval_in <= prodXY_uid499_pT2_uid478_invPolyEval_q;
prodXYTruncFR_uid500_pT2_uid478_invPolyEval_b <= prodXYTruncFR_uid500_pT2_uid478_invPolyEval_in(36 downto 14);
--highBBits_uid480_invPolyEval(BITSELECT,479)@29
highBBits_uid480_invPolyEval_in <= prodXYTruncFR_uid500_pT2_uid478_invPolyEval_b;
highBBits_uid480_invPolyEval_b <= highBBits_uid480_invPolyEval_in(22 downto 2);
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor(LOGICAL,1447)
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_a or ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena(REG,1448)
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd(LOGICAL,1449)
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_inputreg(DELAY,1437)
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid320_z_uid95_fpArctan2Test_b, xout => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem(DUALMEM,1438)
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0(REG,541)@25
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_q <= ld_yAddr_uid320_z_uid95_fpArctan2Test_b_to_reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid465_invTabGen_lutmem(DUALMEM,507)@26
memoryC0_uid465_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid465_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid465_invTabGen_lutmem_ab <= reg_yAddr_uid320_z_uid95_fpArctan2Test_0_to_memoryC0_uid465_invTabGen_lutmem_0_q;
memoryC0_uid465_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC0_uid465_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid465_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid465_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid465_invTabGen_lutmem_iq,
address_a => memoryC0_uid465_invTabGen_lutmem_aa,
data_a => memoryC0_uid465_invTabGen_lutmem_ia
);
memoryC0_uid465_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid465_invTabGen_lutmem_q <= memoryC0_uid465_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0(REG,542)@28
reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0_q <= memoryC0_uid465_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid481_invPolyEval(ADD,480)@29
sumAHighB_uid481_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0_q(28)) & reg_memoryC0_uid465_invTabGen_lutmem_0_to_sumAHighB_uid481_invPolyEval_0_q);
sumAHighB_uid481_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid480_invPolyEval_b(20)) & highBBits_uid480_invPolyEval_b);
sumAHighB_uid481_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid481_invPolyEval_a) + SIGNED(sumAHighB_uid481_invPolyEval_b));
sumAHighB_uid481_invPolyEval_q <= sumAHighB_uid481_invPolyEval_o(29 downto 0);
--lowRangeB_uid479_invPolyEval(BITSELECT,478)@29
lowRangeB_uid479_invPolyEval_in <= prodXYTruncFR_uid500_pT2_uid478_invPolyEval_b(1 downto 0);
lowRangeB_uid479_invPolyEval_b <= lowRangeB_uid479_invPolyEval_in(1 downto 0);
--s2_uid479_uid482_invPolyEval(BITJOIN,481)@29
s2_uid479_uid482_invPolyEval_q <= sumAHighB_uid481_invPolyEval_q & lowRangeB_uid479_invPolyEval_b;
--fxpInverseRes_uid323_z_uid95_fpArctan2Test(BITSELECT,322)@29
fxpInverseRes_uid323_z_uid95_fpArctan2Test_in <= s2_uid479_uid482_invPolyEval_q(28 downto 0);
fxpInverseRes_uid323_z_uid95_fpArctan2Test_b <= fxpInverseRes_uid323_z_uid95_fpArctan2Test_in(28 downto 5);
--fxpInverseResFrac_uid329_z_uid95_fpArctan2Test(BITSELECT,328)@29
fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_in <= fxpInverseRes_uid323_z_uid95_fpArctan2Test_b(22 downto 0);
fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_b <= fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_in(22 downto 0);
--ld_fracXIsZero_uid317_z_uid95_fpArctan2Test_q_to_fracRCalc_uid330_z_uid95_fpArctan2Test_b(DELAY,889)@19
ld_fracXIsZero_uid317_z_uid95_fpArctan2Test_q_to_fracRCalc_uid330_z_uid95_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => fracXIsZero_uid317_z_uid95_fpArctan2Test_q, xout => ld_fracXIsZero_uid317_z_uid95_fpArctan2Test_q_to_fracRCalc_uid330_z_uid95_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid330_z_uid95_fpArctan2Test(MUX,329)@29
fracRCalc_uid330_z_uid95_fpArctan2Test_s <= ld_fracXIsZero_uid317_z_uid95_fpArctan2Test_q_to_fracRCalc_uid330_z_uid95_fpArctan2Test_b_q;
fracRCalc_uid330_z_uid95_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid330_z_uid95_fpArctan2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid330_z_uid95_fpArctan2Test_s IS
WHEN "0" => fracRCalc_uid330_z_uid95_fpArctan2Test_q <= fxpInverseResFrac_uid329_z_uid95_fpArctan2Test_b;
WHEN "1" => fracRCalc_uid330_z_uid95_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN OTHERS => fracRCalc_uid330_z_uid95_fpArctan2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1(REG,543)@20
reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q <= outMuxSelEnc_uid335_z_uid95_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_b(DELAY,902)@21
ld_reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q, xout => ld_reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid336_z_uid95_fpArctan2Test(MUX,335)@30
fracRPostExc_uid336_z_uid95_fpArctan2Test_s <= ld_reg_outMuxSelEnc_uid335_z_uid95_fpArctan2Test_0_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_1_q_to_fracRPostExc_uid336_z_uid95_fpArctan2Test_b_q;
fracRPostExc_uid336_z_uid95_fpArctan2Test: PROCESS (fracRPostExc_uid336_z_uid95_fpArctan2Test_s, en, cstAllZWF_uid7_fpArctan2Test_q, fracRCalc_uid330_z_uid95_fpArctan2Test_q, cstAllZWF_uid7_fpArctan2Test_q, cstNaNWF_uid55_fpArctan2Test_q)
BEGIN
CASE fracRPostExc_uid336_z_uid95_fpArctan2Test_s IS
WHEN "00" => fracRPostExc_uid336_z_uid95_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "01" => fracRPostExc_uid336_z_uid95_fpArctan2Test_q <= fracRCalc_uid330_z_uid95_fpArctan2Test_q;
WHEN "10" => fracRPostExc_uid336_z_uid95_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "11" => fracRPostExc_uid336_z_uid95_fpArctan2Test_q <= cstNaNWF_uid55_fpArctan2Test_q;
WHEN OTHERS => fracRPostExc_uid336_z_uid95_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid340_z_uid95_fpArctan2Test(BITJOIN,339)@30
R_uid340_z_uid95_fpArctan2Test_q <= ld_signR_uid339_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_c_q & ld_expRPostExc_uid337_z_uid95_fpArctan2Test_q_to_R_uid340_z_uid95_fpArctan2Test_b_replace_mem_q & fracRPostExc_uid336_z_uid95_fpArctan2Test_q;
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor(LOGICAL,1190)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_b <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_q <= not (ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_a or ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_b);
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena(REG,1191)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_nor_q = "1") THEN
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd(LOGICAL,1192)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_a <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_sticky_ena_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_b <= en;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_a and ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_b;
--reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2(REG,547)@18
reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q <= divR_uid288_div_uid49_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_inputreg(DELAY,1180)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q, xout => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem(DUALMEM,1181)
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ia <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_inputreg_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_aa <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdreg_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ab <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_rdmux_q;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 9,
width_b => 32,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_iq,
address_a => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_aa,
data_a => ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_ia
);
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_iq(31 downto 0);
--path2_uid94_fpArctan2Test(COMPARE,93)@19
path2_uid94_fpArctan2Test_cin <= GND_q;
path2_uid94_fpArctan2Test_a <= STD_LOGIC_VECTOR("00" & reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q) & '0';
path2_uid94_fpArctan2Test_b <= STD_LOGIC_VECTOR("00" & cstBias_uid57_fpArctan2Test_q) & path2_uid94_fpArctan2Test_cin(0);
path2_uid94_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid94_fpArctan2Test_a) - UNSIGNED(path2_uid94_fpArctan2Test_b));
path2_uid94_fpArctan2Test_n(0) <= not path2_uid94_fpArctan2Test_o(10);
--reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1(REG,546)@19
reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q <= path2_uid94_fpArctan2Test_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q_to_u_uid96_fpArctan2Test_b(DELAY,651)@20
ld_reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q_to_u_uid96_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q, xout => ld_reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q_to_u_uid96_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid96_fpArctan2Test(MUX,95)@30
u_uid96_fpArctan2Test_s <= ld_reg_path2_uid94_fpArctan2Test_2_to_u_uid96_fpArctan2Test_1_q_to_u_uid96_fpArctan2Test_b_q;
u_uid96_fpArctan2Test: PROCESS (u_uid96_fpArctan2Test_s, en, ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_q, R_uid340_z_uid95_fpArctan2Test_q)
BEGIN
CASE u_uid96_fpArctan2Test_s IS
WHEN "0" => u_uid96_fpArctan2Test_q <= ld_reg_divR_uid288_div_uid49_fpArctan2Test_0_to_u_uid96_fpArctan2Test_2_q_to_u_uid96_fpArctan2Test_c_replace_mem_q;
WHEN "1" => u_uid96_fpArctan2Test_q <= R_uid340_z_uid95_fpArctan2Test_q;
WHEN OTHERS => u_uid96_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid98_fpArctan2Test(BITSELECT,97)@30
fracU_uid98_fpArctan2Test_in <= u_uid96_fpArctan2Test_q(22 downto 0);
fracU_uid98_fpArctan2Test_b <= fracU_uid98_fpArctan2Test_in(22 downto 0);
--ld_fracU_uid98_fpArctan2Test_b_to_oFracU_uid99_uid99_fpArctan2Test_a(DELAY,656)@30
ld_fracU_uid98_fpArctan2Test_b_to_oFracU_uid99_uid99_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid98_fpArctan2Test_b, xout => ld_fracU_uid98_fpArctan2Test_b_to_oFracU_uid99_uid99_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid99_uid99_fpArctan2Test(BITJOIN,98)@31
oFracU_uid99_uid99_fpArctan2Test_q <= VCC_q & ld_fracU_uid98_fpArctan2Test_b_to_oFracU_uid99_uid99_fpArctan2Test_a_q;
--oFracUExt_uid108_fpArctan2Test(BITJOIN,107)@31
oFracUExt_uid108_fpArctan2Test_q <= cst01pWShift_uid107_fpArctan2Test_q & oFracU_uid99_uid99_fpArctan2Test_q;
--X24dto0_uid350_fxpU_uid110_fpArctan2Test(BITSELECT,349)@31
X24dto0_uid350_fxpU_uid110_fpArctan2Test_in <= oFracUExt_uid108_fpArctan2Test_q(24 downto 0);
X24dto0_uid350_fxpU_uid110_fpArctan2Test_b <= X24dto0_uid350_fxpU_uid110_fpArctan2Test_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid349_fxpU_uid110_fpArctan2Test(CONSTANT,348)
leftShiftStage0Idx3Pad12_uid349_fxpU_uid110_fpArctan2Test_q <= "000000000000";
--leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test(BITJOIN,350)@31
leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_q <= X24dto0_uid350_fxpU_uid110_fpArctan2Test_b & leftShiftStage0Idx3Pad12_uid349_fxpU_uid110_fpArctan2Test_q;
--reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5(REG,557)@31
reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5_q <= leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid347_fxpU_uid110_fpArctan2Test(BITSELECT,346)@31
X28dto0_uid347_fxpU_uid110_fpArctan2Test_in <= oFracUExt_uid108_fpArctan2Test_q(28 downto 0);
X28dto0_uid347_fxpU_uid110_fpArctan2Test_b <= X28dto0_uid347_fxpU_uid110_fpArctan2Test_in(28 downto 0);
--leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test(BITJOIN,347)@31
leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_q <= X28dto0_uid347_fxpU_uid110_fpArctan2Test_b & cstAllZWE_uid56_fpArctan2Test_q;
--reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4(REG,556)@31
reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4_q <= leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid344_fxpU_uid110_fpArctan2Test(BITSELECT,343)@31
X32dto0_uid344_fxpU_uid110_fpArctan2Test_in <= oFracUExt_uid108_fpArctan2Test_q(32 downto 0);
X32dto0_uid344_fxpU_uid110_fpArctan2Test_b <= X32dto0_uid344_fxpU_uid110_fpArctan2Test_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test(CONSTANT,342)
leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test_q <= "0000";
--leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test(BITJOIN,344)@31
leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_q <= X32dto0_uid344_fxpU_uid110_fpArctan2Test_b & leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test_q;
--reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3(REG,555)@31
reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3_q <= leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2(REG,554)@31
reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2_q <= oFracUExt_uid108_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--zS_uid105_fpArctan2Test(CONSTANT,104)
zS_uid105_fpArctan2Test_q <= "000000000";
--shiftBias_uid102_fpArctan2Test(CONSTANT,101)
shiftBias_uid102_fpArctan2Test_q <= "01110010";
--expU_uid97_fpArctan2Test(BITSELECT,96)@30
expU_uid97_fpArctan2Test_in <= u_uid96_fpArctan2Test_q(30 downto 0);
expU_uid97_fpArctan2Test_b <= expU_uid97_fpArctan2Test_in(30 downto 23);
--reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1(REG,548)@30
reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q <= expU_uid97_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid103_fpArctan2Test(SUB,102)@31
shiftValue_uid103_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q);
shiftValue_uid103_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid102_fpArctan2Test_q);
shiftValue_uid103_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid103_fpArctan2Test_a) - UNSIGNED(shiftValue_uid103_fpArctan2Test_b));
shiftValue_uid103_fpArctan2Test_q <= shiftValue_uid103_fpArctan2Test_o(8 downto 0);
--ShiftValue8_uid104_fpArctan2Test(BITSELECT,103)@31
ShiftValue8_uid104_fpArctan2Test_in <= shiftValue_uid103_fpArctan2Test_q;
ShiftValue8_uid104_fpArctan2Test_b <= ShiftValue8_uid104_fpArctan2Test_in(8 downto 8);
--shiftValuePostNeg_uid106_fpArctan2Test(MUX,105)@31
shiftValuePostNeg_uid106_fpArctan2Test_s <= ShiftValue8_uid104_fpArctan2Test_b;
shiftValuePostNeg_uid106_fpArctan2Test: PROCESS (shiftValuePostNeg_uid106_fpArctan2Test_s, en, shiftValue_uid103_fpArctan2Test_q, zS_uid105_fpArctan2Test_q)
BEGIN
CASE shiftValuePostNeg_uid106_fpArctan2Test_s IS
WHEN "0" => shiftValuePostNeg_uid106_fpArctan2Test_q <= shiftValue_uid103_fpArctan2Test_q;
WHEN "1" => shiftValuePostNeg_uid106_fpArctan2Test_q <= zS_uid105_fpArctan2Test_q;
WHEN OTHERS => shiftValuePostNeg_uid106_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid109_fpArctan2Test(BITSELECT,108)@31
fxpShifterBits_uid109_fpArctan2Test_in <= shiftValuePostNeg_uid106_fpArctan2Test_q(3 downto 0);
fxpShifterBits_uid109_fpArctan2Test_b <= fxpShifterBits_uid109_fpArctan2Test_in(3 downto 0);
--leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test(BITSELECT,351)@31
leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_in <= fxpShifterBits_uid109_fpArctan2Test_b;
leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_b <= leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1(REG,553)@31
reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1_q <= leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test(MUX,352)@32
leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_s <= reg_leftShiftStageSel3Dto2_uid352_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_1_q;
leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test: PROCESS (leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_s, en, reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2_q, reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3_q, reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4_q, reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5_q)
BEGIN
CASE leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_s IS
WHEN "00" => leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q <= reg_oFracUExt_uid108_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_2_q;
WHEN "01" => leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q <= reg_leftShiftStage0Idx1_uid345_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_3_q;
WHEN "10" => leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q <= reg_leftShiftStage0Idx2_uid348_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_4_q;
WHEN "11" => leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q <= reg_leftShiftStage0Idx3_uid351_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_5_q;
WHEN OTHERS => leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test(BITSELECT,360)@32
LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_in <= leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q(33 downto 0);
LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b <= LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_b(DELAY,928)@32
ld_LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b, xout => ld_LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid360_fxpU_uid110_fpArctan2Test(CONSTANT,359)
leftShiftStage1Idx3Pad3_uid360_fxpU_uid110_fpArctan2Test_q <= "000";
--leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test(BITJOIN,361)@33
leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_q <= ld_LeftShiftStage033dto0_uid361_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_b_q & leftShiftStage1Idx3Pad3_uid360_fxpU_uid110_fpArctan2Test_q;
--LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test(BITSELECT,357)@32
LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_in <= leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q(34 downto 0);
LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b <= LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_b(DELAY,926)@32
ld_LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b, xout => ld_LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test(BITJOIN,358)@33
leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_q <= ld_LeftShiftStage034dto0_uid358_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_b_q & z_uid243_div_uid49_fpArctan2Test_q;
--LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test(BITSELECT,354)@32
LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_in <= leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q(35 downto 0);
LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b <= LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_b(DELAY,924)@32
ld_LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b, xout => ld_LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test(BITJOIN,355)@33
leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_q <= ld_LeftShiftStage035dto0_uid355_fxpU_uid110_fpArctan2Test_b_to_leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_b_q & GND_q;
--reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2(REG,559)@32
reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2_q <= leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test(BITSELECT,362)@31
leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_in <= fxpShifterBits_uid109_fpArctan2Test_b(1 downto 0);
leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_b <= leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1(REG,558)@31
reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q <= leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_b(DELAY,930)@32
ld_reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test(MUX,363)@33
leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_s <= ld_reg_leftShiftStageSel1Dto0_uid363_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_1_q_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_b_q;
leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test: PROCESS (leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_s, en, reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2_q, leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_q, leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_q, leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_q)
BEGIN
CASE leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_s IS
WHEN "00" => leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q <= reg_leftShiftStage0_uid353_fxpU_uid110_fpArctan2Test_0_to_leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_2_q;
WHEN "01" => leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q <= leftShiftStage1Idx1_uid356_fxpU_uid110_fpArctan2Test_q;
WHEN "10" => leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q <= leftShiftStage1Idx2_uid359_fxpU_uid110_fpArctan2Test_q;
WHEN "11" => leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q <= leftShiftStage1Idx3_uid362_fxpU_uid110_fpArctan2Test_q;
WHEN OTHERS => leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid111_fpArctan2Test(BITSELECT,110)@33
y_uid111_fpArctan2Test_in <= leftShiftStage1_uid364_fxpU_uid110_fpArctan2Test_q(35 downto 0);
y_uid111_fpArctan2Test_b <= y_uid111_fpArctan2Test_in(35 downto 1);
--yAddr_uid113_fpArctan2Test(BITSELECT,112)@33
yAddr_uid113_fpArctan2Test_in <= y_uid111_fpArctan2Test_b;
yAddr_uid113_fpArctan2Test_b <= yAddr_uid113_fpArctan2Test_in(34 downto 27);
--reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0(REG,560)@33
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0_q <= yAddr_uid113_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid370_atanXOXTabGen_lutmem(DUALMEM,503)@34
memoryC2_uid370_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid370_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid370_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0_q;
memoryC2_uid370_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC2_uid370_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid370_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid370_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid370_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid370_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid370_atanXOXTabGen_lutmem_ia
);
memoryC2_uid370_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid370_atanXOXTabGen_lutmem_q <= memoryC2_uid370_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1(REG,562)@36
reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1_q <= memoryC2_uid370_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid114_fpArctan2Test(BITSELECT,113)@33
yPPolyEval_uid114_fpArctan2Test_in <= y_uid111_fpArctan2Test_b(26 downto 0);
yPPolyEval_uid114_fpArctan2Test_b <= yPPolyEval_uid114_fpArctan2Test_in(26 downto 9);
--yT1_uid372_atanXOXPolyEval(BITSELECT,371)@33
yT1_uid372_atanXOXPolyEval_in <= yPPolyEval_uid114_fpArctan2Test_b;
yT1_uid372_atanXOXPolyEval_b <= yT1_uid372_atanXOXPolyEval_in(17 downto 5);
--reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0(REG,561)@33
reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q <= yT1_uid372_atanXOXPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_inputreg(DELAY,1359)
ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q, xout => ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a(DELAY,1037)@34
ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid484_pT1_uid373_atanXOXPolyEval(MULT,483)@37
prodXY_uid484_pT1_uid373_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid373_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid484_pT1_uid373_atanXOXPolyEval_b);
prodXY_uid484_pT1_uid373_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid373_atanXOXPolyEval_a <= (others => '0');
prodXY_uid484_pT1_uid373_atanXOXPolyEval_b <= (others => '0');
prodXY_uid484_pT1_uid373_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid373_atanXOXPolyEval_a <= ld_reg_yT1_uid372_atanXOXPolyEval_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_0_q_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_a_q;
prodXY_uid484_pT1_uid373_atanXOXPolyEval_b <= reg_memoryC2_uid370_atanXOXTabGen_lutmem_0_to_prodXY_uid484_pT1_uid373_atanXOXPolyEval_1_q;
prodXY_uid484_pT1_uid373_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid373_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid373_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid373_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid373_atanXOXPolyEval_q <= prodXY_uid484_pT1_uid373_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval(BITSELECT,484)@40
prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_in <= prodXY_uid484_pT1_uid373_atanXOXPolyEval_q;
prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_b <= prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid375_atanXOXPolyEval(BITSELECT,374)@40
highBBits_uid375_atanXOXPolyEval_in <= prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_b;
highBBits_uid375_atanXOXPolyEval_b <= highBBits_uid375_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid113_fpArctan2Test_b_to_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_a(DELAY,1117)@33
ld_yAddr_uid113_fpArctan2Test_b_to_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid113_fpArctan2Test_b, xout => ld_yAddr_uid113_fpArctan2Test_b_to_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0(REG,563)@36
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid113_fpArctan2Test_b_to_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid368_atanXOXTabGen_lutmem(DUALMEM,502)@37
memoryC1_uid368_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid368_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid368_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid113_fpArctan2Test_0_to_memoryC1_uid368_atanXOXTabGen_lutmem_0_q;
memoryC1_uid368_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC1_uid368_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid368_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid368_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid368_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid368_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid368_atanXOXTabGen_lutmem_ia
);
memoryC1_uid368_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid368_atanXOXTabGen_lutmem_q <= memoryC1_uid368_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0(REG,564)@39
reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0_q <= memoryC1_uid368_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid376_atanXOXPolyEval(ADD,375)@40
sumAHighB_uid376_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid368_atanXOXTabGen_lutmem_0_to_sumAHighB_uid376_atanXOXPolyEval_0_q);
sumAHighB_uid376_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid375_atanXOXPolyEval_b(12)) & highBBits_uid375_atanXOXPolyEval_b);
sumAHighB_uid376_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid376_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid376_atanXOXPolyEval_b));
sumAHighB_uid376_atanXOXPolyEval_q <= sumAHighB_uid376_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid374_atanXOXPolyEval(BITSELECT,373)@40
lowRangeB_uid374_atanXOXPolyEval_in <= prodXYTruncFR_uid485_pT1_uid373_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid374_atanXOXPolyEval_b <= lowRangeB_uid374_atanXOXPolyEval_in(0 downto 0);
--s1_uid374_uid377_atanXOXPolyEval(BITJOIN,376)@40
s1_uid374_uid377_atanXOXPolyEval_q <= sumAHighB_uid376_atanXOXPolyEval_q & lowRangeB_uid374_atanXOXPolyEval_b;
--reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1(REG,566)@40
reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1_q <= s1_uid374_uid377_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor(LOGICAL,1370)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena(REG,1371)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd(LOGICAL,1372)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0(REG,565)@33
reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q <= yPPolyEval_uid114_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_inputreg(DELAY,1360)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem(DUALMEM,1361)
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid487_pT2_uid379_atanXOXPolyEval(MULT,486)@41
prodXY_uid487_pT2_uid379_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid379_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid487_pT2_uid379_atanXOXPolyEval_b);
prodXY_uid487_pT2_uid379_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid379_atanXOXPolyEval_a <= (others => '0');
prodXY_uid487_pT2_uid379_atanXOXPolyEval_b <= (others => '0');
prodXY_uid487_pT2_uid379_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid379_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid487_pT2_uid379_atanXOXPolyEval_b <= reg_s1_uid374_uid377_atanXOXPolyEval_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_1_q;
prodXY_uid487_pT2_uid379_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid379_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid379_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid379_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid379_atanXOXPolyEval_q <= prodXY_uid487_pT2_uid379_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval(BITSELECT,487)@44
prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_in <= prodXY_uid487_pT2_uid379_atanXOXPolyEval_q;
prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_b <= prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid381_atanXOXPolyEval(BITSELECT,380)@44
highBBits_uid381_atanXOXPolyEval_in <= prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_b;
highBBits_uid381_atanXOXPolyEval_b <= highBBits_uid381_atanXOXPolyEval_in(23 downto 2);
--ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor(LOGICAL,1395)
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_b);
--ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena(REG,1396)
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd(LOGICAL,1397)
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_inputreg(DELAY,1385)
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid113_fpArctan2Test_0_to_memoryC2_uid370_atanXOXTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem(DUALMEM,1386)
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid114_fpArctan2Test_0_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_0_q_to_prodXY_uid487_pT2_uid379_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid366_atanXOXTabGen_lutmem(DUALMEM,501)@41
memoryC0_uid366_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid366_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid366_atanXOXTabGen_lutmem_ab <= ld_reg_yAddr_uid113_fpArctan2Test_0_to_memoryC0_uid366_atanXOXTabGen_lutmem_0_q_to_memoryC0_uid366_atanXOXTabGen_lutmem_a_replace_mem_q;
memoryC0_uid366_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan2_s5_memoryC0_uid366_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid366_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid366_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid366_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid366_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid366_atanXOXTabGen_lutmem_ia
);
memoryC0_uid366_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid366_atanXOXTabGen_lutmem_q <= memoryC0_uid366_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0(REG,568)@43
reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0_q <= memoryC0_uid366_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid382_atanXOXPolyEval(ADD,381)@44
sumAHighB_uid382_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid366_atanXOXTabGen_lutmem_0_to_sumAHighB_uid382_atanXOXPolyEval_0_q);
sumAHighB_uid382_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid381_atanXOXPolyEval_b(21)) & highBBits_uid381_atanXOXPolyEval_b);
sumAHighB_uid382_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid382_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid382_atanXOXPolyEval_b));
sumAHighB_uid382_atanXOXPolyEval_q <= sumAHighB_uid382_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid380_atanXOXPolyEval(BITSELECT,379)@44
lowRangeB_uid380_atanXOXPolyEval_in <= prodXYTruncFR_uid488_pT2_uid379_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid380_atanXOXPolyEval_b <= lowRangeB_uid380_atanXOXPolyEval_in(1 downto 0);
--s2_uid380_uid383_atanXOXPolyEval(BITJOIN,382)@44
s2_uid380_uid383_atanXOXPolyEval_q <= sumAHighB_uid382_atanXOXPolyEval_q & lowRangeB_uid380_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid116_fpArctan2Test(BITSELECT,115)@44
fxpAtanXOXRes_uid116_fpArctan2Test_in <= s2_uid380_uid383_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid116_fpArctan2Test_b <= fxpAtanXOXRes_uid116_fpArctan2Test_in(31 downto 5);
--reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1(REG,570)@44
reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1_q <= fxpAtanXOXRes_uid116_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor(LOGICAL,1473)
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_b <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_q <= not (ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_a or ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_b);
--ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena(REG,1474)
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_nor_q = "1") THEN
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd(LOGICAL,1475)
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_a <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_sticky_ena_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_b <= en;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_q <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_a and ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_b;
--ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_inputreg(DELAY,1463)
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracU_uid99_uid99_fpArctan2Test_q, xout => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem(DUALMEM,1464)
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ia <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_inputreg_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_aa <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdreg_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ab <= ld_expXmY_uid232_div_uid49_fpArctan2Test_q_to_expR_uid233_div_uid49_fpArctan2Test_a_replace_rdmux_q;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_iq,
address_a => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_aa,
data_a => ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_ia
);
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_reset0 <= areset;
ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_q <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_iq(23 downto 0);
--reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0(REG,569)@44
reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_q <= ld_oFracU_uid99_uid99_fpArctan2Test_q_to_reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulXAtanXOXRes_uid117_fpArctan2Test(MULT,116)@45
mulXAtanXOXRes_uid117_fpArctan2Test_pr <= UNSIGNED(mulXAtanXOXRes_uid117_fpArctan2Test_a) * UNSIGNED(mulXAtanXOXRes_uid117_fpArctan2Test_b);
mulXAtanXOXRes_uid117_fpArctan2Test_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid117_fpArctan2Test_a <= (others => '0');
mulXAtanXOXRes_uid117_fpArctan2Test_b <= (others => '0');
mulXAtanXOXRes_uid117_fpArctan2Test_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid117_fpArctan2Test_a <= reg_oFracU_uid99_uid99_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_0_q;
mulXAtanXOXRes_uid117_fpArctan2Test_b <= reg_fxpAtanXOXRes_uid116_fpArctan2Test_0_to_mulXAtanXOXRes_uid117_fpArctan2Test_1_q;
mulXAtanXOXRes_uid117_fpArctan2Test_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid117_fpArctan2Test_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid117_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid117_fpArctan2Test_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid117_fpArctan2Test_q <= mulXAtanXOXRes_uid117_fpArctan2Test_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid118_fpArctan2Test(BITSELECT,117)@48
normBit_uid118_fpArctan2Test_in <= mulXAtanXOXRes_uid117_fpArctan2Test_q(49 downto 0);
normBit_uid118_fpArctan2Test_b <= normBit_uid118_fpArctan2Test_in(49 downto 49);
--InvNormBit_uid122_fpArctan2Test(LOGICAL,121)@48
InvNormBit_uid122_fpArctan2Test_a <= normBit_uid118_fpArctan2Test_b;
InvNormBit_uid122_fpArctan2Test_q <= not InvNormBit_uid122_fpArctan2Test_a;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor(LOGICAL,1203)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_b <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_q <= not (ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_a or ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_b);
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_mem_top(CONSTANT,1199)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_mem_top_q <= "01111";
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp(LOGICAL,1200)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_a <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_mem_top_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q);
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_q <= "1" when ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_a = ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_b else "0";
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg(REG,1201)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena(REG,1204)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_nor_q = "1") THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd(LOGICAL,1205)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_a <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_sticky_ena_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_b <= en;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_a and ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_b;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_inputreg(DELAY,1193)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid97_fpArctan2Test_b, xout => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt(COUNTER,1195)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_i <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_i,4));
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg(REG,1196)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux(MUX,1197)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_s <= en;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux: PROCESS (ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_s, ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q, ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem(DUALMEM,1194)
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ia <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_inputreg_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_aa <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdreg_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ab <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_rdmux_q;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_iq,
address_a => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_aa,
data_a => ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_ia
);
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_reset0 <= areset;
ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_q <= ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid123_fpArctan2Test(SUB,122)@48
expRPath3Ext_uid123_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid97_fpArctan2Test_b_to_expRPath3Ext_uid123_fpArctan2Test_a_replace_mem_q);
expRPath3Ext_uid123_fpArctan2Test_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid122_fpArctan2Test_q);
expRPath3Ext_uid123_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid123_fpArctan2Test_a) - UNSIGNED(expRPath3Ext_uid123_fpArctan2Test_b));
expRPath3Ext_uid123_fpArctan2Test_q <= expRPath3Ext_uid123_fpArctan2Test_o(8 downto 0);
--expRPath3PreRnd_uid124_fpArctan2Test(BITSELECT,123)@48
expRPath3PreRnd_uid124_fpArctan2Test_in <= expRPath3Ext_uid123_fpArctan2Test_q(7 downto 0);
expRPath3PreRnd_uid124_fpArctan2Test_b <= expRPath3PreRnd_uid124_fpArctan2Test_in(7 downto 0);
--fracRPath3High_uid119_fpArctan2Test(BITSELECT,118)@48
fracRPath3High_uid119_fpArctan2Test_in <= mulXAtanXOXRes_uid117_fpArctan2Test_q(48 downto 0);
fracRPath3High_uid119_fpArctan2Test_b <= fracRPath3High_uid119_fpArctan2Test_in(48 downto 25);
--fracRPath3Low_uid120_fpArctan2Test(BITSELECT,119)@48
fracRPath3Low_uid120_fpArctan2Test_in <= mulXAtanXOXRes_uid117_fpArctan2Test_q(47 downto 0);
fracRPath3Low_uid120_fpArctan2Test_b <= fracRPath3Low_uid120_fpArctan2Test_in(47 downto 24);
--fracRPath3Pre_uid121_fpArctan2Test(MUX,120)@48
fracRPath3Pre_uid121_fpArctan2Test_s <= normBit_uid118_fpArctan2Test_b;
fracRPath3Pre_uid121_fpArctan2Test: PROCESS (fracRPath3Pre_uid121_fpArctan2Test_s, en, fracRPath3Low_uid120_fpArctan2Test_b, fracRPath3High_uid119_fpArctan2Test_b)
BEGIN
CASE fracRPath3Pre_uid121_fpArctan2Test_s IS
WHEN "0" => fracRPath3Pre_uid121_fpArctan2Test_q <= fracRPath3Low_uid120_fpArctan2Test_b;
WHEN "1" => fracRPath3Pre_uid121_fpArctan2Test_q <= fracRPath3High_uid119_fpArctan2Test_b;
WHEN OTHERS => fracRPath3Pre_uid121_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRPath3PreRnd_uid125_uid125_fpArctan2Test(BITJOIN,124)@48
expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_q <= expRPath3PreRnd_uid124_fpArctan2Test_b & fracRPath3Pre_uid121_fpArctan2Test_q;
--reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0(REG,578)@48
reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0_q <= expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--fracRPath3PostRnd_uid126_fpArctan2Test(ADD,125)@49
fracRPath3PostRnd_uid126_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & reg_expFracRPath3PreRnd_uid125_uid125_fpArctan2Test_0_to_fracRPath3PostRnd_uid126_fpArctan2Test_0_q);
fracRPath3PostRnd_uid126_fpArctan2Test_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
fracRPath3PostRnd_uid126_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(fracRPath3PostRnd_uid126_fpArctan2Test_a) + UNSIGNED(fracRPath3PostRnd_uid126_fpArctan2Test_b));
fracRPath3PostRnd_uid126_fpArctan2Test_q <= fracRPath3PostRnd_uid126_fpArctan2Test_o(32 downto 0);
--fracRPath3_uid127_fpArctan2Test(BITSELECT,126)@49
fracRPath3_uid127_fpArctan2Test_in <= fracRPath3PostRnd_uid126_fpArctan2Test_q(23 downto 0);
fracRPath3_uid127_fpArctan2Test_b <= fracRPath3_uid127_fpArctan2Test_in(23 downto 1);
--reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4(REG,583)@49
reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q <= fracRPath3_uid127_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_inputreg(DELAY,1206)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q, xout => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem(DUALMEM,1207)
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ia <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_inputreg_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_aa <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdreg_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ab <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_rdmux_q;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_ia
);
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_iq(22 downto 0);
--RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,407)@51
RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_in <= rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q;
RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_b <= RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 1);
--rightShiftStage2Idx1_uid410_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,409)@51
rightShiftStage2Idx1_uid410_fxpOp2Path2_uid135_fpArctan2Test_q <= GND_q & RightShiftStage124dto1_uid408_fxpOp2Path2_uid135_fpArctan2Test_b;
--X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,391)@50
X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_in <= oFracRPath2_uid133_uid133_fpArctan2Test_q;
X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_b <= X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 24);
--rightShiftStage0Idx3_uid394_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,393)@50
rightShiftStage0Idx3_uid394_fxpOp2Path2_uid135_fpArctan2Test_q <= padConst_uid161_fpArctan2Test_q & X24dto24_uid392_fxpOp2Path2_uid135_fpArctan2Test_b;
--X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,388)@50
X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_in <= oFracRPath2_uid133_uid133_fpArctan2Test_q;
X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_b <= X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 16);
--rightShiftStage0Idx2_uid391_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,390)@50
rightShiftStage0Idx2_uid391_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage0Idx2Pad16_uid390_fxpOp2Path2_uid135_fpArctan2Test_q & X24dto16_uid389_fxpOp2Path2_uid135_fpArctan2Test_b;
--X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,385)@50
X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_in <= oFracRPath2_uid133_uid133_fpArctan2Test_q;
X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_b <= X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 8);
--rightShiftStage0Idx1_uid388_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,387)@50
rightShiftStage0Idx1_uid388_fxpOp2Path2_uid135_fpArctan2Test_q <= cstAllZWE_uid56_fpArctan2Test_q & X24dto8_uid386_fxpOp2Path2_uid135_fpArctan2Test_b;
--ld_fracRPath3Pre_uid121_fpArctan2Test_q_to_oFracRPath2_uid133_uid133_fpArctan2Test_a(DELAY,690)@48
ld_fracRPath3Pre_uid121_fpArctan2Test_q_to_oFracRPath2_uid133_uid133_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid121_fpArctan2Test_q, xout => ld_fracRPath3Pre_uid121_fpArctan2Test_q_to_oFracRPath2_uid133_uid133_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid133_uid133_fpArctan2Test(BITJOIN,132)@50
oFracRPath2_uid133_uid133_fpArctan2Test_q <= VCC_q & ld_fracRPath3Pre_uid121_fpArctan2Test_q_to_oFracRPath2_uid133_uid133_fpArctan2Test_a_q;
--cstWFP2_uid62_fpArctan2Test(CONSTANT,61)
cstWFP2_uid62_fpArctan2Test_q <= "00011001";
--reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1(REG,571)@48
reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1_q <= expRPath3PreRnd_uid124_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid129_fpArctan2Test(SUB,128)@49
shiftValPath2PreSub_uid129_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & cstBias_uid57_fpArctan2Test_q);
shiftValPath2PreSub_uid129_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & reg_expRPath3PreRnd_uid124_fpArctan2Test_0_to_shiftValPath2PreSub_uid129_fpArctan2Test_1_q);
shiftValPath2PreSub_uid129_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValPath2PreSub_uid129_fpArctan2Test_a) - UNSIGNED(shiftValPath2PreSub_uid129_fpArctan2Test_b));
shiftValPath2PreSub_uid129_fpArctan2Test_q <= shiftValPath2PreSub_uid129_fpArctan2Test_o(8 downto 0);
--shiftValPath2PreSubR_uid131_fpArctan2Test(BITSELECT,130)@49
shiftValPath2PreSubR_uid131_fpArctan2Test_in <= shiftValPath2PreSub_uid129_fpArctan2Test_q(7 downto 0);
shiftValPath2PreSubR_uid131_fpArctan2Test_b <= shiftValPath2PreSubR_uid131_fpArctan2Test_in(7 downto 0);
--cstBiasMWF_uid59_fpArctan2Test(CONSTANT,58)
cstBiasMWF_uid59_fpArctan2Test_q <= "01101000";
--shiftOut_uid130_fpArctan2Test(COMPARE,129)@31
shiftOut_uid130_fpArctan2Test_cin <= GND_q;
shiftOut_uid130_fpArctan2Test_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q) & '0';
shiftOut_uid130_fpArctan2Test_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid59_fpArctan2Test_q) & shiftOut_uid130_fpArctan2Test_cin(0);
shiftOut_uid130_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid130_fpArctan2Test_a) - UNSIGNED(shiftOut_uid130_fpArctan2Test_b));
shiftOut_uid130_fpArctan2Test_c(0) <= shiftOut_uid130_fpArctan2Test_o(10);
--ld_shiftOut_uid130_fpArctan2Test_c_to_sValPostSOut_uid132_fpArctan2Test_b(DELAY,688)@31
ld_shiftOut_uid130_fpArctan2Test_c_to_sValPostSOut_uid132_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid130_fpArctan2Test_c, xout => ld_shiftOut_uid130_fpArctan2Test_c_to_sValPostSOut_uid132_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid132_fpArctan2Test(MUX,131)@49
sValPostSOut_uid132_fpArctan2Test_s <= ld_shiftOut_uid130_fpArctan2Test_c_to_sValPostSOut_uid132_fpArctan2Test_b_q;
sValPostSOut_uid132_fpArctan2Test: PROCESS (sValPostSOut_uid132_fpArctan2Test_s, en, shiftValPath2PreSubR_uid131_fpArctan2Test_b, cstWFP2_uid62_fpArctan2Test_q)
BEGIN
CASE sValPostSOut_uid132_fpArctan2Test_s IS
WHEN "0" => sValPostSOut_uid132_fpArctan2Test_q <= shiftValPath2PreSubR_uid131_fpArctan2Test_b;
WHEN "1" => sValPostSOut_uid132_fpArctan2Test_q <= cstWFP2_uid62_fpArctan2Test_q;
WHEN OTHERS => sValPostSOut_uid132_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid134_fpArctan2Test(BITSELECT,133)@49
sValPostSOutR_uid134_fpArctan2Test_in <= sValPostSOut_uid132_fpArctan2Test_q(4 downto 0);
sValPostSOutR_uid134_fpArctan2Test_b <= sValPostSOutR_uid134_fpArctan2Test_in(4 downto 0);
--rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,394)@49
rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_in <= sValPostSOutR_uid134_fpArctan2Test_b;
rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_b <= rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1(REG,572)@49
reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1_q <= rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test(MUX,395)@50
rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_s <= reg_rightShiftStageSel4Dto3_uid395_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_1_q;
rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test: PROCESS (rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_s, en, oFracRPath2_uid133_uid133_fpArctan2Test_q, rightShiftStage0Idx1_uid388_fxpOp2Path2_uid135_fpArctan2Test_q, rightShiftStage0Idx2_uid391_fxpOp2Path2_uid135_fpArctan2Test_q, rightShiftStage0Idx3_uid394_fxpOp2Path2_uid135_fpArctan2Test_q)
BEGIN
CASE rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_s IS
WHEN "00" => rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q <= oFracRPath2_uid133_uid133_fpArctan2Test_q;
WHEN "01" => rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage0Idx1_uid388_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN "10" => rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage0Idx2_uid391_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN "11" => rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage0Idx3_uid394_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,402)@50
RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_in <= rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q;
RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b <= RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 6);
--ld_RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_a(DELAY,965)@50
ld_RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b, xout => ld_RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,404)@51
rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage1Idx3Pad6_uid404_fxpOp2Path2_uid135_fpArctan2Test_q & ld_RightShiftStage024dto6_uid403_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_a_q;
--RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,399)@50
RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_in <= rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q;
RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b <= RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 4);
--ld_RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_a(DELAY,963)@50
ld_RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b, xout => ld_RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,401)@51
rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_q <= leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test_q & ld_RightShiftStage024dto4_uid400_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_a_q;
--RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,396)@50
RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_in <= rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q;
RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b <= RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_in(24 downto 2);
--ld_RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_a(DELAY,961)@50
ld_RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b, xout => ld_RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test(BITJOIN,398)@51
rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_q <= z_uid243_div_uid49_fpArctan2Test_q & ld_RightShiftStage024dto2_uid397_fxpOp2Path2_uid135_fpArctan2Test_b_to_rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_a_q;
--reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2(REG,574)@50
reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2_q <= rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,405)@49
rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_in <= sValPostSOutR_uid134_fpArctan2Test_b(2 downto 0);
rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b <= rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_a(DELAY,1127)@49
ld_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b, xout => ld_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1(REG,573)@50
reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_q <= ld_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test(MUX,406)@51
rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_s <= reg_rightShiftStageSel2Dto1_uid406_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_1_q;
rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test: PROCESS (rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_s, en, reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2_q, rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_q, rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_q, rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_q)
BEGIN
CASE rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_s IS
WHEN "00" => rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q <= reg_rightShiftStage0_uid396_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_2_q;
WHEN "01" => rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage1Idx1_uid399_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN "10" => rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage1Idx2_uid402_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN "11" => rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage1Idx3_uid405_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test(BITSELECT,410)@49
rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_in <= sValPostSOutR_uid134_fpArctan2Test_b(0 downto 0);
rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b <= rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_a(DELAY,1129)@49
ld_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b, xout => ld_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1(REG,575)@50
reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_q <= ld_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_b_to_reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test(MUX,411)@51
rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_s <= reg_rightShiftStageSel0Dto0_uid411_fxpOp2Path2_uid135_fpArctan2Test_0_to_rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_1_q;
rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test: PROCESS (rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_s, en, rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q, rightShiftStage2Idx1_uid410_fxpOp2Path2_uid135_fpArctan2Test_q)
BEGIN
CASE rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_s IS
WHEN "0" => rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage1_uid407_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN "1" => rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_q <= rightShiftStage2Idx1_uid410_fxpOp2Path2_uid135_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid135_uid136_fpArctan2Test(BITJOIN,135)@51
pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_q <= rightShiftStage2_uid412_fxpOp2Path2_uid135_fpArctan2Test_q & GND_q;
--reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1(REG,576)@51
reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1_q <= pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid136_fpArctan2Test(SUB,136)@52
path2Diff_uid136_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & piO2_uid83_fpArctan2Test_q);
path2Diff_uid136_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid135_uid136_fpArctan2Test_0_to_path2Diff_uid136_fpArctan2Test_1_q);
path2Diff_uid136_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid136_fpArctan2Test_a) - UNSIGNED(path2Diff_uid136_fpArctan2Test_b));
path2Diff_uid136_fpArctan2Test_q <= path2Diff_uid136_fpArctan2Test_o(26 downto 0);
--normBitPath2Diff_uid138_fpArctan2Test(BITSELECT,137)@52
normBitPath2Diff_uid138_fpArctan2Test_in <= path2Diff_uid136_fpArctan2Test_q(25 downto 0);
normBitPath2Diff_uid138_fpArctan2Test_b <= normBitPath2Diff_uid138_fpArctan2Test_in(25 downto 25);
--expRPath2_uid142_fpArctan2Test(MUX,141)@52
expRPath2_uid142_fpArctan2Test_s <= normBitPath2Diff_uid138_fpArctan2Test_b;
expRPath2_uid142_fpArctan2Test: PROCESS (expRPath2_uid142_fpArctan2Test_s, en, cstBiasM1_uid58_fpArctan2Test_q, cstBias_uid57_fpArctan2Test_q)
BEGIN
CASE expRPath2_uid142_fpArctan2Test_s IS
WHEN "0" => expRPath2_uid142_fpArctan2Test_q <= cstBiasM1_uid58_fpArctan2Test_q;
WHEN "1" => expRPath2_uid142_fpArctan2Test_q <= cstBias_uid57_fpArctan2Test_q;
WHEN OTHERS => expRPath2_uid142_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid139_fpArctan2Test(BITSELECT,138)@52
path2DiffHigh_uid139_fpArctan2Test_in <= path2Diff_uid136_fpArctan2Test_q(24 downto 0);
path2DiffHigh_uid139_fpArctan2Test_b <= path2DiffHigh_uid139_fpArctan2Test_in(24 downto 1);
--path2DiffLow_uid140_fpArctan2Test(BITSELECT,139)@52
path2DiffLow_uid140_fpArctan2Test_in <= path2Diff_uid136_fpArctan2Test_q(23 downto 0);
path2DiffLow_uid140_fpArctan2Test_b <= path2DiffLow_uid140_fpArctan2Test_in(23 downto 0);
--fracRPath2_uid141_fpArctan2Test(MUX,140)@52
fracRPath2_uid141_fpArctan2Test_s <= normBitPath2Diff_uid138_fpArctan2Test_b;
fracRPath2_uid141_fpArctan2Test: PROCESS (fracRPath2_uid141_fpArctan2Test_s, en, path2DiffLow_uid140_fpArctan2Test_b, path2DiffHigh_uid139_fpArctan2Test_b)
BEGIN
CASE fracRPath2_uid141_fpArctan2Test_s IS
WHEN "0" => fracRPath2_uid141_fpArctan2Test_q <= path2DiffLow_uid140_fpArctan2Test_b;
WHEN "1" => fracRPath2_uid141_fpArctan2Test_q <= path2DiffHigh_uid139_fpArctan2Test_b;
WHEN OTHERS => fracRPath2_uid141_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid143_uid143_fpArctan2Test(BITJOIN,142)@52
expFracConc_uid143_uid143_fpArctan2Test_q <= expRPath2_uid142_fpArctan2Test_q & fracRPath2_uid141_fpArctan2Test_q;
--reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0(REG,577)@52
reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0_q <= expFracConc_uid143_uid143_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid144_fpArctan2Test(ADD,143)@53
expFracRPath2PostRnd_uid144_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid143_uid143_fpArctan2Test_0_to_expFracRPath2PostRnd_uid144_fpArctan2Test_0_q);
expFracRPath2PostRnd_uid144_fpArctan2Test_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid144_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid144_fpArctan2Test_a) + UNSIGNED(expFracRPath2PostRnd_uid144_fpArctan2Test_b));
expFracRPath2PostRnd_uid144_fpArctan2Test_q <= expFracRPath2PostRnd_uid144_fpArctan2Test_o(32 downto 0);
--fracRPath2_uid145_fpArctan2Test(BITSELECT,144)@53
fracRPath2_uid145_fpArctan2Test_in <= expFracRPath2PostRnd_uid144_fpArctan2Test_q(23 downto 0);
fracRPath2_uid145_fpArctan2Test_b <= fracRPath2_uid145_fpArctan2Test_in(23 downto 1);
--reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3(REG,582)@53
reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3_q <= fracRPath2_uid145_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor(LOGICAL,1486)
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_b <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_q <= not (ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_a or ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_b);
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_mem_top(CONSTANT,1223)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_mem_top_q <= "0100000";
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp(LOGICAL,1224)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_a <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_mem_top_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q);
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_q <= "1" when ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_a = ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_b else "0";
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg(REG,1225)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena(REG,1487)
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_nor_q = "1") THEN
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd(LOGICAL,1488)
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_a <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_sticky_ena_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_b <= en;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_q <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_a and ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_b;
--ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_inputreg(DELAY,1476)
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid51_fpArctan2Test_b, xout => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt(COUNTER,1219)
-- every=1, low=0, high=32, step=1, init=1
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i = 31 THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_eq <= '1';
ELSE
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_eq = '1') THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i - 32;
ELSE
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_i,6));
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg(REG,1220)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux(MUX,1221)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_s <= en;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux: PROCESS (ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_s, ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q, ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_q)
BEGIN
CASE ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_s IS
WHEN "0" => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q;
WHEN "1" => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem(DUALMEM,1477)
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ia <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_inputreg_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_aa <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ab <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_iq,
address_a => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_aa,
data_a => ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_ia
);
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_reset0 <= areset;
ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_q <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_iq(22 downto 0);
--reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2(REG,581)@53
reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_q <= ld_fracX_uid51_fpArctan2Test_b_to_reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor(LOGICAL,1460)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_b <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_q <= not (ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_a or ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_b);
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_mem_top(CONSTANT,1456)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_mem_top_q <= "010010";
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp(LOGICAL,1457)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_a <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_mem_top_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q);
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_q <= "1" when ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_a = ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_b else "0";
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg(REG,1458)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena(REG,1461)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_nor_q = "1") THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd(LOGICAL,1462)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_a <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_sticky_ena_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_b <= en;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_a and ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_b;
--xyInInf_uid92_fpArctan2Test(LOGICAL,91)@0
xyInInf_uid92_fpArctan2Test_a <= exc_I_uid15_fpArctan2Test_q;
xyInInf_uid92_fpArctan2Test_b <= exc_I_uid31_fpArctan2Test_q;
xyInInf_uid92_fpArctan2Test_q <= xyInInf_uid92_fpArctan2Test_a and xyInInf_uid92_fpArctan2Test_b;
--ld_xyInInf_uid92_fpArctan2Test_q_to_arctanIsConst_uid93_fpArctan2Test_c(DELAY,649)@0
ld_xyInInf_uid92_fpArctan2Test_q_to_arctanIsConst_uid93_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => xyInInf_uid92_fpArctan2Test_q, xout => ld_xyInInf_uid92_fpArctan2Test_q_to_arctanIsConst_uid93_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--expXIsBias_uid81_fpArctan2Test(LOGICAL,80)@19
expXIsBias_uid81_fpArctan2Test_a <= reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q;
expXIsBias_uid81_fpArctan2Test_b <= cstBias_uid57_fpArctan2Test_q;
expXIsBias_uid81_fpArctan2Test_q <= "1" when expXIsBias_uid81_fpArctan2Test_a = expXIsBias_uid81_fpArctan2Test_b else "0";
--inIsOne_uid82_fpArctan2Test(LOGICAL,81)@19
inIsOne_uid82_fpArctan2Test_a <= fracXIsZero_uid72_fpArctan2Test_q;
inIsOne_uid82_fpArctan2Test_b <= expXIsBias_uid81_fpArctan2Test_q;
inIsOne_uid82_fpArctan2Test_q <= inIsOne_uid82_fpArctan2Test_a and inIsOne_uid82_fpArctan2Test_b;
--arctanIsConst_uid93_fpArctan2Test(LOGICAL,92)@19
arctanIsConst_uid93_fpArctan2Test_a <= exc_I_uid73_fpArctan2Test_q;
arctanIsConst_uid93_fpArctan2Test_b <= inIsOne_uid82_fpArctan2Test_q;
arctanIsConst_uid93_fpArctan2Test_c <= ld_xyInInf_uid92_fpArctan2Test_q_to_arctanIsConst_uid93_fpArctan2Test_c_q;
arctanIsConst_uid93_fpArctan2Test_q_i <= arctanIsConst_uid93_fpArctan2Test_a or arctanIsConst_uid93_fpArctan2Test_b or arctanIsConst_uid93_fpArctan2Test_c;
arctanIsConst_uid93_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => arctanIsConst_uid93_fpArctan2Test_q, xin => arctanIsConst_uid93_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_arctanIsConst_uid93_fpArctan2Test_q_to_pathSelBits_uid147_fpArctan2Test_c(DELAY,708)@20
ld_arctanIsConst_uid93_fpArctan2Test_q_to_pathSelBits_uid147_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => arctanIsConst_uid93_fpArctan2Test_q, xout => ld_arctanIsConst_uid93_fpArctan2Test_q_to_pathSelBits_uid147_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid100_fpArctan2Test(CONSTANT,99)
biasMwShift_uid100_fpArctan2Test_q <= "01110011";
--atanUIsU_uid101_fpArctan2Test(COMPARE,100)@31
atanUIsU_uid101_fpArctan2Test_cin <= GND_q;
atanUIsU_uid101_fpArctan2Test_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid100_fpArctan2Test_q) & '0';
atanUIsU_uid101_fpArctan2Test_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid97_fpArctan2Test_0_to_atanUIsU_uid101_fpArctan2Test_1_q) & atanUIsU_uid101_fpArctan2Test_cin(0);
atanUIsU_uid101_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid101_fpArctan2Test_a) - UNSIGNED(atanUIsU_uid101_fpArctan2Test_b));
atanUIsU_uid101_fpArctan2Test_n(0) <= not atanUIsU_uid101_fpArctan2Test_o(10);
--ld_path2_uid94_fpArctan2Test_n_to_pathSelBits_uid147_fpArctan2Test_a(DELAY,706)@19
ld_path2_uid94_fpArctan2Test_n_to_pathSelBits_uid147_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => path2_uid94_fpArctan2Test_n, xout => ld_path2_uid94_fpArctan2Test_n_to_pathSelBits_uid147_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid147_fpArctan2Test(BITJOIN,146)@31
pathSelBits_uid147_fpArctan2Test_q <= ld_arctanIsConst_uid93_fpArctan2Test_q_to_pathSelBits_uid147_fpArctan2Test_c_q & atanUIsU_uid101_fpArctan2Test_n & ld_path2_uid94_fpArctan2Test_n_to_pathSelBits_uid147_fpArctan2Test_a_q;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_inputreg(DELAY,1450)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid147_fpArctan2Test_q, xout => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt(COUNTER,1452)
-- every=1, low=0, high=18, step=1, init=1
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i = 17 THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i - 18;
ELSE
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_i,5));
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg(REG,1453)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux(MUX,1454)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_s <= en;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux: PROCESS (ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_s, ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q, ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem(DUALMEM,1451)
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ia <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_inputreg_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_aa <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdreg_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ab <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_rdmux_q;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_iq,
address_a => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_aa,
data_a => ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_ia
);
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_iq(2 downto 0);
--reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0(REG,550)@52
reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_q <= ld_pathSelBits_uid147_fpArctan2Test_q_to_reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracOutMuxSelEnc_uid148_fpArctan2Test(LOOKUP,147)@53
fracOutMuxSelEnc_uid148_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_pathSelBits_uid147_fpArctan2Test_0_to_fracOutMuxSelEnc_uid148_fpArctan2Test_0_q) IS
WHEN "000" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid148_fpArctan2Test_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid148_fpArctan2Test_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid150_fpArctan2Test(MUX,149)@54
fracRCalc_uid150_fpArctan2Test_s <= fracOutMuxSelEnc_uid148_fpArctan2Test_q;
fracRCalc_uid150_fpArctan2Test: PROCESS (fracRCalc_uid150_fpArctan2Test_s, en, reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_q, reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3_q, ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_q, reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5_q)
BEGIN
CASE fracRCalc_uid150_fpArctan2Test_s IS
WHEN "00" => fracRCalc_uid150_fpArctan2Test_q <= reg_fracX_uid51_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_2_q;
WHEN "01" => fracRCalc_uid150_fpArctan2Test_q <= reg_fracRPath2_uid145_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_3_q;
WHEN "10" => fracRCalc_uid150_fpArctan2Test_q <= ld_reg_fracRPath3_uid127_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_4_q_to_fracRCalc_uid150_fpArctan2Test_e_replace_mem_q;
WHEN "11" => fracRCalc_uid150_fpArctan2Test_q <= reg_fracOutCst_uid149_fpArctan2Test_0_to_fracRCalc_uid150_fpArctan2Test_5_q;
WHEN OTHERS => fracRCalc_uid150_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracRCalc_uid150_fpArctan2Test_q_to_oFracRCalc_uid160_uid160_fpArctan2Test_a(DELAY,730)@54
ld_fracRCalc_uid150_fpArctan2Test_q_to_oFracRCalc_uid160_uid160_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRCalc_uid150_fpArctan2Test_q, xout => ld_fracRCalc_uid150_fpArctan2Test_q_to_oFracRCalc_uid160_uid160_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRCalc_uid160_uid160_fpArctan2Test(BITJOIN,159)@56
oFracRCalc_uid160_uid160_fpArctan2Test_q <= VCC_q & ld_fracRCalc_uid150_fpArctan2Test_q_to_oFracRCalc_uid160_uid160_fpArctan2Test_a_q;
--rightPaddedIn_uid162_fpArctan2Test(BITJOIN,161)@56
rightPaddedIn_uid162_fpArctan2Test_q <= oFracRCalc_uid160_uid160_fpArctan2Test_q & padConst_uid161_fpArctan2Test_q;
--cstWFP1_uid61_fpArctan2Test(CONSTANT,60)
cstWFP1_uid61_fpArctan2Test_q <= "00011000";
--expOutCst_uid151_fpArctan2Test(BITSELECT,150)@53
expOutCst_uid151_fpArctan2Test_in <= constOut_uid91_fpArctan2Test_q(30 downto 0);
expOutCst_uid151_fpArctan2Test_b <= expOutCst_uid151_fpArctan2Test_in(30 downto 23);
--reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5(REG,588)@53
reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5_q <= expOutCst_uid151_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--expRPath3_uid128_fpArctan2Test(BITSELECT,127)@49
expRPath3_uid128_fpArctan2Test_in <= fracRPath3PostRnd_uid126_fpArctan2Test_q(31 downto 0);
expRPath3_uid128_fpArctan2Test_b <= expRPath3_uid128_fpArctan2Test_in(31 downto 24);
--ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_inputreg(DELAY,1489)
ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPath3_uid128_fpArctan2Test_b, xout => ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a(DELAY,1141)@49
ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_inputreg_q, xout => ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4(REG,587)@53
reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_q <= ld_expRPath3_uid128_fpArctan2Test_b_to_reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_a_q;
END IF;
END IF;
END PROCESS;
--expRPath2_uid146_fpArctan2Test(BITSELECT,145)@53
expRPath2_uid146_fpArctan2Test_in <= expFracRPath2PostRnd_uid144_fpArctan2Test_q(31 downto 0);
expRPath2_uid146_fpArctan2Test_b <= expRPath2_uid146_fpArctan2Test_in(31 downto 24);
--reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3(REG,586)@53
reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3_q <= expRPath2_uid146_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor(LOGICAL,1227)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_b <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_q <= not (ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_a or ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_b);
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena(REG,1228)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_nor_q = "1") THEN
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd(LOGICAL,1229)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_a <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_sticky_ena_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_b <= en;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_a and ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_b;
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_inputreg(DELAY,1217)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expX_uid50_fpArctan2Test_0_to_expXIsZero_uid68_fpArctan2Test_1_q, xout => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem(DUALMEM,1218)
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ia <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_inputreg_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_aa <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdreg_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ab <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_rdmux_q;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_iq,
address_a => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_aa,
data_a => ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_ia
);
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_iq(7 downto 0);
--expRCalc_uid152_fpArctan2Test(MUX,151)@54
expRCalc_uid152_fpArctan2Test_s <= fracOutMuxSelEnc_uid148_fpArctan2Test_q;
expRCalc_uid152_fpArctan2Test: PROCESS (expRCalc_uid152_fpArctan2Test_s, en, ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_q, reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3_q, reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_q, reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5_q)
BEGIN
CASE expRCalc_uid152_fpArctan2Test_s IS
WHEN "00" => expRCalc_uid152_fpArctan2Test_q <= ld_reg_expX_uid50_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_2_q_to_expRCalc_uid152_fpArctan2Test_c_replace_mem_q;
WHEN "01" => expRCalc_uid152_fpArctan2Test_q <= reg_expRPath2_uid146_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_3_q;
WHEN "10" => expRCalc_uid152_fpArctan2Test_q <= reg_expRPath3_uid128_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_4_q;
WHEN "11" => expRCalc_uid152_fpArctan2Test_q <= reg_expOutCst_uid151_fpArctan2Test_0_to_expRCalc_uid152_fpArctan2Test_5_q;
WHEN OTHERS => expRCalc_uid152_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0(REG,589)@54
reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0_q <= expRCalc_uid152_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--sValAlignRes_uid154_fpArctan2Test(SUB,153)@55
sValAlignRes_uid154_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & cstBias_uid57_fpArctan2Test_q);
sValAlignRes_uid154_fpArctan2Test_b <= STD_LOGIC_VECTOR("0" & reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0_q);
sValAlignRes_uid154_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(sValAlignRes_uid154_fpArctan2Test_a) - UNSIGNED(sValAlignRes_uid154_fpArctan2Test_b));
sValAlignRes_uid154_fpArctan2Test_q <= sValAlignRes_uid154_fpArctan2Test_o(8 downto 0);
--sValAlignResRange_uid157_fpArctan2Test(BITSELECT,156)@55
sValAlignResRange_uid157_fpArctan2Test_in <= sValAlignRes_uid154_fpArctan2Test_q(7 downto 0);
sValAlignResRange_uid157_fpArctan2Test_b <= sValAlignResRange_uid157_fpArctan2Test_in(7 downto 0);
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor(LOGICAL,1240)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_b <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_q <= not (ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_a or ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_b);
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_mem_top(CONSTANT,1236)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_mem_top_q <= "0110100";
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp(LOGICAL,1237)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_a <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_mem_top_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q);
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_q <= "1" when ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_a = ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_b else "0";
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg(REG,1238)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena(REG,1241)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_nor_q = "1") THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd(LOGICAL,1242)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_a <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_sticky_ena_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_b <= en;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_a and ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_b;
--zwEwF_uid40_fpArctan2Test(CONSTANT,39)
zwEwF_uid40_fpArctan2Test_q <= "0000000000000000000000000000000";
--join_uid43_fpArctan2Test(BITJOIN,42)@0
join_uid43_fpArctan2Test_q <= exp_uid27_fpArctan2Test_b & frac_uid29_fpArctan2Test_b;
--yInZero_uid44_fpArctan2Test(LOGICAL,43)@0
yInZero_uid44_fpArctan2Test_a <= join_uid43_fpArctan2Test_q;
yInZero_uid44_fpArctan2Test_b <= zwEwF_uid40_fpArctan2Test_q;
yInZero_uid44_fpArctan2Test_q <= "1" when yInZero_uid44_fpArctan2Test_a = yInZero_uid44_fpArctan2Test_b else "0";
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_inputreg(DELAY,1230)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yInZero_uid44_fpArctan2Test_q, xout => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt(COUNTER,1232)
-- every=1, low=0, high=52, step=1, init=1
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i = 51 THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_eq = '1') THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i - 52;
ELSE
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_i,6));
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg(REG,1233)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux(MUX,1234)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_s <= en;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux: PROCESS (ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_s, ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q, ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_s IS
WHEN "0" => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q;
WHEN "1" => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem(DUALMEM,1231)
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ia <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_inputreg_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_aa <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdreg_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ab <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_rdmux_q;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 53,
width_b => 1,
widthad_b => 6,
numwords_b => 53,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_iq,
address_a => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_aa,
data_a => ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_ia
);
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_reset0 <= areset;
ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_q <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_iq(0 downto 0);
--sOutAlignRes_uid155_fpArctan2Test(COMPARE,154)@55
sOutAlignRes_uid155_fpArctan2Test_cin <= GND_q;
sOutAlignRes_uid155_fpArctan2Test_a <= STD_LOGIC_VECTOR("00" & reg_expRCalc_uid152_fpArctan2Test_0_to_sOutAlignRes_uid155_fpArctan2Test_0_q) & '0';
sOutAlignRes_uid155_fpArctan2Test_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid59_fpArctan2Test_q) & sOutAlignRes_uid155_fpArctan2Test_cin(0);
sOutAlignRes_uid155_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(sOutAlignRes_uid155_fpArctan2Test_a) - UNSIGNED(sOutAlignRes_uid155_fpArctan2Test_b));
sOutAlignRes_uid155_fpArctan2Test_c(0) <= sOutAlignRes_uid155_fpArctan2Test_o(10);
--yInZOrsOutAlignRes_uid156_fpArctan2Test(LOGICAL,155)@55
yInZOrsOutAlignRes_uid156_fpArctan2Test_a <= sOutAlignRes_uid155_fpArctan2Test_c;
yInZOrsOutAlignRes_uid156_fpArctan2Test_b <= ld_yInZero_uid44_fpArctan2Test_q_to_yInZOrsOutAlignRes_uid156_fpArctan2Test_b_replace_mem_q;
yInZOrsOutAlignRes_uid156_fpArctan2Test_q <= yInZOrsOutAlignRes_uid156_fpArctan2Test_a or yInZOrsOutAlignRes_uid156_fpArctan2Test_b;
--sValPostSAlignOut_uid158_fpArctan2Test(MUX,157)@55
sValPostSAlignOut_uid158_fpArctan2Test_s <= yInZOrsOutAlignRes_uid156_fpArctan2Test_q;
sValPostSAlignOut_uid158_fpArctan2Test: PROCESS (sValPostSAlignOut_uid158_fpArctan2Test_s, en, sValAlignResRange_uid157_fpArctan2Test_b, cstWFP1_uid61_fpArctan2Test_q)
BEGIN
CASE sValPostSAlignOut_uid158_fpArctan2Test_s IS
WHEN "0" => sValPostSAlignOut_uid158_fpArctan2Test_q <= sValAlignResRange_uid157_fpArctan2Test_b;
WHEN "1" => sValPostSAlignOut_uid158_fpArctan2Test_q <= cstWFP1_uid61_fpArctan2Test_q;
WHEN OTHERS => sValPostSAlignOut_uid158_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutRange_uid159_fpArctan2Test(BITSELECT,158)@55
sValPostSOutRange_uid159_fpArctan2Test_in <= sValPostSAlignOut_uid158_fpArctan2Test_q(4 downto 0);
sValPostSOutRange_uid159_fpArctan2Test_b <= sValPostSOutRange_uid159_fpArctan2Test_in(4 downto 0);
--rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,423)@55
rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_in <= sValPostSOutRange_uid159_fpArctan2Test_b;
rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_b <= rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1(REG,591)@55
reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1_q <= rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test(MUX,424)@56
rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_s <= reg_rightShiftStageSel4Dto3_uid424_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_1_q;
rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test: PROCESS (rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_s, en, rightPaddedIn_uid162_fpArctan2Test_q, rightShiftStage0Idx1_uid417_fxpAlignedRes_uid161_fpArctan2Test_q, rightShiftStage0Idx2_uid420_fxpAlignedRes_uid161_fpArctan2Test_q, rightShiftStage0Idx3_uid423_fxpAlignedRes_uid161_fpArctan2Test_q)
BEGIN
CASE rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_s IS
WHEN "00" => rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q <= rightPaddedIn_uid162_fpArctan2Test_q;
WHEN "01" => rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage0Idx1_uid417_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN "10" => rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage0Idx2_uid420_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN "11" => rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage0Idx3_uid423_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,431)@56
RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_in <= rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q;
RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b <= RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 6);
--ld_RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_a(DELAY,995)@56
ld_RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b, xout => ld_RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,433)@57
rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage1Idx3Pad6_uid404_fxpOp2Path2_uid135_fpArctan2Test_q & ld_RightShiftStage047dto6_uid432_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_a_q;
--RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,428)@56
RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_in <= rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q;
RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b <= RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 4);
--ld_RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_a(DELAY,993)@56
ld_RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 44, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b, xout => ld_RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,430)@57
rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_q <= leftShiftStage0Idx1Pad4_uid343_fxpU_uid110_fpArctan2Test_q & ld_RightShiftStage047dto4_uid429_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_a_q;
--RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,425)@56
RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_in <= rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q;
RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b <= RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_in(47 downto 2);
--ld_RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_a(DELAY,991)@56
ld_RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b, xout => ld_RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test(BITJOIN,427)@57
rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_q <= z_uid243_div_uid49_fpArctan2Test_q & ld_RightShiftStage047dto2_uid426_fxpAlignedRes_uid161_fpArctan2Test_b_to_rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_a_q;
--reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2(REG,593)@56
reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2_q <= rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,434)@55
rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_in <= sValPostSOutRange_uid159_fpArctan2Test_b(2 downto 0);
rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b <= rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_a(DELAY,1146)@55
ld_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b, xout => ld_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1(REG,592)@56
reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_q <= ld_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_b_to_reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test(MUX,435)@57
rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_s <= reg_rightShiftStageSel2Dto1_uid435_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_1_q;
rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test: PROCESS (rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_s, en, reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2_q, rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_q, rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_q, rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_q)
BEGIN
CASE rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_s IS
WHEN "00" => rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q <= reg_rightShiftStage0_uid425_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_2_q;
WHEN "01" => rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage1Idx1_uid428_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN "10" => rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage1Idx2_uid431_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN "11" => rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage1Idx3_uid434_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test(BITSELECT,439)@55
rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_in <= sValPostSOutRange_uid159_fpArctan2Test_b(0 downto 0);
rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_b <= rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1(REG,594)@55
reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q <= rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_b(DELAY,1005)@56
ld_reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test(MUX,440)@57
rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid440_fxpAlignedRes_uid161_fpArctan2Test_0_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_1_q_to_rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_b_q;
rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_s IS
WHEN "0" => rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage1_uid436_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN "1" => rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q <= rightShiftStage2Idx1_uid439_fxpAlignedRes_uid161_fpArctan2Test_q;
WHEN OTHERS => rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstPi_uid153_fpArctan2Test(CONSTANT,152)
cstPi_uid153_fpArctan2Test_q <= "11001001000011111101101010100010001000010110100";
--pad_cstPi_uid153_uid164_fpArctan2Test(BITJOIN,163)@57
pad_cstPi_uid153_uid164_fpArctan2Test_q <= cstPi_uid153_fpArctan2Test_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0(REG,595)@57
reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0_q <= "0000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0_q <= pad_cstPi_uid153_uid164_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--subRes_uid164_fpArctan2Test(SUB,164)@58
subRes_uid164_fpArctan2Test_a <= STD_LOGIC_VECTOR("0" & reg_pad_cstPi_uid153_uid164_fpArctan2Test_0_to_subRes_uid164_fpArctan2Test_0_q);
subRes_uid164_fpArctan2Test_b <= STD_LOGIC_VECTOR("00" & rightShiftStage2_uid441_fxpAlignedRes_uid161_fpArctan2Test_q);
subRes_uid164_fpArctan2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(subRes_uid164_fpArctan2Test_a) - UNSIGNED(subRes_uid164_fpArctan2Test_b));
subRes_uid164_fpArctan2Test_q <= subRes_uid164_fpArctan2Test_o(49 downto 0);
--subResNormBit_uid166_fpArctan2Test(BITSELECT,165)@58
subResNormBit_uid166_fpArctan2Test_in <= subRes_uid164_fpArctan2Test_q(48 downto 0);
subResNormBit_uid166_fpArctan2Test_b <= subResNormBit_uid166_fpArctan2Test_in(48 downto 48);
--reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1(REG,596)@58
reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1_q <= subResNormBit_uid166_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--expRSub_uid170_fpArctan2Test(MUX,169)@59
expRSub_uid170_fpArctan2Test_s <= reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1_q;
expRSub_uid170_fpArctan2Test: PROCESS (expRSub_uid170_fpArctan2Test_s, en, cstBias_uid57_fpArctan2Test_q, cstBiasP1_uid60_fpArctan2Test_q)
BEGIN
CASE expRSub_uid170_fpArctan2Test_s IS
WHEN "0" => expRSub_uid170_fpArctan2Test_q <= cstBias_uid57_fpArctan2Test_q;
WHEN "1" => expRSub_uid170_fpArctan2Test_q <= cstBiasP1_uid60_fpArctan2Test_q;
WHEN OTHERS => expRSub_uid170_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor(LOGICAL,1279)
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_b <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_q <= not (ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_a or ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_b);
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_mem_top(CONSTANT,1262)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_mem_top_q <= "010";
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp(LOGICAL,1263)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_a <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_mem_top_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q);
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_q <= "1" when ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_a = ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_b else "0";
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg(REG,1264)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena(REG,1280)
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_nor_q = "1") THEN
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd(LOGICAL,1281)
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_a <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_sticky_ena_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_b <= en;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_q <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_a and ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_b;
--ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_inputreg(DELAY,1269)
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRCalc_uid152_fpArctan2Test_q, xout => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt(COUNTER,1258)
-- every=1, low=0, high=2, step=1, init=1
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i = 1 THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_eq <= '1';
ELSE
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_eq = '1') THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i - 2;
ELSE
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_i,2));
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg(REG,1259)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux(MUX,1260)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_s <= en;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux: PROCESS (ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_s, ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q, ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_q)
BEGIN
CASE ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_s IS
WHEN "0" => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q;
WHEN "1" => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdcnt_q;
WHEN OTHERS => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem(DUALMEM,1270)
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ia <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_inputreg_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_aa <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ab <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 3,
width_b => 8,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_iq,
address_a => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_aa,
data_a => ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_ia
);
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_q <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_iq(7 downto 0);
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor(LOGICAL,1253)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_b <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_q <= not (ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_a or ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_b);
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_mem_top(CONSTANT,1249)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_mem_top_q <= "0110111";
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp(LOGICAL,1250)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_a <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_mem_top_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q);
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_q <= "1" when ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_a = ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_b else "0";
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg(REG,1251)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena(REG,1254)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_nor_q = "1") THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd(LOGICAL,1255)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_a <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_sticky_ena_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_b <= en;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_a and ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_b;
--join_uid47_fpArctan2Test(BITJOIN,46)@0
join_uid47_fpArctan2Test_q <= exp_uid11_fpArctan2Test_b & frac_uid13_fpArctan2Test_b;
--xInZero_uid48_fpArctan2Test(LOGICAL,47)@0
xInZero_uid48_fpArctan2Test_a <= join_uid47_fpArctan2Test_q;
xInZero_uid48_fpArctan2Test_b <= zwEwF_uid40_fpArctan2Test_q;
xInZero_uid48_fpArctan2Test_q <= "1" when xInZero_uid48_fpArctan2Test_a = xInZero_uid48_fpArctan2Test_b else "0";
--xInIsLTEZero_uid171_fpArctan2Test(LOGICAL,170)@0
xInIsLTEZero_uid171_fpArctan2Test_a <= xInSign_uid39_fpArctan2Test_b;
xInIsLTEZero_uid171_fpArctan2Test_b <= xInZero_uid48_fpArctan2Test_q;
xInIsLTEZero_uid171_fpArctan2Test_q_i <= xInIsLTEZero_uid171_fpArctan2Test_a or xInIsLTEZero_uid171_fpArctan2Test_b;
xInIsLTEZero_uid171_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => xInIsLTEZero_uid171_fpArctan2Test_q, xin => xInIsLTEZero_uid171_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_inputreg(DELAY,1243)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xInIsLTEZero_uid171_fpArctan2Test_q, xout => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt(COUNTER,1245)
-- every=1, low=0, high=55, step=1, init=1
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i = 54 THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_eq = '1') THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i - 55;
ELSE
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_i,6));
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg(REG,1246)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux(MUX,1247)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_s <= en;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux: PROCESS (ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_s, ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q, ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_s IS
WHEN "0" => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q;
WHEN "1" => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem(DUALMEM,1244)
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ia <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_inputreg_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_aa <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdreg_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ab <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_rdmux_q;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 56,
width_b => 1,
widthad_b => 6,
numwords_b => 56,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_iq,
address_a => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_aa,
data_a => ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_ia
);
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_reset0 <= areset;
ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_q <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_iq(0 downto 0);
--expRFinal_uid173_fpArctan2Test(MUX,172)@59
expRFinal_uid173_fpArctan2Test_s <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_q;
expRFinal_uid173_fpArctan2Test: PROCESS (expRFinal_uid173_fpArctan2Test_s, en, ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_q, expRSub_uid170_fpArctan2Test_q)
BEGIN
CASE expRFinal_uid173_fpArctan2Test_s IS
WHEN "0" => expRFinal_uid173_fpArctan2Test_q <= ld_expRCalc_uid152_fpArctan2Test_q_to_expRFinal_uid173_fpArctan2Test_c_replace_mem_q;
WHEN "1" => expRFinal_uid173_fpArctan2Test_q <= expRSub_uid170_fpArctan2Test_q;
WHEN OTHERS => expRFinal_uid173_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid56_fpArctan2Test(CONSTANT,55)
cstAllZWE_uid56_fpArctan2Test_q <= "00000000";
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor(LOGICAL,1434)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_b <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_q <= not (ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_a or ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_b);
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_mem_top(CONSTANT,1430)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_mem_top_q <= "0110110";
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp(LOGICAL,1431)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_a <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_mem_top_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q);
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_q <= "1" when ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_a = ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_b else "0";
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg(REG,1432)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena(REG,1435)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_nor_q = "1") THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd(LOGICAL,1436)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_a <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_sticky_ena_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_b <= en;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_a and ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_b;
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_inputreg(DELAY,1424)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid180_fpArctan2Test_q, xout => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt(COUNTER,1426)
-- every=1, low=0, high=54, step=1, init=1
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i = 53 THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_eq <= '1';
ELSE
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_eq = '1') THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i - 54;
ELSE
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_i,6));
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg(REG,1427)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux(MUX,1428)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_s <= en;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux: PROCESS (ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_s, ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q, ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_q)
BEGIN
CASE ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_s IS
WHEN "0" => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q;
WHEN "1" => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdcnt_q;
WHEN OTHERS => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem(DUALMEM,1425)
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ia <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_inputreg_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_aa <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdreg_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ab <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_rdmux_q;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 55,
width_b => 1,
widthad_b => 6,
numwords_b => 55,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_iq,
address_a => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_aa,
data_a => ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_ia
);
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_reset0 <= areset;
ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_iq(0 downto 0);
--reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2(REG,526)@57
reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_q <= ld_excRNaN_uid180_fpArctan2Test_q_to_reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor(LOGICAL,1292)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_b <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_q <= not (ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_a or ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_b);
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_mem_top(CONSTANT,1288)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_mem_top_q <= "0100100";
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp(LOGICAL,1289)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_a <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_mem_top_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q);
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_q <= "1" when ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_a = ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_b else "0";
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg(REG,1290)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena(REG,1293)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_nor_q = "1") THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd(LOGICAL,1294)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_a <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_sticky_ena_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_b <= en;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_a and ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_b;
--InvXInSign_uid174_fpArctan2Test(LOGICAL,173)@0
InvXInSign_uid174_fpArctan2Test_a <= xInSign_uid39_fpArctan2Test_b;
InvXInSign_uid174_fpArctan2Test_q <= not InvXInSign_uid174_fpArctan2Test_a;
--excRZero2_uid175_fpArctan2Test(LOGICAL,174)@0
excRZero2_uid175_fpArctan2Test_a <= xInZero_uid48_fpArctan2Test_q;
excRZero2_uid175_fpArctan2Test_b <= yInZero_uid44_fpArctan2Test_q;
excRZero2_uid175_fpArctan2Test_c <= InvXInSign_uid174_fpArctan2Test_q;
excRZero2_uid175_fpArctan2Test_q_i <= excRZero2_uid175_fpArctan2Test_a and excRZero2_uid175_fpArctan2Test_b and excRZero2_uid175_fpArctan2Test_c;
excRZero2_uid175_fpArctan2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRZero2_uid175_fpArctan2Test_q, xin => excRZero2_uid175_fpArctan2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_excRZero2_uid175_fpArctan2Test_q_to_excRZero_uid179_fpArctan2Test_b(DELAY,758)@1
ld_excRZero2_uid175_fpArctan2Test_q_to_excRZero_uid179_fpArctan2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => excRZero2_uid175_fpArctan2Test_q, xout => ld_excRZero2_uid175_fpArctan2Test_q_to_excRZero_uid179_fpArctan2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_InvXInSign_uid174_fpArctan2Test_q_to_excRZero1_uid178_fpArctan2Test_c(DELAY,756)@0
ld_InvXInSign_uid174_fpArctan2Test_q_to_excRZero1_uid178_fpArctan2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => InvXInSign_uid174_fpArctan2Test_q, xout => ld_InvXInSign_uid174_fpArctan2Test_q_to_excRZero1_uid178_fpArctan2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_yInSign_uid38_fpArctan2Test_b_to_InvYInSign_uid177_fpArctan2Test_a(DELAY,753)@0
ld_yInSign_uid38_fpArctan2Test_b_to_InvYInSign_uid177_fpArctan2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => yInSign_uid38_fpArctan2Test_b, xout => ld_yInSign_uid38_fpArctan2Test_b_to_InvYInSign_uid177_fpArctan2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYInSign_uid177_fpArctan2Test(LOGICAL,176)@19
InvYInSign_uid177_fpArctan2Test_a <= ld_yInSign_uid38_fpArctan2Test_b_to_InvYInSign_uid177_fpArctan2Test_a_q;
InvYInSign_uid177_fpArctan2Test_q <= not InvYInSign_uid177_fpArctan2Test_a;
--excRZero1_uid178_fpArctan2Test(LOGICAL,177)@19
excRZero1_uid178_fpArctan2Test_a <= expXIsZero_uid68_fpArctan2Test_q;
excRZero1_uid178_fpArctan2Test_b <= InvYInSign_uid177_fpArctan2Test_q;
excRZero1_uid178_fpArctan2Test_c <= ld_InvXInSign_uid174_fpArctan2Test_q_to_excRZero1_uid178_fpArctan2Test_c_q;
excRZero1_uid178_fpArctan2Test_q <= excRZero1_uid178_fpArctan2Test_a and excRZero1_uid178_fpArctan2Test_b and excRZero1_uid178_fpArctan2Test_c;
--excRZero_uid179_fpArctan2Test(LOGICAL,178)@19
excRZero_uid179_fpArctan2Test_a <= excRZero1_uid178_fpArctan2Test_q;
excRZero_uid179_fpArctan2Test_b <= ld_excRZero2_uid175_fpArctan2Test_q_to_excRZero_uid179_fpArctan2Test_b_q;
excRZero_uid179_fpArctan2Test_q <= excRZero_uid179_fpArctan2Test_a or excRZero_uid179_fpArctan2Test_b;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_inputreg(DELAY,1282)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRZero_uid179_fpArctan2Test_q, xout => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt(COUNTER,1284)
-- every=1, low=0, high=36, step=1, init=1
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i = 35 THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_eq <= '1';
ELSE
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_eq = '1') THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i - 36;
ELSE
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_i,6));
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg(REG,1285)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux(MUX,1286)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_s <= en;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux: PROCESS (ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_s, ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q, ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_q)
BEGIN
CASE ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_s IS
WHEN "0" => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q;
WHEN "1" => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdcnt_q;
WHEN OTHERS => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem(DUALMEM,1283)
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ia <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_inputreg_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_aa <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdreg_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ab <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_rdmux_q;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 37,
width_b => 1,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_iq,
address_a => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_aa,
data_a => ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_ia
);
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_reset0 <= areset;
ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_q <= ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_iq(0 downto 0);
--excSelBits_uid181_fpArctan2Test(BITJOIN,180)@58
excSelBits_uid181_fpArctan2Test_q <= reg_excRNaN_uid180_fpArctan2Test_0_to_excSelBits_uid181_fpArctan2Test_2_q & GND_q & ld_excRZero_uid179_fpArctan2Test_q_to_excSelBits_uid181_fpArctan2Test_a_replace_mem_q;
--reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0(REG,527)@58
reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0_q <= excSelBits_uid181_fpArctan2Test_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid182_fpArctan2Test(LOOKUP,181)@59
outMuxSelEnc_uid182_fpArctan2Test: PROCESS (reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid181_fpArctan2Test_0_to_outMuxSelEnc_uid182_fpArctan2Test_0_q) IS
WHEN "000" => outMuxSelEnc_uid182_fpArctan2Test_q <= "01";
WHEN "001" => outMuxSelEnc_uid182_fpArctan2Test_q <= "00";
WHEN "010" => outMuxSelEnc_uid182_fpArctan2Test_q <= "10";
WHEN "011" => outMuxSelEnc_uid182_fpArctan2Test_q <= "01";
WHEN "100" => outMuxSelEnc_uid182_fpArctan2Test_q <= "11";
WHEN "101" => outMuxSelEnc_uid182_fpArctan2Test_q <= "01";
WHEN "110" => outMuxSelEnc_uid182_fpArctan2Test_q <= "01";
WHEN "111" => outMuxSelEnc_uid182_fpArctan2Test_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid182_fpArctan2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid184_fpArctan2Test(MUX,183)@59
expRPostExc_uid184_fpArctan2Test_s <= outMuxSelEnc_uid182_fpArctan2Test_q;
expRPostExc_uid184_fpArctan2Test: PROCESS (expRPostExc_uid184_fpArctan2Test_s, en, cstAllZWE_uid56_fpArctan2Test_q, expRFinal_uid173_fpArctan2Test_q, cstAllOWE_uid6_fpArctan2Test_q, cstAllOWE_uid6_fpArctan2Test_q)
BEGIN
CASE expRPostExc_uid184_fpArctan2Test_s IS
WHEN "00" => expRPostExc_uid184_fpArctan2Test_q <= cstAllZWE_uid56_fpArctan2Test_q;
WHEN "01" => expRPostExc_uid184_fpArctan2Test_q <= expRFinal_uid173_fpArctan2Test_q;
WHEN "10" => expRPostExc_uid184_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN "11" => expRPostExc_uid184_fpArctan2Test_q <= cstAllOWE_uid6_fpArctan2Test_q;
WHEN OTHERS => expRPostExc_uid184_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--subResHigh_uid167_fpArctan2Test(BITSELECT,166)@58
subResHigh_uid167_fpArctan2Test_in <= subRes_uid164_fpArctan2Test_q(47 downto 0);
subResHigh_uid167_fpArctan2Test_b <= subResHigh_uid167_fpArctan2Test_in(47 downto 25);
--reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3(REG,598)@58
reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3_q <= subResHigh_uid167_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--subResLow_uid168_fpArctan2Test(BITSELECT,167)@58
subResLow_uid168_fpArctan2Test_in <= subRes_uid164_fpArctan2Test_q(46 downto 0);
subResLow_uid168_fpArctan2Test_b <= subResLow_uid168_fpArctan2Test_in(46 downto 24);
--reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2(REG,597)@58
reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2_q <= subResLow_uid168_fpArctan2Test_b;
END IF;
END IF;
END PROCESS;
--fracRSub_uid169_fpArctan2Test(MUX,168)@59
fracRSub_uid169_fpArctan2Test_s <= reg_subResNormBit_uid166_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_1_q;
fracRSub_uid169_fpArctan2Test: PROCESS (fracRSub_uid169_fpArctan2Test_s, en, reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2_q, reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3_q)
BEGIN
CASE fracRSub_uid169_fpArctan2Test_s IS
WHEN "0" => fracRSub_uid169_fpArctan2Test_q <= reg_subResLow_uid168_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_2_q;
WHEN "1" => fracRSub_uid169_fpArctan2Test_q <= reg_subResHigh_uid167_fpArctan2Test_0_to_fracRSub_uid169_fpArctan2Test_3_q;
WHEN OTHERS => fracRSub_uid169_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor(LOGICAL,1266)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_a <= ld_singX_uid52_fpArctan2Test_b_to_fpPiO2C_uid86_fpArctan2Test_c_notEnable_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_b <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_q <= not (ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_a or ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_b);
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena(REG,1267)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_nor_q = "1") THEN
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd(LOGICAL,1268)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_a <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_sticky_ena_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_b <= en;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_a and ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_b;
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_inputreg(DELAY,1256)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRCalc_uid150_fpArctan2Test_q, xout => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem(DUALMEM,1257)
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ia <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_inputreg_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_aa <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdreg_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ab <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_rdmux_q;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 2,
numwords_a => 3,
width_b => 23,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_iq,
address_a => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_aa,
data_a => ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_ia
);
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_reset0 <= areset;
ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_iq(22 downto 0);
--fracRFinal_uid172_fpArctan2Test(MUX,171)@59
fracRFinal_uid172_fpArctan2Test_s <= ld_xInIsLTEZero_uid171_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_b_replace_mem_q;
fracRFinal_uid172_fpArctan2Test: PROCESS (fracRFinal_uid172_fpArctan2Test_s, en, ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_q, fracRSub_uid169_fpArctan2Test_q)
BEGIN
CASE fracRFinal_uid172_fpArctan2Test_s IS
WHEN "0" => fracRFinal_uid172_fpArctan2Test_q <= ld_fracRCalc_uid150_fpArctan2Test_q_to_fracRFinal_uid172_fpArctan2Test_c_replace_mem_q;
WHEN "1" => fracRFinal_uid172_fpArctan2Test_q <= fracRSub_uid169_fpArctan2Test_q;
WHEN OTHERS => fracRFinal_uid172_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid183_fpArctan2Test(MUX,182)@59
fracRPostExc_uid183_fpArctan2Test_s <= outMuxSelEnc_uid182_fpArctan2Test_q;
fracRPostExc_uid183_fpArctan2Test: PROCESS (fracRPostExc_uid183_fpArctan2Test_s, en, cstAllZWF_uid7_fpArctan2Test_q, fracRFinal_uid172_fpArctan2Test_q, cstAllZWF_uid7_fpArctan2Test_q, cstNaNWF_uid55_fpArctan2Test_q)
BEGIN
CASE fracRPostExc_uid183_fpArctan2Test_s IS
WHEN "00" => fracRPostExc_uid183_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "01" => fracRPostExc_uid183_fpArctan2Test_q <= fracRFinal_uid172_fpArctan2Test_q;
WHEN "10" => fracRPostExc_uid183_fpArctan2Test_q <= cstAllZWF_uid7_fpArctan2Test_q;
WHEN "11" => fracRPostExc_uid183_fpArctan2Test_q <= cstNaNWF_uid55_fpArctan2Test_q;
WHEN OTHERS => fracRPostExc_uid183_fpArctan2Test_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid187_fpArctan2Test(BITJOIN,186)@59
R_uid187_fpArctan2Test_q <= ld_signR_uid186_fpArctan2Test_q_to_R_uid187_fpArctan2Test_c_replace_mem_q & expRPostExc_uid184_fpArctan2Test_q & fracRPostExc_uid183_fpArctan2Test_q;
--xOut(GPOUT,4)@59
q <= R_uid187_fpArctan2Test_q;
end normal;
|
mit
|
QuantumRipple/VHDL
|
cores/uart/fixed_uart_rx.vhd
|
1
|
4114
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.general_pkg.all;
entity fixed_uart_rx is
generic(
clocks_per_bit : positive := 16;
data_bits : positive := 8;
parity_odd : boolean := false;
parity_even : boolean := false
--will wait for next start bit regardless of how many stop bits transmitter uses
);
port(
clk : in std_logic;
srst : in std_logic;
rxd : in std_logic; --must by syncronized to clk
data : out std_logic_vector(data_bits-1 downto 0);
valid : out std_logic; --pulses once per word. concurrent with error upon parity failure
error : out std_logic --pulse upon parity or stop error
);
end fixed_uart_rx;
architecture rtl of fixed_uart_rx is
signal data_i : std_logic_vector(data_bits-1 downto 0);
signal parity_i : std_logic;
signal clk_cnt : unsigned(f_log2_ceil(clocks_per_bit)-1 downto 0);
signal data_cnt : unsigned(f_log2_ceil(data_bits)-1 downto 0);
type t_state is (s_idle, s_start, s_data, s_parity, s_stop, s_err, s_err_wait);
signal state : t_state := s_err;
begin
assert not(parity_odd and parity_even) report "fixed_uart_rx parity misconfigured" severity error;
p_rx : process(clk)
begin
if rising_edge(clk) then
if f_is_pow2(clocks_per_bit) or clk_cnt /= clocks_per_bit-1 then --don't need an explicit rollover if the counter is a power of 2
clk_cnt <= clk_cnt+1; --default
else
clk_cnt <= (others=>'0');
end if;
error <= '0'; --default
valid <= '0'; --default
case state is
when s_idle =>
clk_cnt <= to_unsigned(clocks_per_bit/2, clk_cnt'length); --50% phase offset for sampling for best signal integrity
data_cnt <= (others=>'0');
parity_i <= '0';
if rxd='0' then
state <= s_start;
end if;
when s_start =>
if clk_cnt = clocks_per_bit-1 then
state <= s_data;
end if;
when s_data =>
if clk_cnt = clocks_per_bit-1 then
data_i <= rxd & data_i(data_i'left downto 1); --lsb sent first, so we need to fill from the top
parity_i <= parity_i xor rxd;
data_cnt <= data_cnt+1;
if data_cnt = data_bits-1 then
if parity_odd or parity_even then
state <= s_parity;
else
state <= s_stop;
end if;
end if;
end if;
when s_parity =>
if clk_cnt = clocks_per_bit-1 then
state <= s_stop;
parity_i <= parity_i xor rxd;
end if;
when s_stop =>
if clk_cnt = clocks_per_bit-1 then
data <= data_i;
if rxd='1' then
state <= s_idle;
valid <= '1';
if (parity_odd and parity_i='0') or (parity_even and parity_i='1') then --failed parity
error <= '1'; --but stop bit is okay, so we go to idle
end if;
else
state <= s_err;
error <= '1';
end if;
end if;
when s_err =>
clk_cnt <= to_unsigned(clocks_per_bit/2, clk_cnt'length);
if rxd='1' then
state <= s_err_wait;
end if;
when s_err_wait =>
if clk_cnt = clocks_per_bit-1 then
state <= s_idle;
end if;
end case;
if srst='1' then
state <= s_err; --waits until we have an idle signal before becoming ready
end if;
end if;
end process;
end rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_mul54us_38s.vhd
|
10
|
3962
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY fp_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_38s;
ARCHITECTURE rtl OF fp_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone + (zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 19));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_mul54us_38s.vhd
|
10
|
3962
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY fp_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_38s;
ARCHITECTURE rtl OF fp_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone + (zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 19));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_divnornd.vhd
|
10
|
4552
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_tanlut2.vhd
|
10
|
45103
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TANLUT2.VHD ***
--*** ***
--*** Function: Tangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_tanlut2 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_tanlut2;
ARCHITECTURE rtl OF fp_tanlut2 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(1024,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(2048,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(3072,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1,18);
WHEN "00000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(4096,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1,18);
WHEN "00000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(5120,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3,18);
WHEN "00000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(6144,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5,18);
WHEN "00000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(7168,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7,18);
WHEN "00001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(8192,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11,18);
WHEN "00001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(9216,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15,18);
WHEN "00001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(10240,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(21,18);
WHEN "00001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(11264,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(28,18);
WHEN "00001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(12288,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36,18);
WHEN "00001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(13312,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(46,18);
WHEN "00001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(14336,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(57,18);
WHEN "00001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(15360,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(70,18);
WHEN "00010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(16384,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(85,18);
WHEN "00010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(17408,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(102,18);
WHEN "00010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(18432,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(122,18);
WHEN "00010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(19456,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(143,18);
WHEN "00010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(20480,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(167,18);
WHEN "00010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(21504,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(193,18);
WHEN "00010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(22528,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(222,18);
WHEN "00010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(23552,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(253,18);
WHEN "00011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(24576,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(288,18);
WHEN "00011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(25600,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(326,18);
WHEN "00011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(26624,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(366,18);
WHEN "00011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(27648,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(410,18);
WHEN "00011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(28672,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(457,18);
WHEN "00011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(29696,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(508,18);
WHEN "00011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(30720,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(563,18);
WHEN "00011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(31744,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(621,18);
WHEN "00100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(32768,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(683,18);
WHEN "00100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(33792,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(749,18);
WHEN "00100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(34816,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(819,18);
WHEN "00100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(35840,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(893,18);
WHEN "00100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(36864,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(972,18);
WHEN "00100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(37888,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1055,18);
WHEN "00100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(38912,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1143,18);
WHEN "00100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(39936,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1236,18);
WHEN "00101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(40960,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1333,18);
WHEN "00101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(41984,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1436,18);
WHEN "00101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(43008,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1544,18);
WHEN "00101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(44032,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1656,18);
WHEN "00101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(45056,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1775,18);
WHEN "00101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(46080,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1898,18);
WHEN "00101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(47104,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2028,18);
WHEN "00101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(48128,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2163,18);
WHEN "00110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(49152,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2304,18);
WHEN "00110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(50176,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2451,18);
WHEN "00110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(51200,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2604,18);
WHEN "00110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(52224,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2764,18);
WHEN "00110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(53248,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2929,18);
WHEN "00110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(54272,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3102,18);
WHEN "00110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(55296,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3281,18);
WHEN "00110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(56320,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3466,18);
WHEN "00111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(57344,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3659,18);
WHEN "00111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(58368,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3858,18);
WHEN "00111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(59392,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4065,18);
WHEN "00111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(60416,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4279,18);
WHEN "00111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(61440,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4500,18);
WHEN "00111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(62464,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4729,18);
WHEN "00111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(63488,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4965,18);
WHEN "00111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(64512,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5209,18);
WHEN "01000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(65536,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5461,18);
WHEN "01000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(66560,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5721,18);
WHEN "01000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(67584,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5990,18);
WHEN "01000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(68608,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6266,18);
WHEN "01000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(69632,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6551,18);
WHEN "01000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(70656,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6844,18);
WHEN "01000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(71680,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7146,18);
WHEN "01000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(72704,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7456,18);
WHEN "01001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(73728,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7776,18);
WHEN "01001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(74752,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8105,18);
WHEN "01001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(75776,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8442,18);
WHEN "01001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(76800,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8789,18);
WHEN "01001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(77824,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9145,18);
WHEN "01001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(78848,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9511,18);
WHEN "01001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(79872,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9887,18);
WHEN "01001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(80896,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(10272,18);
WHEN "01010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(81920,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(10667,18);
WHEN "01010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(82944,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11072,18);
WHEN "01010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(83968,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11487,18);
WHEN "01010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(84992,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11912,18);
WHEN "01010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(86016,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(12348,18);
WHEN "01010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(87040,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(12794,18);
WHEN "01010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(88064,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(13251,18);
WHEN "01010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(89088,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(13719,18);
WHEN "01011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(90112,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(14197,18);
WHEN "01011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(91136,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(14687,18);
WHEN "01011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(92160,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15188,18);
WHEN "01011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(93184,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15699,18);
WHEN "01011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(94208,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(16223,18);
WHEN "01011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(95232,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(16757,18);
WHEN "01011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(96256,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(17304,18);
WHEN "01011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(97280,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(17862,18);
WHEN "01100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(98304,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(18432,18);
WHEN "01100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(99328,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(19014,18);
WHEN "01100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(100352,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(19608,18);
WHEN "01100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(101376,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(20215,18);
WHEN "01100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(102400,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(20833,18);
WHEN "01100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(103424,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(21465,18);
WHEN "01100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(104448,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22109,18);
WHEN "01100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(105472,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22765,18);
WHEN "01101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(106496,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(23435,18);
WHEN "01101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(107520,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(24117,18);
WHEN "01101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(108544,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(24813,18);
WHEN "01101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(109568,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(25522,18);
WHEN "01101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(110592,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(26244,18);
WHEN "01101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(111616,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(26980,18);
WHEN "01101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(112640,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(27729,18);
WHEN "01101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(113664,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(28492,18);
WHEN "01110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(114688,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(29269,18);
WHEN "01110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(115712,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(30060,18);
WHEN "01110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(116736,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(30866,18);
WHEN "01110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(117760,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(31685,18);
WHEN "01110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(118784,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(32519,18);
WHEN "01110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(119808,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(33367,18);
WHEN "01110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(120832,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(34230,18);
WHEN "01110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(121856,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(35108,18);
WHEN "01111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(122880,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36000,18);
WHEN "01111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(123904,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36908,18);
WHEN "01111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(124928,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(37830,18);
WHEN "01111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(125952,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(38768,18);
WHEN "01111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(126976,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(39721,18);
WHEN "01111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(128000,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(40690,18);
WHEN "01111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(129024,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(41675,18);
WHEN "01111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(130048,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(42675,18);
WHEN "10000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(131072,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(43691,18);
WHEN "10000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(132096,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(44723,18);
WHEN "10000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(133120,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(45771,18);
WHEN "10000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(134144,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(46835,18);
WHEN "10000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(135168,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(47916,18);
WHEN "10000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(136192,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(49013,18);
WHEN "10000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(137216,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(50127,18);
WHEN "10000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(138240,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(51258,18);
WHEN "10001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(139264,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(52405,18);
WHEN "10001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(140288,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(53570,18);
WHEN "10001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(141312,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(54752,18);
WHEN "10001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(142336,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(55950,18);
WHEN "10001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(143360,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(57167,18);
WHEN "10001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(144384,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(58401,18);
WHEN "10001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(145408,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(59652,18);
WHEN "10001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(146432,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(60921,18);
WHEN "10010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(147456,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(62208,18);
WHEN "10010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(148480,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(63513,18);
WHEN "10010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(149504,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(64836,18);
WHEN "10010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(150528,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(66178,18);
WHEN "10010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(151552,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(67537,18);
WHEN "10010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(152576,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(68916,18);
WHEN "10010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(153600,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(70313,18);
WHEN "10010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(154624,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(71728,18);
WHEN "10011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(155648,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(73163,18);
WHEN "10011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(156672,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(74616,18);
WHEN "10011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(157696,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(76089,18);
WHEN "10011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(158720,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(77581,18);
WHEN "10011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(159744,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(79092,18);
WHEN "10011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(160768,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(80623,18);
WHEN "10011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(161792,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(82173,18);
WHEN "10011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(162816,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(83744,18);
WHEN "10100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(163840,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(85334,18);
WHEN "10100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(164864,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(86944,18);
WHEN "10100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(165888,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(88574,18);
WHEN "10100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(166912,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(90224,18);
WHEN "10100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(167936,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(91895,18);
WHEN "10100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(168960,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(93586,18);
WHEN "10100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(169984,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(95298,18);
WHEN "10100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(171008,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(97031,18);
WHEN "10101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(172032,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(98784,18);
WHEN "10101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(173056,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(100559,18);
WHEN "10101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(174080,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(102354,18);
WHEN "10101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(175104,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(104171,18);
WHEN "10101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(176128,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(106010,18);
WHEN "10101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(177152,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(107869,18);
WHEN "10101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(178176,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(109751,18);
WHEN "10101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(179200,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(111654,18);
WHEN "10110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(180224,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(113579,18);
WHEN "10110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(181248,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(115526,18);
WHEN "10110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(182272,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(117495,18);
WHEN "10110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(183296,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(119487,18);
WHEN "10110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(184320,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(121500,18);
WHEN "10110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(185344,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(123537,18);
WHEN "10110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(186368,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(125596,18);
WHEN "10110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(187392,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(127677,18);
WHEN "10111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(188416,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(129782,18);
WHEN "10111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(189440,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(131909,18);
WHEN "10111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(190464,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(134060,18);
WHEN "10111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(191488,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(136234,18);
WHEN "10111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(192512,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(138431,18);
WHEN "10111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(193536,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(140652,18);
WHEN "10111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(194560,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(142896,18);
WHEN "10111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(195584,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(145164,18);
WHEN "11000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(196608,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(147457,18);
WHEN "11000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(197632,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(149773,18);
WHEN "11000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(198656,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(152113,18);
WHEN "11000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(199680,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(154477,18);
WHEN "11000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(200704,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(156866,18);
WHEN "11000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(201728,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(159279,18);
WHEN "11000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(202752,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(161717,18);
WHEN "11000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(203776,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(164180,18);
WHEN "11001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(204800,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(166667,18);
WHEN "11001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(205824,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(169180,18);
WHEN "11001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(206848,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(171717,18);
WHEN "11001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(207872,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(174280,18);
WHEN "11001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(208896,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(176869,18);
WHEN "11001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(209920,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(179482,18);
WHEN "11001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(210944,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(182122,18);
WHEN "11001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(211968,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(184787,18);
WHEN "11010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(212992,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(187478,18);
WHEN "11010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(214016,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(190195,18);
WHEN "11010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(215040,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(192938,18);
WHEN "11010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(216064,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(195708,18);
WHEN "11010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(217088,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(198503,18);
WHEN "11010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(218112,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(201326,18);
WHEN "11010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(219136,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(204175,18);
WHEN "11010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(220160,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(207050,18);
WHEN "11011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(221184,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(209953,18);
WHEN "11011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(222208,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(212882,18);
WHEN "11011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(223232,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(215839,18);
WHEN "11011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(224256,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(218823,18);
WHEN "11011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(225280,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(221834,18);
WHEN "11011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(226304,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(224873,18);
WHEN "11011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(227328,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(227940,18);
WHEN "11011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(228352,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(231034,18);
WHEN "11100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(229376,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(234156,18);
WHEN "11100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(230400,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(237306,18);
WHEN "11100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(231424,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(240484,18);
WHEN "11100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(232448,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(243690,18);
WHEN "11100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(233472,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(246925,18);
WHEN "11100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(234496,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(250188,18);
WHEN "11100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(235520,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(253480,18);
WHEN "11100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(236544,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(256801,18);
WHEN "11101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(237568,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(260151,18);
WHEN "11101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(238593,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1385,18);
WHEN "11101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(239617,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4793,18);
WHEN "11101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(240641,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8230,18);
WHEN "11101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(241665,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11696,18);
WHEN "11101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(242689,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15192,18);
WHEN "11101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(243713,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(18717,18);
WHEN "11101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(244737,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22272,18);
WHEN "11110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(245761,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(25858,18);
WHEN "11110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(246785,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(29473,18);
WHEN "11110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(247809,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(33118,18);
WHEN "11110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(248833,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36793,18);
WHEN "11110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(249857,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(40499,18);
WHEN "11110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(250881,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(44235,18);
WHEN "11110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(251905,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(48002,18);
WHEN "11110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(252929,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(51800,18);
WHEN "11111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(253953,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(55628,18);
WHEN "11111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(254977,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(59488,18);
WHEN "11111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(256001,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(63379,18);
WHEN "11111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(257025,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(67301,18);
WHEN "11111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(258049,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(71254,18);
WHEN "11111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(259073,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(75239,18);
WHEN "11111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(260097,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(79255,18);
WHEN "11111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(261121,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(83303,18);
WHEN others =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_cos.vhd
|
10
|
12425
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/dp_explut10.vhd
|
10
|
174445
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_package_sv.vhd
|
10
|
22851
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/sgm_fpmm64.vhd
|
10
|
118317
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY sgm_fpmm64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END sgm_fpmm64;
ARCHITECTURE gen OF sgm_fpmm64 IS
COMPONENT hcc_mulfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_alufp1x
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
COMPONENT hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
signal dp00 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp01 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp02 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp03 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp04 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp05 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp06 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp07 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal mid00 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal mid01 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0001 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0002 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0003 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0004 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0005 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0006 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0007 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0008 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0009 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0010 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0011 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0012 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0013 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0014 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0015 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0016 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0017 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0018 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0019 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0020 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0021 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0022 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0023 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0024 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0025 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0026 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0027 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0028 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0029 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0030 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0031 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0032 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0033 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0034 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0035 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0036 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0037 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0038 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0039 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0040 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0041 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0042 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0043 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0044 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0045 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0046 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0047 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0048 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0049 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0050 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0051 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0052 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0053 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0054 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0055 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0056 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0057 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0058 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0059 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0060 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0061 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0062 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0063 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0064 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0065 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0066 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0067 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0068 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0069 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0070 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0071 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0072 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0073 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0074 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0075 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0076 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0077 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0078 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0079 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0080 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0081 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0082 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0083 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0084 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0085 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0086 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0087 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0088 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0089 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0090 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0091 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0092 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0093 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0094 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0095 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0096 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0097 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0098 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0099 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0100 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0101 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0102 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0103 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0104 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0105 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0106 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0107 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0108 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0109 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0110 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0111 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0112 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0113 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0114 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0115 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0116 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0117 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0118 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0119 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0120 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0121 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0122 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0123 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0124 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0125 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0126 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0127 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0128 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0129 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0130 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0131 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0132 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0133 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0134 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0135 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0136 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0137 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0138 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0139 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0140 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0141 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0142 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0143 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0144 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0145 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0146 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0147 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0148 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0149 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0150 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0151 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0152 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0153 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0154 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0155 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0156 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0157 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0158 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0159 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0160 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0161 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0162 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0163 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0164 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0165 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0166 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0167 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0168 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0169 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0170 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0171 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0172 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0173 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0174 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0175 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0176 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0177 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0178 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0179 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0180 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0181 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0182 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0183 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0184 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0185 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0186 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0187 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0188 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0189 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0190 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0191 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0192 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0193 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0194 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0195 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0196 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0197 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0198 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0199 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0200 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0201 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0202 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0203 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0204 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0205 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0206 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0207 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0208 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0209 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0210 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0211 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0212 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0213 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0214 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0215 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0216 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0217 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0218 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0219 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0220 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0221 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0222 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0223 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0224 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0225 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0226 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0227 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0228 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0229 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0230 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0231 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0232 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0233 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0234 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0235 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0236 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0237 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0238 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0239 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0240 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0241 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0242 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0243 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0244 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0245 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0246 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0247 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0248 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0249 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0250 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0251 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0252 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0253 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0254 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0255 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0256 : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal synth0257 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0258 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0259 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0260 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0261 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0262 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0263 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0264 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal startff : STD_LOGIC_VECTOR (46 DOWNTO 1);
BEGIN
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 46 LOOP
startff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
startff(1) <= startin;
FOR k IN 2 TO 46 LOOP
startff(k) <= startff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
dp00 <= synth0015;
dp01 <= synth0030;
dp02 <= synth0045;
dp03 <= synth0060;
dp04 <= synth0075;
dp05 <= synth0090;
dp06 <= synth0105;
dp07 <= synth0120;
mid00 <= synth0123;
mid01 <= synth0126;
cmp0: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0135(42 DOWNTO 1),
aasat=>castx0135(43),aazip=>castx0135(44),
bb=>castx0199(42 DOWNTO 1),
bbsat=>castx0199(43),bbzip=>castx0199(44),
cc=>synth0001(42 DOWNTO 1),
ccsat=>synth0001(43),cczip=>synth0001(44));
cmp1: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0134(42 DOWNTO 1),
aasat=>castx0134(43),aazip=>castx0134(44),
bb=>castx0198(42 DOWNTO 1),
bbsat=>castx0198(43),bbzip=>castx0198(44),
cc=>synth0002(42 DOWNTO 1),
ccsat=>synth0002(43),cczip=>synth0002(44));
cmp2: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0133(42 DOWNTO 1),
aasat=>castx0133(43),aazip=>castx0133(44),
bb=>castx0197(42 DOWNTO 1),
bbsat=>castx0197(43),bbzip=>castx0197(44),
cc=>synth0003(42 DOWNTO 1),
ccsat=>synth0003(43),cczip=>synth0003(44));
cmp3: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0132(42 DOWNTO 1),
aasat=>castx0132(43),aazip=>castx0132(44),
bb=>castx0196(42 DOWNTO 1),
bbsat=>castx0196(43),bbzip=>castx0196(44),
cc=>synth0004(42 DOWNTO 1),
ccsat=>synth0004(43),cczip=>synth0004(44));
cmp4: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0131(42 DOWNTO 1),
aasat=>castx0131(43),aazip=>castx0131(44),
bb=>castx0195(42 DOWNTO 1),
bbsat=>castx0195(43),bbzip=>castx0195(44),
cc=>synth0005(42 DOWNTO 1),
ccsat=>synth0005(43),cczip=>synth0005(44));
cmp5: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0130(42 DOWNTO 1),
aasat=>castx0130(43),aazip=>castx0130(44),
bb=>castx0194(42 DOWNTO 1),
bbsat=>castx0194(43),bbzip=>castx0194(44),
cc=>synth0006(42 DOWNTO 1),
ccsat=>synth0006(43),cczip=>synth0006(44));
cmp6: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0129(42 DOWNTO 1),
aasat=>castx0129(43),aazip=>castx0129(44),
bb=>castx0193(42 DOWNTO 1),
bbsat=>castx0193(43),bbzip=>castx0193(44),
cc=>synth0007(42 DOWNTO 1),
ccsat=>synth0007(43),cczip=>synth0007(44));
cmp7: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0128(42 DOWNTO 1),
aasat=>castx0128(43),aazip=>castx0128(44),
bb=>castx0192(42 DOWNTO 1),
bbsat=>castx0192(43),bbzip=>castx0192(44),
cc=>synth0008(42 DOWNTO 1),
ccsat=>synth0008(43),cczip=>synth0008(44));
cmp8: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0002(42 DOWNTO 1),
aasat=>synth0002(43),aazip=>synth0002(44),
bb=>synth0001(42 DOWNTO 1),
bbsat=>synth0001(43),bbzip=>synth0001(44),
cc=>synth0009(42 DOWNTO 1),
ccsat=>synth0009(43),cczip=>synth0009(44));
cmp9: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0004(42 DOWNTO 1),
aasat=>synth0004(43),aazip=>synth0004(44),
bb=>synth0003(42 DOWNTO 1),
bbsat=>synth0003(43),bbzip=>synth0003(44),
cc=>synth0010(42 DOWNTO 1),
ccsat=>synth0010(43),cczip=>synth0010(44));
cmp10: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0006(42 DOWNTO 1),
aasat=>synth0006(43),aazip=>synth0006(44),
bb=>synth0005(42 DOWNTO 1),
bbsat=>synth0005(43),bbzip=>synth0005(44),
cc=>synth0011(42 DOWNTO 1),
ccsat=>synth0011(43),cczip=>synth0011(44));
cmp11: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0008(42 DOWNTO 1),
aasat=>synth0008(43),aazip=>synth0008(44),
bb=>synth0007(42 DOWNTO 1),
bbsat=>synth0007(43),bbzip=>synth0007(44),
cc=>synth0012(42 DOWNTO 1),
ccsat=>synth0012(43),cczip=>synth0012(44));
cmp12: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0010(42 DOWNTO 1),
aasat=>synth0010(43),aazip=>synth0010(44),
bb=>synth0009(42 DOWNTO 1),
bbsat=>synth0009(43),bbzip=>synth0009(44),
cc=>synth0013(42 DOWNTO 1),
ccsat=>synth0013(43),cczip=>synth0013(44));
cmp13: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0012(42 DOWNTO 1),
aasat=>synth0012(43),aazip=>synth0012(44),
bb=>synth0011(42 DOWNTO 1),
bbsat=>synth0011(43),bbzip=>synth0011(44),
cc=>synth0014(42 DOWNTO 1),
ccsat=>synth0014(43),cczip=>synth0014(44));
cmp14: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0014(42 DOWNTO 1),
aasat=>synth0014(43),aazip=>synth0014(44),
bb=>synth0013(42 DOWNTO 1),
bbsat=>synth0013(43),bbzip=>synth0013(44),
cc=>synth0015(42 DOWNTO 1),
ccsat=>synth0015(43),cczip=>synth0015(44));
cmp15: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0143(42 DOWNTO 1),
aasat=>castx0143(43),aazip=>castx0143(44),
bb=>castx0207(42 DOWNTO 1),
bbsat=>castx0207(43),bbzip=>castx0207(44),
cc=>synth0016(42 DOWNTO 1),
ccsat=>synth0016(43),cczip=>synth0016(44));
cmp16: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0142(42 DOWNTO 1),
aasat=>castx0142(43),aazip=>castx0142(44),
bb=>castx0206(42 DOWNTO 1),
bbsat=>castx0206(43),bbzip=>castx0206(44),
cc=>synth0017(42 DOWNTO 1),
ccsat=>synth0017(43),cczip=>synth0017(44));
cmp17: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0141(42 DOWNTO 1),
aasat=>castx0141(43),aazip=>castx0141(44),
bb=>castx0205(42 DOWNTO 1),
bbsat=>castx0205(43),bbzip=>castx0205(44),
cc=>synth0018(42 DOWNTO 1),
ccsat=>synth0018(43),cczip=>synth0018(44));
cmp18: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0140(42 DOWNTO 1),
aasat=>castx0140(43),aazip=>castx0140(44),
bb=>castx0204(42 DOWNTO 1),
bbsat=>castx0204(43),bbzip=>castx0204(44),
cc=>synth0019(42 DOWNTO 1),
ccsat=>synth0019(43),cczip=>synth0019(44));
cmp19: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0139(42 DOWNTO 1),
aasat=>castx0139(43),aazip=>castx0139(44),
bb=>castx0203(42 DOWNTO 1),
bbsat=>castx0203(43),bbzip=>castx0203(44),
cc=>synth0020(42 DOWNTO 1),
ccsat=>synth0020(43),cczip=>synth0020(44));
cmp20: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0138(42 DOWNTO 1),
aasat=>castx0138(43),aazip=>castx0138(44),
bb=>castx0202(42 DOWNTO 1),
bbsat=>castx0202(43),bbzip=>castx0202(44),
cc=>synth0021(42 DOWNTO 1),
ccsat=>synth0021(43),cczip=>synth0021(44));
cmp21: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0137(42 DOWNTO 1),
aasat=>castx0137(43),aazip=>castx0137(44),
bb=>castx0201(42 DOWNTO 1),
bbsat=>castx0201(43),bbzip=>castx0201(44),
cc=>synth0022(42 DOWNTO 1),
ccsat=>synth0022(43),cczip=>synth0022(44));
cmp22: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0136(42 DOWNTO 1),
aasat=>castx0136(43),aazip=>castx0136(44),
bb=>castx0200(42 DOWNTO 1),
bbsat=>castx0200(43),bbzip=>castx0200(44),
cc=>synth0023(42 DOWNTO 1),
ccsat=>synth0023(43),cczip=>synth0023(44));
cmp23: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0017(42 DOWNTO 1),
aasat=>synth0017(43),aazip=>synth0017(44),
bb=>synth0016(42 DOWNTO 1),
bbsat=>synth0016(43),bbzip=>synth0016(44),
cc=>synth0024(42 DOWNTO 1),
ccsat=>synth0024(43),cczip=>synth0024(44));
cmp24: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0019(42 DOWNTO 1),
aasat=>synth0019(43),aazip=>synth0019(44),
bb=>synth0018(42 DOWNTO 1),
bbsat=>synth0018(43),bbzip=>synth0018(44),
cc=>synth0025(42 DOWNTO 1),
ccsat=>synth0025(43),cczip=>synth0025(44));
cmp25: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0021(42 DOWNTO 1),
aasat=>synth0021(43),aazip=>synth0021(44),
bb=>synth0020(42 DOWNTO 1),
bbsat=>synth0020(43),bbzip=>synth0020(44),
cc=>synth0026(42 DOWNTO 1),
ccsat=>synth0026(43),cczip=>synth0026(44));
cmp26: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0023(42 DOWNTO 1),
aasat=>synth0023(43),aazip=>synth0023(44),
bb=>synth0022(42 DOWNTO 1),
bbsat=>synth0022(43),bbzip=>synth0022(44),
cc=>synth0027(42 DOWNTO 1),
ccsat=>synth0027(43),cczip=>synth0027(44));
cmp27: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0025(42 DOWNTO 1),
aasat=>synth0025(43),aazip=>synth0025(44),
bb=>synth0024(42 DOWNTO 1),
bbsat=>synth0024(43),bbzip=>synth0024(44),
cc=>synth0028(42 DOWNTO 1),
ccsat=>synth0028(43),cczip=>synth0028(44));
cmp28: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0027(42 DOWNTO 1),
aasat=>synth0027(43),aazip=>synth0027(44),
bb=>synth0026(42 DOWNTO 1),
bbsat=>synth0026(43),bbzip=>synth0026(44),
cc=>synth0029(42 DOWNTO 1),
ccsat=>synth0029(43),cczip=>synth0029(44));
cmp29: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0029(42 DOWNTO 1),
aasat=>synth0029(43),aazip=>synth0029(44),
bb=>synth0028(42 DOWNTO 1),
bbsat=>synth0028(43),bbzip=>synth0028(44),
cc=>synth0030(42 DOWNTO 1),
ccsat=>synth0030(43),cczip=>synth0030(44));
cmp30: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0151(42 DOWNTO 1),
aasat=>castx0151(43),aazip=>castx0151(44),
bb=>castx0215(42 DOWNTO 1),
bbsat=>castx0215(43),bbzip=>castx0215(44),
cc=>synth0031(42 DOWNTO 1),
ccsat=>synth0031(43),cczip=>synth0031(44));
cmp31: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0150(42 DOWNTO 1),
aasat=>castx0150(43),aazip=>castx0150(44),
bb=>castx0214(42 DOWNTO 1),
bbsat=>castx0214(43),bbzip=>castx0214(44),
cc=>synth0032(42 DOWNTO 1),
ccsat=>synth0032(43),cczip=>synth0032(44));
cmp32: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0149(42 DOWNTO 1),
aasat=>castx0149(43),aazip=>castx0149(44),
bb=>castx0213(42 DOWNTO 1),
bbsat=>castx0213(43),bbzip=>castx0213(44),
cc=>synth0033(42 DOWNTO 1),
ccsat=>synth0033(43),cczip=>synth0033(44));
cmp33: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0148(42 DOWNTO 1),
aasat=>castx0148(43),aazip=>castx0148(44),
bb=>castx0212(42 DOWNTO 1),
bbsat=>castx0212(43),bbzip=>castx0212(44),
cc=>synth0034(42 DOWNTO 1),
ccsat=>synth0034(43),cczip=>synth0034(44));
cmp34: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0147(42 DOWNTO 1),
aasat=>castx0147(43),aazip=>castx0147(44),
bb=>castx0211(42 DOWNTO 1),
bbsat=>castx0211(43),bbzip=>castx0211(44),
cc=>synth0035(42 DOWNTO 1),
ccsat=>synth0035(43),cczip=>synth0035(44));
cmp35: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0146(42 DOWNTO 1),
aasat=>castx0146(43),aazip=>castx0146(44),
bb=>castx0210(42 DOWNTO 1),
bbsat=>castx0210(43),bbzip=>castx0210(44),
cc=>synth0036(42 DOWNTO 1),
ccsat=>synth0036(43),cczip=>synth0036(44));
cmp36: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0145(42 DOWNTO 1),
aasat=>castx0145(43),aazip=>castx0145(44),
bb=>castx0209(42 DOWNTO 1),
bbsat=>castx0209(43),bbzip=>castx0209(44),
cc=>synth0037(42 DOWNTO 1),
ccsat=>synth0037(43),cczip=>synth0037(44));
cmp37: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0144(42 DOWNTO 1),
aasat=>castx0144(43),aazip=>castx0144(44),
bb=>castx0208(42 DOWNTO 1),
bbsat=>castx0208(43),bbzip=>castx0208(44),
cc=>synth0038(42 DOWNTO 1),
ccsat=>synth0038(43),cczip=>synth0038(44));
cmp38: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0032(42 DOWNTO 1),
aasat=>synth0032(43),aazip=>synth0032(44),
bb=>synth0031(42 DOWNTO 1),
bbsat=>synth0031(43),bbzip=>synth0031(44),
cc=>synth0039(42 DOWNTO 1),
ccsat=>synth0039(43),cczip=>synth0039(44));
cmp39: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0034(42 DOWNTO 1),
aasat=>synth0034(43),aazip=>synth0034(44),
bb=>synth0033(42 DOWNTO 1),
bbsat=>synth0033(43),bbzip=>synth0033(44),
cc=>synth0040(42 DOWNTO 1),
ccsat=>synth0040(43),cczip=>synth0040(44));
cmp40: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0036(42 DOWNTO 1),
aasat=>synth0036(43),aazip=>synth0036(44),
bb=>synth0035(42 DOWNTO 1),
bbsat=>synth0035(43),bbzip=>synth0035(44),
cc=>synth0041(42 DOWNTO 1),
ccsat=>synth0041(43),cczip=>synth0041(44));
cmp41: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0038(42 DOWNTO 1),
aasat=>synth0038(43),aazip=>synth0038(44),
bb=>synth0037(42 DOWNTO 1),
bbsat=>synth0037(43),bbzip=>synth0037(44),
cc=>synth0042(42 DOWNTO 1),
ccsat=>synth0042(43),cczip=>synth0042(44));
cmp42: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0040(42 DOWNTO 1),
aasat=>synth0040(43),aazip=>synth0040(44),
bb=>synth0039(42 DOWNTO 1),
bbsat=>synth0039(43),bbzip=>synth0039(44),
cc=>synth0043(42 DOWNTO 1),
ccsat=>synth0043(43),cczip=>synth0043(44));
cmp43: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0042(42 DOWNTO 1),
aasat=>synth0042(43),aazip=>synth0042(44),
bb=>synth0041(42 DOWNTO 1),
bbsat=>synth0041(43),bbzip=>synth0041(44),
cc=>synth0044(42 DOWNTO 1),
ccsat=>synth0044(43),cczip=>synth0044(44));
cmp44: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0044(42 DOWNTO 1),
aasat=>synth0044(43),aazip=>synth0044(44),
bb=>synth0043(42 DOWNTO 1),
bbsat=>synth0043(43),bbzip=>synth0043(44),
cc=>synth0045(42 DOWNTO 1),
ccsat=>synth0045(43),cczip=>synth0045(44));
cmp45: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0159(42 DOWNTO 1),
aasat=>castx0159(43),aazip=>castx0159(44),
bb=>castx0223(42 DOWNTO 1),
bbsat=>castx0223(43),bbzip=>castx0223(44),
cc=>synth0046(42 DOWNTO 1),
ccsat=>synth0046(43),cczip=>synth0046(44));
cmp46: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0158(42 DOWNTO 1),
aasat=>castx0158(43),aazip=>castx0158(44),
bb=>castx0222(42 DOWNTO 1),
bbsat=>castx0222(43),bbzip=>castx0222(44),
cc=>synth0047(42 DOWNTO 1),
ccsat=>synth0047(43),cczip=>synth0047(44));
cmp47: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0157(42 DOWNTO 1),
aasat=>castx0157(43),aazip=>castx0157(44),
bb=>castx0221(42 DOWNTO 1),
bbsat=>castx0221(43),bbzip=>castx0221(44),
cc=>synth0048(42 DOWNTO 1),
ccsat=>synth0048(43),cczip=>synth0048(44));
cmp48: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0156(42 DOWNTO 1),
aasat=>castx0156(43),aazip=>castx0156(44),
bb=>castx0220(42 DOWNTO 1),
bbsat=>castx0220(43),bbzip=>castx0220(44),
cc=>synth0049(42 DOWNTO 1),
ccsat=>synth0049(43),cczip=>synth0049(44));
cmp49: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0155(42 DOWNTO 1),
aasat=>castx0155(43),aazip=>castx0155(44),
bb=>castx0219(42 DOWNTO 1),
bbsat=>castx0219(43),bbzip=>castx0219(44),
cc=>synth0050(42 DOWNTO 1),
ccsat=>synth0050(43),cczip=>synth0050(44));
cmp50: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0154(42 DOWNTO 1),
aasat=>castx0154(43),aazip=>castx0154(44),
bb=>castx0218(42 DOWNTO 1),
bbsat=>castx0218(43),bbzip=>castx0218(44),
cc=>synth0051(42 DOWNTO 1),
ccsat=>synth0051(43),cczip=>synth0051(44));
cmp51: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0153(42 DOWNTO 1),
aasat=>castx0153(43),aazip=>castx0153(44),
bb=>castx0217(42 DOWNTO 1),
bbsat=>castx0217(43),bbzip=>castx0217(44),
cc=>synth0052(42 DOWNTO 1),
ccsat=>synth0052(43),cczip=>synth0052(44));
cmp52: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0152(42 DOWNTO 1),
aasat=>castx0152(43),aazip=>castx0152(44),
bb=>castx0216(42 DOWNTO 1),
bbsat=>castx0216(43),bbzip=>castx0216(44),
cc=>synth0053(42 DOWNTO 1),
ccsat=>synth0053(43),cczip=>synth0053(44));
cmp53: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0047(42 DOWNTO 1),
aasat=>synth0047(43),aazip=>synth0047(44),
bb=>synth0046(42 DOWNTO 1),
bbsat=>synth0046(43),bbzip=>synth0046(44),
cc=>synth0054(42 DOWNTO 1),
ccsat=>synth0054(43),cczip=>synth0054(44));
cmp54: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0049(42 DOWNTO 1),
aasat=>synth0049(43),aazip=>synth0049(44),
bb=>synth0048(42 DOWNTO 1),
bbsat=>synth0048(43),bbzip=>synth0048(44),
cc=>synth0055(42 DOWNTO 1),
ccsat=>synth0055(43),cczip=>synth0055(44));
cmp55: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0051(42 DOWNTO 1),
aasat=>synth0051(43),aazip=>synth0051(44),
bb=>synth0050(42 DOWNTO 1),
bbsat=>synth0050(43),bbzip=>synth0050(44),
cc=>synth0056(42 DOWNTO 1),
ccsat=>synth0056(43),cczip=>synth0056(44));
cmp56: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0053(42 DOWNTO 1),
aasat=>synth0053(43),aazip=>synth0053(44),
bb=>synth0052(42 DOWNTO 1),
bbsat=>synth0052(43),bbzip=>synth0052(44),
cc=>synth0057(42 DOWNTO 1),
ccsat=>synth0057(43),cczip=>synth0057(44));
cmp57: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0055(42 DOWNTO 1),
aasat=>synth0055(43),aazip=>synth0055(44),
bb=>synth0054(42 DOWNTO 1),
bbsat=>synth0054(43),bbzip=>synth0054(44),
cc=>synth0058(42 DOWNTO 1),
ccsat=>synth0058(43),cczip=>synth0058(44));
cmp58: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0057(42 DOWNTO 1),
aasat=>synth0057(43),aazip=>synth0057(44),
bb=>synth0056(42 DOWNTO 1),
bbsat=>synth0056(43),bbzip=>synth0056(44),
cc=>synth0059(42 DOWNTO 1),
ccsat=>synth0059(43),cczip=>synth0059(44));
cmp59: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0059(42 DOWNTO 1),
aasat=>synth0059(43),aazip=>synth0059(44),
bb=>synth0058(42 DOWNTO 1),
bbsat=>synth0058(43),bbzip=>synth0058(44),
cc=>synth0060(42 DOWNTO 1),
ccsat=>synth0060(43),cczip=>synth0060(44));
cmp60: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0167(42 DOWNTO 1),
aasat=>castx0167(43),aazip=>castx0167(44),
bb=>castx0231(42 DOWNTO 1),
bbsat=>castx0231(43),bbzip=>castx0231(44),
cc=>synth0061(42 DOWNTO 1),
ccsat=>synth0061(43),cczip=>synth0061(44));
cmp61: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0166(42 DOWNTO 1),
aasat=>castx0166(43),aazip=>castx0166(44),
bb=>castx0230(42 DOWNTO 1),
bbsat=>castx0230(43),bbzip=>castx0230(44),
cc=>synth0062(42 DOWNTO 1),
ccsat=>synth0062(43),cczip=>synth0062(44));
cmp62: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0165(42 DOWNTO 1),
aasat=>castx0165(43),aazip=>castx0165(44),
bb=>castx0229(42 DOWNTO 1),
bbsat=>castx0229(43),bbzip=>castx0229(44),
cc=>synth0063(42 DOWNTO 1),
ccsat=>synth0063(43),cczip=>synth0063(44));
cmp63: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0164(42 DOWNTO 1),
aasat=>castx0164(43),aazip=>castx0164(44),
bb=>castx0228(42 DOWNTO 1),
bbsat=>castx0228(43),bbzip=>castx0228(44),
cc=>synth0064(42 DOWNTO 1),
ccsat=>synth0064(43),cczip=>synth0064(44));
cmp64: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0163(42 DOWNTO 1),
aasat=>castx0163(43),aazip=>castx0163(44),
bb=>castx0227(42 DOWNTO 1),
bbsat=>castx0227(43),bbzip=>castx0227(44),
cc=>synth0065(42 DOWNTO 1),
ccsat=>synth0065(43),cczip=>synth0065(44));
cmp65: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0162(42 DOWNTO 1),
aasat=>castx0162(43),aazip=>castx0162(44),
bb=>castx0226(42 DOWNTO 1),
bbsat=>castx0226(43),bbzip=>castx0226(44),
cc=>synth0066(42 DOWNTO 1),
ccsat=>synth0066(43),cczip=>synth0066(44));
cmp66: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0161(42 DOWNTO 1),
aasat=>castx0161(43),aazip=>castx0161(44),
bb=>castx0225(42 DOWNTO 1),
bbsat=>castx0225(43),bbzip=>castx0225(44),
cc=>synth0067(42 DOWNTO 1),
ccsat=>synth0067(43),cczip=>synth0067(44));
cmp67: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0160(42 DOWNTO 1),
aasat=>castx0160(43),aazip=>castx0160(44),
bb=>castx0224(42 DOWNTO 1),
bbsat=>castx0224(43),bbzip=>castx0224(44),
cc=>synth0068(42 DOWNTO 1),
ccsat=>synth0068(43),cczip=>synth0068(44));
cmp68: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0062(42 DOWNTO 1),
aasat=>synth0062(43),aazip=>synth0062(44),
bb=>synth0061(42 DOWNTO 1),
bbsat=>synth0061(43),bbzip=>synth0061(44),
cc=>synth0069(42 DOWNTO 1),
ccsat=>synth0069(43),cczip=>synth0069(44));
cmp69: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0064(42 DOWNTO 1),
aasat=>synth0064(43),aazip=>synth0064(44),
bb=>synth0063(42 DOWNTO 1),
bbsat=>synth0063(43),bbzip=>synth0063(44),
cc=>synth0070(42 DOWNTO 1),
ccsat=>synth0070(43),cczip=>synth0070(44));
cmp70: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0066(42 DOWNTO 1),
aasat=>synth0066(43),aazip=>synth0066(44),
bb=>synth0065(42 DOWNTO 1),
bbsat=>synth0065(43),bbzip=>synth0065(44),
cc=>synth0071(42 DOWNTO 1),
ccsat=>synth0071(43),cczip=>synth0071(44));
cmp71: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0068(42 DOWNTO 1),
aasat=>synth0068(43),aazip=>synth0068(44),
bb=>synth0067(42 DOWNTO 1),
bbsat=>synth0067(43),bbzip=>synth0067(44),
cc=>synth0072(42 DOWNTO 1),
ccsat=>synth0072(43),cczip=>synth0072(44));
cmp72: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0070(42 DOWNTO 1),
aasat=>synth0070(43),aazip=>synth0070(44),
bb=>synth0069(42 DOWNTO 1),
bbsat=>synth0069(43),bbzip=>synth0069(44),
cc=>synth0073(42 DOWNTO 1),
ccsat=>synth0073(43),cczip=>synth0073(44));
cmp73: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0072(42 DOWNTO 1),
aasat=>synth0072(43),aazip=>synth0072(44),
bb=>synth0071(42 DOWNTO 1),
bbsat=>synth0071(43),bbzip=>synth0071(44),
cc=>synth0074(42 DOWNTO 1),
ccsat=>synth0074(43),cczip=>synth0074(44));
cmp74: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0074(42 DOWNTO 1),
aasat=>synth0074(43),aazip=>synth0074(44),
bb=>synth0073(42 DOWNTO 1),
bbsat=>synth0073(43),bbzip=>synth0073(44),
cc=>synth0075(42 DOWNTO 1),
ccsat=>synth0075(43),cczip=>synth0075(44));
cmp75: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0175(42 DOWNTO 1),
aasat=>castx0175(43),aazip=>castx0175(44),
bb=>castx0239(42 DOWNTO 1),
bbsat=>castx0239(43),bbzip=>castx0239(44),
cc=>synth0076(42 DOWNTO 1),
ccsat=>synth0076(43),cczip=>synth0076(44));
cmp76: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0174(42 DOWNTO 1),
aasat=>castx0174(43),aazip=>castx0174(44),
bb=>castx0238(42 DOWNTO 1),
bbsat=>castx0238(43),bbzip=>castx0238(44),
cc=>synth0077(42 DOWNTO 1),
ccsat=>synth0077(43),cczip=>synth0077(44));
cmp77: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0173(42 DOWNTO 1),
aasat=>castx0173(43),aazip=>castx0173(44),
bb=>castx0237(42 DOWNTO 1),
bbsat=>castx0237(43),bbzip=>castx0237(44),
cc=>synth0078(42 DOWNTO 1),
ccsat=>synth0078(43),cczip=>synth0078(44));
cmp78: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0172(42 DOWNTO 1),
aasat=>castx0172(43),aazip=>castx0172(44),
bb=>castx0236(42 DOWNTO 1),
bbsat=>castx0236(43),bbzip=>castx0236(44),
cc=>synth0079(42 DOWNTO 1),
ccsat=>synth0079(43),cczip=>synth0079(44));
cmp79: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0171(42 DOWNTO 1),
aasat=>castx0171(43),aazip=>castx0171(44),
bb=>castx0235(42 DOWNTO 1),
bbsat=>castx0235(43),bbzip=>castx0235(44),
cc=>synth0080(42 DOWNTO 1),
ccsat=>synth0080(43),cczip=>synth0080(44));
cmp80: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0170(42 DOWNTO 1),
aasat=>castx0170(43),aazip=>castx0170(44),
bb=>castx0234(42 DOWNTO 1),
bbsat=>castx0234(43),bbzip=>castx0234(44),
cc=>synth0081(42 DOWNTO 1),
ccsat=>synth0081(43),cczip=>synth0081(44));
cmp81: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0169(42 DOWNTO 1),
aasat=>castx0169(43),aazip=>castx0169(44),
bb=>castx0233(42 DOWNTO 1),
bbsat=>castx0233(43),bbzip=>castx0233(44),
cc=>synth0082(42 DOWNTO 1),
ccsat=>synth0082(43),cczip=>synth0082(44));
cmp82: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0168(42 DOWNTO 1),
aasat=>castx0168(43),aazip=>castx0168(44),
bb=>castx0232(42 DOWNTO 1),
bbsat=>castx0232(43),bbzip=>castx0232(44),
cc=>synth0083(42 DOWNTO 1),
ccsat=>synth0083(43),cczip=>synth0083(44));
cmp83: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0077(42 DOWNTO 1),
aasat=>synth0077(43),aazip=>synth0077(44),
bb=>synth0076(42 DOWNTO 1),
bbsat=>synth0076(43),bbzip=>synth0076(44),
cc=>synth0084(42 DOWNTO 1),
ccsat=>synth0084(43),cczip=>synth0084(44));
cmp84: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0079(42 DOWNTO 1),
aasat=>synth0079(43),aazip=>synth0079(44),
bb=>synth0078(42 DOWNTO 1),
bbsat=>synth0078(43),bbzip=>synth0078(44),
cc=>synth0085(42 DOWNTO 1),
ccsat=>synth0085(43),cczip=>synth0085(44));
cmp85: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0081(42 DOWNTO 1),
aasat=>synth0081(43),aazip=>synth0081(44),
bb=>synth0080(42 DOWNTO 1),
bbsat=>synth0080(43),bbzip=>synth0080(44),
cc=>synth0086(42 DOWNTO 1),
ccsat=>synth0086(43),cczip=>synth0086(44));
cmp86: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0083(42 DOWNTO 1),
aasat=>synth0083(43),aazip=>synth0083(44),
bb=>synth0082(42 DOWNTO 1),
bbsat=>synth0082(43),bbzip=>synth0082(44),
cc=>synth0087(42 DOWNTO 1),
ccsat=>synth0087(43),cczip=>synth0087(44));
cmp87: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0085(42 DOWNTO 1),
aasat=>synth0085(43),aazip=>synth0085(44),
bb=>synth0084(42 DOWNTO 1),
bbsat=>synth0084(43),bbzip=>synth0084(44),
cc=>synth0088(42 DOWNTO 1),
ccsat=>synth0088(43),cczip=>synth0088(44));
cmp88: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0087(42 DOWNTO 1),
aasat=>synth0087(43),aazip=>synth0087(44),
bb=>synth0086(42 DOWNTO 1),
bbsat=>synth0086(43),bbzip=>synth0086(44),
cc=>synth0089(42 DOWNTO 1),
ccsat=>synth0089(43),cczip=>synth0089(44));
cmp89: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0089(42 DOWNTO 1),
aasat=>synth0089(43),aazip=>synth0089(44),
bb=>synth0088(42 DOWNTO 1),
bbsat=>synth0088(43),bbzip=>synth0088(44),
cc=>synth0090(42 DOWNTO 1),
ccsat=>synth0090(43),cczip=>synth0090(44));
cmp90: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0183(42 DOWNTO 1),
aasat=>castx0183(43),aazip=>castx0183(44),
bb=>castx0247(42 DOWNTO 1),
bbsat=>castx0247(43),bbzip=>castx0247(44),
cc=>synth0091(42 DOWNTO 1),
ccsat=>synth0091(43),cczip=>synth0091(44));
cmp91: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0182(42 DOWNTO 1),
aasat=>castx0182(43),aazip=>castx0182(44),
bb=>castx0246(42 DOWNTO 1),
bbsat=>castx0246(43),bbzip=>castx0246(44),
cc=>synth0092(42 DOWNTO 1),
ccsat=>synth0092(43),cczip=>synth0092(44));
cmp92: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0181(42 DOWNTO 1),
aasat=>castx0181(43),aazip=>castx0181(44),
bb=>castx0245(42 DOWNTO 1),
bbsat=>castx0245(43),bbzip=>castx0245(44),
cc=>synth0093(42 DOWNTO 1),
ccsat=>synth0093(43),cczip=>synth0093(44));
cmp93: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0180(42 DOWNTO 1),
aasat=>castx0180(43),aazip=>castx0180(44),
bb=>castx0244(42 DOWNTO 1),
bbsat=>castx0244(43),bbzip=>castx0244(44),
cc=>synth0094(42 DOWNTO 1),
ccsat=>synth0094(43),cczip=>synth0094(44));
cmp94: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0179(42 DOWNTO 1),
aasat=>castx0179(43),aazip=>castx0179(44),
bb=>castx0243(42 DOWNTO 1),
bbsat=>castx0243(43),bbzip=>castx0243(44),
cc=>synth0095(42 DOWNTO 1),
ccsat=>synth0095(43),cczip=>synth0095(44));
cmp95: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0178(42 DOWNTO 1),
aasat=>castx0178(43),aazip=>castx0178(44),
bb=>castx0242(42 DOWNTO 1),
bbsat=>castx0242(43),bbzip=>castx0242(44),
cc=>synth0096(42 DOWNTO 1),
ccsat=>synth0096(43),cczip=>synth0096(44));
cmp96: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0177(42 DOWNTO 1),
aasat=>castx0177(43),aazip=>castx0177(44),
bb=>castx0241(42 DOWNTO 1),
bbsat=>castx0241(43),bbzip=>castx0241(44),
cc=>synth0097(42 DOWNTO 1),
ccsat=>synth0097(43),cczip=>synth0097(44));
cmp97: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0176(42 DOWNTO 1),
aasat=>castx0176(43),aazip=>castx0176(44),
bb=>castx0240(42 DOWNTO 1),
bbsat=>castx0240(43),bbzip=>castx0240(44),
cc=>synth0098(42 DOWNTO 1),
ccsat=>synth0098(43),cczip=>synth0098(44));
cmp98: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0092(42 DOWNTO 1),
aasat=>synth0092(43),aazip=>synth0092(44),
bb=>synth0091(42 DOWNTO 1),
bbsat=>synth0091(43),bbzip=>synth0091(44),
cc=>synth0099(42 DOWNTO 1),
ccsat=>synth0099(43),cczip=>synth0099(44));
cmp99: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0094(42 DOWNTO 1),
aasat=>synth0094(43),aazip=>synth0094(44),
bb=>synth0093(42 DOWNTO 1),
bbsat=>synth0093(43),bbzip=>synth0093(44),
cc=>synth0100(42 DOWNTO 1),
ccsat=>synth0100(43),cczip=>synth0100(44));
cmp100: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0096(42 DOWNTO 1),
aasat=>synth0096(43),aazip=>synth0096(44),
bb=>synth0095(42 DOWNTO 1),
bbsat=>synth0095(43),bbzip=>synth0095(44),
cc=>synth0101(42 DOWNTO 1),
ccsat=>synth0101(43),cczip=>synth0101(44));
cmp101: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0098(42 DOWNTO 1),
aasat=>synth0098(43),aazip=>synth0098(44),
bb=>synth0097(42 DOWNTO 1),
bbsat=>synth0097(43),bbzip=>synth0097(44),
cc=>synth0102(42 DOWNTO 1),
ccsat=>synth0102(43),cczip=>synth0102(44));
cmp102: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0100(42 DOWNTO 1),
aasat=>synth0100(43),aazip=>synth0100(44),
bb=>synth0099(42 DOWNTO 1),
bbsat=>synth0099(43),bbzip=>synth0099(44),
cc=>synth0103(42 DOWNTO 1),
ccsat=>synth0103(43),cczip=>synth0103(44));
cmp103: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0102(42 DOWNTO 1),
aasat=>synth0102(43),aazip=>synth0102(44),
bb=>synth0101(42 DOWNTO 1),
bbsat=>synth0101(43),bbzip=>synth0101(44),
cc=>synth0104(42 DOWNTO 1),
ccsat=>synth0104(43),cczip=>synth0104(44));
cmp104: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0104(42 DOWNTO 1),
aasat=>synth0104(43),aazip=>synth0104(44),
bb=>synth0103(42 DOWNTO 1),
bbsat=>synth0103(43),bbzip=>synth0103(44),
cc=>synth0105(42 DOWNTO 1),
ccsat=>synth0105(43),cczip=>synth0105(44));
cmp105: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0191(42 DOWNTO 1),
aasat=>castx0191(43),aazip=>castx0191(44),
bb=>castx0255(42 DOWNTO 1),
bbsat=>castx0255(43),bbzip=>castx0255(44),
cc=>synth0106(42 DOWNTO 1),
ccsat=>synth0106(43),cczip=>synth0106(44));
cmp106: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0190(42 DOWNTO 1),
aasat=>castx0190(43),aazip=>castx0190(44),
bb=>castx0254(42 DOWNTO 1),
bbsat=>castx0254(43),bbzip=>castx0254(44),
cc=>synth0107(42 DOWNTO 1),
ccsat=>synth0107(43),cczip=>synth0107(44));
cmp107: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0189(42 DOWNTO 1),
aasat=>castx0189(43),aazip=>castx0189(44),
bb=>castx0253(42 DOWNTO 1),
bbsat=>castx0253(43),bbzip=>castx0253(44),
cc=>synth0108(42 DOWNTO 1),
ccsat=>synth0108(43),cczip=>synth0108(44));
cmp108: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0188(42 DOWNTO 1),
aasat=>castx0188(43),aazip=>castx0188(44),
bb=>castx0252(42 DOWNTO 1),
bbsat=>castx0252(43),bbzip=>castx0252(44),
cc=>synth0109(42 DOWNTO 1),
ccsat=>synth0109(43),cczip=>synth0109(44));
cmp109: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0187(42 DOWNTO 1),
aasat=>castx0187(43),aazip=>castx0187(44),
bb=>castx0251(42 DOWNTO 1),
bbsat=>castx0251(43),bbzip=>castx0251(44),
cc=>synth0110(42 DOWNTO 1),
ccsat=>synth0110(43),cczip=>synth0110(44));
cmp110: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0186(42 DOWNTO 1),
aasat=>castx0186(43),aazip=>castx0186(44),
bb=>castx0250(42 DOWNTO 1),
bbsat=>castx0250(43),bbzip=>castx0250(44),
cc=>synth0111(42 DOWNTO 1),
ccsat=>synth0111(43),cczip=>synth0111(44));
cmp111: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0185(42 DOWNTO 1),
aasat=>castx0185(43),aazip=>castx0185(44),
bb=>castx0249(42 DOWNTO 1),
bbsat=>castx0249(43),bbzip=>castx0249(44),
cc=>synth0112(42 DOWNTO 1),
ccsat=>synth0112(43),cczip=>synth0112(44));
cmp112: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0184(42 DOWNTO 1),
aasat=>castx0184(43),aazip=>castx0184(44),
bb=>castx0248(42 DOWNTO 1),
bbsat=>castx0248(43),bbzip=>castx0248(44),
cc=>synth0113(42 DOWNTO 1),
ccsat=>synth0113(43),cczip=>synth0113(44));
cmp113: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0107(42 DOWNTO 1),
aasat=>synth0107(43),aazip=>synth0107(44),
bb=>synth0106(42 DOWNTO 1),
bbsat=>synth0106(43),bbzip=>synth0106(44),
cc=>synth0114(42 DOWNTO 1),
ccsat=>synth0114(43),cczip=>synth0114(44));
cmp114: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0109(42 DOWNTO 1),
aasat=>synth0109(43),aazip=>synth0109(44),
bb=>synth0108(42 DOWNTO 1),
bbsat=>synth0108(43),bbzip=>synth0108(44),
cc=>synth0115(42 DOWNTO 1),
ccsat=>synth0115(43),cczip=>synth0115(44));
cmp115: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0111(42 DOWNTO 1),
aasat=>synth0111(43),aazip=>synth0111(44),
bb=>synth0110(42 DOWNTO 1),
bbsat=>synth0110(43),bbzip=>synth0110(44),
cc=>synth0116(42 DOWNTO 1),
ccsat=>synth0116(43),cczip=>synth0116(44));
cmp116: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0113(42 DOWNTO 1),
aasat=>synth0113(43),aazip=>synth0113(44),
bb=>synth0112(42 DOWNTO 1),
bbsat=>synth0112(43),bbzip=>synth0112(44),
cc=>synth0117(42 DOWNTO 1),
ccsat=>synth0117(43),cczip=>synth0117(44));
cmp117: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0115(42 DOWNTO 1),
aasat=>synth0115(43),aazip=>synth0115(44),
bb=>synth0114(42 DOWNTO 1),
bbsat=>synth0114(43),bbzip=>synth0114(44),
cc=>synth0118(42 DOWNTO 1),
ccsat=>synth0118(43),cczip=>synth0118(44));
cmp118: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0117(42 DOWNTO 1),
aasat=>synth0117(43),aazip=>synth0117(44),
bb=>synth0116(42 DOWNTO 1),
bbsat=>synth0116(43),bbzip=>synth0116(44),
cc=>synth0119(42 DOWNTO 1),
ccsat=>synth0119(43),cczip=>synth0119(44));
cmp119: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0119(42 DOWNTO 1),
aasat=>synth0119(43),aazip=>synth0119(44),
bb=>synth0118(42 DOWNTO 1),
bbsat=>synth0118(43),bbzip=>synth0118(44),
cc=>synth0120(42 DOWNTO 1),
ccsat=>synth0120(43),cczip=>synth0120(44));
cmp120: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0259(42 DOWNTO 1),
aasat=>synth0259(43),aazip=>synth0259(44),
bb=>synth0260(42 DOWNTO 1),
bbsat=>synth0260(43),bbzip=>synth0260(44),
cc=>synth0121(42 DOWNTO 1),
ccsat=>synth0121(43),cczip=>synth0121(44));
cmp121: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0257(42 DOWNTO 1),
aasat=>synth0257(43),aazip=>synth0257(44),
bb=>synth0258(42 DOWNTO 1),
bbsat=>synth0258(43),bbzip=>synth0258(44),
cc=>synth0122(42 DOWNTO 1),
ccsat=>synth0122(43),cczip=>synth0122(44));
cmp122: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0122(42 DOWNTO 1),
aasat=>synth0122(43),aazip=>synth0122(44),
bb=>synth0121(42 DOWNTO 1),
bbsat=>synth0121(43),bbzip=>synth0121(44),
cc=>synth0123(42 DOWNTO 1),
ccsat=>synth0123(43),cczip=>synth0123(44));
cmp123: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0263(42 DOWNTO 1),
aasat=>synth0263(43),aazip=>synth0263(44),
bb=>synth0264(42 DOWNTO 1),
bbsat=>synth0264(43),bbzip=>synth0264(44),
cc=>synth0124(42 DOWNTO 1),
ccsat=>synth0124(43),cczip=>synth0124(44));
cmp124: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0261(42 DOWNTO 1),
aasat=>synth0261(43),aazip=>synth0261(44),
bb=>synth0262(42 DOWNTO 1),
bbsat=>synth0262(43),bbzip=>synth0262(44),
cc=>synth0125(42 DOWNTO 1),
ccsat=>synth0125(43),cczip=>synth0125(44));
cmp125: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0125(42 DOWNTO 1),
aasat=>synth0125(43),aazip=>synth0125(44),
bb=>synth0124(42 DOWNTO 1),
bbsat=>synth0124(43),bbzip=>synth0124(44),
cc=>synth0126(42 DOWNTO 1),
ccsat=>synth0126(43),cczip=>synth0126(44));
cmp126: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>mid00(42 DOWNTO 1),
aasat=>mid00(43),aazip=>mid00(44),
bb=>mid01(42 DOWNTO 1),
bbsat=>mid01(43),bbzip=>mid01(44),
cc=>synth0127(42 DOWNTO 1),
ccsat=>synth0127(43),cczip=>synth0127(44));
cmp127: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx00(32 DOWNTO 1),
cc=>castx0128(42 DOWNTO 1),
ccsat=>castx0128(43),cczip=>castx0128(44));
cmp128: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx01(32 DOWNTO 1),
cc=>castx0129(42 DOWNTO 1),
ccsat=>castx0129(43),cczip=>castx0129(44));
cmp129: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx02(32 DOWNTO 1),
cc=>castx0130(42 DOWNTO 1),
ccsat=>castx0130(43),cczip=>castx0130(44));
cmp130: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx03(32 DOWNTO 1),
cc=>castx0131(42 DOWNTO 1),
ccsat=>castx0131(43),cczip=>castx0131(44));
cmp131: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx04(32 DOWNTO 1),
cc=>castx0132(42 DOWNTO 1),
ccsat=>castx0132(43),cczip=>castx0132(44));
cmp132: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx05(32 DOWNTO 1),
cc=>castx0133(42 DOWNTO 1),
ccsat=>castx0133(43),cczip=>castx0133(44));
cmp133: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx06(32 DOWNTO 1),
cc=>castx0134(42 DOWNTO 1),
ccsat=>castx0134(43),cczip=>castx0134(44));
cmp134: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx07(32 DOWNTO 1),
cc=>castx0135(42 DOWNTO 1),
ccsat=>castx0135(43),cczip=>castx0135(44));
cmp135: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx08(32 DOWNTO 1),
cc=>castx0136(42 DOWNTO 1),
ccsat=>castx0136(43),cczip=>castx0136(44));
cmp136: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx09(32 DOWNTO 1),
cc=>castx0137(42 DOWNTO 1),
ccsat=>castx0137(43),cczip=>castx0137(44));
cmp137: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0a(32 DOWNTO 1),
cc=>castx0138(42 DOWNTO 1),
ccsat=>castx0138(43),cczip=>castx0138(44));
cmp138: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0b(32 DOWNTO 1),
cc=>castx0139(42 DOWNTO 1),
ccsat=>castx0139(43),cczip=>castx0139(44));
cmp139: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0c(32 DOWNTO 1),
cc=>castx0140(42 DOWNTO 1),
ccsat=>castx0140(43),cczip=>castx0140(44));
cmp140: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0d(32 DOWNTO 1),
cc=>castx0141(42 DOWNTO 1),
ccsat=>castx0141(43),cczip=>castx0141(44));
cmp141: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0e(32 DOWNTO 1),
cc=>castx0142(42 DOWNTO 1),
ccsat=>castx0142(43),cczip=>castx0142(44));
cmp142: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0f(32 DOWNTO 1),
cc=>castx0143(42 DOWNTO 1),
ccsat=>castx0143(43),cczip=>castx0143(44));
cmp143: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx10(32 DOWNTO 1),
cc=>castx0144(42 DOWNTO 1),
ccsat=>castx0144(43),cczip=>castx0144(44));
cmp144: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx11(32 DOWNTO 1),
cc=>castx0145(42 DOWNTO 1),
ccsat=>castx0145(43),cczip=>castx0145(44));
cmp145: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx12(32 DOWNTO 1),
cc=>castx0146(42 DOWNTO 1),
ccsat=>castx0146(43),cczip=>castx0146(44));
cmp146: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx13(32 DOWNTO 1),
cc=>castx0147(42 DOWNTO 1),
ccsat=>castx0147(43),cczip=>castx0147(44));
cmp147: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx14(32 DOWNTO 1),
cc=>castx0148(42 DOWNTO 1),
ccsat=>castx0148(43),cczip=>castx0148(44));
cmp148: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx15(32 DOWNTO 1),
cc=>castx0149(42 DOWNTO 1),
ccsat=>castx0149(43),cczip=>castx0149(44));
cmp149: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx16(32 DOWNTO 1),
cc=>castx0150(42 DOWNTO 1),
ccsat=>castx0150(43),cczip=>castx0150(44));
cmp150: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx17(32 DOWNTO 1),
cc=>castx0151(42 DOWNTO 1),
ccsat=>castx0151(43),cczip=>castx0151(44));
cmp151: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx18(32 DOWNTO 1),
cc=>castx0152(42 DOWNTO 1),
ccsat=>castx0152(43),cczip=>castx0152(44));
cmp152: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx19(32 DOWNTO 1),
cc=>castx0153(42 DOWNTO 1),
ccsat=>castx0153(43),cczip=>castx0153(44));
cmp153: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1a(32 DOWNTO 1),
cc=>castx0154(42 DOWNTO 1),
ccsat=>castx0154(43),cczip=>castx0154(44));
cmp154: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1b(32 DOWNTO 1),
cc=>castx0155(42 DOWNTO 1),
ccsat=>castx0155(43),cczip=>castx0155(44));
cmp155: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1c(32 DOWNTO 1),
cc=>castx0156(42 DOWNTO 1),
ccsat=>castx0156(43),cczip=>castx0156(44));
cmp156: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1d(32 DOWNTO 1),
cc=>castx0157(42 DOWNTO 1),
ccsat=>castx0157(43),cczip=>castx0157(44));
cmp157: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1e(32 DOWNTO 1),
cc=>castx0158(42 DOWNTO 1),
ccsat=>castx0158(43),cczip=>castx0158(44));
cmp158: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1f(32 DOWNTO 1),
cc=>castx0159(42 DOWNTO 1),
ccsat=>castx0159(43),cczip=>castx0159(44));
cmp159: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx20(32 DOWNTO 1),
cc=>castx0160(42 DOWNTO 1),
ccsat=>castx0160(43),cczip=>castx0160(44));
cmp160: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx21(32 DOWNTO 1),
cc=>castx0161(42 DOWNTO 1),
ccsat=>castx0161(43),cczip=>castx0161(44));
cmp161: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx22(32 DOWNTO 1),
cc=>castx0162(42 DOWNTO 1),
ccsat=>castx0162(43),cczip=>castx0162(44));
cmp162: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx23(32 DOWNTO 1),
cc=>castx0163(42 DOWNTO 1),
ccsat=>castx0163(43),cczip=>castx0163(44));
cmp163: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx24(32 DOWNTO 1),
cc=>castx0164(42 DOWNTO 1),
ccsat=>castx0164(43),cczip=>castx0164(44));
cmp164: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx25(32 DOWNTO 1),
cc=>castx0165(42 DOWNTO 1),
ccsat=>castx0165(43),cczip=>castx0165(44));
cmp165: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx26(32 DOWNTO 1),
cc=>castx0166(42 DOWNTO 1),
ccsat=>castx0166(43),cczip=>castx0166(44));
cmp166: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx27(32 DOWNTO 1),
cc=>castx0167(42 DOWNTO 1),
ccsat=>castx0167(43),cczip=>castx0167(44));
cmp167: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx28(32 DOWNTO 1),
cc=>castx0168(42 DOWNTO 1),
ccsat=>castx0168(43),cczip=>castx0168(44));
cmp168: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx29(32 DOWNTO 1),
cc=>castx0169(42 DOWNTO 1),
ccsat=>castx0169(43),cczip=>castx0169(44));
cmp169: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2a(32 DOWNTO 1),
cc=>castx0170(42 DOWNTO 1),
ccsat=>castx0170(43),cczip=>castx0170(44));
cmp170: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2b(32 DOWNTO 1),
cc=>castx0171(42 DOWNTO 1),
ccsat=>castx0171(43),cczip=>castx0171(44));
cmp171: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2c(32 DOWNTO 1),
cc=>castx0172(42 DOWNTO 1),
ccsat=>castx0172(43),cczip=>castx0172(44));
cmp172: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2d(32 DOWNTO 1),
cc=>castx0173(42 DOWNTO 1),
ccsat=>castx0173(43),cczip=>castx0173(44));
cmp173: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2e(32 DOWNTO 1),
cc=>castx0174(42 DOWNTO 1),
ccsat=>castx0174(43),cczip=>castx0174(44));
cmp174: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2f(32 DOWNTO 1),
cc=>castx0175(42 DOWNTO 1),
ccsat=>castx0175(43),cczip=>castx0175(44));
cmp175: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx30(32 DOWNTO 1),
cc=>castx0176(42 DOWNTO 1),
ccsat=>castx0176(43),cczip=>castx0176(44));
cmp176: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx31(32 DOWNTO 1),
cc=>castx0177(42 DOWNTO 1),
ccsat=>castx0177(43),cczip=>castx0177(44));
cmp177: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx32(32 DOWNTO 1),
cc=>castx0178(42 DOWNTO 1),
ccsat=>castx0178(43),cczip=>castx0178(44));
cmp178: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx33(32 DOWNTO 1),
cc=>castx0179(42 DOWNTO 1),
ccsat=>castx0179(43),cczip=>castx0179(44));
cmp179: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx34(32 DOWNTO 1),
cc=>castx0180(42 DOWNTO 1),
ccsat=>castx0180(43),cczip=>castx0180(44));
cmp180: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx35(32 DOWNTO 1),
cc=>castx0181(42 DOWNTO 1),
ccsat=>castx0181(43),cczip=>castx0181(44));
cmp181: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx36(32 DOWNTO 1),
cc=>castx0182(42 DOWNTO 1),
ccsat=>castx0182(43),cczip=>castx0182(44));
cmp182: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx37(32 DOWNTO 1),
cc=>castx0183(42 DOWNTO 1),
ccsat=>castx0183(43),cczip=>castx0183(44));
cmp183: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx38(32 DOWNTO 1),
cc=>castx0184(42 DOWNTO 1),
ccsat=>castx0184(43),cczip=>castx0184(44));
cmp184: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx39(32 DOWNTO 1),
cc=>castx0185(42 DOWNTO 1),
ccsat=>castx0185(43),cczip=>castx0185(44));
cmp185: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3a(32 DOWNTO 1),
cc=>castx0186(42 DOWNTO 1),
ccsat=>castx0186(43),cczip=>castx0186(44));
cmp186: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3b(32 DOWNTO 1),
cc=>castx0187(42 DOWNTO 1),
ccsat=>castx0187(43),cczip=>castx0187(44));
cmp187: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3c(32 DOWNTO 1),
cc=>castx0188(42 DOWNTO 1),
ccsat=>castx0188(43),cczip=>castx0188(44));
cmp188: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3d(32 DOWNTO 1),
cc=>castx0189(42 DOWNTO 1),
ccsat=>castx0189(43),cczip=>castx0189(44));
cmp189: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3e(32 DOWNTO 1),
cc=>castx0190(42 DOWNTO 1),
ccsat=>castx0190(43),cczip=>castx0190(44));
cmp190: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3f(32 DOWNTO 1),
cc=>castx0191(42 DOWNTO 1),
ccsat=>castx0191(43),cczip=>castx0191(44));
cmp191: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc00(32 DOWNTO 1),
cc=>castx0192(42 DOWNTO 1),
ccsat=>castx0192(43),cczip=>castx0192(44));
cmp192: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc01(32 DOWNTO 1),
cc=>castx0193(42 DOWNTO 1),
ccsat=>castx0193(43),cczip=>castx0193(44));
cmp193: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc02(32 DOWNTO 1),
cc=>castx0194(42 DOWNTO 1),
ccsat=>castx0194(43),cczip=>castx0194(44));
cmp194: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc03(32 DOWNTO 1),
cc=>castx0195(42 DOWNTO 1),
ccsat=>castx0195(43),cczip=>castx0195(44));
cmp195: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc04(32 DOWNTO 1),
cc=>castx0196(42 DOWNTO 1),
ccsat=>castx0196(43),cczip=>castx0196(44));
cmp196: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc05(32 DOWNTO 1),
cc=>castx0197(42 DOWNTO 1),
ccsat=>castx0197(43),cczip=>castx0197(44));
cmp197: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc06(32 DOWNTO 1),
cc=>castx0198(42 DOWNTO 1),
ccsat=>castx0198(43),cczip=>castx0198(44));
cmp198: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc07(32 DOWNTO 1),
cc=>castx0199(42 DOWNTO 1),
ccsat=>castx0199(43),cczip=>castx0199(44));
cmp199: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc08(32 DOWNTO 1),
cc=>castx0200(42 DOWNTO 1),
ccsat=>castx0200(43),cczip=>castx0200(44));
cmp200: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc09(32 DOWNTO 1),
cc=>castx0201(42 DOWNTO 1),
ccsat=>castx0201(43),cczip=>castx0201(44));
cmp201: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0a(32 DOWNTO 1),
cc=>castx0202(42 DOWNTO 1),
ccsat=>castx0202(43),cczip=>castx0202(44));
cmp202: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0b(32 DOWNTO 1),
cc=>castx0203(42 DOWNTO 1),
ccsat=>castx0203(43),cczip=>castx0203(44));
cmp203: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0c(32 DOWNTO 1),
cc=>castx0204(42 DOWNTO 1),
ccsat=>castx0204(43),cczip=>castx0204(44));
cmp204: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0d(32 DOWNTO 1),
cc=>castx0205(42 DOWNTO 1),
ccsat=>castx0205(43),cczip=>castx0205(44));
cmp205: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0e(32 DOWNTO 1),
cc=>castx0206(42 DOWNTO 1),
ccsat=>castx0206(43),cczip=>castx0206(44));
cmp206: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0f(32 DOWNTO 1),
cc=>castx0207(42 DOWNTO 1),
ccsat=>castx0207(43),cczip=>castx0207(44));
cmp207: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc10(32 DOWNTO 1),
cc=>castx0208(42 DOWNTO 1),
ccsat=>castx0208(43),cczip=>castx0208(44));
cmp208: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc11(32 DOWNTO 1),
cc=>castx0209(42 DOWNTO 1),
ccsat=>castx0209(43),cczip=>castx0209(44));
cmp209: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc12(32 DOWNTO 1),
cc=>castx0210(42 DOWNTO 1),
ccsat=>castx0210(43),cczip=>castx0210(44));
cmp210: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc13(32 DOWNTO 1),
cc=>castx0211(42 DOWNTO 1),
ccsat=>castx0211(43),cczip=>castx0211(44));
cmp211: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc14(32 DOWNTO 1),
cc=>castx0212(42 DOWNTO 1),
ccsat=>castx0212(43),cczip=>castx0212(44));
cmp212: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc15(32 DOWNTO 1),
cc=>castx0213(42 DOWNTO 1),
ccsat=>castx0213(43),cczip=>castx0213(44));
cmp213: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc16(32 DOWNTO 1),
cc=>castx0214(42 DOWNTO 1),
ccsat=>castx0214(43),cczip=>castx0214(44));
cmp214: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc17(32 DOWNTO 1),
cc=>castx0215(42 DOWNTO 1),
ccsat=>castx0215(43),cczip=>castx0215(44));
cmp215: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc18(32 DOWNTO 1),
cc=>castx0216(42 DOWNTO 1),
ccsat=>castx0216(43),cczip=>castx0216(44));
cmp216: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc19(32 DOWNTO 1),
cc=>castx0217(42 DOWNTO 1),
ccsat=>castx0217(43),cczip=>castx0217(44));
cmp217: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1a(32 DOWNTO 1),
cc=>castx0218(42 DOWNTO 1),
ccsat=>castx0218(43),cczip=>castx0218(44));
cmp218: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1b(32 DOWNTO 1),
cc=>castx0219(42 DOWNTO 1),
ccsat=>castx0219(43),cczip=>castx0219(44));
cmp219: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1c(32 DOWNTO 1),
cc=>castx0220(42 DOWNTO 1),
ccsat=>castx0220(43),cczip=>castx0220(44));
cmp220: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1d(32 DOWNTO 1),
cc=>castx0221(42 DOWNTO 1),
ccsat=>castx0221(43),cczip=>castx0221(44));
cmp221: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1e(32 DOWNTO 1),
cc=>castx0222(42 DOWNTO 1),
ccsat=>castx0222(43),cczip=>castx0222(44));
cmp222: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1f(32 DOWNTO 1),
cc=>castx0223(42 DOWNTO 1),
ccsat=>castx0223(43),cczip=>castx0223(44));
cmp223: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc20(32 DOWNTO 1),
cc=>castx0224(42 DOWNTO 1),
ccsat=>castx0224(43),cczip=>castx0224(44));
cmp224: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc21(32 DOWNTO 1),
cc=>castx0225(42 DOWNTO 1),
ccsat=>castx0225(43),cczip=>castx0225(44));
cmp225: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc22(32 DOWNTO 1),
cc=>castx0226(42 DOWNTO 1),
ccsat=>castx0226(43),cczip=>castx0226(44));
cmp226: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc23(32 DOWNTO 1),
cc=>castx0227(42 DOWNTO 1),
ccsat=>castx0227(43),cczip=>castx0227(44));
cmp227: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc24(32 DOWNTO 1),
cc=>castx0228(42 DOWNTO 1),
ccsat=>castx0228(43),cczip=>castx0228(44));
cmp228: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc25(32 DOWNTO 1),
cc=>castx0229(42 DOWNTO 1),
ccsat=>castx0229(43),cczip=>castx0229(44));
cmp229: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc26(32 DOWNTO 1),
cc=>castx0230(42 DOWNTO 1),
ccsat=>castx0230(43),cczip=>castx0230(44));
cmp230: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc27(32 DOWNTO 1),
cc=>castx0231(42 DOWNTO 1),
ccsat=>castx0231(43),cczip=>castx0231(44));
cmp231: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc28(32 DOWNTO 1),
cc=>castx0232(42 DOWNTO 1),
ccsat=>castx0232(43),cczip=>castx0232(44));
cmp232: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc29(32 DOWNTO 1),
cc=>castx0233(42 DOWNTO 1),
ccsat=>castx0233(43),cczip=>castx0233(44));
cmp233: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2a(32 DOWNTO 1),
cc=>castx0234(42 DOWNTO 1),
ccsat=>castx0234(43),cczip=>castx0234(44));
cmp234: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2b(32 DOWNTO 1),
cc=>castx0235(42 DOWNTO 1),
ccsat=>castx0235(43),cczip=>castx0235(44));
cmp235: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2c(32 DOWNTO 1),
cc=>castx0236(42 DOWNTO 1),
ccsat=>castx0236(43),cczip=>castx0236(44));
cmp236: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2d(32 DOWNTO 1),
cc=>castx0237(42 DOWNTO 1),
ccsat=>castx0237(43),cczip=>castx0237(44));
cmp237: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2e(32 DOWNTO 1),
cc=>castx0238(42 DOWNTO 1),
ccsat=>castx0238(43),cczip=>castx0238(44));
cmp238: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2f(32 DOWNTO 1),
cc=>castx0239(42 DOWNTO 1),
ccsat=>castx0239(43),cczip=>castx0239(44));
cmp239: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc30(32 DOWNTO 1),
cc=>castx0240(42 DOWNTO 1),
ccsat=>castx0240(43),cczip=>castx0240(44));
cmp240: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc31(32 DOWNTO 1),
cc=>castx0241(42 DOWNTO 1),
ccsat=>castx0241(43),cczip=>castx0241(44));
cmp241: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc32(32 DOWNTO 1),
cc=>castx0242(42 DOWNTO 1),
ccsat=>castx0242(43),cczip=>castx0242(44));
cmp242: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc33(32 DOWNTO 1),
cc=>castx0243(42 DOWNTO 1),
ccsat=>castx0243(43),cczip=>castx0243(44));
cmp243: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc34(32 DOWNTO 1),
cc=>castx0244(42 DOWNTO 1),
ccsat=>castx0244(43),cczip=>castx0244(44));
cmp244: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc35(32 DOWNTO 1),
cc=>castx0245(42 DOWNTO 1),
ccsat=>castx0245(43),cczip=>castx0245(44));
cmp245: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc36(32 DOWNTO 1),
cc=>castx0246(42 DOWNTO 1),
ccsat=>castx0246(43),cczip=>castx0246(44));
cmp246: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc37(32 DOWNTO 1),
cc=>castx0247(42 DOWNTO 1),
ccsat=>castx0247(43),cczip=>castx0247(44));
cmp247: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc38(32 DOWNTO 1),
cc=>castx0248(42 DOWNTO 1),
ccsat=>castx0248(43),cczip=>castx0248(44));
cmp248: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc39(32 DOWNTO 1),
cc=>castx0249(42 DOWNTO 1),
ccsat=>castx0249(43),cczip=>castx0249(44));
cmp249: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3a(32 DOWNTO 1),
cc=>castx0250(42 DOWNTO 1),
ccsat=>castx0250(43),cczip=>castx0250(44));
cmp250: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3b(32 DOWNTO 1),
cc=>castx0251(42 DOWNTO 1),
ccsat=>castx0251(43),cczip=>castx0251(44));
cmp251: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3c(32 DOWNTO 1),
cc=>castx0252(42 DOWNTO 1),
ccsat=>castx0252(43),cczip=>castx0252(44));
cmp252: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3d(32 DOWNTO 1),
cc=>castx0253(42 DOWNTO 1),
ccsat=>castx0253(43),cczip=>castx0253(44));
cmp253: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3e(32 DOWNTO 1),
cc=>castx0254(42 DOWNTO 1),
ccsat=>castx0254(43),cczip=>castx0254(44));
cmp254: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3f(32 DOWNTO 1),
cc=>castx0255(42 DOWNTO 1),
ccsat=>castx0255(43),cczip=>castx0255(44));
cmp255: hcc_castxtof
GENERIC MAP (mantissa=>32,normspeed=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>synth0127(42 DOWNTO 1),
aasat=>synth0127(43),aazip=>synth0127(44),
cc=>castx0256(32 DOWNTO 1));
cmp256: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp00(42 DOWNTO 1),
aasat=>dp00(43),aazip=>dp00(44),
cc=>synth0257(42 DOWNTO 1),
ccsat=>synth0257(43), cczip=>synth0257(44));
cmp257: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp01(42 DOWNTO 1),
aasat=>dp01(43),aazip=>dp01(44),
cc=>synth0258(42 DOWNTO 1),
ccsat=>synth0258(43), cczip=>synth0258(44));
cmp258: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp02(42 DOWNTO 1),
aasat=>dp02(43),aazip=>dp02(44),
cc=>synth0259(42 DOWNTO 1),
ccsat=>synth0259(43), cczip=>synth0259(44));
cmp259: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp03(42 DOWNTO 1),
aasat=>dp03(43),aazip=>dp03(44),
cc=>synth0260(42 DOWNTO 1),
ccsat=>synth0260(43), cczip=>synth0260(44));
cmp260: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp04(42 DOWNTO 1),
aasat=>dp04(43),aazip=>dp04(44),
cc=>synth0261(42 DOWNTO 1),
ccsat=>synth0261(43), cczip=>synth0261(44));
cmp261: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp05(42 DOWNTO 1),
aasat=>dp05(43),aazip=>dp05(44),
cc=>synth0262(42 DOWNTO 1),
ccsat=>synth0262(43), cczip=>synth0262(44));
cmp262: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp06(42 DOWNTO 1),
aasat=>dp06(43),aazip=>dp06(44),
cc=>synth0263(42 DOWNTO 1),
ccsat=>synth0263(43), cczip=>synth0263(44));
cmp263: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp07(42 DOWNTO 1),
aasat=>dp07(43),aazip=>dp07(44),
cc=>synth0264(42 DOWNTO 1),
ccsat=>synth0264(43), cczip=>synth0264(44));
--*** OUTPUTS ***
result <= castx0256;
startout <= startff(46);
END GEN;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/sgm_fpmm64.vhd
|
10
|
118317
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY sgm_fpmm64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END sgm_fpmm64;
ARCHITECTURE gen OF sgm_fpmm64 IS
COMPONENT hcc_mulfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_alufp1x
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
COMPONENT hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
COMPONENT hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END component;
signal dp00 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp01 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp02 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp03 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp04 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp05 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp06 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal dp07 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal mid00 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal mid01 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0001 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0002 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0003 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0004 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0005 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0006 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0007 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0008 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0009 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0010 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0011 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0012 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0013 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0014 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0015 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0016 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0017 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0018 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0019 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0020 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0021 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0022 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0023 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0024 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0025 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0026 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0027 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0028 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0029 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0030 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0031 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0032 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0033 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0034 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0035 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0036 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0037 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0038 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0039 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0040 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0041 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0042 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0043 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0044 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0045 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0046 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0047 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0048 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0049 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0050 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0051 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0052 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0053 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0054 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0055 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0056 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0057 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0058 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0059 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0060 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0061 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0062 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0063 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0064 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0065 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0066 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0067 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0068 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0069 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0070 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0071 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0072 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0073 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0074 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0075 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0076 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0077 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0078 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0079 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0080 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0081 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0082 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0083 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0084 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0085 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0086 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0087 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0088 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0089 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0090 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0091 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0092 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0093 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0094 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0095 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0096 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0097 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0098 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0099 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0100 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0101 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0102 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0103 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0104 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0105 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0106 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0107 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0108 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0109 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0110 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0111 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0112 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0113 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0114 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0115 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0116 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0117 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0118 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0119 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0120 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0121 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0122 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0123 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0124 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0125 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0126 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0127 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0128 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0129 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0130 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0131 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0132 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0133 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0134 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0135 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0136 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0137 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0138 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0139 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0140 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0141 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0142 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0143 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0144 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0145 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0146 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0147 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0148 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0149 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0150 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0151 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0152 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0153 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0154 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0155 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0156 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0157 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0158 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0159 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0160 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0161 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0162 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0163 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0164 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0165 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0166 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0167 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0168 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0169 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0170 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0171 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0172 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0173 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0174 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0175 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0176 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0177 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0178 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0179 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0180 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0181 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0182 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0183 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0184 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0185 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0186 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0187 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0188 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0189 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0190 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0191 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0192 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0193 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0194 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0195 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0196 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0197 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0198 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0199 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0200 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0201 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0202 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0203 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0204 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0205 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0206 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0207 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0208 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0209 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0210 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0211 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0212 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0213 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0214 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0215 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0216 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0217 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0218 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0219 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0220 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0221 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0222 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0223 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0224 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0225 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0226 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0227 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0228 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0229 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0230 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0231 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0232 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0233 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0234 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0235 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0236 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0237 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0238 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0239 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0240 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0241 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0242 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0243 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0244 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0245 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0246 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0247 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0248 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0249 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0250 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0251 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0252 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0253 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0254 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0255 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal castx0256 : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal synth0257 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0258 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0259 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0260 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0261 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0262 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0263 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal synth0264 : STD_LOGIC_VECTOR (44 DOWNTO 1);
signal startff : STD_LOGIC_VECTOR (46 DOWNTO 1);
BEGIN
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 46 LOOP
startff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
startff(1) <= startin;
FOR k IN 2 TO 46 LOOP
startff(k) <= startff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
dp00 <= synth0015;
dp01 <= synth0030;
dp02 <= synth0045;
dp03 <= synth0060;
dp04 <= synth0075;
dp05 <= synth0090;
dp06 <= synth0105;
dp07 <= synth0120;
mid00 <= synth0123;
mid01 <= synth0126;
cmp0: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0135(42 DOWNTO 1),
aasat=>castx0135(43),aazip=>castx0135(44),
bb=>castx0199(42 DOWNTO 1),
bbsat=>castx0199(43),bbzip=>castx0199(44),
cc=>synth0001(42 DOWNTO 1),
ccsat=>synth0001(43),cczip=>synth0001(44));
cmp1: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0134(42 DOWNTO 1),
aasat=>castx0134(43),aazip=>castx0134(44),
bb=>castx0198(42 DOWNTO 1),
bbsat=>castx0198(43),bbzip=>castx0198(44),
cc=>synth0002(42 DOWNTO 1),
ccsat=>synth0002(43),cczip=>synth0002(44));
cmp2: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0133(42 DOWNTO 1),
aasat=>castx0133(43),aazip=>castx0133(44),
bb=>castx0197(42 DOWNTO 1),
bbsat=>castx0197(43),bbzip=>castx0197(44),
cc=>synth0003(42 DOWNTO 1),
ccsat=>synth0003(43),cczip=>synth0003(44));
cmp3: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0132(42 DOWNTO 1),
aasat=>castx0132(43),aazip=>castx0132(44),
bb=>castx0196(42 DOWNTO 1),
bbsat=>castx0196(43),bbzip=>castx0196(44),
cc=>synth0004(42 DOWNTO 1),
ccsat=>synth0004(43),cczip=>synth0004(44));
cmp4: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0131(42 DOWNTO 1),
aasat=>castx0131(43),aazip=>castx0131(44),
bb=>castx0195(42 DOWNTO 1),
bbsat=>castx0195(43),bbzip=>castx0195(44),
cc=>synth0005(42 DOWNTO 1),
ccsat=>synth0005(43),cczip=>synth0005(44));
cmp5: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0130(42 DOWNTO 1),
aasat=>castx0130(43),aazip=>castx0130(44),
bb=>castx0194(42 DOWNTO 1),
bbsat=>castx0194(43),bbzip=>castx0194(44),
cc=>synth0006(42 DOWNTO 1),
ccsat=>synth0006(43),cczip=>synth0006(44));
cmp6: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0129(42 DOWNTO 1),
aasat=>castx0129(43),aazip=>castx0129(44),
bb=>castx0193(42 DOWNTO 1),
bbsat=>castx0193(43),bbzip=>castx0193(44),
cc=>synth0007(42 DOWNTO 1),
ccsat=>synth0007(43),cczip=>synth0007(44));
cmp7: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0128(42 DOWNTO 1),
aasat=>castx0128(43),aazip=>castx0128(44),
bb=>castx0192(42 DOWNTO 1),
bbsat=>castx0192(43),bbzip=>castx0192(44),
cc=>synth0008(42 DOWNTO 1),
ccsat=>synth0008(43),cczip=>synth0008(44));
cmp8: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0002(42 DOWNTO 1),
aasat=>synth0002(43),aazip=>synth0002(44),
bb=>synth0001(42 DOWNTO 1),
bbsat=>synth0001(43),bbzip=>synth0001(44),
cc=>synth0009(42 DOWNTO 1),
ccsat=>synth0009(43),cczip=>synth0009(44));
cmp9: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0004(42 DOWNTO 1),
aasat=>synth0004(43),aazip=>synth0004(44),
bb=>synth0003(42 DOWNTO 1),
bbsat=>synth0003(43),bbzip=>synth0003(44),
cc=>synth0010(42 DOWNTO 1),
ccsat=>synth0010(43),cczip=>synth0010(44));
cmp10: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0006(42 DOWNTO 1),
aasat=>synth0006(43),aazip=>synth0006(44),
bb=>synth0005(42 DOWNTO 1),
bbsat=>synth0005(43),bbzip=>synth0005(44),
cc=>synth0011(42 DOWNTO 1),
ccsat=>synth0011(43),cczip=>synth0011(44));
cmp11: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0008(42 DOWNTO 1),
aasat=>synth0008(43),aazip=>synth0008(44),
bb=>synth0007(42 DOWNTO 1),
bbsat=>synth0007(43),bbzip=>synth0007(44),
cc=>synth0012(42 DOWNTO 1),
ccsat=>synth0012(43),cczip=>synth0012(44));
cmp12: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0010(42 DOWNTO 1),
aasat=>synth0010(43),aazip=>synth0010(44),
bb=>synth0009(42 DOWNTO 1),
bbsat=>synth0009(43),bbzip=>synth0009(44),
cc=>synth0013(42 DOWNTO 1),
ccsat=>synth0013(43),cczip=>synth0013(44));
cmp13: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0012(42 DOWNTO 1),
aasat=>synth0012(43),aazip=>synth0012(44),
bb=>synth0011(42 DOWNTO 1),
bbsat=>synth0011(43),bbzip=>synth0011(44),
cc=>synth0014(42 DOWNTO 1),
ccsat=>synth0014(43),cczip=>synth0014(44));
cmp14: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0014(42 DOWNTO 1),
aasat=>synth0014(43),aazip=>synth0014(44),
bb=>synth0013(42 DOWNTO 1),
bbsat=>synth0013(43),bbzip=>synth0013(44),
cc=>synth0015(42 DOWNTO 1),
ccsat=>synth0015(43),cczip=>synth0015(44));
cmp15: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0143(42 DOWNTO 1),
aasat=>castx0143(43),aazip=>castx0143(44),
bb=>castx0207(42 DOWNTO 1),
bbsat=>castx0207(43),bbzip=>castx0207(44),
cc=>synth0016(42 DOWNTO 1),
ccsat=>synth0016(43),cczip=>synth0016(44));
cmp16: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0142(42 DOWNTO 1),
aasat=>castx0142(43),aazip=>castx0142(44),
bb=>castx0206(42 DOWNTO 1),
bbsat=>castx0206(43),bbzip=>castx0206(44),
cc=>synth0017(42 DOWNTO 1),
ccsat=>synth0017(43),cczip=>synth0017(44));
cmp17: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0141(42 DOWNTO 1),
aasat=>castx0141(43),aazip=>castx0141(44),
bb=>castx0205(42 DOWNTO 1),
bbsat=>castx0205(43),bbzip=>castx0205(44),
cc=>synth0018(42 DOWNTO 1),
ccsat=>synth0018(43),cczip=>synth0018(44));
cmp18: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0140(42 DOWNTO 1),
aasat=>castx0140(43),aazip=>castx0140(44),
bb=>castx0204(42 DOWNTO 1),
bbsat=>castx0204(43),bbzip=>castx0204(44),
cc=>synth0019(42 DOWNTO 1),
ccsat=>synth0019(43),cczip=>synth0019(44));
cmp19: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0139(42 DOWNTO 1),
aasat=>castx0139(43),aazip=>castx0139(44),
bb=>castx0203(42 DOWNTO 1),
bbsat=>castx0203(43),bbzip=>castx0203(44),
cc=>synth0020(42 DOWNTO 1),
ccsat=>synth0020(43),cczip=>synth0020(44));
cmp20: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0138(42 DOWNTO 1),
aasat=>castx0138(43),aazip=>castx0138(44),
bb=>castx0202(42 DOWNTO 1),
bbsat=>castx0202(43),bbzip=>castx0202(44),
cc=>synth0021(42 DOWNTO 1),
ccsat=>synth0021(43),cczip=>synth0021(44));
cmp21: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0137(42 DOWNTO 1),
aasat=>castx0137(43),aazip=>castx0137(44),
bb=>castx0201(42 DOWNTO 1),
bbsat=>castx0201(43),bbzip=>castx0201(44),
cc=>synth0022(42 DOWNTO 1),
ccsat=>synth0022(43),cczip=>synth0022(44));
cmp22: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0136(42 DOWNTO 1),
aasat=>castx0136(43),aazip=>castx0136(44),
bb=>castx0200(42 DOWNTO 1),
bbsat=>castx0200(43),bbzip=>castx0200(44),
cc=>synth0023(42 DOWNTO 1),
ccsat=>synth0023(43),cczip=>synth0023(44));
cmp23: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0017(42 DOWNTO 1),
aasat=>synth0017(43),aazip=>synth0017(44),
bb=>synth0016(42 DOWNTO 1),
bbsat=>synth0016(43),bbzip=>synth0016(44),
cc=>synth0024(42 DOWNTO 1),
ccsat=>synth0024(43),cczip=>synth0024(44));
cmp24: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0019(42 DOWNTO 1),
aasat=>synth0019(43),aazip=>synth0019(44),
bb=>synth0018(42 DOWNTO 1),
bbsat=>synth0018(43),bbzip=>synth0018(44),
cc=>synth0025(42 DOWNTO 1),
ccsat=>synth0025(43),cczip=>synth0025(44));
cmp25: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0021(42 DOWNTO 1),
aasat=>synth0021(43),aazip=>synth0021(44),
bb=>synth0020(42 DOWNTO 1),
bbsat=>synth0020(43),bbzip=>synth0020(44),
cc=>synth0026(42 DOWNTO 1),
ccsat=>synth0026(43),cczip=>synth0026(44));
cmp26: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0023(42 DOWNTO 1),
aasat=>synth0023(43),aazip=>synth0023(44),
bb=>synth0022(42 DOWNTO 1),
bbsat=>synth0022(43),bbzip=>synth0022(44),
cc=>synth0027(42 DOWNTO 1),
ccsat=>synth0027(43),cczip=>synth0027(44));
cmp27: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0025(42 DOWNTO 1),
aasat=>synth0025(43),aazip=>synth0025(44),
bb=>synth0024(42 DOWNTO 1),
bbsat=>synth0024(43),bbzip=>synth0024(44),
cc=>synth0028(42 DOWNTO 1),
ccsat=>synth0028(43),cczip=>synth0028(44));
cmp28: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0027(42 DOWNTO 1),
aasat=>synth0027(43),aazip=>synth0027(44),
bb=>synth0026(42 DOWNTO 1),
bbsat=>synth0026(43),bbzip=>synth0026(44),
cc=>synth0029(42 DOWNTO 1),
ccsat=>synth0029(43),cczip=>synth0029(44));
cmp29: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0029(42 DOWNTO 1),
aasat=>synth0029(43),aazip=>synth0029(44),
bb=>synth0028(42 DOWNTO 1),
bbsat=>synth0028(43),bbzip=>synth0028(44),
cc=>synth0030(42 DOWNTO 1),
ccsat=>synth0030(43),cczip=>synth0030(44));
cmp30: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0151(42 DOWNTO 1),
aasat=>castx0151(43),aazip=>castx0151(44),
bb=>castx0215(42 DOWNTO 1),
bbsat=>castx0215(43),bbzip=>castx0215(44),
cc=>synth0031(42 DOWNTO 1),
ccsat=>synth0031(43),cczip=>synth0031(44));
cmp31: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0150(42 DOWNTO 1),
aasat=>castx0150(43),aazip=>castx0150(44),
bb=>castx0214(42 DOWNTO 1),
bbsat=>castx0214(43),bbzip=>castx0214(44),
cc=>synth0032(42 DOWNTO 1),
ccsat=>synth0032(43),cczip=>synth0032(44));
cmp32: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0149(42 DOWNTO 1),
aasat=>castx0149(43),aazip=>castx0149(44),
bb=>castx0213(42 DOWNTO 1),
bbsat=>castx0213(43),bbzip=>castx0213(44),
cc=>synth0033(42 DOWNTO 1),
ccsat=>synth0033(43),cczip=>synth0033(44));
cmp33: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0148(42 DOWNTO 1),
aasat=>castx0148(43),aazip=>castx0148(44),
bb=>castx0212(42 DOWNTO 1),
bbsat=>castx0212(43),bbzip=>castx0212(44),
cc=>synth0034(42 DOWNTO 1),
ccsat=>synth0034(43),cczip=>synth0034(44));
cmp34: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0147(42 DOWNTO 1),
aasat=>castx0147(43),aazip=>castx0147(44),
bb=>castx0211(42 DOWNTO 1),
bbsat=>castx0211(43),bbzip=>castx0211(44),
cc=>synth0035(42 DOWNTO 1),
ccsat=>synth0035(43),cczip=>synth0035(44));
cmp35: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0146(42 DOWNTO 1),
aasat=>castx0146(43),aazip=>castx0146(44),
bb=>castx0210(42 DOWNTO 1),
bbsat=>castx0210(43),bbzip=>castx0210(44),
cc=>synth0036(42 DOWNTO 1),
ccsat=>synth0036(43),cczip=>synth0036(44));
cmp36: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0145(42 DOWNTO 1),
aasat=>castx0145(43),aazip=>castx0145(44),
bb=>castx0209(42 DOWNTO 1),
bbsat=>castx0209(43),bbzip=>castx0209(44),
cc=>synth0037(42 DOWNTO 1),
ccsat=>synth0037(43),cczip=>synth0037(44));
cmp37: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0144(42 DOWNTO 1),
aasat=>castx0144(43),aazip=>castx0144(44),
bb=>castx0208(42 DOWNTO 1),
bbsat=>castx0208(43),bbzip=>castx0208(44),
cc=>synth0038(42 DOWNTO 1),
ccsat=>synth0038(43),cczip=>synth0038(44));
cmp38: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0032(42 DOWNTO 1),
aasat=>synth0032(43),aazip=>synth0032(44),
bb=>synth0031(42 DOWNTO 1),
bbsat=>synth0031(43),bbzip=>synth0031(44),
cc=>synth0039(42 DOWNTO 1),
ccsat=>synth0039(43),cczip=>synth0039(44));
cmp39: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0034(42 DOWNTO 1),
aasat=>synth0034(43),aazip=>synth0034(44),
bb=>synth0033(42 DOWNTO 1),
bbsat=>synth0033(43),bbzip=>synth0033(44),
cc=>synth0040(42 DOWNTO 1),
ccsat=>synth0040(43),cczip=>synth0040(44));
cmp40: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0036(42 DOWNTO 1),
aasat=>synth0036(43),aazip=>synth0036(44),
bb=>synth0035(42 DOWNTO 1),
bbsat=>synth0035(43),bbzip=>synth0035(44),
cc=>synth0041(42 DOWNTO 1),
ccsat=>synth0041(43),cczip=>synth0041(44));
cmp41: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0038(42 DOWNTO 1),
aasat=>synth0038(43),aazip=>synth0038(44),
bb=>synth0037(42 DOWNTO 1),
bbsat=>synth0037(43),bbzip=>synth0037(44),
cc=>synth0042(42 DOWNTO 1),
ccsat=>synth0042(43),cczip=>synth0042(44));
cmp42: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0040(42 DOWNTO 1),
aasat=>synth0040(43),aazip=>synth0040(44),
bb=>synth0039(42 DOWNTO 1),
bbsat=>synth0039(43),bbzip=>synth0039(44),
cc=>synth0043(42 DOWNTO 1),
ccsat=>synth0043(43),cczip=>synth0043(44));
cmp43: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0042(42 DOWNTO 1),
aasat=>synth0042(43),aazip=>synth0042(44),
bb=>synth0041(42 DOWNTO 1),
bbsat=>synth0041(43),bbzip=>synth0041(44),
cc=>synth0044(42 DOWNTO 1),
ccsat=>synth0044(43),cczip=>synth0044(44));
cmp44: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0044(42 DOWNTO 1),
aasat=>synth0044(43),aazip=>synth0044(44),
bb=>synth0043(42 DOWNTO 1),
bbsat=>synth0043(43),bbzip=>synth0043(44),
cc=>synth0045(42 DOWNTO 1),
ccsat=>synth0045(43),cczip=>synth0045(44));
cmp45: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0159(42 DOWNTO 1),
aasat=>castx0159(43),aazip=>castx0159(44),
bb=>castx0223(42 DOWNTO 1),
bbsat=>castx0223(43),bbzip=>castx0223(44),
cc=>synth0046(42 DOWNTO 1),
ccsat=>synth0046(43),cczip=>synth0046(44));
cmp46: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0158(42 DOWNTO 1),
aasat=>castx0158(43),aazip=>castx0158(44),
bb=>castx0222(42 DOWNTO 1),
bbsat=>castx0222(43),bbzip=>castx0222(44),
cc=>synth0047(42 DOWNTO 1),
ccsat=>synth0047(43),cczip=>synth0047(44));
cmp47: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0157(42 DOWNTO 1),
aasat=>castx0157(43),aazip=>castx0157(44),
bb=>castx0221(42 DOWNTO 1),
bbsat=>castx0221(43),bbzip=>castx0221(44),
cc=>synth0048(42 DOWNTO 1),
ccsat=>synth0048(43),cczip=>synth0048(44));
cmp48: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0156(42 DOWNTO 1),
aasat=>castx0156(43),aazip=>castx0156(44),
bb=>castx0220(42 DOWNTO 1),
bbsat=>castx0220(43),bbzip=>castx0220(44),
cc=>synth0049(42 DOWNTO 1),
ccsat=>synth0049(43),cczip=>synth0049(44));
cmp49: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0155(42 DOWNTO 1),
aasat=>castx0155(43),aazip=>castx0155(44),
bb=>castx0219(42 DOWNTO 1),
bbsat=>castx0219(43),bbzip=>castx0219(44),
cc=>synth0050(42 DOWNTO 1),
ccsat=>synth0050(43),cczip=>synth0050(44));
cmp50: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0154(42 DOWNTO 1),
aasat=>castx0154(43),aazip=>castx0154(44),
bb=>castx0218(42 DOWNTO 1),
bbsat=>castx0218(43),bbzip=>castx0218(44),
cc=>synth0051(42 DOWNTO 1),
ccsat=>synth0051(43),cczip=>synth0051(44));
cmp51: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0153(42 DOWNTO 1),
aasat=>castx0153(43),aazip=>castx0153(44),
bb=>castx0217(42 DOWNTO 1),
bbsat=>castx0217(43),bbzip=>castx0217(44),
cc=>synth0052(42 DOWNTO 1),
ccsat=>synth0052(43),cczip=>synth0052(44));
cmp52: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0152(42 DOWNTO 1),
aasat=>castx0152(43),aazip=>castx0152(44),
bb=>castx0216(42 DOWNTO 1),
bbsat=>castx0216(43),bbzip=>castx0216(44),
cc=>synth0053(42 DOWNTO 1),
ccsat=>synth0053(43),cczip=>synth0053(44));
cmp53: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0047(42 DOWNTO 1),
aasat=>synth0047(43),aazip=>synth0047(44),
bb=>synth0046(42 DOWNTO 1),
bbsat=>synth0046(43),bbzip=>synth0046(44),
cc=>synth0054(42 DOWNTO 1),
ccsat=>synth0054(43),cczip=>synth0054(44));
cmp54: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0049(42 DOWNTO 1),
aasat=>synth0049(43),aazip=>synth0049(44),
bb=>synth0048(42 DOWNTO 1),
bbsat=>synth0048(43),bbzip=>synth0048(44),
cc=>synth0055(42 DOWNTO 1),
ccsat=>synth0055(43),cczip=>synth0055(44));
cmp55: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0051(42 DOWNTO 1),
aasat=>synth0051(43),aazip=>synth0051(44),
bb=>synth0050(42 DOWNTO 1),
bbsat=>synth0050(43),bbzip=>synth0050(44),
cc=>synth0056(42 DOWNTO 1),
ccsat=>synth0056(43),cczip=>synth0056(44));
cmp56: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0053(42 DOWNTO 1),
aasat=>synth0053(43),aazip=>synth0053(44),
bb=>synth0052(42 DOWNTO 1),
bbsat=>synth0052(43),bbzip=>synth0052(44),
cc=>synth0057(42 DOWNTO 1),
ccsat=>synth0057(43),cczip=>synth0057(44));
cmp57: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0055(42 DOWNTO 1),
aasat=>synth0055(43),aazip=>synth0055(44),
bb=>synth0054(42 DOWNTO 1),
bbsat=>synth0054(43),bbzip=>synth0054(44),
cc=>synth0058(42 DOWNTO 1),
ccsat=>synth0058(43),cczip=>synth0058(44));
cmp58: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0057(42 DOWNTO 1),
aasat=>synth0057(43),aazip=>synth0057(44),
bb=>synth0056(42 DOWNTO 1),
bbsat=>synth0056(43),bbzip=>synth0056(44),
cc=>synth0059(42 DOWNTO 1),
ccsat=>synth0059(43),cczip=>synth0059(44));
cmp59: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0059(42 DOWNTO 1),
aasat=>synth0059(43),aazip=>synth0059(44),
bb=>synth0058(42 DOWNTO 1),
bbsat=>synth0058(43),bbzip=>synth0058(44),
cc=>synth0060(42 DOWNTO 1),
ccsat=>synth0060(43),cczip=>synth0060(44));
cmp60: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0167(42 DOWNTO 1),
aasat=>castx0167(43),aazip=>castx0167(44),
bb=>castx0231(42 DOWNTO 1),
bbsat=>castx0231(43),bbzip=>castx0231(44),
cc=>synth0061(42 DOWNTO 1),
ccsat=>synth0061(43),cczip=>synth0061(44));
cmp61: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0166(42 DOWNTO 1),
aasat=>castx0166(43),aazip=>castx0166(44),
bb=>castx0230(42 DOWNTO 1),
bbsat=>castx0230(43),bbzip=>castx0230(44),
cc=>synth0062(42 DOWNTO 1),
ccsat=>synth0062(43),cczip=>synth0062(44));
cmp62: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0165(42 DOWNTO 1),
aasat=>castx0165(43),aazip=>castx0165(44),
bb=>castx0229(42 DOWNTO 1),
bbsat=>castx0229(43),bbzip=>castx0229(44),
cc=>synth0063(42 DOWNTO 1),
ccsat=>synth0063(43),cczip=>synth0063(44));
cmp63: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0164(42 DOWNTO 1),
aasat=>castx0164(43),aazip=>castx0164(44),
bb=>castx0228(42 DOWNTO 1),
bbsat=>castx0228(43),bbzip=>castx0228(44),
cc=>synth0064(42 DOWNTO 1),
ccsat=>synth0064(43),cczip=>synth0064(44));
cmp64: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0163(42 DOWNTO 1),
aasat=>castx0163(43),aazip=>castx0163(44),
bb=>castx0227(42 DOWNTO 1),
bbsat=>castx0227(43),bbzip=>castx0227(44),
cc=>synth0065(42 DOWNTO 1),
ccsat=>synth0065(43),cczip=>synth0065(44));
cmp65: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0162(42 DOWNTO 1),
aasat=>castx0162(43),aazip=>castx0162(44),
bb=>castx0226(42 DOWNTO 1),
bbsat=>castx0226(43),bbzip=>castx0226(44),
cc=>synth0066(42 DOWNTO 1),
ccsat=>synth0066(43),cczip=>synth0066(44));
cmp66: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0161(42 DOWNTO 1),
aasat=>castx0161(43),aazip=>castx0161(44),
bb=>castx0225(42 DOWNTO 1),
bbsat=>castx0225(43),bbzip=>castx0225(44),
cc=>synth0067(42 DOWNTO 1),
ccsat=>synth0067(43),cczip=>synth0067(44));
cmp67: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0160(42 DOWNTO 1),
aasat=>castx0160(43),aazip=>castx0160(44),
bb=>castx0224(42 DOWNTO 1),
bbsat=>castx0224(43),bbzip=>castx0224(44),
cc=>synth0068(42 DOWNTO 1),
ccsat=>synth0068(43),cczip=>synth0068(44));
cmp68: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0062(42 DOWNTO 1),
aasat=>synth0062(43),aazip=>synth0062(44),
bb=>synth0061(42 DOWNTO 1),
bbsat=>synth0061(43),bbzip=>synth0061(44),
cc=>synth0069(42 DOWNTO 1),
ccsat=>synth0069(43),cczip=>synth0069(44));
cmp69: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0064(42 DOWNTO 1),
aasat=>synth0064(43),aazip=>synth0064(44),
bb=>synth0063(42 DOWNTO 1),
bbsat=>synth0063(43),bbzip=>synth0063(44),
cc=>synth0070(42 DOWNTO 1),
ccsat=>synth0070(43),cczip=>synth0070(44));
cmp70: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0066(42 DOWNTO 1),
aasat=>synth0066(43),aazip=>synth0066(44),
bb=>synth0065(42 DOWNTO 1),
bbsat=>synth0065(43),bbzip=>synth0065(44),
cc=>synth0071(42 DOWNTO 1),
ccsat=>synth0071(43),cczip=>synth0071(44));
cmp71: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0068(42 DOWNTO 1),
aasat=>synth0068(43),aazip=>synth0068(44),
bb=>synth0067(42 DOWNTO 1),
bbsat=>synth0067(43),bbzip=>synth0067(44),
cc=>synth0072(42 DOWNTO 1),
ccsat=>synth0072(43),cczip=>synth0072(44));
cmp72: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0070(42 DOWNTO 1),
aasat=>synth0070(43),aazip=>synth0070(44),
bb=>synth0069(42 DOWNTO 1),
bbsat=>synth0069(43),bbzip=>synth0069(44),
cc=>synth0073(42 DOWNTO 1),
ccsat=>synth0073(43),cczip=>synth0073(44));
cmp73: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0072(42 DOWNTO 1),
aasat=>synth0072(43),aazip=>synth0072(44),
bb=>synth0071(42 DOWNTO 1),
bbsat=>synth0071(43),bbzip=>synth0071(44),
cc=>synth0074(42 DOWNTO 1),
ccsat=>synth0074(43),cczip=>synth0074(44));
cmp74: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0074(42 DOWNTO 1),
aasat=>synth0074(43),aazip=>synth0074(44),
bb=>synth0073(42 DOWNTO 1),
bbsat=>synth0073(43),bbzip=>synth0073(44),
cc=>synth0075(42 DOWNTO 1),
ccsat=>synth0075(43),cczip=>synth0075(44));
cmp75: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0175(42 DOWNTO 1),
aasat=>castx0175(43),aazip=>castx0175(44),
bb=>castx0239(42 DOWNTO 1),
bbsat=>castx0239(43),bbzip=>castx0239(44),
cc=>synth0076(42 DOWNTO 1),
ccsat=>synth0076(43),cczip=>synth0076(44));
cmp76: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0174(42 DOWNTO 1),
aasat=>castx0174(43),aazip=>castx0174(44),
bb=>castx0238(42 DOWNTO 1),
bbsat=>castx0238(43),bbzip=>castx0238(44),
cc=>synth0077(42 DOWNTO 1),
ccsat=>synth0077(43),cczip=>synth0077(44));
cmp77: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0173(42 DOWNTO 1),
aasat=>castx0173(43),aazip=>castx0173(44),
bb=>castx0237(42 DOWNTO 1),
bbsat=>castx0237(43),bbzip=>castx0237(44),
cc=>synth0078(42 DOWNTO 1),
ccsat=>synth0078(43),cczip=>synth0078(44));
cmp78: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0172(42 DOWNTO 1),
aasat=>castx0172(43),aazip=>castx0172(44),
bb=>castx0236(42 DOWNTO 1),
bbsat=>castx0236(43),bbzip=>castx0236(44),
cc=>synth0079(42 DOWNTO 1),
ccsat=>synth0079(43),cczip=>synth0079(44));
cmp79: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0171(42 DOWNTO 1),
aasat=>castx0171(43),aazip=>castx0171(44),
bb=>castx0235(42 DOWNTO 1),
bbsat=>castx0235(43),bbzip=>castx0235(44),
cc=>synth0080(42 DOWNTO 1),
ccsat=>synth0080(43),cczip=>synth0080(44));
cmp80: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0170(42 DOWNTO 1),
aasat=>castx0170(43),aazip=>castx0170(44),
bb=>castx0234(42 DOWNTO 1),
bbsat=>castx0234(43),bbzip=>castx0234(44),
cc=>synth0081(42 DOWNTO 1),
ccsat=>synth0081(43),cczip=>synth0081(44));
cmp81: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0169(42 DOWNTO 1),
aasat=>castx0169(43),aazip=>castx0169(44),
bb=>castx0233(42 DOWNTO 1),
bbsat=>castx0233(43),bbzip=>castx0233(44),
cc=>synth0082(42 DOWNTO 1),
ccsat=>synth0082(43),cczip=>synth0082(44));
cmp82: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0168(42 DOWNTO 1),
aasat=>castx0168(43),aazip=>castx0168(44),
bb=>castx0232(42 DOWNTO 1),
bbsat=>castx0232(43),bbzip=>castx0232(44),
cc=>synth0083(42 DOWNTO 1),
ccsat=>synth0083(43),cczip=>synth0083(44));
cmp83: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0077(42 DOWNTO 1),
aasat=>synth0077(43),aazip=>synth0077(44),
bb=>synth0076(42 DOWNTO 1),
bbsat=>synth0076(43),bbzip=>synth0076(44),
cc=>synth0084(42 DOWNTO 1),
ccsat=>synth0084(43),cczip=>synth0084(44));
cmp84: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0079(42 DOWNTO 1),
aasat=>synth0079(43),aazip=>synth0079(44),
bb=>synth0078(42 DOWNTO 1),
bbsat=>synth0078(43),bbzip=>synth0078(44),
cc=>synth0085(42 DOWNTO 1),
ccsat=>synth0085(43),cczip=>synth0085(44));
cmp85: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0081(42 DOWNTO 1),
aasat=>synth0081(43),aazip=>synth0081(44),
bb=>synth0080(42 DOWNTO 1),
bbsat=>synth0080(43),bbzip=>synth0080(44),
cc=>synth0086(42 DOWNTO 1),
ccsat=>synth0086(43),cczip=>synth0086(44));
cmp86: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0083(42 DOWNTO 1),
aasat=>synth0083(43),aazip=>synth0083(44),
bb=>synth0082(42 DOWNTO 1),
bbsat=>synth0082(43),bbzip=>synth0082(44),
cc=>synth0087(42 DOWNTO 1),
ccsat=>synth0087(43),cczip=>synth0087(44));
cmp87: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0085(42 DOWNTO 1),
aasat=>synth0085(43),aazip=>synth0085(44),
bb=>synth0084(42 DOWNTO 1),
bbsat=>synth0084(43),bbzip=>synth0084(44),
cc=>synth0088(42 DOWNTO 1),
ccsat=>synth0088(43),cczip=>synth0088(44));
cmp88: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0087(42 DOWNTO 1),
aasat=>synth0087(43),aazip=>synth0087(44),
bb=>synth0086(42 DOWNTO 1),
bbsat=>synth0086(43),bbzip=>synth0086(44),
cc=>synth0089(42 DOWNTO 1),
ccsat=>synth0089(43),cczip=>synth0089(44));
cmp89: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0089(42 DOWNTO 1),
aasat=>synth0089(43),aazip=>synth0089(44),
bb=>synth0088(42 DOWNTO 1),
bbsat=>synth0088(43),bbzip=>synth0088(44),
cc=>synth0090(42 DOWNTO 1),
ccsat=>synth0090(43),cczip=>synth0090(44));
cmp90: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0183(42 DOWNTO 1),
aasat=>castx0183(43),aazip=>castx0183(44),
bb=>castx0247(42 DOWNTO 1),
bbsat=>castx0247(43),bbzip=>castx0247(44),
cc=>synth0091(42 DOWNTO 1),
ccsat=>synth0091(43),cczip=>synth0091(44));
cmp91: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0182(42 DOWNTO 1),
aasat=>castx0182(43),aazip=>castx0182(44),
bb=>castx0246(42 DOWNTO 1),
bbsat=>castx0246(43),bbzip=>castx0246(44),
cc=>synth0092(42 DOWNTO 1),
ccsat=>synth0092(43),cczip=>synth0092(44));
cmp92: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0181(42 DOWNTO 1),
aasat=>castx0181(43),aazip=>castx0181(44),
bb=>castx0245(42 DOWNTO 1),
bbsat=>castx0245(43),bbzip=>castx0245(44),
cc=>synth0093(42 DOWNTO 1),
ccsat=>synth0093(43),cczip=>synth0093(44));
cmp93: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0180(42 DOWNTO 1),
aasat=>castx0180(43),aazip=>castx0180(44),
bb=>castx0244(42 DOWNTO 1),
bbsat=>castx0244(43),bbzip=>castx0244(44),
cc=>synth0094(42 DOWNTO 1),
ccsat=>synth0094(43),cczip=>synth0094(44));
cmp94: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0179(42 DOWNTO 1),
aasat=>castx0179(43),aazip=>castx0179(44),
bb=>castx0243(42 DOWNTO 1),
bbsat=>castx0243(43),bbzip=>castx0243(44),
cc=>synth0095(42 DOWNTO 1),
ccsat=>synth0095(43),cczip=>synth0095(44));
cmp95: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0178(42 DOWNTO 1),
aasat=>castx0178(43),aazip=>castx0178(44),
bb=>castx0242(42 DOWNTO 1),
bbsat=>castx0242(43),bbzip=>castx0242(44),
cc=>synth0096(42 DOWNTO 1),
ccsat=>synth0096(43),cczip=>synth0096(44));
cmp96: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0177(42 DOWNTO 1),
aasat=>castx0177(43),aazip=>castx0177(44),
bb=>castx0241(42 DOWNTO 1),
bbsat=>castx0241(43),bbzip=>castx0241(44),
cc=>synth0097(42 DOWNTO 1),
ccsat=>synth0097(43),cczip=>synth0097(44));
cmp97: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0176(42 DOWNTO 1),
aasat=>castx0176(43),aazip=>castx0176(44),
bb=>castx0240(42 DOWNTO 1),
bbsat=>castx0240(43),bbzip=>castx0240(44),
cc=>synth0098(42 DOWNTO 1),
ccsat=>synth0098(43),cczip=>synth0098(44));
cmp98: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0092(42 DOWNTO 1),
aasat=>synth0092(43),aazip=>synth0092(44),
bb=>synth0091(42 DOWNTO 1),
bbsat=>synth0091(43),bbzip=>synth0091(44),
cc=>synth0099(42 DOWNTO 1),
ccsat=>synth0099(43),cczip=>synth0099(44));
cmp99: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0094(42 DOWNTO 1),
aasat=>synth0094(43),aazip=>synth0094(44),
bb=>synth0093(42 DOWNTO 1),
bbsat=>synth0093(43),bbzip=>synth0093(44),
cc=>synth0100(42 DOWNTO 1),
ccsat=>synth0100(43),cczip=>synth0100(44));
cmp100: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0096(42 DOWNTO 1),
aasat=>synth0096(43),aazip=>synth0096(44),
bb=>synth0095(42 DOWNTO 1),
bbsat=>synth0095(43),bbzip=>synth0095(44),
cc=>synth0101(42 DOWNTO 1),
ccsat=>synth0101(43),cczip=>synth0101(44));
cmp101: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0098(42 DOWNTO 1),
aasat=>synth0098(43),aazip=>synth0098(44),
bb=>synth0097(42 DOWNTO 1),
bbsat=>synth0097(43),bbzip=>synth0097(44),
cc=>synth0102(42 DOWNTO 1),
ccsat=>synth0102(43),cczip=>synth0102(44));
cmp102: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0100(42 DOWNTO 1),
aasat=>synth0100(43),aazip=>synth0100(44),
bb=>synth0099(42 DOWNTO 1),
bbsat=>synth0099(43),bbzip=>synth0099(44),
cc=>synth0103(42 DOWNTO 1),
ccsat=>synth0103(43),cczip=>synth0103(44));
cmp103: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0102(42 DOWNTO 1),
aasat=>synth0102(43),aazip=>synth0102(44),
bb=>synth0101(42 DOWNTO 1),
bbsat=>synth0101(43),bbzip=>synth0101(44),
cc=>synth0104(42 DOWNTO 1),
ccsat=>synth0104(43),cczip=>synth0104(44));
cmp104: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0104(42 DOWNTO 1),
aasat=>synth0104(43),aazip=>synth0104(44),
bb=>synth0103(42 DOWNTO 1),
bbsat=>synth0103(43),bbzip=>synth0103(44),
cc=>synth0105(42 DOWNTO 1),
ccsat=>synth0105(43),cczip=>synth0105(44));
cmp105: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0191(42 DOWNTO 1),
aasat=>castx0191(43),aazip=>castx0191(44),
bb=>castx0255(42 DOWNTO 1),
bbsat=>castx0255(43),bbzip=>castx0255(44),
cc=>synth0106(42 DOWNTO 1),
ccsat=>synth0106(43),cczip=>synth0106(44));
cmp106: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0190(42 DOWNTO 1),
aasat=>castx0190(43),aazip=>castx0190(44),
bb=>castx0254(42 DOWNTO 1),
bbsat=>castx0254(43),bbzip=>castx0254(44),
cc=>synth0107(42 DOWNTO 1),
ccsat=>synth0107(43),cczip=>synth0107(44));
cmp107: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0189(42 DOWNTO 1),
aasat=>castx0189(43),aazip=>castx0189(44),
bb=>castx0253(42 DOWNTO 1),
bbsat=>castx0253(43),bbzip=>castx0253(44),
cc=>synth0108(42 DOWNTO 1),
ccsat=>synth0108(43),cczip=>synth0108(44));
cmp108: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0188(42 DOWNTO 1),
aasat=>castx0188(43),aazip=>castx0188(44),
bb=>castx0252(42 DOWNTO 1),
bbsat=>castx0252(43),bbzip=>castx0252(44),
cc=>synth0109(42 DOWNTO 1),
ccsat=>synth0109(43),cczip=>synth0109(44));
cmp109: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0187(42 DOWNTO 1),
aasat=>castx0187(43),aazip=>castx0187(44),
bb=>castx0251(42 DOWNTO 1),
bbsat=>castx0251(43),bbzip=>castx0251(44),
cc=>synth0110(42 DOWNTO 1),
ccsat=>synth0110(43),cczip=>synth0110(44));
cmp110: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0186(42 DOWNTO 1),
aasat=>castx0186(43),aazip=>castx0186(44),
bb=>castx0250(42 DOWNTO 1),
bbsat=>castx0250(43),bbzip=>castx0250(44),
cc=>synth0111(42 DOWNTO 1),
ccsat=>synth0111(43),cczip=>synth0111(44));
cmp111: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0185(42 DOWNTO 1),
aasat=>castx0185(43),aazip=>castx0185(44),
bb=>castx0249(42 DOWNTO 1),
bbsat=>castx0249(43),bbzip=>castx0249(44),
cc=>synth0112(42 DOWNTO 1),
ccsat=>synth0112(43),cczip=>synth0112(44));
cmp112: hcc_mulfp1x
GENERIC MAP (mantissa=>32,outputscale=>0,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>castx0184(42 DOWNTO 1),
aasat=>castx0184(43),aazip=>castx0184(44),
bb=>castx0248(42 DOWNTO 1),
bbsat=>castx0248(43),bbzip=>castx0248(44),
cc=>synth0113(42 DOWNTO 1),
ccsat=>synth0113(43),cczip=>synth0113(44));
cmp113: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0107(42 DOWNTO 1),
aasat=>synth0107(43),aazip=>synth0107(44),
bb=>synth0106(42 DOWNTO 1),
bbsat=>synth0106(43),bbzip=>synth0106(44),
cc=>synth0114(42 DOWNTO 1),
ccsat=>synth0114(43),cczip=>synth0114(44));
cmp114: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0109(42 DOWNTO 1),
aasat=>synth0109(43),aazip=>synth0109(44),
bb=>synth0108(42 DOWNTO 1),
bbsat=>synth0108(43),bbzip=>synth0108(44),
cc=>synth0115(42 DOWNTO 1),
ccsat=>synth0115(43),cczip=>synth0115(44));
cmp115: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0111(42 DOWNTO 1),
aasat=>synth0111(43),aazip=>synth0111(44),
bb=>synth0110(42 DOWNTO 1),
bbsat=>synth0110(43),bbzip=>synth0110(44),
cc=>synth0116(42 DOWNTO 1),
ccsat=>synth0116(43),cczip=>synth0116(44));
cmp116: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0113(42 DOWNTO 1),
aasat=>synth0113(43),aazip=>synth0113(44),
bb=>synth0112(42 DOWNTO 1),
bbsat=>synth0112(43),bbzip=>synth0112(44),
cc=>synth0117(42 DOWNTO 1),
ccsat=>synth0117(43),cczip=>synth0117(44));
cmp117: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0115(42 DOWNTO 1),
aasat=>synth0115(43),aazip=>synth0115(44),
bb=>synth0114(42 DOWNTO 1),
bbsat=>synth0114(43),bbzip=>synth0114(44),
cc=>synth0118(42 DOWNTO 1),
ccsat=>synth0118(43),cczip=>synth0118(44));
cmp118: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0117(42 DOWNTO 1),
aasat=>synth0117(43),aazip=>synth0117(44),
bb=>synth0116(42 DOWNTO 1),
bbsat=>synth0116(43),bbzip=>synth0116(44),
cc=>synth0119(42 DOWNTO 1),
ccsat=>synth0119(43),cczip=>synth0119(44));
cmp119: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0119(42 DOWNTO 1),
aasat=>synth0119(43),aazip=>synth0119(44),
bb=>synth0118(42 DOWNTO 1),
bbsat=>synth0118(43),bbzip=>synth0118(44),
cc=>synth0120(42 DOWNTO 1),
ccsat=>synth0120(43),cczip=>synth0120(44));
cmp120: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0259(42 DOWNTO 1),
aasat=>synth0259(43),aazip=>synth0259(44),
bb=>synth0260(42 DOWNTO 1),
bbsat=>synth0260(43),bbzip=>synth0260(44),
cc=>synth0121(42 DOWNTO 1),
ccsat=>synth0121(43),cczip=>synth0121(44));
cmp121: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0257(42 DOWNTO 1),
aasat=>synth0257(43),aazip=>synth0257(44),
bb=>synth0258(42 DOWNTO 1),
bbsat=>synth0258(43),bbzip=>synth0258(44),
cc=>synth0122(42 DOWNTO 1),
ccsat=>synth0122(43),cczip=>synth0122(44));
cmp122: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0122(42 DOWNTO 1),
aasat=>synth0122(43),aazip=>synth0122(44),
bb=>synth0121(42 DOWNTO 1),
bbsat=>synth0121(43),bbzip=>synth0121(44),
cc=>synth0123(42 DOWNTO 1),
ccsat=>synth0123(43),cczip=>synth0123(44));
cmp123: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0263(42 DOWNTO 1),
aasat=>synth0263(43),aazip=>synth0263(44),
bb=>synth0264(42 DOWNTO 1),
bbsat=>synth0264(43),bbzip=>synth0264(44),
cc=>synth0124(42 DOWNTO 1),
ccsat=>synth0124(43),cczip=>synth0124(44));
cmp124: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0261(42 DOWNTO 1),
aasat=>synth0261(43),aazip=>synth0261(44),
bb=>synth0262(42 DOWNTO 1),
bbsat=>synth0262(43),bbzip=>synth0262(44),
cc=>synth0125(42 DOWNTO 1),
ccsat=>synth0125(43),cczip=>synth0125(44));
cmp125: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>synth0125(42 DOWNTO 1),
aasat=>synth0125(43),aazip=>synth0125(44),
bb=>synth0124(42 DOWNTO 1),
bbsat=>synth0124(43),bbzip=>synth0124(44),
cc=>synth0126(42 DOWNTO 1),
ccsat=>synth0126(43),cczip=>synth0126(44));
cmp126: hcc_alufp1x
GENERIC MAP (mantissa=>32,shiftspeed=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
addsub=>'0',
aa=>mid00(42 DOWNTO 1),
aasat=>mid00(43),aazip=>mid00(44),
bb=>mid01(42 DOWNTO 1),
bbsat=>mid01(43),bbzip=>mid01(44),
cc=>synth0127(42 DOWNTO 1),
ccsat=>synth0127(43),cczip=>synth0127(44));
cmp127: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx00(32 DOWNTO 1),
cc=>castx0128(42 DOWNTO 1),
ccsat=>castx0128(43),cczip=>castx0128(44));
cmp128: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx01(32 DOWNTO 1),
cc=>castx0129(42 DOWNTO 1),
ccsat=>castx0129(43),cczip=>castx0129(44));
cmp129: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx02(32 DOWNTO 1),
cc=>castx0130(42 DOWNTO 1),
ccsat=>castx0130(43),cczip=>castx0130(44));
cmp130: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx03(32 DOWNTO 1),
cc=>castx0131(42 DOWNTO 1),
ccsat=>castx0131(43),cczip=>castx0131(44));
cmp131: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx04(32 DOWNTO 1),
cc=>castx0132(42 DOWNTO 1),
ccsat=>castx0132(43),cczip=>castx0132(44));
cmp132: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx05(32 DOWNTO 1),
cc=>castx0133(42 DOWNTO 1),
ccsat=>castx0133(43),cczip=>castx0133(44));
cmp133: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx06(32 DOWNTO 1),
cc=>castx0134(42 DOWNTO 1),
ccsat=>castx0134(43),cczip=>castx0134(44));
cmp134: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx07(32 DOWNTO 1),
cc=>castx0135(42 DOWNTO 1),
ccsat=>castx0135(43),cczip=>castx0135(44));
cmp135: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx08(32 DOWNTO 1),
cc=>castx0136(42 DOWNTO 1),
ccsat=>castx0136(43),cczip=>castx0136(44));
cmp136: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx09(32 DOWNTO 1),
cc=>castx0137(42 DOWNTO 1),
ccsat=>castx0137(43),cczip=>castx0137(44));
cmp137: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0a(32 DOWNTO 1),
cc=>castx0138(42 DOWNTO 1),
ccsat=>castx0138(43),cczip=>castx0138(44));
cmp138: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0b(32 DOWNTO 1),
cc=>castx0139(42 DOWNTO 1),
ccsat=>castx0139(43),cczip=>castx0139(44));
cmp139: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0c(32 DOWNTO 1),
cc=>castx0140(42 DOWNTO 1),
ccsat=>castx0140(43),cczip=>castx0140(44));
cmp140: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0d(32 DOWNTO 1),
cc=>castx0141(42 DOWNTO 1),
ccsat=>castx0141(43),cczip=>castx0141(44));
cmp141: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0e(32 DOWNTO 1),
cc=>castx0142(42 DOWNTO 1),
ccsat=>castx0142(43),cczip=>castx0142(44));
cmp142: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx0f(32 DOWNTO 1),
cc=>castx0143(42 DOWNTO 1),
ccsat=>castx0143(43),cczip=>castx0143(44));
cmp143: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx10(32 DOWNTO 1),
cc=>castx0144(42 DOWNTO 1),
ccsat=>castx0144(43),cczip=>castx0144(44));
cmp144: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx11(32 DOWNTO 1),
cc=>castx0145(42 DOWNTO 1),
ccsat=>castx0145(43),cczip=>castx0145(44));
cmp145: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx12(32 DOWNTO 1),
cc=>castx0146(42 DOWNTO 1),
ccsat=>castx0146(43),cczip=>castx0146(44));
cmp146: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx13(32 DOWNTO 1),
cc=>castx0147(42 DOWNTO 1),
ccsat=>castx0147(43),cczip=>castx0147(44));
cmp147: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx14(32 DOWNTO 1),
cc=>castx0148(42 DOWNTO 1),
ccsat=>castx0148(43),cczip=>castx0148(44));
cmp148: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx15(32 DOWNTO 1),
cc=>castx0149(42 DOWNTO 1),
ccsat=>castx0149(43),cczip=>castx0149(44));
cmp149: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx16(32 DOWNTO 1),
cc=>castx0150(42 DOWNTO 1),
ccsat=>castx0150(43),cczip=>castx0150(44));
cmp150: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx17(32 DOWNTO 1),
cc=>castx0151(42 DOWNTO 1),
ccsat=>castx0151(43),cczip=>castx0151(44));
cmp151: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx18(32 DOWNTO 1),
cc=>castx0152(42 DOWNTO 1),
ccsat=>castx0152(43),cczip=>castx0152(44));
cmp152: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx19(32 DOWNTO 1),
cc=>castx0153(42 DOWNTO 1),
ccsat=>castx0153(43),cczip=>castx0153(44));
cmp153: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1a(32 DOWNTO 1),
cc=>castx0154(42 DOWNTO 1),
ccsat=>castx0154(43),cczip=>castx0154(44));
cmp154: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1b(32 DOWNTO 1),
cc=>castx0155(42 DOWNTO 1),
ccsat=>castx0155(43),cczip=>castx0155(44));
cmp155: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1c(32 DOWNTO 1),
cc=>castx0156(42 DOWNTO 1),
ccsat=>castx0156(43),cczip=>castx0156(44));
cmp156: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1d(32 DOWNTO 1),
cc=>castx0157(42 DOWNTO 1),
ccsat=>castx0157(43),cczip=>castx0157(44));
cmp157: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1e(32 DOWNTO 1),
cc=>castx0158(42 DOWNTO 1),
ccsat=>castx0158(43),cczip=>castx0158(44));
cmp158: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx1f(32 DOWNTO 1),
cc=>castx0159(42 DOWNTO 1),
ccsat=>castx0159(43),cczip=>castx0159(44));
cmp159: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx20(32 DOWNTO 1),
cc=>castx0160(42 DOWNTO 1),
ccsat=>castx0160(43),cczip=>castx0160(44));
cmp160: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx21(32 DOWNTO 1),
cc=>castx0161(42 DOWNTO 1),
ccsat=>castx0161(43),cczip=>castx0161(44));
cmp161: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx22(32 DOWNTO 1),
cc=>castx0162(42 DOWNTO 1),
ccsat=>castx0162(43),cczip=>castx0162(44));
cmp162: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx23(32 DOWNTO 1),
cc=>castx0163(42 DOWNTO 1),
ccsat=>castx0163(43),cczip=>castx0163(44));
cmp163: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx24(32 DOWNTO 1),
cc=>castx0164(42 DOWNTO 1),
ccsat=>castx0164(43),cczip=>castx0164(44));
cmp164: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx25(32 DOWNTO 1),
cc=>castx0165(42 DOWNTO 1),
ccsat=>castx0165(43),cczip=>castx0165(44));
cmp165: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx26(32 DOWNTO 1),
cc=>castx0166(42 DOWNTO 1),
ccsat=>castx0166(43),cczip=>castx0166(44));
cmp166: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx27(32 DOWNTO 1),
cc=>castx0167(42 DOWNTO 1),
ccsat=>castx0167(43),cczip=>castx0167(44));
cmp167: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx28(32 DOWNTO 1),
cc=>castx0168(42 DOWNTO 1),
ccsat=>castx0168(43),cczip=>castx0168(44));
cmp168: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx29(32 DOWNTO 1),
cc=>castx0169(42 DOWNTO 1),
ccsat=>castx0169(43),cczip=>castx0169(44));
cmp169: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2a(32 DOWNTO 1),
cc=>castx0170(42 DOWNTO 1),
ccsat=>castx0170(43),cczip=>castx0170(44));
cmp170: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2b(32 DOWNTO 1),
cc=>castx0171(42 DOWNTO 1),
ccsat=>castx0171(43),cczip=>castx0171(44));
cmp171: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2c(32 DOWNTO 1),
cc=>castx0172(42 DOWNTO 1),
ccsat=>castx0172(43),cczip=>castx0172(44));
cmp172: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2d(32 DOWNTO 1),
cc=>castx0173(42 DOWNTO 1),
ccsat=>castx0173(43),cczip=>castx0173(44));
cmp173: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2e(32 DOWNTO 1),
cc=>castx0174(42 DOWNTO 1),
ccsat=>castx0174(43),cczip=>castx0174(44));
cmp174: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx2f(32 DOWNTO 1),
cc=>castx0175(42 DOWNTO 1),
ccsat=>castx0175(43),cczip=>castx0175(44));
cmp175: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx30(32 DOWNTO 1),
cc=>castx0176(42 DOWNTO 1),
ccsat=>castx0176(43),cczip=>castx0176(44));
cmp176: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx31(32 DOWNTO 1),
cc=>castx0177(42 DOWNTO 1),
ccsat=>castx0177(43),cczip=>castx0177(44));
cmp177: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx32(32 DOWNTO 1),
cc=>castx0178(42 DOWNTO 1),
ccsat=>castx0178(43),cczip=>castx0178(44));
cmp178: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx33(32 DOWNTO 1),
cc=>castx0179(42 DOWNTO 1),
ccsat=>castx0179(43),cczip=>castx0179(44));
cmp179: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx34(32 DOWNTO 1),
cc=>castx0180(42 DOWNTO 1),
ccsat=>castx0180(43),cczip=>castx0180(44));
cmp180: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx35(32 DOWNTO 1),
cc=>castx0181(42 DOWNTO 1),
ccsat=>castx0181(43),cczip=>castx0181(44));
cmp181: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx36(32 DOWNTO 1),
cc=>castx0182(42 DOWNTO 1),
ccsat=>castx0182(43),cczip=>castx0182(44));
cmp182: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx37(32 DOWNTO 1),
cc=>castx0183(42 DOWNTO 1),
ccsat=>castx0183(43),cczip=>castx0183(44));
cmp183: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx38(32 DOWNTO 1),
cc=>castx0184(42 DOWNTO 1),
ccsat=>castx0184(43),cczip=>castx0184(44));
cmp184: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx39(32 DOWNTO 1),
cc=>castx0185(42 DOWNTO 1),
ccsat=>castx0185(43),cczip=>castx0185(44));
cmp185: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3a(32 DOWNTO 1),
cc=>castx0186(42 DOWNTO 1),
ccsat=>castx0186(43),cczip=>castx0186(44));
cmp186: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3b(32 DOWNTO 1),
cc=>castx0187(42 DOWNTO 1),
ccsat=>castx0187(43),cczip=>castx0187(44));
cmp187: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3c(32 DOWNTO 1),
cc=>castx0188(42 DOWNTO 1),
ccsat=>castx0188(43),cczip=>castx0188(44));
cmp188: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3d(32 DOWNTO 1),
cc=>castx0189(42 DOWNTO 1),
ccsat=>castx0189(43),cczip=>castx0189(44));
cmp189: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3e(32 DOWNTO 1),
cc=>castx0190(42 DOWNTO 1),
ccsat=>castx0190(43),cczip=>castx0190(44));
cmp190: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xx3f(32 DOWNTO 1),
cc=>castx0191(42 DOWNTO 1),
ccsat=>castx0191(43),cczip=>castx0191(44));
cmp191: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc00(32 DOWNTO 1),
cc=>castx0192(42 DOWNTO 1),
ccsat=>castx0192(43),cczip=>castx0192(44));
cmp192: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc01(32 DOWNTO 1),
cc=>castx0193(42 DOWNTO 1),
ccsat=>castx0193(43),cczip=>castx0193(44));
cmp193: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc02(32 DOWNTO 1),
cc=>castx0194(42 DOWNTO 1),
ccsat=>castx0194(43),cczip=>castx0194(44));
cmp194: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc03(32 DOWNTO 1),
cc=>castx0195(42 DOWNTO 1),
ccsat=>castx0195(43),cczip=>castx0195(44));
cmp195: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc04(32 DOWNTO 1),
cc=>castx0196(42 DOWNTO 1),
ccsat=>castx0196(43),cczip=>castx0196(44));
cmp196: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc05(32 DOWNTO 1),
cc=>castx0197(42 DOWNTO 1),
ccsat=>castx0197(43),cczip=>castx0197(44));
cmp197: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc06(32 DOWNTO 1),
cc=>castx0198(42 DOWNTO 1),
ccsat=>castx0198(43),cczip=>castx0198(44));
cmp198: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc07(32 DOWNTO 1),
cc=>castx0199(42 DOWNTO 1),
ccsat=>castx0199(43),cczip=>castx0199(44));
cmp199: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc08(32 DOWNTO 1),
cc=>castx0200(42 DOWNTO 1),
ccsat=>castx0200(43),cczip=>castx0200(44));
cmp200: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc09(32 DOWNTO 1),
cc=>castx0201(42 DOWNTO 1),
ccsat=>castx0201(43),cczip=>castx0201(44));
cmp201: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0a(32 DOWNTO 1),
cc=>castx0202(42 DOWNTO 1),
ccsat=>castx0202(43),cczip=>castx0202(44));
cmp202: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0b(32 DOWNTO 1),
cc=>castx0203(42 DOWNTO 1),
ccsat=>castx0203(43),cczip=>castx0203(44));
cmp203: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0c(32 DOWNTO 1),
cc=>castx0204(42 DOWNTO 1),
ccsat=>castx0204(43),cczip=>castx0204(44));
cmp204: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0d(32 DOWNTO 1),
cc=>castx0205(42 DOWNTO 1),
ccsat=>castx0205(43),cczip=>castx0205(44));
cmp205: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0e(32 DOWNTO 1),
cc=>castx0206(42 DOWNTO 1),
ccsat=>castx0206(43),cczip=>castx0206(44));
cmp206: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc0f(32 DOWNTO 1),
cc=>castx0207(42 DOWNTO 1),
ccsat=>castx0207(43),cczip=>castx0207(44));
cmp207: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc10(32 DOWNTO 1),
cc=>castx0208(42 DOWNTO 1),
ccsat=>castx0208(43),cczip=>castx0208(44));
cmp208: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc11(32 DOWNTO 1),
cc=>castx0209(42 DOWNTO 1),
ccsat=>castx0209(43),cczip=>castx0209(44));
cmp209: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc12(32 DOWNTO 1),
cc=>castx0210(42 DOWNTO 1),
ccsat=>castx0210(43),cczip=>castx0210(44));
cmp210: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc13(32 DOWNTO 1),
cc=>castx0211(42 DOWNTO 1),
ccsat=>castx0211(43),cczip=>castx0211(44));
cmp211: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc14(32 DOWNTO 1),
cc=>castx0212(42 DOWNTO 1),
ccsat=>castx0212(43),cczip=>castx0212(44));
cmp212: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc15(32 DOWNTO 1),
cc=>castx0213(42 DOWNTO 1),
ccsat=>castx0213(43),cczip=>castx0213(44));
cmp213: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc16(32 DOWNTO 1),
cc=>castx0214(42 DOWNTO 1),
ccsat=>castx0214(43),cczip=>castx0214(44));
cmp214: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc17(32 DOWNTO 1),
cc=>castx0215(42 DOWNTO 1),
ccsat=>castx0215(43),cczip=>castx0215(44));
cmp215: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc18(32 DOWNTO 1),
cc=>castx0216(42 DOWNTO 1),
ccsat=>castx0216(43),cczip=>castx0216(44));
cmp216: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc19(32 DOWNTO 1),
cc=>castx0217(42 DOWNTO 1),
ccsat=>castx0217(43),cczip=>castx0217(44));
cmp217: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1a(32 DOWNTO 1),
cc=>castx0218(42 DOWNTO 1),
ccsat=>castx0218(43),cczip=>castx0218(44));
cmp218: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1b(32 DOWNTO 1),
cc=>castx0219(42 DOWNTO 1),
ccsat=>castx0219(43),cczip=>castx0219(44));
cmp219: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1c(32 DOWNTO 1),
cc=>castx0220(42 DOWNTO 1),
ccsat=>castx0220(43),cczip=>castx0220(44));
cmp220: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1d(32 DOWNTO 1),
cc=>castx0221(42 DOWNTO 1),
ccsat=>castx0221(43),cczip=>castx0221(44));
cmp221: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1e(32 DOWNTO 1),
cc=>castx0222(42 DOWNTO 1),
ccsat=>castx0222(43),cczip=>castx0222(44));
cmp222: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc1f(32 DOWNTO 1),
cc=>castx0223(42 DOWNTO 1),
ccsat=>castx0223(43),cczip=>castx0223(44));
cmp223: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc20(32 DOWNTO 1),
cc=>castx0224(42 DOWNTO 1),
ccsat=>castx0224(43),cczip=>castx0224(44));
cmp224: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc21(32 DOWNTO 1),
cc=>castx0225(42 DOWNTO 1),
ccsat=>castx0225(43),cczip=>castx0225(44));
cmp225: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc22(32 DOWNTO 1),
cc=>castx0226(42 DOWNTO 1),
ccsat=>castx0226(43),cczip=>castx0226(44));
cmp226: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc23(32 DOWNTO 1),
cc=>castx0227(42 DOWNTO 1),
ccsat=>castx0227(43),cczip=>castx0227(44));
cmp227: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc24(32 DOWNTO 1),
cc=>castx0228(42 DOWNTO 1),
ccsat=>castx0228(43),cczip=>castx0228(44));
cmp228: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc25(32 DOWNTO 1),
cc=>castx0229(42 DOWNTO 1),
ccsat=>castx0229(43),cczip=>castx0229(44));
cmp229: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc26(32 DOWNTO 1),
cc=>castx0230(42 DOWNTO 1),
ccsat=>castx0230(43),cczip=>castx0230(44));
cmp230: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc27(32 DOWNTO 1),
cc=>castx0231(42 DOWNTO 1),
ccsat=>castx0231(43),cczip=>castx0231(44));
cmp231: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc28(32 DOWNTO 1),
cc=>castx0232(42 DOWNTO 1),
ccsat=>castx0232(43),cczip=>castx0232(44));
cmp232: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc29(32 DOWNTO 1),
cc=>castx0233(42 DOWNTO 1),
ccsat=>castx0233(43),cczip=>castx0233(44));
cmp233: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2a(32 DOWNTO 1),
cc=>castx0234(42 DOWNTO 1),
ccsat=>castx0234(43),cczip=>castx0234(44));
cmp234: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2b(32 DOWNTO 1),
cc=>castx0235(42 DOWNTO 1),
ccsat=>castx0235(43),cczip=>castx0235(44));
cmp235: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2c(32 DOWNTO 1),
cc=>castx0236(42 DOWNTO 1),
ccsat=>castx0236(43),cczip=>castx0236(44));
cmp236: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2d(32 DOWNTO 1),
cc=>castx0237(42 DOWNTO 1),
ccsat=>castx0237(43),cczip=>castx0237(44));
cmp237: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2e(32 DOWNTO 1),
cc=>castx0238(42 DOWNTO 1),
ccsat=>castx0238(43),cczip=>castx0238(44));
cmp238: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc2f(32 DOWNTO 1),
cc=>castx0239(42 DOWNTO 1),
ccsat=>castx0239(43),cczip=>castx0239(44));
cmp239: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc30(32 DOWNTO 1),
cc=>castx0240(42 DOWNTO 1),
ccsat=>castx0240(43),cczip=>castx0240(44));
cmp240: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc31(32 DOWNTO 1),
cc=>castx0241(42 DOWNTO 1),
ccsat=>castx0241(43),cczip=>castx0241(44));
cmp241: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc32(32 DOWNTO 1),
cc=>castx0242(42 DOWNTO 1),
ccsat=>castx0242(43),cczip=>castx0242(44));
cmp242: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc33(32 DOWNTO 1),
cc=>castx0243(42 DOWNTO 1),
ccsat=>castx0243(43),cczip=>castx0243(44));
cmp243: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc34(32 DOWNTO 1),
cc=>castx0244(42 DOWNTO 1),
ccsat=>castx0244(43),cczip=>castx0244(44));
cmp244: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc35(32 DOWNTO 1),
cc=>castx0245(42 DOWNTO 1),
ccsat=>castx0245(43),cczip=>castx0245(44));
cmp245: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc36(32 DOWNTO 1),
cc=>castx0246(42 DOWNTO 1),
ccsat=>castx0246(43),cczip=>castx0246(44));
cmp246: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc37(32 DOWNTO 1),
cc=>castx0247(42 DOWNTO 1),
ccsat=>castx0247(43),cczip=>castx0247(44));
cmp247: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc38(32 DOWNTO 1),
cc=>castx0248(42 DOWNTO 1),
ccsat=>castx0248(43),cczip=>castx0248(44));
cmp248: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc39(32 DOWNTO 1),
cc=>castx0249(42 DOWNTO 1),
ccsat=>castx0249(43),cczip=>castx0249(44));
cmp249: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3a(32 DOWNTO 1),
cc=>castx0250(42 DOWNTO 1),
ccsat=>castx0250(43),cczip=>castx0250(44));
cmp250: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3b(32 DOWNTO 1),
cc=>castx0251(42 DOWNTO 1),
ccsat=>castx0251(43),cczip=>castx0251(44));
cmp251: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3c(32 DOWNTO 1),
cc=>castx0252(42 DOWNTO 1),
ccsat=>castx0252(43),cczip=>castx0252(44));
cmp252: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3d(32 DOWNTO 1),
cc=>castx0253(42 DOWNTO 1),
ccsat=>castx0253(43),cczip=>castx0253(44));
cmp253: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3e(32 DOWNTO 1),
cc=>castx0254(42 DOWNTO 1),
ccsat=>castx0254(43),cczip=>castx0254(44));
cmp254: hcc_castftox
GENERIC MAP (target=>1,roundconvert=>0,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cc3f(32 DOWNTO 1),
cc=>castx0255(42 DOWNTO 1),
ccsat=>castx0255(43),cczip=>castx0255(44));
cmp255: hcc_castxtof
GENERIC MAP (mantissa=>32,normspeed=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>synth0127(42 DOWNTO 1),
aasat=>synth0127(43),aazip=>synth0127(44),
cc=>castx0256(32 DOWNTO 1));
cmp256: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp00(42 DOWNTO 1),
aasat=>dp00(43),aazip=>dp00(44),
cc=>synth0257(42 DOWNTO 1),
ccsat=>synth0257(43), cczip=>synth0257(44));
cmp257: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp01(42 DOWNTO 1),
aasat=>dp01(43),aazip=>dp01(44),
cc=>synth0258(42 DOWNTO 1),
ccsat=>synth0258(43), cczip=>synth0258(44));
cmp258: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp02(42 DOWNTO 1),
aasat=>dp02(43),aazip=>dp02(44),
cc=>synth0259(42 DOWNTO 1),
ccsat=>synth0259(43), cczip=>synth0259(44));
cmp259: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp03(42 DOWNTO 1),
aasat=>dp03(43),aazip=>dp03(44),
cc=>synth0260(42 DOWNTO 1),
ccsat=>synth0260(43), cczip=>synth0260(44));
cmp260: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp04(42 DOWNTO 1),
aasat=>dp04(43),aazip=>dp04(44),
cc=>synth0261(42 DOWNTO 1),
ccsat=>synth0261(43), cczip=>synth0261(44));
cmp261: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp05(42 DOWNTO 1),
aasat=>dp05(43),aazip=>dp05(44),
cc=>synth0262(42 DOWNTO 1),
ccsat=>synth0262(43), cczip=>synth0262(44));
cmp262: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp06(42 DOWNTO 1),
aasat=>dp06(43),aazip=>dp06(44),
cc=>synth0263(42 DOWNTO 1),
ccsat=>synth0263(43), cczip=>synth0263(44));
cmp263: hcc_normfp1x
GENERIC MAP (mantissa=>32,inputnormalize=>1,roundnormalize=>0,
normspeed=>2,target=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dp07(42 DOWNTO 1),
aasat=>dp07(43),aazip=>dp07(44),
cc=>synth0264(42 DOWNTO 1),
ccsat=>synth0264(43), cczip=>synth0264(44));
--*** OUTPUTS ***
result <= castx0256;
startout <= startff(46);
END GEN;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_rsft64x64.vhd
|
10
|
5109
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFT64X64.VHD ***
--*** ***
--*** Function: Combinatorial Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsft64x64;
ARCHITECTURE rtl of dp_rsft64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(116) AND shift(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(116) AND shift(6) AND NOT(shift(5))) OR
(levtwo(116) AND shift(6) AND shift(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(116) AND (shift(6) OR shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_explutneg.vhd
|
10
|
140760
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explutneg IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_explutneg;
ARCHITECTURE rtl OF dp_explutneg IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(1023,11);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(7910755,24);
manlo <= conv_std_logic_vector(103608120,28);
exponent <= conv_std_logic_vector(1021,11);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(1387178,24);
manlo <= conv_std_logic_vector(62882252,28);
exponent <= conv_std_logic_vector(1020,11);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(9952012,24);
manlo <= conv_std_logic_vector(214872239,28);
exponent <= conv_std_logic_vector(1018,11);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(2889051,24);
manlo <= conv_std_logic_vector(136396020,28);
exponent <= conv_std_logic_vector(1017,11);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(12162046,24);
manlo <= conv_std_logic_vector(873334,28);
exponent <= conv_std_logic_vector(1015,11);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(4515103,24);
manlo <= conv_std_logic_vector(18076886,28);
exponent <= conv_std_logic_vector(1014,11);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(14554809,24);
manlo <= conv_std_logic_vector(203729295,28);
exponent <= conv_std_logic_vector(1012,11);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(6275600,24);
manlo <= conv_std_logic_vector(68167597,28);
exponent <= conv_std_logic_vector(1011,11);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(184098,24);
manlo <= conv_std_logic_vector(86398042,28);
exponent <= conv_std_logic_vector(1010,11);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(8181659,24);
manlo <= conv_std_logic_vector(90471578,28);
exponent <= conv_std_logic_vector(1008,11);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(1586498,24);
manlo <= conv_std_logic_vector(59729764,28);
exponent <= conv_std_logic_vector(1007,11);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(10245315,24);
manlo <= conv_std_logic_vector(188988555,28);
exponent <= conv_std_logic_vector(1005,11);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(3104851,24);
manlo <= conv_std_logic_vector(194518424,28);
exponent <= conv_std_logic_vector(1004,11);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(12479599,24);
manlo <= conv_std_logic_vector(229643794,28);
exponent <= conv_std_logic_vector(1002,11);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(4748746,24);
manlo <= conv_std_logic_vector(36170808,28);
exponent <= conv_std_logic_vector(1001,11);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(14898619,24);
manlo <= conv_std_logic_vector(183403979,28);
exponent <= conv_std_logic_vector(999,11);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(6528561,24);
manlo <= conv_std_logic_vector(123365533,28);
exponent <= conv_std_logic_vector(998,11);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(370216,24);
manlo <= conv_std_logic_vector(208248737,28);
exponent <= conv_std_logic_vector(997,11);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(8455535,24);
manlo <= conv_std_logic_vector(254564210,28);
exponent <= conv_std_logic_vector(995,11);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(1788005,24);
manlo <= conv_std_logic_vector(99840615,28);
exponent <= conv_std_logic_vector(994,11);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(10541837,24);
manlo <= conv_std_logic_vector(14529516,28);
exponent <= conv_std_logic_vector(992,11);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(3323019,24);
manlo <= conv_std_logic_vector(252804514,28);
exponent <= conv_std_logic_vector(991,11);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(12800638,24);
manlo <= conv_std_logic_vector(70515377,28);
exponent <= conv_std_logic_vector(989,11);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(4984952,24);
manlo <= conv_std_logic_vector(266936970,28);
exponent <= conv_std_logic_vector(988,11);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(15246202,24);
manlo <= conv_std_logic_vector(73384750,28);
exponent <= conv_std_logic_vector(986,11);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(6784298,24);
manlo <= conv_std_logic_vector(117472834,28);
exponent <= conv_std_logic_vector(985,11);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(558377,24);
manlo <= conv_std_logic_vector(141983386,28);
exponent <= conv_std_logic_vector(984,11);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(8732417,24);
manlo <= conv_std_logic_vector(225268666,28);
exponent <= conv_std_logic_vector(982,11);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(1991723,24);
manlo <= conv_std_logic_vector(183207072,28);
exponent <= conv_std_logic_vector(981,11);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(10841612,24);
manlo <= conv_std_logic_vector(44859253,28);
exponent <= conv_std_logic_vector(979,11);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(3543582,24);
manlo <= conv_std_logic_vector(38615994,28);
exponent <= conv_std_logic_vector(978,11);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(13125199,24);
manlo <= conv_std_logic_vector(123823208,28);
exponent <= conv_std_logic_vector(976,11);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(5223751,24);
manlo <= conv_std_logic_vector(209149352,28);
exponent <= conv_std_logic_vector(975,11);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(15597598,24);
manlo <= conv_std_logic_vector(248916640,28);
exponent <= conv_std_logic_vector(973,11);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(7042841,24);
manlo <= conv_std_logic_vector(173666528,28);
exponent <= conv_std_logic_vector(972,11);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(748602,24);
manlo <= conv_std_logic_vector(266199140,28);
exponent <= conv_std_logic_vector(971,11);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(9012337,24);
manlo <= conv_std_logic_vector(264921173,28);
exponent <= conv_std_logic_vector(969,11);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(2197677,24);
manlo <= conv_std_logic_vector(112079619,28);
exponent <= conv_std_logic_vector(968,11);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(11144676,24);
manlo <= conv_std_logic_vector(200497976,28);
exponent <= conv_std_logic_vector(966,11);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(3766564,24);
manlo <= conv_std_logic_vector(161159716,28);
exponent <= conv_std_logic_vector(965,11);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(13453322,24);
manlo <= conv_std_logic_vector(28788768,28);
exponent <= conv_std_logic_vector(963,11);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(5465170,24);
manlo <= conv_std_logic_vector(249755484,28);
exponent <= conv_std_logic_vector(962,11);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(15952851,24);
manlo <= conv_std_logic_vector(133443390,28);
exponent <= conv_std_logic_vector(960,11);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(7304221,24);
manlo <= conv_std_logic_vector(236407020,28);
exponent <= conv_std_logic_vector(959,11);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(940915,24);
manlo <= conv_std_logic_vector(220198205,28);
exponent <= conv_std_logic_vector(958,11);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(9295329,24);
manlo <= conv_std_logic_vector(196124030,28);
exponent <= conv_std_logic_vector(956,11);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(2405891,24);
manlo <= conv_std_logic_vector(28613594,28);
exponent <= conv_std_logic_vector(955,11);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(11451066,24);
manlo <= conv_std_logic_vector(238698933,28);
exponent <= conv_std_logic_vector(953,11);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(3991993,24);
manlo <= conv_std_logic_vector(233279365,28);
exponent <= conv_std_logic_vector(952,11);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(13785045,24);
manlo <= conv_std_logic_vector(75368511,28);
exponent <= conv_std_logic_vector(950,11);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(5709239,24);
manlo <= conv_std_logic_vector(54173026,28);
exponent <= conv_std_logic_vector(949,11);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(16312002,24);
manlo <= conv_std_logic_vector(78993710,28);
exponent <= conv_std_logic_vector(947,11);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(7568470,24);
manlo <= conv_std_logic_vector(72422582,28);
exponent <= conv_std_logic_vector(946,11);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(1135338,24);
manlo <= conv_std_logic_vector(246889480,28);
exponent <= conv_std_logic_vector(945,11);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(9581426,24);
manlo <= conv_std_logic_vector(208117876,28);
exponent <= conv_std_logic_vector(943,11);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(2616389,24);
manlo <= conv_std_logic_vector(147217980,28);
exponent <= conv_std_logic_vector(942,11);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(11760819,24);
manlo <= conv_std_logic_vector(23037889,28);
exponent <= conv_std_logic_vector(940,11);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(4219896,24);
manlo <= conv_std_logic_vector(214481816,28);
exponent <= conv_std_logic_vector(939,11);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(14120408,24);
manlo <= conv_std_logic_vector(131761485,28);
exponent <= conv_std_logic_vector(937,11);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(5955985,24);
manlo <= conv_std_logic_vector(177821786,28);
exponent <= conv_std_logic_vector(936,11);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(16675094,24);
manlo <= conv_std_logic_vector(25356748,28);
exponent <= conv_std_logic_vector(934,11);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(7835618,24);
manlo <= conv_std_logic_vector(77011020,28);
exponent <= conv_std_logic_vector(933,11);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1331895,24);
manlo <= conv_std_logic_vector(119779026,28);
exponent <= conv_std_logic_vector(932,11);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(9870663,24);
manlo <= conv_std_logic_vector(52552908,28);
exponent <= conv_std_logic_vector(930,11);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(2829197,24);
manlo <= conv_std_logic_vector(218477336,28);
exponent <= conv_std_logic_vector(929,11);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(12073970,24);
manlo <= conv_std_logic_vector(61450731,28);
exponent <= conv_std_logic_vector(927,11);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(4450300,24);
manlo <= conv_std_logic_vector(143360086,28);
exponent <= conv_std_logic_vector(926,11);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(14459451,24);
manlo <= conv_std_logic_vector(182543396,28);
exponent <= conv_std_logic_vector(924,11);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(6205439,24);
manlo <= conv_std_logic_vector(188004913,28);
exponent <= conv_std_logic_vector(923,11);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(132477,24);
manlo <= conv_std_logic_vector(19160299,28);
exponent <= conv_std_logic_vector(922,11);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(8105697,24);
manlo <= conv_std_logic_vector(201304075,28);
exponent <= conv_std_logic_vector(920,11);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1530608,24);
manlo <= conv_std_logic_vector(217452229,28);
exponent <= conv_std_logic_vector(919,11);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(10163073,24);
manlo <= conv_std_logic_vector(118320126,28);
exponent <= conv_std_logic_vector(917,11);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(3044341,24);
manlo <= conv_std_logic_vector(66824260,28);
exponent <= conv_std_logic_vector(916,11);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(12390557,24);
manlo <= conv_std_logic_vector(165235674,28);
exponent <= conv_std_logic_vector(914,11);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(4683232,24);
manlo <= conv_std_logic_vector(138461149,28);
exponent <= conv_std_logic_vector(913,11);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(14802215,24);
manlo <= conv_std_logic_vector(61508170,28);
exponent <= conv_std_logic_vector(911,11);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(6457631,24);
manlo <= conv_std_logic_vector(7025744,28);
exponent <= conv_std_logic_vector(910,11);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(318029,24);
manlo <= conv_std_logic_vector(21309721,28);
exponent <= conv_std_logic_vector(909,11);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(8378740,24);
manlo <= conv_std_logic_vector(221720132,28);
exponent <= conv_std_logic_vector(907,11);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1731502,24);
manlo <= conv_std_logic_vector(182144977,28);
exponent <= conv_std_logic_vector(906,11);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(10458692,24);
manlo <= conv_std_logic_vector(90475423,28);
exponent <= conv_std_logic_vector(904,11);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(3261845,24);
manlo <= conv_std_logic_vector(128220642,28);
exponent <= conv_std_logic_vector(903,11);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(12710618,24);
manlo <= conv_std_logic_vector(255552070,28);
exponent <= conv_std_logic_vector(901,11);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(4918720,24);
manlo <= conv_std_logic_vector(130727832,28);
exponent <= conv_std_logic_vector(900,11);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(15148739,24);
manlo <= conv_std_logic_vector(258265342,28);
exponent <= conv_std_logic_vector(898,11);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(6712589,24);
manlo <= conv_std_logic_vector(181573149,28);
exponent <= conv_std_logic_vector(897,11);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(505617,24);
manlo <= conv_std_logic_vector(45883390,28);
exponent <= conv_std_logic_vector(896,11);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(8654780,24);
manlo <= conv_std_logic_vector(9428106,28);
exponent <= conv_std_logic_vector(894,11);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1934600,24);
manlo <= conv_std_logic_vector(262677610,28);
exponent <= conv_std_logic_vector(893,11);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(10757555,24);
manlo <= conv_std_logic_vector(25094861,28);
exponent <= conv_std_logic_vector(891,11);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(3481736,24);
manlo <= conv_std_logic_vector(108799619,28);
exponent <= conv_std_logic_vector(890,11);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(13034192,24);
manlo <= conv_std_logic_vector(96190464,28);
exponent <= conv_std_logic_vector(888,11);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(5156792,24);
manlo <= conv_std_logic_vector(132821234,28);
exponent <= conv_std_logic_vector(887,11);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(15499067,24);
manlo <= conv_std_logic_vector(40497064,28);
exponent <= conv_std_logic_vector(885,11);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(6970346,24);
manlo <= conv_std_logic_vector(4633646,28);
exponent <= conv_std_logic_vector(884,11);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(695263,24);
manlo <= conv_std_logic_vector(184734272,28);
exponent <= conv_std_logic_vector(883,11);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(8933848,24);
manlo <= conv_std_logic_vector(68258056,28);
exponent <= conv_std_logic_vector(881,11);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(2139927,24);
manlo <= conv_std_logic_vector(241478077,28);
exponent <= conv_std_logic_vector(880,11);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(11059697,24);
manlo <= conv_std_logic_vector(81964893,28);
exponent <= conv_std_logic_vector(878,11);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(3704040,24);
manlo <= conv_std_logic_vector(59435624,28);
exponent <= conv_std_logic_vector(877,11);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(13361316,24);
manlo <= conv_std_logic_vector(100097713,28);
exponent <= conv_std_logic_vector(875,11);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(5397476,24);
manlo <= conv_std_logic_vector(240017437,28);
exponent <= conv_std_logic_vector(874,11);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(15853238,24);
manlo <= conv_std_logic_vector(139632179,28);
exponent <= conv_std_logic_vector(872,11);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(7230930,24);
manlo <= conv_std_logic_vector(200816807,28);
exponent <= conv_std_logic_vector(871,11);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(886991,24);
manlo <= conv_std_logic_vector(58654941,28);
exponent <= conv_std_logic_vector(870,11);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(9215978,24);
manlo <= conv_std_logic_vector(193575030,28);
exponent <= conv_std_logic_vector(868,11);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(2347507,24);
manlo <= conv_std_logic_vector(240661664,28);
exponent <= conv_std_logic_vector(867,11);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(11365154,24);
manlo <= conv_std_logic_vector(257284930,28);
exponent <= conv_std_logic_vector(865,11);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(3928783,24);
manlo <= conv_std_logic_vector(108146246,28);
exponent <= conv_std_logic_vector(864,11);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(13692029,24);
manlo <= conv_std_logic_vector(256867284,28);
exponent <= conv_std_logic_vector(862,11);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(5640802,24);
manlo <= conv_std_logic_vector(94243132,28);
exponent <= conv_std_logic_vector(861,11);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(16211296,24);
manlo <= conv_std_logic_vector(67825654,28);
exponent <= conv_std_logic_vector(859,11);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(7494374,24);
manlo <= conv_std_logic_vector(242982196,28);
exponent <= conv_std_logic_vector(858,11);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1080822,24);
manlo <= conv_std_logic_vector(160277009,28);
exponent <= conv_std_logic_vector(857,11);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(9501205,24);
manlo <= conv_std_logic_vector(10212621,28);
exponent <= conv_std_logic_vector(855,11);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2557365,24);
manlo <= conv_std_logic_vector(185941944,28);
exponent <= conv_std_logic_vector(854,11);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(11673964,24);
manlo <= conv_std_logic_vector(116382402,28);
exponent <= conv_std_logic_vector(852,11);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(4155992,24);
manlo <= conv_std_logic_vector(192503267,28);
exponent <= conv_std_logic_vector(851,11);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(14026372,24);
manlo <= conv_std_logic_vector(133984890,28);
exponent <= conv_std_logic_vector(849,11);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(5886797,24);
manlo <= conv_std_logic_vector(227169396,28);
exponent <= conv_std_logic_vector(848,11);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(16573282,24);
manlo <= conv_std_logic_vector(266790864,28);
exponent <= conv_std_logic_vector(846,11);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(7760709,24);
manlo <= conv_std_logic_vector(232279832,28);
exponent <= conv_std_logic_vector(845,11);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1276780,24);
manlo <= conv_std_logic_vector(244188460,28);
exponent <= conv_std_logic_vector(844,11);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(9789561,24);
manlo <= conv_std_logic_vector(47289108,28);
exponent <= conv_std_logic_vector(842,11);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2769526,24);
manlo <= conv_std_logic_vector(75856665,28);
exponent <= conv_std_logic_vector(841,11);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(11986162,24);
manlo <= conv_std_logic_vector(137053172,28);
exponent <= conv_std_logic_vector(839,11);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(4385695,24);
manlo <= conv_std_logic_vector(60488459,28);
exponent <= conv_std_logic_vector(838,11);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(14364383,24);
manlo <= conv_std_logic_vector(220265084,28);
exponent <= conv_std_logic_vector(836,11);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(6135492,24);
manlo <= conv_std_logic_vector(182090040,28);
exponent <= conv_std_logic_vector(835,11);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(81012,24);
manlo <= conv_std_logic_vector(249275143,28);
exponent <= conv_std_logic_vector(834,11);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(8029967,24);
manlo <= conv_std_logic_vector(93846972,28);
exponent <= conv_std_logic_vector(832,11);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(1474889,24);
manlo <= conv_std_logic_vector(132978099,28);
exponent <= conv_std_logic_vector(831,11);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(10081081,24);
manlo <= conv_std_logic_vector(128680817,28);
exponent <= conv_std_logic_vector(829,11);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2984014,24);
manlo <= conv_std_logic_vector(251002315,28);
exponent <= conv_std_logic_vector(828,11);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(12301786,24);
manlo <= conv_std_logic_vector(100124707,28);
exponent <= conv_std_logic_vector(826,11);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(4617918,24);
manlo <= conv_std_logic_vector(76665129,28);
exponent <= conv_std_logic_vector(825,11);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(14706104,24);
manlo <= conv_std_logic_vector(48076192,28);
exponent <= conv_std_logic_vector(823,11);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(6386916,24);
manlo <= conv_std_logic_vector(125471070,28);
exponent <= conv_std_logic_vector(822,11);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(266000,24);
manlo <= conv_std_logic_vector(57624675,28);
exponent <= conv_std_logic_vector(821,11);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(8302179,24);
manlo <= conv_std_logic_vector(114693198,28);
exponent <= conv_std_logic_vector(819,11);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(1675171,24);
manlo <= conv_std_logic_vector(254852645,28);
exponent <= conv_std_logic_vector(818,11);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(10375800,24);
manlo <= conv_std_logic_vector(179426511,28);
exponent <= conv_std_logic_vector(816,11);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(3200857,24);
manlo <= conv_std_logic_vector(52664716,28);
exponent <= conv_std_logic_vector(815,11);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(12620873,24);
manlo <= conv_std_logic_vector(164386702,28);
exponent <= conv_std_logic_vector(813,11);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(4852689,24);
manlo <= conv_std_logic_vector(149310968,28);
exponent <= conv_std_logic_vector(812,11);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(15051574,24);
manlo <= conv_std_logic_vector(73675604,28);
exponent <= conv_std_logic_vector(810,11);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(6641099,24);
manlo <= conv_std_logic_vector(42591307,28);
exponent <= conv_std_logic_vector(809,11);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(453017,24);
manlo <= conv_std_logic_vector(104016801,28);
exponent <= conv_std_logic_vector(808,11);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(8577378,24);
manlo <= conv_std_logic_vector(139419332,28);
exponent <= conv_std_logic_vector(806,11);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(1877652,24);
manlo <= conv_std_logic_vector(33778363,28);
exponent <= conv_std_logic_vector(805,11);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(10673753,24);
manlo <= conv_std_logic_vector(226837452,28);
exponent <= conv_std_logic_vector(803,11);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(3420078,24);
manlo <= conv_std_logic_vector(239554874,28);
exponent <= conv_std_logic_vector(802,11);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(12943462,24);
manlo <= conv_std_logic_vector(62486566,28);
exponent <= conv_std_logic_vector(800,11);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(5090036,24);
manlo <= conv_std_logic_vector(268173235,28);
exponent <= conv_std_logic_vector(799,11);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(15400835,24);
manlo <= conv_std_logic_vector(67898261,28);
exponent <= conv_std_logic_vector(797,11);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(6898071,24);
manlo <= conv_std_logic_vector(6935226,28);
exponent <= conv_std_logic_vector(796,11);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(642086,24);
manlo <= conv_std_logic_vector(193616024,28);
exponent <= conv_std_logic_vector(795,11);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(8855597,24);
manlo <= conv_std_logic_vector(108124901,28);
exponent <= conv_std_logic_vector(793,11);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2082354,24);
manlo <= conv_std_logic_vector(37727361,28);
exponent <= conv_std_logic_vector(792,11);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(10974976,24);
manlo <= conv_std_logic_vector(133184200,28);
exponent <= conv_std_logic_vector(790,11);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(3641706,24);
manlo <= conv_std_logic_vector(35844662,28);
exponent <= conv_std_logic_vector(789,11);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(13269590,24);
manlo <= conv_std_logic_vector(175886280,28);
exponent <= conv_std_logic_vector(787,11);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(5329988,24);
manlo <= conv_std_logic_vector(236927280,28);
exponent <= conv_std_logic_vector(786,11);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(15753928,24);
manlo <= conv_std_logic_vector(191213976,28);
exponent <= conv_std_logic_vector(784,11);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(7157862,24);
manlo <= conv_std_logic_vector(181160855,28);
exponent <= conv_std_logic_vector(783,11);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(833230,24);
manlo <= conv_std_logic_vector(197197075,28);
exponent <= conv_std_logic_vector(782,11);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(9136869,24);
manlo <= conv_std_logic_vector(57456047,28);
exponent <= conv_std_logic_vector(780,11);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2289302,24);
manlo <= conv_std_logic_vector(100400411,28);
exponent <= conv_std_logic_vector(779,11);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(11279504,24);
manlo <= conv_std_logic_vector(133702078,28);
exponent <= conv_std_logic_vector(777,11);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3865765,24);
manlo <= conv_std_logic_vector(84791606,28);
exponent <= conv_std_logic_vector(776,11);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(13599297,24);
manlo <= conv_std_logic_vector(193913492,28);
exponent <= conv_std_logic_vector(774,11);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(5572573,24);
manlo <= conv_std_logic_vector(210951234,28);
exponent <= conv_std_logic_vector(773,11);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(16110896,24);
manlo <= conv_std_logic_vector(189751005,28);
exponent <= conv_std_logic_vector(771,11);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(7420505,24);
manlo <= conv_std_logic_vector(12771910,28);
exponent <= conv_std_logic_vector(770,11);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(1026472,24);
manlo <= conv_std_logic_vector(51864863,28);
exponent <= conv_std_logic_vector(769,11);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(9421227,24);
manlo <= conv_std_logic_vector(121664951,28);
exponent <= conv_std_logic_vector(767,11);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2498521,24);
manlo <= conv_std_logic_vector(127312793,28);
exponent <= conv_std_logic_vector(766,11);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(11587374,24);
manlo <= conv_std_logic_vector(32431827,28);
exponent <= conv_std_logic_vector(764,11);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(4092283,24);
manlo <= conv_std_logic_vector(33663701,28);
exponent <= conv_std_logic_vector(763,11);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(13932622,24);
manlo <= conv_std_logic_vector(188745186,28);
exponent <= conv_std_logic_vector(761,11);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(5817820,24);
manlo <= conv_std_logic_vector(161368804,28);
exponent <= conv_std_logic_vector(760,11);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(16471781,24);
manlo <= conv_std_logic_vector(201946939,28);
exponent <= conv_std_logic_vector(758,11);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(7686029,24);
manlo <= conv_std_logic_vector(114155240,28);
exponent <= conv_std_logic_vector(757,11);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(1221834,24);
manlo <= conv_std_logic_vector(30217784,28);
exponent <= conv_std_logic_vector(756,11);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(9708705,24);
manlo <= conv_std_logic_vector(265245416,28);
exponent <= conv_std_logic_vector(754,11);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2710036,24);
manlo <= conv_std_logic_vector(96582323,28);
exponent <= conv_std_logic_vector(753,11);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(11898622,24);
manlo <= conv_std_logic_vector(8685564,28);
exponent <= conv_std_logic_vector(751,11);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(4321286,24);
manlo <= conv_std_logic_vector(145205332,28);
exponent <= conv_std_logic_vector(750,11);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(14269605,24);
manlo <= conv_std_logic_vector(79792252,28);
exponent <= conv_std_logic_vector(748,11);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(6065758,24);
manlo <= conv_std_logic_vector(144408455,28);
exponent <= conv_std_logic_vector(747,11);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(29705,24);
manlo <= conv_std_logic_vector(111518540,28);
exponent <= conv_std_logic_vector(746,11);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(7954467,24);
manlo <= conv_std_logic_vector(116097284,28);
exponent <= conv_std_logic_vector(744,11);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(1419339,24);
manlo <= conv_std_logic_vector(204212637,28);
exponent <= conv_std_logic_vector(743,11);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(9999339,24);
manlo <= conv_std_logic_vector(15580207,28);
exponent <= conv_std_logic_vector(741,11);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(2923872,24);
manlo <= conv_std_logic_vector(59726033,28);
exponent <= conv_std_logic_vector(740,11);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(12213285,24);
manlo <= conv_std_logic_vector(81348195,28);
exponent <= conv_std_logic_vector(738,11);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(4552802,24);
manlo <= conv_std_logic_vector(224758002,28);
exponent <= conv_std_logic_vector(737,11);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(14610285,24);
manlo <= conv_std_logic_vector(171839647,28);
exponent <= conv_std_logic_vector(735,11);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(6316417,24);
manlo <= conv_std_logic_vector(33901818,28);
exponent <= conv_std_logic_vector(734,11);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(214129,24);
manlo <= conv_std_logic_vector(187432044,28);
exponent <= conv_std_logic_vector(733,11);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(8225851,24);
manlo <= conv_std_logic_vector(10972428,28);
exponent <= conv_std_logic_vector(731,11);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(1619012,24);
manlo <= conv_std_logic_vector(177473085,28);
exponent <= conv_std_logic_vector(730,11);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(10293161,24);
manlo <= conv_std_logic_vector(74648462,28);
exponent <= conv_std_logic_vector(728,11);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3140054,24);
manlo <= conv_std_logic_vector(142465582,28);
exponent <= conv_std_logic_vector(727,11);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(12531401,24);
manlo <= conv_std_logic_vector(110062606,28);
exponent <= conv_std_logic_vector(725,11);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(4786859,24);
manlo <= conv_std_logic_vector(158003247,28);
exponent <= conv_std_logic_vector(724,11);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(14954704,24);
manlo <= conv_std_logic_vector(82587752,28);
exponent <= conv_std_logic_vector(722,11);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(6569826,24);
manlo <= conv_std_logic_vector(59098716,28);
exponent <= conv_std_logic_vector(721,11);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(400577,24);
manlo <= conv_std_logic_vector(185198176,28);
exponent <= conv_std_logic_vector(720,11);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(8500212,24);
manlo <= conv_std_logic_vector(153765179,28);
exponent <= conv_std_logic_vector(718,11);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(1820876,24);
manlo <= conv_std_logic_vector(159783545,28);
exponent <= conv_std_logic_vector(717,11);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(10590207,24);
manlo <= conv_std_logic_vector(172648734,28);
exponent <= conv_std_logic_vector(715,11);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3358609,24);
manlo <= conv_std_logic_vector(8670608,28);
exponent <= conv_std_logic_vector(714,11);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(12853008,24);
manlo <= conv_std_logic_vector(64863304,28);
exponent <= conv_std_logic_vector(712,11);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(5023484,24);
manlo <= conv_std_logic_vector(180279682,28);
exponent <= conv_std_logic_vector(711,11);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(15302902,24);
manlo <= conv_std_logic_vector(86126918,28);
exponent <= conv_std_logic_vector(709,11);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(6826016,24);
manlo <= conv_std_logic_vector(315265,28);
exponent <= conv_std_logic_vector(708,11);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(589071,24);
manlo <= conv_std_logic_vector(160219440,28);
exponent <= conv_std_logic_vector(707,11);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(8777584,24);
manlo <= conv_std_logic_vector(189361726,28);
exponent <= conv_std_logic_vector(705,11);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(2024955,24);
manlo <= conv_std_logic_vector(162543151,28);
exponent <= conv_std_logic_vector(704,11);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(10890513,24);
manlo <= conv_std_logic_vector(142859647,28);
exponent <= conv_std_logic_vector(702,11);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3579561,24);
manlo <= conv_std_logic_vector(203359193,28);
exponent <= conv_std_logic_vector(701,11);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(13178144,24);
manlo <= conv_std_logic_vector(27387766,28);
exponent <= conv_std_logic_vector(699,11);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(5262706,24);
manlo <= conv_std_logic_vector(72167880,28);
exponent <= conv_std_logic_vector(698,11);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(15654921,24);
manlo <= conv_std_logic_vector(40507130,28);
exponent <= conv_std_logic_vector(696,11);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(7085016,24);
manlo <= conv_std_logic_vector(263640644,28);
exponent <= conv_std_logic_vector(695,11);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(779633,24);
manlo <= conv_std_logic_vector(233308885,28);
exponent <= conv_std_logic_vector(694,11);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(9058000,24);
manlo <= conv_std_logic_vector(127336500,28);
exponent <= conv_std_logic_vector(692,11);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(2231273,24);
manlo <= conv_std_logic_vector(267969878,28);
exponent <= conv_std_logic_vector(691,11);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(11194114,24);
manlo <= conv_std_logic_vector(191206462,28);
exponent <= conv_std_logic_vector(689,11);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3802939,24);
manlo <= conv_std_logic_vector(6046440,28);
exponent <= conv_std_logic_vector(688,11);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(13506847,24);
manlo <= conv_std_logic_vector(192101060,28);
exponent <= conv_std_logic_vector(686,11);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(5504552,24);
manlo <= conv_std_logic_vector(234133234,28);
exponent <= conv_std_logic_vector(685,11);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(16010802,24);
manlo <= conv_std_logic_vector(194370273,28);
exponent <= conv_std_logic_vector(683,11);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(7346860,24);
manlo <= conv_std_logic_vector(2864438,28);
exponent <= conv_std_logic_vector(682,11);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(972287,24);
manlo <= conv_std_logic_vector(54536955,28);
exponent <= conv_std_logic_vector(681,11);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(9341493,24);
manlo <= conv_std_logic_vector(74572905,28);
exponent <= conv_std_logic_vector(679,11);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(2439856,24);
manlo <= conv_std_logic_vector(93006730,28);
exponent <= conv_std_logic_vector(678,11);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(11501047,24);
manlo <= conv_std_logic_vector(92098230,28);
exponent <= conv_std_logic_vector(676,11);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4028767,24);
manlo <= conv_std_logic_vector(115940390,28);
exponent <= conv_std_logic_vector(675,11);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(13839158,24);
manlo <= conv_std_logic_vector(62227559,28);
exponent <= conv_std_logic_vector(673,11);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(5749053,24);
manlo <= conv_std_logic_vector(76824142,28);
exponent <= conv_std_logic_vector(672,11);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(16370589,24);
manlo <= conv_std_logic_vector(114548734,28);
exponent <= conv_std_logic_vector(670,11);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(7611576,24);
manlo <= conv_std_logic_vector(73252889,28);
exponent <= conv_std_logic_vector(669,11);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(1167054,24);
manlo <= conv_std_logic_vector(146134399,28);
exponent <= conv_std_logic_vector(668,11);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(9628096,24);
manlo <= conv_std_logic_vector(236331104,28);
exponent <= conv_std_logic_vector(666,11);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(2650727,24);
manlo <= conv_std_logic_vector(132284651,28);
exponent <= conv_std_logic_vector(665,11);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(11811347,24);
manlo <= conv_std_logic_vector(263325685,28);
exponent <= conv_std_logic_vector(663,11);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4257073,24);
manlo <= conv_std_logic_vector(236873507,28);
exponent <= conv_std_logic_vector(662,11);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(14175115,24);
manlo <= conv_std_logic_vector(61615323,28);
exponent <= conv_std_logic_vector(660,11);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(5996236,24);
manlo <= conv_std_logic_vector(169476567,28);
exponent <= conv_std_logic_vector(659,11);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(16734324,24);
manlo <= conv_std_logic_vector(29597837,28);
exponent <= conv_std_logic_vector(657,11);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(7879197,24);
manlo <= conv_std_logic_vector(79755942,28);
exponent <= conv_std_logic_vector(656,11);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(1363959,24);
manlo <= conv_std_logic_vector(24177677,28);
exponent <= conv_std_logic_vector(655,11);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(9917845,24);
manlo <= conv_std_logic_vector(112021148,28);
exponent <= conv_std_logic_vector(653,11);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(2863912,24);
manlo <= conv_std_logic_vector(148304045,28);
exponent <= conv_std_logic_vector(652,11);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(12125053,24);
manlo <= conv_std_logic_vector(156617262,28);
exponent <= conv_std_logic_vector(650,11);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4487885,24);
manlo <= conv_std_logic_vector(151904422,28);
exponent <= conv_std_logic_vector(649,11);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(14514758,24);
manlo <= conv_std_logic_vector(193824214,28);
exponent <= conv_std_logic_vector(647,11);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(6246132,24);
manlo <= conv_std_logic_vector(93361418,28);
exponent <= conv_std_logic_vector(646,11);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(162417,24);
manlo <= conv_std_logic_vector(12929741,28);
exponent <= conv_std_logic_vector(645,11);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(8149754,24);
manlo <= conv_std_logic_vector(257063442,28);
exponent <= conv_std_logic_vector(643,11);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(1563024,24);
manlo <= conv_std_logic_vector(78378796,28);
exponent <= conv_std_logic_vector(642,11);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(10210773,24);
manlo <= conv_std_logic_vector(106907060,28);
exponent <= conv_std_logic_vector(640,11);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(3079436,24);
manlo <= conv_std_logic_vector(245979562,28);
exponent <= conv_std_logic_vector(639,11);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(12442201,24);
manlo <= conv_std_logic_vector(137868870,28);
exponent <= conv_std_logic_vector(637,11);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4721229,24);
manlo <= conv_std_logic_vector(261058204,28);
exponent <= conv_std_logic_vector(636,11);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(14858129,24);
manlo <= conv_std_logic_vector(43405174,28);
exponent <= conv_std_logic_vector(634,11);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(6498770,24);
manlo <= conv_std_logic_vector(53338521,28);
exponent <= conv_std_logic_vector(633,11);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(348297,24);
manlo <= conv_std_logic_vector(158641329,28);
exponent <= conv_std_logic_vector(632,11);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(8423281,24);
manlo <= conv_std_logic_vector(128446906,28);
exponent <= conv_std_logic_vector(630,11);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(1764273,24);
manlo <= conv_std_logic_vector(230657816,28);
exponent <= conv_std_logic_vector(629,11);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(10506915,24);
manlo <= conv_std_logic_vector(191032874,28);
exponent <= conv_std_logic_vector(627,11);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(3297326,24);
manlo <= conv_std_logic_vector(68145509,28);
exponent <= conv_std_logic_vector(626,11);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(12762829,24);
manlo <= conv_std_logic_vector(146161159,28);
exponent <= conv_std_logic_vector(624,11);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4957134,24);
manlo <= conv_std_logic_vector(240027976,28);
exponent <= conv_std_logic_vector(623,11);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(15205267,24);
manlo <= conv_std_logic_vector(119370809,28);
exponent <= conv_std_logic_vector(621,11);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(6754180,24);
manlo <= conv_std_logic_vector(73501816,28);
exponent <= conv_std_logic_vector(620,11);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(536217,24);
manlo <= conv_std_logic_vector(220758658,28);
exponent <= conv_std_logic_vector(619,11);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(8699809,24);
manlo <= conv_std_logic_vector(117402516,28);
exponent <= conv_std_logic_vector(617,11);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(1967731,24);
manlo <= conv_std_logic_vector(204336317,28);
exponent <= conv_std_logic_vector(616,11);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(10806307,24);
manlo <= conv_std_logic_vector(168773516,28);
exponent <= conv_std_logic_vector(614,11);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(3517606,24);
manlo <= conv_std_logic_vector(138553816,28);
exponent <= conv_std_logic_vector(613,11);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(13086975,24);
manlo <= conv_std_logic_vector(231838082,28);
exponent <= conv_std_logic_vector(611,11);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5195628,24);
manlo <= conv_std_logic_vector(114805284,28);
exponent <= conv_std_logic_vector(610,11);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(15556214,24);
manlo <= conv_std_logic_vector(245890169,28);
exponent <= conv_std_logic_vector(608,11);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(7012392,24);
manlo <= conv_std_logic_vector(266576824,28);
exponent <= conv_std_logic_vector(607,11);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(726200,24);
manlo <= conv_std_logic_vector(33318175,28);
exponent <= conv_std_logic_vector(606,11);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(8979371,24);
manlo <= conv_std_logic_vector(206515377,28);
exponent <= conv_std_logic_vector(604,11);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(2173422,24);
manlo <= conv_std_logic_vector(61774637,28);
exponent <= conv_std_logic_vector(603,11);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(11108984,24);
manlo <= conv_std_logic_vector(216833386,28);
exponent <= conv_std_logic_vector(601,11);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(3740303,24);
manlo <= conv_std_logic_vector(252090990,28);
exponent <= conv_std_logic_vector(600,11);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(13414679,24);
manlo <= conv_std_logic_vector(20856890,28);
exponent <= conv_std_logic_vector(598,11);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5436738,24);
manlo <= conv_std_logic_vector(262578382,28);
exponent <= conv_std_logic_vector(597,11);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(15911013,24);
manlo <= conv_std_logic_vector(100481506,28);
exponent <= conv_std_logic_vector(595,11);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(7273439,24);
manlo <= conv_std_logic_vector(29586843,28);
exponent <= conv_std_logic_vector(594,11);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(918267,24);
manlo <= conv_std_logic_vector(33154287,28);
exponent <= conv_std_logic_vector(593,11);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(9262001,24);
manlo <= conv_std_logic_vector(206947959,28);
exponent <= conv_std_logic_vector(591,11);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(2381369,24);
manlo <= conv_std_logic_vector(205146615,28);
exponent <= conv_std_logic_vector(590,11);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(11414983,24);
manlo <= conv_std_logic_vector(80080029,28);
exponent <= conv_std_logic_vector(588,11);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(3965445,24);
manlo <= conv_std_logic_vector(12487826,28);
exponent <= conv_std_logic_vector(587,11);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(13745978,24);
manlo <= conv_std_logic_vector(58199715,28);
exponent <= conv_std_logic_vector(585,11);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5680495,24);
manlo <= conv_std_logic_vector(70463110,28);
exponent <= conv_std_logic_vector(584,11);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(16269705,24);
manlo <= conv_std_logic_vector(20654997,28);
exponent <= conv_std_logic_vector(582,11);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(7537349,24);
manlo <= conv_std_logic_vector(192319832,28);
exponent <= conv_std_logic_vector(581,11);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(1112441,24);
manlo <= conv_std_logic_vector(186880957,28);
exponent <= conv_std_logic_vector(580,11);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(9547733,24);
manlo <= conv_std_logic_vector(27940083,28);
exponent <= conv_std_logic_vector(578,11);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(2591599,24);
manlo <= conv_std_logic_vector(35045549,28);
exponent <= conv_std_logic_vector(577,11);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(11724339,24);
manlo <= conv_std_logic_vector(146438512,28);
exponent <= conv_std_logic_vector(575,11);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4193056,24);
manlo <= conv_std_logic_vector(175344679,28);
exponent <= conv_std_logic_vector(574,11);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(14080912,24);
manlo <= conv_std_logic_vector(198508677,28);
exponent <= conv_std_logic_vector(572,11);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5926926,24);
manlo <= conv_std_logic_vector(83904648,28);
exponent <= conv_std_logic_vector(571,11);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(16632332,24);
manlo <= conv_std_logic_vector(199957404,28);
exponent <= conv_std_logic_vector(569,11);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(7804156,24);
manlo <= conv_std_logic_vector(65532420,28);
exponent <= conv_std_logic_vector(568,11);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(1308746,24);
manlo <= conv_std_logic_vector(260058525,28);
exponent <= conv_std_logic_vector(567,11);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(9836599,24);
manlo <= conv_std_logic_vector(214756046,28);
exponent <= conv_std_logic_vector(565,11);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(2804135,24);
manlo <= conv_std_logic_vector(98759674,28);
exponent <= conv_std_logic_vector(564,11);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(12037090,24);
manlo <= conv_std_logic_vector(105879341,28);
exponent <= conv_std_logic_vector(562,11);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(4423165,24);
manlo <= conv_std_logic_vector(233069674,28);
exponent <= conv_std_logic_vector(561,11);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(14419522,24);
manlo <= conv_std_logic_vector(144218340,28);
exponent <= conv_std_logic_vector(559,11);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6176061,24);
manlo <= conv_std_logic_vector(128557517,28);
exponent <= conv_std_logic_vector(558,11);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(110861,24);
manlo <= conv_std_logic_vector(210451229,28);
exponent <= conv_std_logic_vector(557,11);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(8073890,24);
manlo <= conv_std_logic_vector(126309403,28);
exponent <= conv_std_logic_vector(555,11);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(1507206,24);
manlo <= conv_std_logic_vector(86368556,28);
exponent <= conv_std_logic_vector(554,11);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(10128636,24);
manlo <= conv_std_logic_vector(70724454,28);
exponent <= conv_std_logic_vector(552,11);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(3019003,24);
manlo <= conv_std_logic_vector(212024500,28);
exponent <= conv_std_logic_vector(551,11);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(12353273,24);
manlo <= conv_std_logic_vector(25338267,28);
exponent <= conv_std_logic_vector(549,11);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(4655800,24);
manlo <= conv_std_logic_vector(26358145,28);
exponent <= conv_std_logic_vector(548,11);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(14761847,24);
manlo <= conv_std_logic_vector(252137457,28);
exponent <= conv_std_logic_vector(546,11);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6427930,24);
manlo <= conv_std_logic_vector(116530320,28);
exponent <= conv_std_logic_vector(545,11);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(296176,24);
manlo <= conv_std_logic_vector(162393576,28);
exponent <= conv_std_logic_vector(544,11);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(8346584,24);
manlo <= conv_std_logic_vector(140031506,28);
exponent <= conv_std_logic_vector(542,11);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(1707843,24);
manlo <= conv_std_logic_vector(105232250,28);
exponent <= conv_std_logic_vector(541,11);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(10423877,24);
manlo <= conv_std_logic_vector(74257288,28);
exponent <= conv_std_logic_vector(539,11);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(3236229,24);
manlo <= conv_std_logic_vector(265138481,28);
exponent <= conv_std_logic_vector(538,11);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(12672925,24);
manlo <= conv_std_logic_vector(81471742,28);
exponent <= conv_std_logic_vector(536,11);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(4890987,24);
manlo <= conv_std_logic_vector(13504322,28);
exponent <= conv_std_logic_vector(535,11);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(15107929,24);
manlo <= conv_std_logic_vector(192561070,28);
exponent <= conv_std_logic_vector(533,11);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6682563,24);
manlo <= conv_std_logic_vector(47334412,28);
exponent <= conv_std_logic_vector(532,11);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(483524,24);
manlo <= conv_std_logic_vector(243414774,28);
exponent <= conv_std_logic_vector(531,11);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(8622270,24);
manlo <= conv_std_logic_vector(235144322,28);
exponent <= conv_std_logic_vector(529,11);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(1910682,24);
manlo <= conv_std_logic_vector(20388866,28);
exponent <= conv_std_logic_vector(528,11);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(10722358,24);
manlo <= conv_std_logic_vector(913747,28);
exponent <= conv_std_logic_vector(526,11);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(3455839,24);
manlo <= conv_std_logic_vector(223781205,28);
exponent <= conv_std_logic_vector(525,11);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(12996085,24);
manlo <= conv_std_logic_vector(24989984,28);
exponent <= conv_std_logic_vector(523,11);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5128754,24);
manlo <= conv_std_logic_vector(197545335,28);
exponent <= conv_std_logic_vector(522,11);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(15457809,24);
manlo <= conv_std_logic_vector(24315860,28);
exponent <= conv_std_logic_vector(520,11);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6939990,24);
manlo <= conv_std_logic_vector(8842978,28);
exponent <= conv_std_logic_vector(519,11);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(672929,24);
manlo <= conv_std_logic_vector(830489,28);
exponent <= conv_std_logic_vector(518,11);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(8900982,24);
manlo <= conv_std_logic_vector(98890321,28);
exponent <= conv_std_logic_vector(516,11);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(2115746,24);
manlo <= conv_std_logic_vector(142837003,28);
exponent <= conv_std_logic_vector(515,11);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(11024113,24);
manlo <= conv_std_logic_vector(266701758,28);
exponent <= conv_std_logic_vector(513,11);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(3677859,24);
manlo <= conv_std_logic_vector(129840563,28);
exponent <= conv_std_logic_vector(512,11);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(13322790,24);
manlo <= conv_std_logic_vector(255615990,28);
exponent <= conv_std_logic_vector(510,11);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5369131,24);
manlo <= conv_std_logic_vector(127156783,28);
exponent <= conv_std_logic_vector(509,11);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(15811527,24);
manlo <= conv_std_logic_vector(196077973,28);
exponent <= conv_std_logic_vector(507,11);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7200241,24);
manlo <= conv_std_logic_vector(178260644,28);
exponent <= conv_std_logic_vector(506,11);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(864411,24);
manlo <= conv_std_logic_vector(121424610,28);
exponent <= conv_std_logic_vector(505,11);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(9182752,24);
manlo <= conv_std_logic_vector(52100447,28);
exponent <= conv_std_logic_vector(503,11);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(2323061,24);
manlo <= conv_std_logic_vector(49429697,28);
exponent <= conv_std_logic_vector(502,11);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(11329181,24);
manlo <= conv_std_logic_vector(50166358,28);
exponent <= conv_std_logic_vector(500,11);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(3902315,24);
manlo <= conv_std_logic_vector(102248985,28);
exponent <= conv_std_logic_vector(499,11);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(13653081,24);
manlo <= conv_std_logic_vector(212703346,28);
exponent <= conv_std_logic_vector(497,11);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5612145,24);
manlo <= conv_std_logic_vector(239735388,28);
exponent <= conv_std_logic_vector(496,11);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(16169127,24);
manlo <= conv_std_logic_vector(205528034,28);
exponent <= conv_std_logic_vector(494,11);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7463349,24);
manlo <= conv_std_logic_vector(17797346,28);
exponent <= conv_std_logic_vector(493,11);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(1057995,24);
manlo <= conv_std_logic_vector(16251369,28);
exponent <= conv_std_logic_vector(492,11);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(9467613,24);
manlo <= conv_std_logic_vector(244949044,28);
exponent <= conv_std_logic_vector(490,11);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(2532650,24);
manlo <= conv_std_logic_vector(194268012,28);
exponent <= conv_std_logic_vector(489,11);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(11637595,24);
manlo <= conv_std_logic_vector(246328755,28);
exponent <= conv_std_logic_vector(487,11);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(4129234,24);
manlo <= conv_std_logic_vector(69393408,28);
exponent <= conv_std_logic_vector(486,11);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(13986996,24);
manlo <= conv_std_logic_vector(255528468,28);
exponent <= conv_std_logic_vector(484,11);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5857826,24);
manlo <= conv_std_logic_vector(251701587,28);
exponent <= conv_std_logic_vector(483,11);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(16530651,24);
manlo <= conv_std_logic_vector(211310789,28);
exponent <= conv_std_logic_vector(481,11);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7729343,24);
manlo <= conv_std_logic_vector(154707528,28);
exponent <= conv_std_logic_vector(480,11);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(1253702,24);
manlo <= conv_std_logic_vector(237283577,28);
exponent <= conv_std_logic_vector(479,11);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(9755601,24);
manlo <= conv_std_logic_vector(121155884,28);
exponent <= conv_std_logic_vector(477,11);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(2744540,24);
manlo <= conv_std_logic_vector(30442277,28);
exponent <= conv_std_logic_vector(476,11);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(11949394,24);
manlo <= conv_std_logic_vector(246622503,28);
exponent <= conv_std_logic_vector(474,11);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(4358643,24);
manlo <= conv_std_logic_vector(38405425,28);
exponent <= conv_std_logic_vector(473,11);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(14324576,24);
manlo <= conv_std_logic_vector(53935566,28);
exponent <= conv_std_logic_vector(471,11);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6106203,24);
manlo <= conv_std_logic_vector(233166714,28);
exponent <= conv_std_logic_vector(470,11);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(59463,24);
manlo <= conv_std_logic_vector(114545214,28);
exponent <= conv_std_logic_vector(469,11);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7998256,24);
manlo <= conv_std_logic_vector(234808364,28);
exponent <= conv_std_logic_vector(467,11);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(1451558,24);
manlo <= conv_std_logic_vector(62230667,28);
exponent <= conv_std_logic_vector(466,11);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(10046749,24);
manlo <= conv_std_logic_vector(29683609,28);
exponent <= conv_std_logic_vector(464,11);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(2958754,24);
manlo <= conv_std_logic_vector(158313814,28);
exponent <= conv_std_logic_vector(463,11);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(12264615,24);
manlo <= conv_std_logic_vector(87551554,28);
exponent <= conv_std_logic_vector(461,11);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(4590569,24);
manlo <= conv_std_logic_vector(96025360,28);
exponent <= conv_std_logic_vector(460,11);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(14665859,24);
manlo <= conv_std_logic_vector(200220878,28);
exponent <= conv_std_logic_vector(458,11);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6357306,24);
manlo <= conv_std_logic_vector(71997608,28);
exponent <= conv_std_logic_vector(457,11);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(244214,24);
manlo <= conv_std_logic_vector(66463607,28);
exponent <= conv_std_logic_vector(456,11);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(8270120,24);
manlo <= conv_std_logic_vector(265669912,28);
exponent <= conv_std_logic_vector(454,11);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(1651584,24);
manlo <= conv_std_logic_vector(179638473,28);
exponent <= conv_std_logic_vector(453,11);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(10341091,24);
manlo <= conv_std_logic_vector(152092530,28);
exponent <= conv_std_logic_vector(451,11);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(3175319,24);
manlo <= conv_std_logic_vector(178838140,28);
exponent <= conv_std_logic_vector(450,11);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(12583294,24);
manlo <= conv_std_logic_vector(183442082,28);
exponent <= conv_std_logic_vector(448,11);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(4825040,24);
manlo <= conv_std_logic_vector(141040370,28);
exponent <= conv_std_logic_vector(447,11);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(15010888,24);
manlo <= conv_std_logic_vector(62934477,28);
exponent <= conv_std_logic_vector(445,11);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6611164,24);
manlo <= conv_std_logic_vector(11633311,28);
exponent <= conv_std_logic_vector(444,11);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(430992,24);
manlo <= conv_std_logic_vector(96770068,28);
exponent <= conv_std_logic_vector(443,11);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8544968,24);
manlo <= conv_std_logic_vector(80768180,28);
exponent <= conv_std_logic_vector(441,11);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(1853806,24);
manlo <= conv_std_logic_vector(5288079,28);
exponent <= conv_std_logic_vector(440,11);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(10638663,24);
manlo <= conv_std_logic_vector(235213815,28);
exponent <= conv_std_logic_vector(438,11);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(3394261,24);
manlo <= conv_std_logic_vector(36557939,28);
exponent <= conv_std_logic_vector(437,11);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(12905470,24);
manlo <= conv_std_logic_vector(253900977,28);
exponent <= conv_std_logic_vector(435,11);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(5062084,24);
manlo <= conv_std_logic_vector(153603034,28);
exponent <= conv_std_logic_vector(434,11);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(15359702,24);
manlo <= conv_std_logic_vector(204098933,28);
exponent <= conv_std_logic_vector(432,11);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6867807,24);
manlo <= conv_std_logic_vector(115170312,28);
exponent <= conv_std_logic_vector(431,11);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(619820,24);
manlo <= conv_std_logic_vector(2986045,28);
exponent <= conv_std_logic_vector(430,11);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8822831,24);
manlo <= conv_std_logic_vector(145826716,28);
exponent <= conv_std_logic_vector(428,11);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(2058246,24);
manlo <= conv_std_logic_vector(98876593,28);
exponent <= conv_std_logic_vector(427,11);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(10939501,24);
manlo <= conv_std_logic_vector(129141213,28);
exponent <= conv_std_logic_vector(425,11);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(3615605,24);
manlo <= conv_std_logic_vector(20427716,28);
exponent <= conv_std_logic_vector(424,11);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(13231182,24);
manlo <= conv_std_logic_vector(130335695,28);
exponent <= conv_std_logic_vector(422,11);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(5301729,24);
manlo <= conv_std_logic_vector(196124198,28);
exponent <= conv_std_logic_vector(421,11);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(15712344,24);
manlo <= conv_std_logic_vector(233039482,28);
exponent <= conv_std_logic_vector(419,11);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(7127266,24);
manlo <= conv_std_logic_vector(266329205,28);
exponent <= conv_std_logic_vector(418,11);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(810719,24);
manlo <= conv_std_logic_vector(185030259,28);
exponent <= conv_std_logic_vector(417,11);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(9103743,24);
manlo <= conv_std_logic_vector(217685905,28);
exponent <= conv_std_logic_vector(415,11);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(2264930,24);
manlo <= conv_std_logic_vector(17303531,28);
exponent <= conv_std_logic_vector(414,11);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(11243640,24);
manlo <= conv_std_logic_vector(56799625,28);
exponent <= conv_std_logic_vector(412,11);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(3839377,24);
manlo <= conv_std_logic_vector(227776580,28);
exponent <= conv_std_logic_vector(411,11);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(13560468,24);
manlo <= conv_std_logic_vector(25616516,28);
exponent <= conv_std_logic_vector(409,11);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(5544004,24);
manlo <= conv_std_logic_vector(145740137,28);
exponent <= conv_std_logic_vector(408,11);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(16068856,24);
manlo <= conv_std_logic_vector(149889545,28);
exponent <= conv_std_logic_vector(406,11);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(7389573,24);
manlo <= conv_std_logic_vector(170431948,28);
exponent <= conv_std_logic_vector(405,11);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(1003714,24);
manlo <= conv_std_logic_vector(35324999,28);
exponent <= conv_std_logic_vector(404,11);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(9387738,24);
manlo <= conv_std_logic_vector(150667400,28);
exponent <= conv_std_logic_vector(402,11);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(2473881,24);
manlo <= conv_std_logic_vector(194497484,28);
exponent <= conv_std_logic_vector(401,11);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(11551116,24);
manlo <= conv_std_logic_vector(78219737,28);
exponent <= conv_std_logic_vector(399,11);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(4065606,24);
manlo <= conv_std_logic_vector(28280174,28);
exponent <= conv_std_logic_vector(398,11);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(13893366,24);
manlo <= conv_std_logic_vector(266881350,28);
exponent <= conv_std_logic_vector(396,11);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(5788937,24);
manlo <= conv_std_logic_vector(232096008,28);
exponent <= conv_std_logic_vector(395,11);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(16429280,24);
manlo <= conv_std_logic_vector(78498076,28);
exponent <= conv_std_logic_vector(393,11);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(7654758,24);
manlo <= conv_std_logic_vector(160696217,28);
exponent <= conv_std_logic_vector(392,11);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(1198826,24);
manlo <= conv_std_logic_vector(87006684,28);
exponent <= conv_std_logic_vector(391,11);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(9674849,24);
manlo <= conv_std_logic_vector(166079254,28);
exponent <= conv_std_logic_vector(389,11);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(2685126,24);
manlo <= conv_std_logic_vector(63154951,28);
exponent <= conv_std_logic_vector(388,11);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(11861966,24);
manlo <= conv_std_logic_vector(91696135,28);
exponent <= conv_std_logic_vector(386,11);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(4294316,24);
manlo <= conv_std_logic_vector(212296424,28);
exponent <= conv_std_logic_vector(385,11);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(14229918,24);
manlo <= conv_std_logic_vector(223047784,28);
exponent <= conv_std_logic_vector(383,11);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(6036558,24);
manlo <= conv_std_logic_vector(232962025,28);
exponent <= conv_std_logic_vector(382,11);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(8221,24);
manlo <= conv_std_logic_vector(133893557,28);
exponent <= conv_std_logic_vector(381,11);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7922853,24);
manlo <= conv_std_logic_vector(125492404,28);
exponent <= conv_std_logic_vector(379,11);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(1396079,24);
manlo <= conv_std_logic_vector(135612572,28);
exponent <= conv_std_logic_vector(378,11);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9965111,24);
manlo <= conv_std_logic_vector(47990958,28);
exponent <= conv_std_logic_vector(376,11);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(2898688,24);
manlo <= conv_std_logic_vector(203019642,28);
exponent <= conv_std_logic_vector(375,11);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(12176227,24);
manlo <= conv_std_logic_vector(103393586,28);
exponent <= conv_std_logic_vector(373,11);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(4525537,24);
manlo <= conv_std_logic_vector(38936964,28);
exponent <= conv_std_logic_vector(372,11);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(14570163,24);
manlo <= conv_std_logic_vector(185128905,28);
exponent <= conv_std_logic_vector(370,11);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(6286897,24);
manlo <= conv_std_logic_vector(12037044,28);
exponent <= conv_std_logic_vector(369,11);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(192410,24);
manlo <= conv_std_logic_vector(9691196,28);
exponent <= conv_std_logic_vector(368,11);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(8193890,24);
manlo <= conv_std_logic_vector(46224319,28);
exponent <= conv_std_logic_vector(366,11);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(1595497,24);
manlo <= conv_std_logic_vector(45130080,28);
exponent <= conv_std_logic_vector(365,11);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(10258557,24);
manlo <= conv_std_logic_vector(218068546,28);
exponent <= conv_std_logic_vector(363,11);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(3114594,24);
manlo <= conv_std_logic_vector(194203222,28);
exponent <= conv_std_logic_vector(362,11);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(12493936,24);
manlo <= conv_std_logic_vector(228530713,28);
exponent <= conv_std_logic_vector(360,11);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(4759294,24);
manlo <= conv_std_logic_vector(189728046,28);
exponent <= conv_std_logic_vector(359,11);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(14914142,24);
manlo <= conv_std_logic_vector(25337562,28);
exponent <= conv_std_logic_vector(357,11);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(6539982,24);
manlo <= conv_std_logic_vector(56762382,28);
exponent <= conv_std_logic_vector(356,11);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(378619,24);
manlo <= conv_std_logic_vector(186677702,28);
exponent <= conv_std_logic_vector(355,11);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(8467900,24);
manlo <= conv_std_logic_vector(266785510,28);
exponent <= conv_std_logic_vector(353,11);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(1797103,24);
manlo <= conv_std_logic_vector(17183357,28);
exponent <= conv_std_logic_vector(352,11);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(10555224,24);
manlo <= conv_std_logic_vector(126067134,28);
exponent <= conv_std_logic_vector(350,11);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(3332869,24);
manlo <= conv_std_logic_vector(228611260,28);
exponent <= conv_std_logic_vector(349,11);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(12815132,24);
manlo <= conv_std_logic_vector(155705738,28);
exponent <= conv_std_logic_vector(347,11);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(4995617,24);
manlo <= conv_std_logic_vector(85136440,28);
exponent <= conv_std_logic_vector(346,11);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(15261895,24);
manlo <= conv_std_logic_vector(3688335,28);
exponent <= conv_std_logic_vector(344,11);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(6795844,24);
manlo <= conv_std_logic_vector(137097782,28);
exponent <= conv_std_logic_vector(343,11);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(566872,24);
manlo <= conv_std_logic_vector(175764875,28);
exponent <= conv_std_logic_vector(342,11);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(8744918,24);
manlo <= conv_std_logic_vector(152414052,28);
exponent <= conv_std_logic_vector(340,11);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(2000921,24);
manlo <= conv_std_logic_vector(54921723,28);
exponent <= conv_std_logic_vector(339,11);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(10855146,24);
manlo <= conv_std_logic_vector(129996510,28);
exponent <= conv_std_logic_vector(337,11);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(3553540,24);
manlo <= conv_std_logic_vector(37023540,28);
exponent <= conv_std_logic_vector(336,11);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(13139852,24);
manlo <= conv_std_logic_vector(221848100,28);
exponent <= conv_std_logic_vector(334,11);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(5234533,24);
manlo <= conv_std_logic_vector(32943194,28);
exponent <= conv_std_logic_vector(333,11);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(15613463,24);
manlo <= conv_std_logic_vector(232436445,28);
exponent <= conv_std_logic_vector(331,11);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7054514,24);
manlo <= conv_std_logic_vector(111791498,28);
exponent <= conv_std_logic_vector(330,11);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(757191,24);
manlo <= conv_std_logic_vector(90062360,28);
exponent <= conv_std_logic_vector(329,11);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(9024975,24);
manlo <= conv_std_logic_vector(238219590,28);
exponent <= conv_std_logic_vector(327,11);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(2206975,24);
manlo <= conv_std_logic_vector(232222812,28);
exponent <= conv_std_logic_vector(326,11);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(11158359,24);
manlo <= conv_std_logic_vector(155073518,28);
exponent <= conv_std_logic_vector(324,11);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(3776631,24);
manlo <= conv_std_logic_vector(232102510,28);
exponent <= conv_std_logic_vector(323,11);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(13468136,24);
manlo <= conv_std_logic_vector(71264246,28);
exponent <= conv_std_logic_vector(321,11);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(5476070,24);
manlo <= conv_std_logic_vector(155401688,28);
exponent <= conv_std_logic_vector(320,11);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(15968890,24);
manlo <= conv_std_logic_vector(140531032,28);
exponent <= conv_std_logic_vector(318,11);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7316022,24);
manlo <= conv_std_logic_vector(197790036,28);
exponent <= conv_std_logic_vector(317,11);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(949598,24);
manlo <= conv_std_logic_vector(108723575,28);
exponent <= conv_std_logic_vector(316,11);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(9308106,24);
manlo <= conv_std_logic_vector(82754530,28);
exponent <= conv_std_logic_vector(314,11);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(2415291,24);
manlo <= conv_std_logic_vector(157597766,28);
exponent <= conv_std_logic_vector(313,11);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(11464899,24);
manlo <= conv_std_logic_vector(231735034,28);
exponent <= conv_std_logic_vector(311,11);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(4002171,24);
manlo <= conv_std_logic_vector(161749904,28);
exponent <= conv_std_logic_vector(310,11);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(13800021,24);
manlo <= conv_std_logic_vector(267486845,28);
exponent <= conv_std_logic_vector(308,11);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(5720258,24);
manlo <= conv_std_logic_vector(121711942,28);
exponent <= conv_std_logic_vector(307,11);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(16328217,24);
manlo <= conv_std_logic_vector(85566619,28);
exponent <= conv_std_logic_vector(305,11);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7580400,24);
manlo <= conv_std_logic_vector(165916765,28);
exponent <= conv_std_logic_vector(304,11);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(1144116,24);
manlo <= conv_std_logic_vector(209234965,28);
exponent <= conv_std_logic_vector(303,11);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(9594343,24);
manlo <= conv_std_logic_vector(148128653,28);
exponent <= conv_std_logic_vector(301,11);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(2625893,24);
manlo <= conv_std_logic_vector(48717694,28);
exponent <= conv_std_logic_vector(300,11);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(11774803,24);
manlo <= conv_std_logic_vector(228357100,28);
exponent <= conv_std_logic_vector(298,11);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(4230186,24);
manlo <= conv_std_logic_vector(57439900,28);
exponent <= conv_std_logic_vector(297,11);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(14135549,24);
manlo <= conv_std_logic_vector(147041206,28);
exponent <= conv_std_logic_vector(295,11);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(5967125,24);
manlo <= conv_std_logic_vector(222682176,28);
exponent <= conv_std_logic_vector(294,11);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(16691487,24);
manlo <= conv_std_logic_vector(12959237,28);
exponent <= conv_std_logic_vector(292,11);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(7847679,24);
manlo <= conv_std_logic_vector(147174066,28);
exponent <= conv_std_logic_vector(291,11);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(1340769,24);
manlo <= conv_std_logic_vector(168148656,28);
exponent <= conv_std_logic_vector(290,11);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(9883721,24);
manlo <= conv_std_logic_vector(190474495,28);
exponent <= conv_std_logic_vector(288,11);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(2838805,24);
manlo <= conv_std_logic_vector(196335986,28);
exponent <= conv_std_logic_vector(287,11);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(12088108,24);
manlo <= conv_std_logic_vector(120857634,28);
exponent <= conv_std_logic_vector(285,11);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(4460702,24);
manlo <= conv_std_logic_vector(229771569,28);
exponent <= conv_std_logic_vector(284,11);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(14474758,24);
manlo <= conv_std_logic_vector(236628147,28);
exponent <= conv_std_logic_vector(282,11);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(6216702,24);
manlo <= conv_std_logic_vector(29481361,28);
exponent <= conv_std_logic_vector(281,11);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(140763,24);
manlo <= conv_std_logic_vector(131310533,28);
exponent <= conv_std_logic_vector(280,11);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8117891,24);
manlo <= conv_std_logic_vector(96879140,28);
exponent <= conv_std_logic_vector(278,11);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(1539580,24);
manlo <= conv_std_logic_vector(98694067,28);
exponent <= conv_std_logic_vector(277,11);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(10176275,24);
manlo <= conv_std_logic_vector(66343668,28);
exponent <= conv_std_logic_vector(275,11);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(3054054,24);
manlo <= conv_std_logic_vector(159783892,28);
exponent <= conv_std_logic_vector(274,11);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(12404850,24);
manlo <= conv_std_logic_vector(262311967,28);
exponent <= conv_std_logic_vector(272,11);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(4693748,24);
manlo <= conv_std_logic_vector(264030756,28);
exponent <= conv_std_logic_vector(271,11);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(14817690,24);
manlo <= conv_std_logic_vector(106917994,28);
exponent <= conv_std_logic_vector(269,11);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(6469017,24);
manlo <= conv_std_logic_vector(5191992,28);
exponent <= conv_std_logic_vector(268,11);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(326406,24);
manlo <= conv_std_logic_vector(114083215,28);
exponent <= conv_std_logic_vector(267,11);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8391068,24);
manlo <= conv_std_logic_vector(64117214,28);
exponent <= conv_std_logic_vector(265,11);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(1740572,24);
manlo <= conv_std_logic_vector(183091279,28);
exponent <= conv_std_logic_vector(264,11);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(10472039,24);
manlo <= conv_std_logic_vector(2244224,28);
exponent <= conv_std_logic_vector(262,11);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(3271665,24);
manlo <= conv_std_logic_vector(109958542,28);
exponent <= conv_std_logic_vector(261,11);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(12725069,24);
manlo <= conv_std_logic_vector(41968573,28);
exponent <= conv_std_logic_vector(259,11);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(4929352,24);
manlo <= conv_std_logic_vector(94809674,28);
exponent <= conv_std_logic_vector(258,11);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(15164384,24);
manlo <= conv_std_logic_vector(252890425,28);
exponent <= conv_std_logic_vector(256,11);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(6724100,24);
manlo <= conv_std_logic_vector(163583158,28);
exponent <= conv_std_logic_vector(255,11);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(514086,24);
manlo <= conv_std_logic_vector(118679222,28);
exponent <= conv_std_logic_vector(254,11);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8667242,24);
manlo <= conv_std_logic_vector(192770478,28);
exponent <= conv_std_logic_vector(252,11);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(1943770,24);
manlo <= conv_std_logic_vector(136437165,28);
exponent <= conv_std_logic_vector(251,11);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(10771048,24);
manlo <= conv_std_logic_vector(58883744,28);
exponent <= conv_std_logic_vector(249,11);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(3491664,24);
manlo <= conv_std_logic_vector(24836209,28);
exponent <= conv_std_logic_vector(248,11);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(13048801,24);
manlo <= conv_std_logic_vector(33938829,28);
exponent <= conv_std_logic_vector(246,11);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(5167541,24);
manlo <= conv_std_logic_vector(6894318,28);
exponent <= conv_std_logic_vector(245,11);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(15514883,24);
manlo <= conv_std_logic_vector(216092120,28);
exponent <= conv_std_logic_vector(243,11);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(6981983,24);
manlo <= conv_std_logic_vector(70071320,28);
exponent <= conv_std_logic_vector(242,11);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(703825,24);
manlo <= conv_std_logic_vector(239890498,28);
exponent <= conv_std_logic_vector(241,11);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8946447,24);
manlo <= conv_std_logic_vector(185687386,28);
exponent <= conv_std_logic_vector(239,11);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(2149198,24);
manlo <= conv_std_logic_vector(12777107,28);
exponent <= conv_std_logic_vector(238,11);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11073338,24);
manlo <= conv_std_logic_vector(132295567,28);
exponent <= conv_std_logic_vector(236,11);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(3714076,24);
manlo <= conv_std_logic_vector(227171857,28);
exponent <= conv_std_logic_vector(235,11);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(13376085,24);
manlo <= conv_std_logic_vector(119368169,28);
exponent <= conv_std_logic_vector(233,11);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(5408343,24);
manlo <= conv_std_logic_vector(99290689,28);
exponent <= conv_std_logic_vector(232,11);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(15869228,24);
manlo <= conv_std_logic_vector(196569651,28);
exponent <= conv_std_logic_vector(230,11);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(7242695,24);
manlo <= conv_std_logic_vector(184868911,28);
exponent <= conv_std_logic_vector(229,11);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(895647,24);
manlo <= conv_std_logic_vector(101480846,28);
exponent <= conv_std_logic_vector(228,11);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(9228716,24);
manlo <= conv_std_logic_vector(111040654,28);
exponent <= conv_std_logic_vector(226,11);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(2356879,24);
manlo <= conv_std_logic_vector(205878747,28);
exponent <= conv_std_logic_vector(225,11);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(11378945,24);
manlo <= conv_std_logic_vector(223412824,28);
exponent <= conv_std_logic_vector(223,11);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(3938930,24);
manlo <= conv_std_logic_vector(43159582,28);
exponent <= conv_std_logic_vector(222,11);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(13706961,24);
manlo <= conv_std_logic_vector(24539717,28);
exponent <= conv_std_logic_vector(220,11);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(5651788,24);
manlo <= conv_std_logic_vector(17696328,28);
exponent <= conv_std_logic_vector(219,11);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(16227461,24);
manlo <= conv_std_logic_vector(248897772,28);
exponent <= conv_std_logic_vector(217,11);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(7506268,24);
manlo <= conv_std_logic_vector(253353585,28);
exponent <= conv_std_logic_vector(216,11);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(1089573,24);
manlo <= conv_std_logic_vector(199085712,28);
exponent <= conv_std_logic_vector(215,11);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(9514082,24);
manlo <= conv_std_logic_vector(134954983,28);
exponent <= conv_std_logic_vector(213,11);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(2566840,24);
manlo <= conv_std_logic_vector(107836942,28);
exponent <= conv_std_logic_vector(212,11);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(11687906,24);
manlo <= conv_std_logic_vector(170784064,28);
exponent <= conv_std_logic_vector(210,11);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(4166250,24);
manlo <= conv_std_logic_vector(219198631,28);
exponent <= conv_std_logic_vector(209,11);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(14041467,24);
manlo <= conv_std_logic_vector(127426909,28);
exponent <= conv_std_logic_vector(207,11);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(5897904,24);
manlo <= conv_std_logic_vector(29159081,28);
exponent <= conv_std_logic_vector(206,11);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(16589626,24);
manlo <= conv_std_logic_vector(15093248,28);
exponent <= conv_std_logic_vector(204,11);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(7772734,24);
manlo <= conv_std_logic_vector(112367334,28);
exponent <= conv_std_logic_vector(203,11);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(1285628,24);
manlo <= conv_std_logic_vector(21894417,28);
exponent <= conv_std_logic_vector(202,11);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9802579,24);
manlo <= conv_std_logic_vector(254146435,28);
exponent <= conv_std_logic_vector(200,11);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(2779104,24);
manlo <= conv_std_logic_vector(257348234,28);
exponent <= conv_std_logic_vector(199,11);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12000257,24);
manlo <= conv_std_logic_vector(188607876,28);
exponent <= conv_std_logic_vector(197,11);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(4396065,24);
manlo <= conv_std_logic_vector(238395052,28);
exponent <= conv_std_logic_vector(196,11);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(14379644,24);
manlo <= conv_std_logic_vector(116776141,28);
exponent <= conv_std_logic_vector(194,11);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(6146720,24);
manlo <= conv_std_logic_vector(217697734,28);
exponent <= conv_std_logic_vector(193,11);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(89274,24);
manlo <= conv_std_logic_vector(34078121,28);
exponent <= conv_std_logic_vector(192,11);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(8042123,24);
manlo <= conv_std_logic_vector(228091050,28);
exponent <= conv_std_logic_vector(190,11);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(1483833,24);
manlo <= conv_std_logic_vector(200872250,28);
exponent <= conv_std_logic_vector(189,11);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(10094243,24);
manlo <= conv_std_logic_vector(28573613,28);
exponent <= conv_std_logic_vector(187,11);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(2993698,24);
manlo <= conv_std_logic_vector(193026703,28);
exponent <= conv_std_logic_vector(186,11);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12316036,24);
manlo <= conv_std_logic_vector(62602992,28);
exponent <= conv_std_logic_vector(184,11);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(4628402,24);
manlo <= conv_std_logic_vector(200475490,28);
exponent <= conv_std_logic_vector(183,11);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(14721532,24);
manlo <= conv_std_logic_vector(67122338,28);
exponent <= conv_std_logic_vector(181,11);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(6398267,24);
manlo <= conv_std_logic_vector(216803728,28);
exponent <= conv_std_logic_vector(180,11);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(274352,24);
manlo <= conv_std_logic_vector(17200594,28);
exponent <= conv_std_logic_vector(179,11);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(8314469,24);
manlo <= conv_std_logic_vector(86446456,28);
exponent <= conv_std_logic_vector(177,11);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(1684214,24);
manlo <= conv_std_logic_vector(93587914,28);
exponent <= conv_std_logic_vector(176,11);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(10389106,24);
manlo <= conv_std_logic_vector(193148951,28);
exponent <= conv_std_logic_vector(174,11);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(3210647,24);
manlo <= conv_std_logic_vector(64824977,28);
exponent <= conv_std_logic_vector(173,11);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(12635279,24);
manlo <= conv_std_logic_vector(224939505,28);
exponent <= conv_std_logic_vector(171,11);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(4863289,24);
manlo <= conv_std_logic_vector(17355920,28);
exponent <= conv_std_logic_vector(170,11);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(15067171,24);
manlo <= conv_std_logic_vector(171641236,28);
exponent <= conv_std_logic_vector(168,11);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(6652575,24);
manlo <= conv_std_logic_vector(15694991,28);
exponent <= conv_std_logic_vector(167,11);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(461460,24);
manlo <= conv_std_logic_vector(236949593,28);
exponent <= conv_std_logic_vector(166,11);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(8589803,24);
manlo <= conv_std_logic_vector(73170085,28);
exponent <= conv_std_logic_vector(164,11);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(1886793,24);
manlo <= conv_std_logic_vector(200887360,28);
exponent <= conv_std_logic_vector(163,11);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(10687205,24);
manlo <= conv_std_logic_vector(242930225,28);
exponent <= conv_std_logic_vector(161,11);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(3429976,24);
manlo <= conv_std_logic_vector(97980458,28);
exponent <= conv_std_logic_vector(160,11);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(12958026,24);
manlo <= conv_std_logic_vector(144828568,28);
exponent <= conv_std_logic_vector(158,11);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(5100752,24);
manlo <= conv_std_logic_vector(219332721,28);
exponent <= conv_std_logic_vector(157,11);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(15416603,24);
manlo <= conv_std_logic_vector(206580322,28);
exponent <= conv_std_logic_vector(155,11);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(6909672,24);
manlo <= conv_std_logic_vector(228709240,28);
exponent <= conv_std_logic_vector(154,11);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(650622,24);
manlo <= conv_std_logic_vector(232984198,28);
exponent <= conv_std_logic_vector(153,11);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(8868158,24);
manlo <= conv_std_logic_vector(132673062,28);
exponent <= conv_std_logic_vector(151,11);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(2091596,24);
manlo <= conv_std_logic_vector(20173170,28);
exponent <= conv_std_logic_vector(150,11);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(10988576,24);
manlo <= conv_std_logic_vector(44856082,28);
exponent <= conv_std_logic_vector(148,11);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(3651712,24);
manlo <= conv_std_logic_vector(56970522,28);
exponent <= conv_std_logic_vector(147,11);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13284314,24);
manlo <= conv_std_logic_vector(208786223,28);
exponent <= conv_std_logic_vector(145,11);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(5340822,24);
manlo <= conv_std_logic_vector(76928898,28);
exponent <= conv_std_logic_vector(144,11);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(15769870,24);
manlo <= conv_std_logic_vector(69445892,28);
exponent <= conv_std_logic_vector(142,11);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(7169591,24);
manlo <= conv_std_logic_vector(217224162,28);
exponent <= conv_std_logic_vector(141,11);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(841860,24);
manlo <= conv_std_logic_vector(147476782,28);
exponent <= conv_std_logic_vector(140,11);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9149568,24);
manlo <= conv_std_logic_vector(37524984,28);
exponent <= conv_std_logic_vector(138,11);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(2298645,24);
manlo <= conv_std_logic_vector(193659590,28);
exponent <= conv_std_logic_vector(137,11);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(11293253,24);
manlo <= conv_std_logic_vector(107316618,28);
exponent <= conv_std_logic_vector(135,11);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(3875881,24);
manlo <= conv_std_logic_vector(51654059,28);
exponent <= conv_std_logic_vector(134,11);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13614183,24);
manlo <= conv_std_logic_vector(111249634,28);
exponent <= conv_std_logic_vector(132,11);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(5583526,24);
manlo <= conv_std_logic_vector(17717412,28);
exponent <= conv_std_logic_vector(131,11);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(16127013,24);
manlo <= conv_std_logic_vector(48769099,28);
exponent <= conv_std_logic_vector(129,11);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(7432362,24);
manlo <= conv_std_logic_vector(238120049,28);
exponent <= conv_std_logic_vector(128,11);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(1035196,24);
manlo <= conv_std_logic_vector(188962402,28);
exponent <= conv_std_logic_vector(127,11);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9434065,24);
manlo <= conv_std_logic_vector(194820226,28);
exponent <= conv_std_logic_vector(125,11);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(2507967,24);
manlo <= conv_std_logic_vector(93233285,28);
exponent <= conv_std_logic_vector(124,11);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(11601273,24);
manlo <= conv_std_logic_vector(239123672,28);
exponent <= conv_std_logic_vector(122,11);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(4102510,24);
manlo <= conv_std_logic_vector(1244898,28);
exponent <= conv_std_logic_vector(121,11);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(13947671,24);
manlo <= conv_std_logic_vector(197996828,28);
exponent <= conv_std_logic_vector(119,11);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(5828893,24);
manlo <= conv_std_logic_vector(16622593,28);
exponent <= conv_std_logic_vector(118,11);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(16488075,24);
manlo <= conv_std_logic_vector(20144764,28);
exponent <= conv_std_logic_vector(116,11);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(7698017,24);
manlo <= conv_std_logic_vector(102592250,28);
exponent <= conv_std_logic_vector(115,11);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(1230654,24);
manlo <= conv_std_logic_vector(96196092,28);
exponent <= conv_std_logic_vector(114,11);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(9721685,24);
manlo <= conv_std_logic_vector(36636777,28);
exponent <= conv_std_logic_vector(112,11);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(2719585,24);
manlo <= conv_std_logic_vector(237160861,28);
exponent <= conv_std_logic_vector(111,11);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(11912674,24);
manlo <= conv_std_logic_vector(87541902,28);
exponent <= conv_std_logic_vector(109,11);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(4331625,24);
manlo <= conv_std_logic_vector(172036325,28);
exponent <= conv_std_logic_vector(108,11);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14284819,24);
manlo <= conv_std_logic_vector(125225503,28);
exponent <= conv_std_logic_vector(106,11);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(6076952,24);
manlo <= conv_std_logic_vector(133715238,28);
exponent <= conv_std_logic_vector(105,11);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(37941,24);
manlo <= conv_std_logic_vector(126448851,28);
exponent <= conv_std_logic_vector(104,11);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(7966586,24);
manlo <= conv_std_logic_vector(250893596,28);
exponent <= conv_std_logic_vector(102,11);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(1428256,24);
manlo <= conv_std_logic_vector(212630882,28);
exponent <= conv_std_logic_vector(101,11);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10012460,24);
manlo <= conv_std_logic_vector(168603206,28);
exponent <= conv_std_logic_vector(99,11);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(2933526,24);
manlo <= conv_std_logic_vector(143402282,28);
exponent <= conv_std_logic_vector(98,11);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(12227491,24);
manlo <= conv_std_logic_vector(213203509,28);
exponent <= conv_std_logic_vector(96,11);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(4563255,24);
manlo <= conv_std_logic_vector(104522224,28);
exponent <= conv_std_logic_vector(95,11);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14625666,24);
manlo <= conv_std_logic_vector(203000190,28);
exponent <= conv_std_logic_vector(93,11);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(6327733,24);
manlo <= conv_std_logic_vector(246711469,28);
exponent <= conv_std_logic_vector(92,11);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(222456,24);
manlo <= conv_std_logic_vector(34640152,28);
exponent <= conv_std_logic_vector(91,11);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(8238103,24);
manlo <= conv_std_logic_vector(142733230,28);
exponent <= conv_std_logic_vector(89,11);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(1628027,24);
manlo <= conv_std_logic_vector(144984792,28);
exponent <= conv_std_logic_vector(88,11);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10306426,24);
manlo <= conv_std_logic_vector(223510234,28);
exponent <= conv_std_logic_vector(86,11);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(3149814,24);
manlo <= conv_std_logic_vector(209464872,28);
exponent <= conv_std_logic_vector(85,11);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(12545763,24);
manlo <= conv_std_logic_vector(212245812,28);
exponent <= conv_std_logic_vector(83,11);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(4797426,24);
manlo <= conv_std_logic_vector(224882259,28);
exponent <= conv_std_logic_vector(82,11);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14970254,24);
manlo <= conv_std_logic_vector(54358776,28);
exponent <= conv_std_logic_vector(80,11);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(6581267,24);
manlo <= conv_std_logic_vector(51917314,28);
exponent <= conv_std_logic_vector(79,11);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(408995,24);
manlo <= conv_std_logic_vector(130890803,28);
exponent <= conv_std_logic_vector(78,11);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(8512599,24);
manlo <= conv_std_logic_vector(137347476,28);
exponent <= conv_std_logic_vector(76,11);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(1829990,24);
manlo <= conv_std_logic_vector(106170554,28);
exponent <= conv_std_logic_vector(75,11);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10603618,24);
manlo <= conv_std_logic_vector(204595238,28);
exponent <= conv_std_logic_vector(73,11);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(3368476,24);
manlo <= conv_std_logic_vector(102605239,28);
exponent <= conv_std_logic_vector(72,11);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(12867528,24);
manlo <= conv_std_logic_vector(59687307,28);
exponent <= conv_std_logic_vector(70,11);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(5034167,24);
manlo <= conv_std_logic_vector(235251142,28);
exponent <= conv_std_logic_vector(69,11);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15318622,24);
manlo <= conv_std_logic_vector(227223140,28);
exponent <= conv_std_logic_vector(67,11);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(6837582,24);
manlo <= conv_std_logic_vector(138925467,28);
exponent <= conv_std_logic_vector(66,11);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(597581,24);
manlo <= conv_std_logic_vector(205088968,28);
exponent <= conv_std_logic_vector(65,11);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(8790107,24);
manlo <= conv_std_logic_vector(152356460,28);
exponent <= conv_std_logic_vector(63,11);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(2034169,24);
manlo <= conv_std_logic_vector(110749946,28);
exponent <= conv_std_logic_vector(62,11);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10904071,24);
manlo <= conv_std_logic_vector(218226183,28);
exponent <= conv_std_logic_vector(60,11);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(3589537,24);
manlo <= conv_std_logic_vector(102830143,28);
exponent <= conv_std_logic_vector(59,11);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(13192823,24);
manlo <= conv_std_logic_vector(110639602,28);
exponent <= conv_std_logic_vector(57,11);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(5273506,24);
manlo <= conv_std_logic_vector(188352155,28);
exponent <= conv_std_logic_vector(56,11);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15670814,24);
manlo <= conv_std_logic_vector(48227643,28);
exponent <= conv_std_logic_vector(54,11);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(7096710,24);
manlo <= conv_std_logic_vector(112532514,28);
exponent <= conv_std_logic_vector(53,11);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(788237,24);
manlo <= conv_std_logic_vector(112565412,28);
exponent <= conv_std_logic_vector(52,11);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(9070660,24);
manlo <= conv_std_logic_vector(201680253,28);
exponent <= conv_std_logic_vector(50,11);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(2240588,24);
manlo <= conv_std_logic_vector(244138286,28);
exponent <= conv_std_logic_vector(49,11);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(11207821,24);
manlo <= conv_std_logic_vector(206597824,28);
exponent <= conv_std_logic_vector(47,11);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(3813024,24);
manlo <= conv_std_logic_vector(29987310,28);
exponent <= conv_std_logic_vector(46,11);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(13521688,24);
manlo <= conv_std_logic_vector(27790821,28);
exponent <= conv_std_logic_vector(44,11);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(5515471,24);
manlo <= conv_std_logic_vector(219963166,28);
exponent <= conv_std_logic_vector(43,11);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(16026870,24);
manlo <= conv_std_logic_vector(39964772,28);
exponent <= conv_std_logic_vector(41,11);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(7358681,24);
manlo <= conv_std_logic_vector(204327682,28);
exponent <= conv_std_logic_vector(40,11);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(980985,24);
manlo <= conv_std_logic_vector(43247066,28);
exponent <= conv_std_logic_vector(39,11);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(9354292,24);
manlo <= conv_std_logic_vector(128160132,28);
exponent <= conv_std_logic_vector(37,11);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(2449273,24);
manlo <= conv_std_logic_vector(126511008,28);
exponent <= conv_std_logic_vector(36,11);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(11514904,24);
manlo <= conv_std_logic_vector(217311246,28);
exponent <= conv_std_logic_vector(34,11);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(4038963,24);
manlo <= conv_std_logic_vector(49913566,28);
exponent <= conv_std_logic_vector(33,11);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(13854161,24);
manlo <= conv_std_logic_vector(124821568,28);
exponent <= conv_std_logic_vector(31,11);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(5760092,24);
manlo <= conv_std_logic_vector(12957085,28);
exponent <= conv_std_logic_vector(30,11);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16386833,24);
manlo <= conv_std_logic_vector(43278038,28);
exponent <= conv_std_logic_vector(28,11);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(7623527,24);
manlo <= conv_std_logic_vector(199937734,28);
exponent <= conv_std_logic_vector(27,11);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(1175847,24);
manlo <= conv_std_logic_vector(253947561,28);
exponent <= conv_std_logic_vector(26,11);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(9641036,24);
manlo <= conv_std_logic_vector(141497796,28);
exponent <= conv_std_logic_vector(24,11);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(2660247,24);
manlo <= conv_std_logic_vector(255766959,28);
exponent <= conv_std_logic_vector(23,11);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11825357,24);
manlo <= conv_std_logic_vector(136095046,28);
exponent <= conv_std_logic_vector(21,11);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(4267381,24);
manlo <= conv_std_logic_vector(138414926,28);
exponent <= conv_std_logic_vector(20,11);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(14190283,24);
manlo <= conv_std_logic_vector(25479908,28);
exponent <= conv_std_logic_vector(18,11);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(6007396,24);
manlo <= conv_std_logic_vector(140400514,28);
exponent <= conv_std_logic_vector(17,11);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16750746,24);
manlo <= conv_std_logic_vector(23924155,28);
exponent <= conv_std_logic_vector(15,11);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(7891279,24);
manlo <= conv_std_logic_vector(245330892,28);
exponent <= conv_std_logic_vector(14,11);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(1372848,24);
manlo <= conv_std_logic_vector(263794815,28);
exponent <= conv_std_logic_vector(13,11);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(9930927,24);
manlo <= conv_std_logic_vector(14029030,28);
exponent <= conv_std_logic_vector(11,11);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(2873537,24);
manlo <= conv_std_logic_vector(129274844,28);
exponent <= conv_std_logic_vector(10,11);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(12139216,24);
manlo <= conv_std_logic_vector(224845565,28);
exponent <= conv_std_logic_vector(8,11);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(4498306,24);
manlo <= conv_std_logic_vector(82126943,28);
exponent <= conv_std_logic_vector(7,11);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(14530093,24);
manlo <= conv_std_logic_vector(7024665,28);
exponent <= conv_std_logic_vector(5,11);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(6257414,24);
manlo <= conv_std_logic_vector(187437029,28);
exponent <= conv_std_logic_vector(4,11);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(170718,24);
manlo <= conv_std_logic_vector(36971864,28);
exponent <= conv_std_logic_vector(3,11);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(8161970,24);
manlo <= conv_std_logic_vector(42518955,28);
exponent <= conv_std_logic_vector(1,11);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(1572011,24);
manlo <= conv_std_logic_vector(197150320,28);
exponent <= conv_std_logic_vector(0,11);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_explutneg.vhd
|
10
|
140760
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explutneg IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_explutneg;
ARCHITECTURE rtl OF dp_explutneg IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(1023,11);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(7910755,24);
manlo <= conv_std_logic_vector(103608120,28);
exponent <= conv_std_logic_vector(1021,11);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(1387178,24);
manlo <= conv_std_logic_vector(62882252,28);
exponent <= conv_std_logic_vector(1020,11);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(9952012,24);
manlo <= conv_std_logic_vector(214872239,28);
exponent <= conv_std_logic_vector(1018,11);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(2889051,24);
manlo <= conv_std_logic_vector(136396020,28);
exponent <= conv_std_logic_vector(1017,11);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(12162046,24);
manlo <= conv_std_logic_vector(873334,28);
exponent <= conv_std_logic_vector(1015,11);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(4515103,24);
manlo <= conv_std_logic_vector(18076886,28);
exponent <= conv_std_logic_vector(1014,11);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(14554809,24);
manlo <= conv_std_logic_vector(203729295,28);
exponent <= conv_std_logic_vector(1012,11);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(6275600,24);
manlo <= conv_std_logic_vector(68167597,28);
exponent <= conv_std_logic_vector(1011,11);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(184098,24);
manlo <= conv_std_logic_vector(86398042,28);
exponent <= conv_std_logic_vector(1010,11);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(8181659,24);
manlo <= conv_std_logic_vector(90471578,28);
exponent <= conv_std_logic_vector(1008,11);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(1586498,24);
manlo <= conv_std_logic_vector(59729764,28);
exponent <= conv_std_logic_vector(1007,11);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(10245315,24);
manlo <= conv_std_logic_vector(188988555,28);
exponent <= conv_std_logic_vector(1005,11);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(3104851,24);
manlo <= conv_std_logic_vector(194518424,28);
exponent <= conv_std_logic_vector(1004,11);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(12479599,24);
manlo <= conv_std_logic_vector(229643794,28);
exponent <= conv_std_logic_vector(1002,11);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(4748746,24);
manlo <= conv_std_logic_vector(36170808,28);
exponent <= conv_std_logic_vector(1001,11);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(14898619,24);
manlo <= conv_std_logic_vector(183403979,28);
exponent <= conv_std_logic_vector(999,11);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(6528561,24);
manlo <= conv_std_logic_vector(123365533,28);
exponent <= conv_std_logic_vector(998,11);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(370216,24);
manlo <= conv_std_logic_vector(208248737,28);
exponent <= conv_std_logic_vector(997,11);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(8455535,24);
manlo <= conv_std_logic_vector(254564210,28);
exponent <= conv_std_logic_vector(995,11);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(1788005,24);
manlo <= conv_std_logic_vector(99840615,28);
exponent <= conv_std_logic_vector(994,11);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(10541837,24);
manlo <= conv_std_logic_vector(14529516,28);
exponent <= conv_std_logic_vector(992,11);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(3323019,24);
manlo <= conv_std_logic_vector(252804514,28);
exponent <= conv_std_logic_vector(991,11);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(12800638,24);
manlo <= conv_std_logic_vector(70515377,28);
exponent <= conv_std_logic_vector(989,11);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(4984952,24);
manlo <= conv_std_logic_vector(266936970,28);
exponent <= conv_std_logic_vector(988,11);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(15246202,24);
manlo <= conv_std_logic_vector(73384750,28);
exponent <= conv_std_logic_vector(986,11);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(6784298,24);
manlo <= conv_std_logic_vector(117472834,28);
exponent <= conv_std_logic_vector(985,11);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(558377,24);
manlo <= conv_std_logic_vector(141983386,28);
exponent <= conv_std_logic_vector(984,11);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(8732417,24);
manlo <= conv_std_logic_vector(225268666,28);
exponent <= conv_std_logic_vector(982,11);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(1991723,24);
manlo <= conv_std_logic_vector(183207072,28);
exponent <= conv_std_logic_vector(981,11);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(10841612,24);
manlo <= conv_std_logic_vector(44859253,28);
exponent <= conv_std_logic_vector(979,11);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(3543582,24);
manlo <= conv_std_logic_vector(38615994,28);
exponent <= conv_std_logic_vector(978,11);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(13125199,24);
manlo <= conv_std_logic_vector(123823208,28);
exponent <= conv_std_logic_vector(976,11);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(5223751,24);
manlo <= conv_std_logic_vector(209149352,28);
exponent <= conv_std_logic_vector(975,11);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(15597598,24);
manlo <= conv_std_logic_vector(248916640,28);
exponent <= conv_std_logic_vector(973,11);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(7042841,24);
manlo <= conv_std_logic_vector(173666528,28);
exponent <= conv_std_logic_vector(972,11);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(748602,24);
manlo <= conv_std_logic_vector(266199140,28);
exponent <= conv_std_logic_vector(971,11);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(9012337,24);
manlo <= conv_std_logic_vector(264921173,28);
exponent <= conv_std_logic_vector(969,11);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(2197677,24);
manlo <= conv_std_logic_vector(112079619,28);
exponent <= conv_std_logic_vector(968,11);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(11144676,24);
manlo <= conv_std_logic_vector(200497976,28);
exponent <= conv_std_logic_vector(966,11);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(3766564,24);
manlo <= conv_std_logic_vector(161159716,28);
exponent <= conv_std_logic_vector(965,11);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(13453322,24);
manlo <= conv_std_logic_vector(28788768,28);
exponent <= conv_std_logic_vector(963,11);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(5465170,24);
manlo <= conv_std_logic_vector(249755484,28);
exponent <= conv_std_logic_vector(962,11);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(15952851,24);
manlo <= conv_std_logic_vector(133443390,28);
exponent <= conv_std_logic_vector(960,11);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(7304221,24);
manlo <= conv_std_logic_vector(236407020,28);
exponent <= conv_std_logic_vector(959,11);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(940915,24);
manlo <= conv_std_logic_vector(220198205,28);
exponent <= conv_std_logic_vector(958,11);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(9295329,24);
manlo <= conv_std_logic_vector(196124030,28);
exponent <= conv_std_logic_vector(956,11);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(2405891,24);
manlo <= conv_std_logic_vector(28613594,28);
exponent <= conv_std_logic_vector(955,11);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(11451066,24);
manlo <= conv_std_logic_vector(238698933,28);
exponent <= conv_std_logic_vector(953,11);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(3991993,24);
manlo <= conv_std_logic_vector(233279365,28);
exponent <= conv_std_logic_vector(952,11);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(13785045,24);
manlo <= conv_std_logic_vector(75368511,28);
exponent <= conv_std_logic_vector(950,11);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(5709239,24);
manlo <= conv_std_logic_vector(54173026,28);
exponent <= conv_std_logic_vector(949,11);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(16312002,24);
manlo <= conv_std_logic_vector(78993710,28);
exponent <= conv_std_logic_vector(947,11);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(7568470,24);
manlo <= conv_std_logic_vector(72422582,28);
exponent <= conv_std_logic_vector(946,11);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(1135338,24);
manlo <= conv_std_logic_vector(246889480,28);
exponent <= conv_std_logic_vector(945,11);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(9581426,24);
manlo <= conv_std_logic_vector(208117876,28);
exponent <= conv_std_logic_vector(943,11);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(2616389,24);
manlo <= conv_std_logic_vector(147217980,28);
exponent <= conv_std_logic_vector(942,11);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(11760819,24);
manlo <= conv_std_logic_vector(23037889,28);
exponent <= conv_std_logic_vector(940,11);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(4219896,24);
manlo <= conv_std_logic_vector(214481816,28);
exponent <= conv_std_logic_vector(939,11);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(14120408,24);
manlo <= conv_std_logic_vector(131761485,28);
exponent <= conv_std_logic_vector(937,11);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(5955985,24);
manlo <= conv_std_logic_vector(177821786,28);
exponent <= conv_std_logic_vector(936,11);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(16675094,24);
manlo <= conv_std_logic_vector(25356748,28);
exponent <= conv_std_logic_vector(934,11);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(7835618,24);
manlo <= conv_std_logic_vector(77011020,28);
exponent <= conv_std_logic_vector(933,11);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1331895,24);
manlo <= conv_std_logic_vector(119779026,28);
exponent <= conv_std_logic_vector(932,11);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(9870663,24);
manlo <= conv_std_logic_vector(52552908,28);
exponent <= conv_std_logic_vector(930,11);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(2829197,24);
manlo <= conv_std_logic_vector(218477336,28);
exponent <= conv_std_logic_vector(929,11);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(12073970,24);
manlo <= conv_std_logic_vector(61450731,28);
exponent <= conv_std_logic_vector(927,11);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(4450300,24);
manlo <= conv_std_logic_vector(143360086,28);
exponent <= conv_std_logic_vector(926,11);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(14459451,24);
manlo <= conv_std_logic_vector(182543396,28);
exponent <= conv_std_logic_vector(924,11);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(6205439,24);
manlo <= conv_std_logic_vector(188004913,28);
exponent <= conv_std_logic_vector(923,11);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(132477,24);
manlo <= conv_std_logic_vector(19160299,28);
exponent <= conv_std_logic_vector(922,11);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(8105697,24);
manlo <= conv_std_logic_vector(201304075,28);
exponent <= conv_std_logic_vector(920,11);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1530608,24);
manlo <= conv_std_logic_vector(217452229,28);
exponent <= conv_std_logic_vector(919,11);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(10163073,24);
manlo <= conv_std_logic_vector(118320126,28);
exponent <= conv_std_logic_vector(917,11);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(3044341,24);
manlo <= conv_std_logic_vector(66824260,28);
exponent <= conv_std_logic_vector(916,11);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(12390557,24);
manlo <= conv_std_logic_vector(165235674,28);
exponent <= conv_std_logic_vector(914,11);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(4683232,24);
manlo <= conv_std_logic_vector(138461149,28);
exponent <= conv_std_logic_vector(913,11);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(14802215,24);
manlo <= conv_std_logic_vector(61508170,28);
exponent <= conv_std_logic_vector(911,11);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(6457631,24);
manlo <= conv_std_logic_vector(7025744,28);
exponent <= conv_std_logic_vector(910,11);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(318029,24);
manlo <= conv_std_logic_vector(21309721,28);
exponent <= conv_std_logic_vector(909,11);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(8378740,24);
manlo <= conv_std_logic_vector(221720132,28);
exponent <= conv_std_logic_vector(907,11);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1731502,24);
manlo <= conv_std_logic_vector(182144977,28);
exponent <= conv_std_logic_vector(906,11);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(10458692,24);
manlo <= conv_std_logic_vector(90475423,28);
exponent <= conv_std_logic_vector(904,11);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(3261845,24);
manlo <= conv_std_logic_vector(128220642,28);
exponent <= conv_std_logic_vector(903,11);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(12710618,24);
manlo <= conv_std_logic_vector(255552070,28);
exponent <= conv_std_logic_vector(901,11);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(4918720,24);
manlo <= conv_std_logic_vector(130727832,28);
exponent <= conv_std_logic_vector(900,11);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(15148739,24);
manlo <= conv_std_logic_vector(258265342,28);
exponent <= conv_std_logic_vector(898,11);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(6712589,24);
manlo <= conv_std_logic_vector(181573149,28);
exponent <= conv_std_logic_vector(897,11);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(505617,24);
manlo <= conv_std_logic_vector(45883390,28);
exponent <= conv_std_logic_vector(896,11);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(8654780,24);
manlo <= conv_std_logic_vector(9428106,28);
exponent <= conv_std_logic_vector(894,11);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1934600,24);
manlo <= conv_std_logic_vector(262677610,28);
exponent <= conv_std_logic_vector(893,11);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(10757555,24);
manlo <= conv_std_logic_vector(25094861,28);
exponent <= conv_std_logic_vector(891,11);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(3481736,24);
manlo <= conv_std_logic_vector(108799619,28);
exponent <= conv_std_logic_vector(890,11);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(13034192,24);
manlo <= conv_std_logic_vector(96190464,28);
exponent <= conv_std_logic_vector(888,11);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(5156792,24);
manlo <= conv_std_logic_vector(132821234,28);
exponent <= conv_std_logic_vector(887,11);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(15499067,24);
manlo <= conv_std_logic_vector(40497064,28);
exponent <= conv_std_logic_vector(885,11);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(6970346,24);
manlo <= conv_std_logic_vector(4633646,28);
exponent <= conv_std_logic_vector(884,11);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(695263,24);
manlo <= conv_std_logic_vector(184734272,28);
exponent <= conv_std_logic_vector(883,11);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(8933848,24);
manlo <= conv_std_logic_vector(68258056,28);
exponent <= conv_std_logic_vector(881,11);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(2139927,24);
manlo <= conv_std_logic_vector(241478077,28);
exponent <= conv_std_logic_vector(880,11);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(11059697,24);
manlo <= conv_std_logic_vector(81964893,28);
exponent <= conv_std_logic_vector(878,11);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(3704040,24);
manlo <= conv_std_logic_vector(59435624,28);
exponent <= conv_std_logic_vector(877,11);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(13361316,24);
manlo <= conv_std_logic_vector(100097713,28);
exponent <= conv_std_logic_vector(875,11);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(5397476,24);
manlo <= conv_std_logic_vector(240017437,28);
exponent <= conv_std_logic_vector(874,11);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(15853238,24);
manlo <= conv_std_logic_vector(139632179,28);
exponent <= conv_std_logic_vector(872,11);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(7230930,24);
manlo <= conv_std_logic_vector(200816807,28);
exponent <= conv_std_logic_vector(871,11);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(886991,24);
manlo <= conv_std_logic_vector(58654941,28);
exponent <= conv_std_logic_vector(870,11);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(9215978,24);
manlo <= conv_std_logic_vector(193575030,28);
exponent <= conv_std_logic_vector(868,11);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(2347507,24);
manlo <= conv_std_logic_vector(240661664,28);
exponent <= conv_std_logic_vector(867,11);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(11365154,24);
manlo <= conv_std_logic_vector(257284930,28);
exponent <= conv_std_logic_vector(865,11);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(3928783,24);
manlo <= conv_std_logic_vector(108146246,28);
exponent <= conv_std_logic_vector(864,11);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(13692029,24);
manlo <= conv_std_logic_vector(256867284,28);
exponent <= conv_std_logic_vector(862,11);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(5640802,24);
manlo <= conv_std_logic_vector(94243132,28);
exponent <= conv_std_logic_vector(861,11);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(16211296,24);
manlo <= conv_std_logic_vector(67825654,28);
exponent <= conv_std_logic_vector(859,11);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(7494374,24);
manlo <= conv_std_logic_vector(242982196,28);
exponent <= conv_std_logic_vector(858,11);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1080822,24);
manlo <= conv_std_logic_vector(160277009,28);
exponent <= conv_std_logic_vector(857,11);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(9501205,24);
manlo <= conv_std_logic_vector(10212621,28);
exponent <= conv_std_logic_vector(855,11);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2557365,24);
manlo <= conv_std_logic_vector(185941944,28);
exponent <= conv_std_logic_vector(854,11);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(11673964,24);
manlo <= conv_std_logic_vector(116382402,28);
exponent <= conv_std_logic_vector(852,11);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(4155992,24);
manlo <= conv_std_logic_vector(192503267,28);
exponent <= conv_std_logic_vector(851,11);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(14026372,24);
manlo <= conv_std_logic_vector(133984890,28);
exponent <= conv_std_logic_vector(849,11);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(5886797,24);
manlo <= conv_std_logic_vector(227169396,28);
exponent <= conv_std_logic_vector(848,11);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(16573282,24);
manlo <= conv_std_logic_vector(266790864,28);
exponent <= conv_std_logic_vector(846,11);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(7760709,24);
manlo <= conv_std_logic_vector(232279832,28);
exponent <= conv_std_logic_vector(845,11);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1276780,24);
manlo <= conv_std_logic_vector(244188460,28);
exponent <= conv_std_logic_vector(844,11);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(9789561,24);
manlo <= conv_std_logic_vector(47289108,28);
exponent <= conv_std_logic_vector(842,11);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2769526,24);
manlo <= conv_std_logic_vector(75856665,28);
exponent <= conv_std_logic_vector(841,11);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(11986162,24);
manlo <= conv_std_logic_vector(137053172,28);
exponent <= conv_std_logic_vector(839,11);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(4385695,24);
manlo <= conv_std_logic_vector(60488459,28);
exponent <= conv_std_logic_vector(838,11);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(14364383,24);
manlo <= conv_std_logic_vector(220265084,28);
exponent <= conv_std_logic_vector(836,11);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(6135492,24);
manlo <= conv_std_logic_vector(182090040,28);
exponent <= conv_std_logic_vector(835,11);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(81012,24);
manlo <= conv_std_logic_vector(249275143,28);
exponent <= conv_std_logic_vector(834,11);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(8029967,24);
manlo <= conv_std_logic_vector(93846972,28);
exponent <= conv_std_logic_vector(832,11);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(1474889,24);
manlo <= conv_std_logic_vector(132978099,28);
exponent <= conv_std_logic_vector(831,11);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(10081081,24);
manlo <= conv_std_logic_vector(128680817,28);
exponent <= conv_std_logic_vector(829,11);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2984014,24);
manlo <= conv_std_logic_vector(251002315,28);
exponent <= conv_std_logic_vector(828,11);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(12301786,24);
manlo <= conv_std_logic_vector(100124707,28);
exponent <= conv_std_logic_vector(826,11);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(4617918,24);
manlo <= conv_std_logic_vector(76665129,28);
exponent <= conv_std_logic_vector(825,11);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(14706104,24);
manlo <= conv_std_logic_vector(48076192,28);
exponent <= conv_std_logic_vector(823,11);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(6386916,24);
manlo <= conv_std_logic_vector(125471070,28);
exponent <= conv_std_logic_vector(822,11);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(266000,24);
manlo <= conv_std_logic_vector(57624675,28);
exponent <= conv_std_logic_vector(821,11);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(8302179,24);
manlo <= conv_std_logic_vector(114693198,28);
exponent <= conv_std_logic_vector(819,11);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(1675171,24);
manlo <= conv_std_logic_vector(254852645,28);
exponent <= conv_std_logic_vector(818,11);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(10375800,24);
manlo <= conv_std_logic_vector(179426511,28);
exponent <= conv_std_logic_vector(816,11);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(3200857,24);
manlo <= conv_std_logic_vector(52664716,28);
exponent <= conv_std_logic_vector(815,11);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(12620873,24);
manlo <= conv_std_logic_vector(164386702,28);
exponent <= conv_std_logic_vector(813,11);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(4852689,24);
manlo <= conv_std_logic_vector(149310968,28);
exponent <= conv_std_logic_vector(812,11);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(15051574,24);
manlo <= conv_std_logic_vector(73675604,28);
exponent <= conv_std_logic_vector(810,11);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(6641099,24);
manlo <= conv_std_logic_vector(42591307,28);
exponent <= conv_std_logic_vector(809,11);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(453017,24);
manlo <= conv_std_logic_vector(104016801,28);
exponent <= conv_std_logic_vector(808,11);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(8577378,24);
manlo <= conv_std_logic_vector(139419332,28);
exponent <= conv_std_logic_vector(806,11);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(1877652,24);
manlo <= conv_std_logic_vector(33778363,28);
exponent <= conv_std_logic_vector(805,11);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(10673753,24);
manlo <= conv_std_logic_vector(226837452,28);
exponent <= conv_std_logic_vector(803,11);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(3420078,24);
manlo <= conv_std_logic_vector(239554874,28);
exponent <= conv_std_logic_vector(802,11);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(12943462,24);
manlo <= conv_std_logic_vector(62486566,28);
exponent <= conv_std_logic_vector(800,11);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(5090036,24);
manlo <= conv_std_logic_vector(268173235,28);
exponent <= conv_std_logic_vector(799,11);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(15400835,24);
manlo <= conv_std_logic_vector(67898261,28);
exponent <= conv_std_logic_vector(797,11);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(6898071,24);
manlo <= conv_std_logic_vector(6935226,28);
exponent <= conv_std_logic_vector(796,11);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(642086,24);
manlo <= conv_std_logic_vector(193616024,28);
exponent <= conv_std_logic_vector(795,11);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(8855597,24);
manlo <= conv_std_logic_vector(108124901,28);
exponent <= conv_std_logic_vector(793,11);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2082354,24);
manlo <= conv_std_logic_vector(37727361,28);
exponent <= conv_std_logic_vector(792,11);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(10974976,24);
manlo <= conv_std_logic_vector(133184200,28);
exponent <= conv_std_logic_vector(790,11);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(3641706,24);
manlo <= conv_std_logic_vector(35844662,28);
exponent <= conv_std_logic_vector(789,11);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(13269590,24);
manlo <= conv_std_logic_vector(175886280,28);
exponent <= conv_std_logic_vector(787,11);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(5329988,24);
manlo <= conv_std_logic_vector(236927280,28);
exponent <= conv_std_logic_vector(786,11);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(15753928,24);
manlo <= conv_std_logic_vector(191213976,28);
exponent <= conv_std_logic_vector(784,11);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(7157862,24);
manlo <= conv_std_logic_vector(181160855,28);
exponent <= conv_std_logic_vector(783,11);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(833230,24);
manlo <= conv_std_logic_vector(197197075,28);
exponent <= conv_std_logic_vector(782,11);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(9136869,24);
manlo <= conv_std_logic_vector(57456047,28);
exponent <= conv_std_logic_vector(780,11);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2289302,24);
manlo <= conv_std_logic_vector(100400411,28);
exponent <= conv_std_logic_vector(779,11);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(11279504,24);
manlo <= conv_std_logic_vector(133702078,28);
exponent <= conv_std_logic_vector(777,11);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3865765,24);
manlo <= conv_std_logic_vector(84791606,28);
exponent <= conv_std_logic_vector(776,11);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(13599297,24);
manlo <= conv_std_logic_vector(193913492,28);
exponent <= conv_std_logic_vector(774,11);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(5572573,24);
manlo <= conv_std_logic_vector(210951234,28);
exponent <= conv_std_logic_vector(773,11);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(16110896,24);
manlo <= conv_std_logic_vector(189751005,28);
exponent <= conv_std_logic_vector(771,11);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(7420505,24);
manlo <= conv_std_logic_vector(12771910,28);
exponent <= conv_std_logic_vector(770,11);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(1026472,24);
manlo <= conv_std_logic_vector(51864863,28);
exponent <= conv_std_logic_vector(769,11);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(9421227,24);
manlo <= conv_std_logic_vector(121664951,28);
exponent <= conv_std_logic_vector(767,11);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2498521,24);
manlo <= conv_std_logic_vector(127312793,28);
exponent <= conv_std_logic_vector(766,11);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(11587374,24);
manlo <= conv_std_logic_vector(32431827,28);
exponent <= conv_std_logic_vector(764,11);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(4092283,24);
manlo <= conv_std_logic_vector(33663701,28);
exponent <= conv_std_logic_vector(763,11);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(13932622,24);
manlo <= conv_std_logic_vector(188745186,28);
exponent <= conv_std_logic_vector(761,11);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(5817820,24);
manlo <= conv_std_logic_vector(161368804,28);
exponent <= conv_std_logic_vector(760,11);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(16471781,24);
manlo <= conv_std_logic_vector(201946939,28);
exponent <= conv_std_logic_vector(758,11);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(7686029,24);
manlo <= conv_std_logic_vector(114155240,28);
exponent <= conv_std_logic_vector(757,11);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(1221834,24);
manlo <= conv_std_logic_vector(30217784,28);
exponent <= conv_std_logic_vector(756,11);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(9708705,24);
manlo <= conv_std_logic_vector(265245416,28);
exponent <= conv_std_logic_vector(754,11);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2710036,24);
manlo <= conv_std_logic_vector(96582323,28);
exponent <= conv_std_logic_vector(753,11);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(11898622,24);
manlo <= conv_std_logic_vector(8685564,28);
exponent <= conv_std_logic_vector(751,11);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(4321286,24);
manlo <= conv_std_logic_vector(145205332,28);
exponent <= conv_std_logic_vector(750,11);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(14269605,24);
manlo <= conv_std_logic_vector(79792252,28);
exponent <= conv_std_logic_vector(748,11);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(6065758,24);
manlo <= conv_std_logic_vector(144408455,28);
exponent <= conv_std_logic_vector(747,11);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(29705,24);
manlo <= conv_std_logic_vector(111518540,28);
exponent <= conv_std_logic_vector(746,11);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(7954467,24);
manlo <= conv_std_logic_vector(116097284,28);
exponent <= conv_std_logic_vector(744,11);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(1419339,24);
manlo <= conv_std_logic_vector(204212637,28);
exponent <= conv_std_logic_vector(743,11);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(9999339,24);
manlo <= conv_std_logic_vector(15580207,28);
exponent <= conv_std_logic_vector(741,11);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(2923872,24);
manlo <= conv_std_logic_vector(59726033,28);
exponent <= conv_std_logic_vector(740,11);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(12213285,24);
manlo <= conv_std_logic_vector(81348195,28);
exponent <= conv_std_logic_vector(738,11);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(4552802,24);
manlo <= conv_std_logic_vector(224758002,28);
exponent <= conv_std_logic_vector(737,11);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(14610285,24);
manlo <= conv_std_logic_vector(171839647,28);
exponent <= conv_std_logic_vector(735,11);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(6316417,24);
manlo <= conv_std_logic_vector(33901818,28);
exponent <= conv_std_logic_vector(734,11);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(214129,24);
manlo <= conv_std_logic_vector(187432044,28);
exponent <= conv_std_logic_vector(733,11);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(8225851,24);
manlo <= conv_std_logic_vector(10972428,28);
exponent <= conv_std_logic_vector(731,11);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(1619012,24);
manlo <= conv_std_logic_vector(177473085,28);
exponent <= conv_std_logic_vector(730,11);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(10293161,24);
manlo <= conv_std_logic_vector(74648462,28);
exponent <= conv_std_logic_vector(728,11);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3140054,24);
manlo <= conv_std_logic_vector(142465582,28);
exponent <= conv_std_logic_vector(727,11);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(12531401,24);
manlo <= conv_std_logic_vector(110062606,28);
exponent <= conv_std_logic_vector(725,11);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(4786859,24);
manlo <= conv_std_logic_vector(158003247,28);
exponent <= conv_std_logic_vector(724,11);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(14954704,24);
manlo <= conv_std_logic_vector(82587752,28);
exponent <= conv_std_logic_vector(722,11);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(6569826,24);
manlo <= conv_std_logic_vector(59098716,28);
exponent <= conv_std_logic_vector(721,11);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(400577,24);
manlo <= conv_std_logic_vector(185198176,28);
exponent <= conv_std_logic_vector(720,11);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(8500212,24);
manlo <= conv_std_logic_vector(153765179,28);
exponent <= conv_std_logic_vector(718,11);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(1820876,24);
manlo <= conv_std_logic_vector(159783545,28);
exponent <= conv_std_logic_vector(717,11);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(10590207,24);
manlo <= conv_std_logic_vector(172648734,28);
exponent <= conv_std_logic_vector(715,11);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3358609,24);
manlo <= conv_std_logic_vector(8670608,28);
exponent <= conv_std_logic_vector(714,11);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(12853008,24);
manlo <= conv_std_logic_vector(64863304,28);
exponent <= conv_std_logic_vector(712,11);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(5023484,24);
manlo <= conv_std_logic_vector(180279682,28);
exponent <= conv_std_logic_vector(711,11);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(15302902,24);
manlo <= conv_std_logic_vector(86126918,28);
exponent <= conv_std_logic_vector(709,11);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(6826016,24);
manlo <= conv_std_logic_vector(315265,28);
exponent <= conv_std_logic_vector(708,11);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(589071,24);
manlo <= conv_std_logic_vector(160219440,28);
exponent <= conv_std_logic_vector(707,11);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(8777584,24);
manlo <= conv_std_logic_vector(189361726,28);
exponent <= conv_std_logic_vector(705,11);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(2024955,24);
manlo <= conv_std_logic_vector(162543151,28);
exponent <= conv_std_logic_vector(704,11);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(10890513,24);
manlo <= conv_std_logic_vector(142859647,28);
exponent <= conv_std_logic_vector(702,11);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3579561,24);
manlo <= conv_std_logic_vector(203359193,28);
exponent <= conv_std_logic_vector(701,11);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(13178144,24);
manlo <= conv_std_logic_vector(27387766,28);
exponent <= conv_std_logic_vector(699,11);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(5262706,24);
manlo <= conv_std_logic_vector(72167880,28);
exponent <= conv_std_logic_vector(698,11);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(15654921,24);
manlo <= conv_std_logic_vector(40507130,28);
exponent <= conv_std_logic_vector(696,11);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(7085016,24);
manlo <= conv_std_logic_vector(263640644,28);
exponent <= conv_std_logic_vector(695,11);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(779633,24);
manlo <= conv_std_logic_vector(233308885,28);
exponent <= conv_std_logic_vector(694,11);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(9058000,24);
manlo <= conv_std_logic_vector(127336500,28);
exponent <= conv_std_logic_vector(692,11);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(2231273,24);
manlo <= conv_std_logic_vector(267969878,28);
exponent <= conv_std_logic_vector(691,11);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(11194114,24);
manlo <= conv_std_logic_vector(191206462,28);
exponent <= conv_std_logic_vector(689,11);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3802939,24);
manlo <= conv_std_logic_vector(6046440,28);
exponent <= conv_std_logic_vector(688,11);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(13506847,24);
manlo <= conv_std_logic_vector(192101060,28);
exponent <= conv_std_logic_vector(686,11);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(5504552,24);
manlo <= conv_std_logic_vector(234133234,28);
exponent <= conv_std_logic_vector(685,11);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(16010802,24);
manlo <= conv_std_logic_vector(194370273,28);
exponent <= conv_std_logic_vector(683,11);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(7346860,24);
manlo <= conv_std_logic_vector(2864438,28);
exponent <= conv_std_logic_vector(682,11);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(972287,24);
manlo <= conv_std_logic_vector(54536955,28);
exponent <= conv_std_logic_vector(681,11);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(9341493,24);
manlo <= conv_std_logic_vector(74572905,28);
exponent <= conv_std_logic_vector(679,11);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(2439856,24);
manlo <= conv_std_logic_vector(93006730,28);
exponent <= conv_std_logic_vector(678,11);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(11501047,24);
manlo <= conv_std_logic_vector(92098230,28);
exponent <= conv_std_logic_vector(676,11);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4028767,24);
manlo <= conv_std_logic_vector(115940390,28);
exponent <= conv_std_logic_vector(675,11);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(13839158,24);
manlo <= conv_std_logic_vector(62227559,28);
exponent <= conv_std_logic_vector(673,11);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(5749053,24);
manlo <= conv_std_logic_vector(76824142,28);
exponent <= conv_std_logic_vector(672,11);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(16370589,24);
manlo <= conv_std_logic_vector(114548734,28);
exponent <= conv_std_logic_vector(670,11);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(7611576,24);
manlo <= conv_std_logic_vector(73252889,28);
exponent <= conv_std_logic_vector(669,11);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(1167054,24);
manlo <= conv_std_logic_vector(146134399,28);
exponent <= conv_std_logic_vector(668,11);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(9628096,24);
manlo <= conv_std_logic_vector(236331104,28);
exponent <= conv_std_logic_vector(666,11);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(2650727,24);
manlo <= conv_std_logic_vector(132284651,28);
exponent <= conv_std_logic_vector(665,11);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(11811347,24);
manlo <= conv_std_logic_vector(263325685,28);
exponent <= conv_std_logic_vector(663,11);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4257073,24);
manlo <= conv_std_logic_vector(236873507,28);
exponent <= conv_std_logic_vector(662,11);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(14175115,24);
manlo <= conv_std_logic_vector(61615323,28);
exponent <= conv_std_logic_vector(660,11);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(5996236,24);
manlo <= conv_std_logic_vector(169476567,28);
exponent <= conv_std_logic_vector(659,11);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(16734324,24);
manlo <= conv_std_logic_vector(29597837,28);
exponent <= conv_std_logic_vector(657,11);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(7879197,24);
manlo <= conv_std_logic_vector(79755942,28);
exponent <= conv_std_logic_vector(656,11);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(1363959,24);
manlo <= conv_std_logic_vector(24177677,28);
exponent <= conv_std_logic_vector(655,11);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(9917845,24);
manlo <= conv_std_logic_vector(112021148,28);
exponent <= conv_std_logic_vector(653,11);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(2863912,24);
manlo <= conv_std_logic_vector(148304045,28);
exponent <= conv_std_logic_vector(652,11);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(12125053,24);
manlo <= conv_std_logic_vector(156617262,28);
exponent <= conv_std_logic_vector(650,11);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4487885,24);
manlo <= conv_std_logic_vector(151904422,28);
exponent <= conv_std_logic_vector(649,11);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(14514758,24);
manlo <= conv_std_logic_vector(193824214,28);
exponent <= conv_std_logic_vector(647,11);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(6246132,24);
manlo <= conv_std_logic_vector(93361418,28);
exponent <= conv_std_logic_vector(646,11);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(162417,24);
manlo <= conv_std_logic_vector(12929741,28);
exponent <= conv_std_logic_vector(645,11);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(8149754,24);
manlo <= conv_std_logic_vector(257063442,28);
exponent <= conv_std_logic_vector(643,11);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(1563024,24);
manlo <= conv_std_logic_vector(78378796,28);
exponent <= conv_std_logic_vector(642,11);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(10210773,24);
manlo <= conv_std_logic_vector(106907060,28);
exponent <= conv_std_logic_vector(640,11);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(3079436,24);
manlo <= conv_std_logic_vector(245979562,28);
exponent <= conv_std_logic_vector(639,11);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(12442201,24);
manlo <= conv_std_logic_vector(137868870,28);
exponent <= conv_std_logic_vector(637,11);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4721229,24);
manlo <= conv_std_logic_vector(261058204,28);
exponent <= conv_std_logic_vector(636,11);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(14858129,24);
manlo <= conv_std_logic_vector(43405174,28);
exponent <= conv_std_logic_vector(634,11);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(6498770,24);
manlo <= conv_std_logic_vector(53338521,28);
exponent <= conv_std_logic_vector(633,11);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(348297,24);
manlo <= conv_std_logic_vector(158641329,28);
exponent <= conv_std_logic_vector(632,11);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(8423281,24);
manlo <= conv_std_logic_vector(128446906,28);
exponent <= conv_std_logic_vector(630,11);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(1764273,24);
manlo <= conv_std_logic_vector(230657816,28);
exponent <= conv_std_logic_vector(629,11);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(10506915,24);
manlo <= conv_std_logic_vector(191032874,28);
exponent <= conv_std_logic_vector(627,11);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(3297326,24);
manlo <= conv_std_logic_vector(68145509,28);
exponent <= conv_std_logic_vector(626,11);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(12762829,24);
manlo <= conv_std_logic_vector(146161159,28);
exponent <= conv_std_logic_vector(624,11);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4957134,24);
manlo <= conv_std_logic_vector(240027976,28);
exponent <= conv_std_logic_vector(623,11);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(15205267,24);
manlo <= conv_std_logic_vector(119370809,28);
exponent <= conv_std_logic_vector(621,11);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(6754180,24);
manlo <= conv_std_logic_vector(73501816,28);
exponent <= conv_std_logic_vector(620,11);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(536217,24);
manlo <= conv_std_logic_vector(220758658,28);
exponent <= conv_std_logic_vector(619,11);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(8699809,24);
manlo <= conv_std_logic_vector(117402516,28);
exponent <= conv_std_logic_vector(617,11);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(1967731,24);
manlo <= conv_std_logic_vector(204336317,28);
exponent <= conv_std_logic_vector(616,11);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(10806307,24);
manlo <= conv_std_logic_vector(168773516,28);
exponent <= conv_std_logic_vector(614,11);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(3517606,24);
manlo <= conv_std_logic_vector(138553816,28);
exponent <= conv_std_logic_vector(613,11);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(13086975,24);
manlo <= conv_std_logic_vector(231838082,28);
exponent <= conv_std_logic_vector(611,11);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5195628,24);
manlo <= conv_std_logic_vector(114805284,28);
exponent <= conv_std_logic_vector(610,11);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(15556214,24);
manlo <= conv_std_logic_vector(245890169,28);
exponent <= conv_std_logic_vector(608,11);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(7012392,24);
manlo <= conv_std_logic_vector(266576824,28);
exponent <= conv_std_logic_vector(607,11);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(726200,24);
manlo <= conv_std_logic_vector(33318175,28);
exponent <= conv_std_logic_vector(606,11);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(8979371,24);
manlo <= conv_std_logic_vector(206515377,28);
exponent <= conv_std_logic_vector(604,11);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(2173422,24);
manlo <= conv_std_logic_vector(61774637,28);
exponent <= conv_std_logic_vector(603,11);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(11108984,24);
manlo <= conv_std_logic_vector(216833386,28);
exponent <= conv_std_logic_vector(601,11);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(3740303,24);
manlo <= conv_std_logic_vector(252090990,28);
exponent <= conv_std_logic_vector(600,11);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(13414679,24);
manlo <= conv_std_logic_vector(20856890,28);
exponent <= conv_std_logic_vector(598,11);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5436738,24);
manlo <= conv_std_logic_vector(262578382,28);
exponent <= conv_std_logic_vector(597,11);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(15911013,24);
manlo <= conv_std_logic_vector(100481506,28);
exponent <= conv_std_logic_vector(595,11);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(7273439,24);
manlo <= conv_std_logic_vector(29586843,28);
exponent <= conv_std_logic_vector(594,11);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(918267,24);
manlo <= conv_std_logic_vector(33154287,28);
exponent <= conv_std_logic_vector(593,11);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(9262001,24);
manlo <= conv_std_logic_vector(206947959,28);
exponent <= conv_std_logic_vector(591,11);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(2381369,24);
manlo <= conv_std_logic_vector(205146615,28);
exponent <= conv_std_logic_vector(590,11);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(11414983,24);
manlo <= conv_std_logic_vector(80080029,28);
exponent <= conv_std_logic_vector(588,11);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(3965445,24);
manlo <= conv_std_logic_vector(12487826,28);
exponent <= conv_std_logic_vector(587,11);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(13745978,24);
manlo <= conv_std_logic_vector(58199715,28);
exponent <= conv_std_logic_vector(585,11);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5680495,24);
manlo <= conv_std_logic_vector(70463110,28);
exponent <= conv_std_logic_vector(584,11);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(16269705,24);
manlo <= conv_std_logic_vector(20654997,28);
exponent <= conv_std_logic_vector(582,11);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(7537349,24);
manlo <= conv_std_logic_vector(192319832,28);
exponent <= conv_std_logic_vector(581,11);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(1112441,24);
manlo <= conv_std_logic_vector(186880957,28);
exponent <= conv_std_logic_vector(580,11);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(9547733,24);
manlo <= conv_std_logic_vector(27940083,28);
exponent <= conv_std_logic_vector(578,11);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(2591599,24);
manlo <= conv_std_logic_vector(35045549,28);
exponent <= conv_std_logic_vector(577,11);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(11724339,24);
manlo <= conv_std_logic_vector(146438512,28);
exponent <= conv_std_logic_vector(575,11);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4193056,24);
manlo <= conv_std_logic_vector(175344679,28);
exponent <= conv_std_logic_vector(574,11);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(14080912,24);
manlo <= conv_std_logic_vector(198508677,28);
exponent <= conv_std_logic_vector(572,11);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5926926,24);
manlo <= conv_std_logic_vector(83904648,28);
exponent <= conv_std_logic_vector(571,11);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(16632332,24);
manlo <= conv_std_logic_vector(199957404,28);
exponent <= conv_std_logic_vector(569,11);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(7804156,24);
manlo <= conv_std_logic_vector(65532420,28);
exponent <= conv_std_logic_vector(568,11);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(1308746,24);
manlo <= conv_std_logic_vector(260058525,28);
exponent <= conv_std_logic_vector(567,11);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(9836599,24);
manlo <= conv_std_logic_vector(214756046,28);
exponent <= conv_std_logic_vector(565,11);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(2804135,24);
manlo <= conv_std_logic_vector(98759674,28);
exponent <= conv_std_logic_vector(564,11);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(12037090,24);
manlo <= conv_std_logic_vector(105879341,28);
exponent <= conv_std_logic_vector(562,11);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(4423165,24);
manlo <= conv_std_logic_vector(233069674,28);
exponent <= conv_std_logic_vector(561,11);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(14419522,24);
manlo <= conv_std_logic_vector(144218340,28);
exponent <= conv_std_logic_vector(559,11);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6176061,24);
manlo <= conv_std_logic_vector(128557517,28);
exponent <= conv_std_logic_vector(558,11);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(110861,24);
manlo <= conv_std_logic_vector(210451229,28);
exponent <= conv_std_logic_vector(557,11);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(8073890,24);
manlo <= conv_std_logic_vector(126309403,28);
exponent <= conv_std_logic_vector(555,11);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(1507206,24);
manlo <= conv_std_logic_vector(86368556,28);
exponent <= conv_std_logic_vector(554,11);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(10128636,24);
manlo <= conv_std_logic_vector(70724454,28);
exponent <= conv_std_logic_vector(552,11);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(3019003,24);
manlo <= conv_std_logic_vector(212024500,28);
exponent <= conv_std_logic_vector(551,11);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(12353273,24);
manlo <= conv_std_logic_vector(25338267,28);
exponent <= conv_std_logic_vector(549,11);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(4655800,24);
manlo <= conv_std_logic_vector(26358145,28);
exponent <= conv_std_logic_vector(548,11);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(14761847,24);
manlo <= conv_std_logic_vector(252137457,28);
exponent <= conv_std_logic_vector(546,11);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6427930,24);
manlo <= conv_std_logic_vector(116530320,28);
exponent <= conv_std_logic_vector(545,11);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(296176,24);
manlo <= conv_std_logic_vector(162393576,28);
exponent <= conv_std_logic_vector(544,11);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(8346584,24);
manlo <= conv_std_logic_vector(140031506,28);
exponent <= conv_std_logic_vector(542,11);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(1707843,24);
manlo <= conv_std_logic_vector(105232250,28);
exponent <= conv_std_logic_vector(541,11);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(10423877,24);
manlo <= conv_std_logic_vector(74257288,28);
exponent <= conv_std_logic_vector(539,11);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(3236229,24);
manlo <= conv_std_logic_vector(265138481,28);
exponent <= conv_std_logic_vector(538,11);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(12672925,24);
manlo <= conv_std_logic_vector(81471742,28);
exponent <= conv_std_logic_vector(536,11);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(4890987,24);
manlo <= conv_std_logic_vector(13504322,28);
exponent <= conv_std_logic_vector(535,11);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(15107929,24);
manlo <= conv_std_logic_vector(192561070,28);
exponent <= conv_std_logic_vector(533,11);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6682563,24);
manlo <= conv_std_logic_vector(47334412,28);
exponent <= conv_std_logic_vector(532,11);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(483524,24);
manlo <= conv_std_logic_vector(243414774,28);
exponent <= conv_std_logic_vector(531,11);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(8622270,24);
manlo <= conv_std_logic_vector(235144322,28);
exponent <= conv_std_logic_vector(529,11);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(1910682,24);
manlo <= conv_std_logic_vector(20388866,28);
exponent <= conv_std_logic_vector(528,11);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(10722358,24);
manlo <= conv_std_logic_vector(913747,28);
exponent <= conv_std_logic_vector(526,11);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(3455839,24);
manlo <= conv_std_logic_vector(223781205,28);
exponent <= conv_std_logic_vector(525,11);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(12996085,24);
manlo <= conv_std_logic_vector(24989984,28);
exponent <= conv_std_logic_vector(523,11);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5128754,24);
manlo <= conv_std_logic_vector(197545335,28);
exponent <= conv_std_logic_vector(522,11);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(15457809,24);
manlo <= conv_std_logic_vector(24315860,28);
exponent <= conv_std_logic_vector(520,11);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6939990,24);
manlo <= conv_std_logic_vector(8842978,28);
exponent <= conv_std_logic_vector(519,11);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(672929,24);
manlo <= conv_std_logic_vector(830489,28);
exponent <= conv_std_logic_vector(518,11);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(8900982,24);
manlo <= conv_std_logic_vector(98890321,28);
exponent <= conv_std_logic_vector(516,11);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(2115746,24);
manlo <= conv_std_logic_vector(142837003,28);
exponent <= conv_std_logic_vector(515,11);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(11024113,24);
manlo <= conv_std_logic_vector(266701758,28);
exponent <= conv_std_logic_vector(513,11);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(3677859,24);
manlo <= conv_std_logic_vector(129840563,28);
exponent <= conv_std_logic_vector(512,11);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(13322790,24);
manlo <= conv_std_logic_vector(255615990,28);
exponent <= conv_std_logic_vector(510,11);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5369131,24);
manlo <= conv_std_logic_vector(127156783,28);
exponent <= conv_std_logic_vector(509,11);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(15811527,24);
manlo <= conv_std_logic_vector(196077973,28);
exponent <= conv_std_logic_vector(507,11);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7200241,24);
manlo <= conv_std_logic_vector(178260644,28);
exponent <= conv_std_logic_vector(506,11);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(864411,24);
manlo <= conv_std_logic_vector(121424610,28);
exponent <= conv_std_logic_vector(505,11);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(9182752,24);
manlo <= conv_std_logic_vector(52100447,28);
exponent <= conv_std_logic_vector(503,11);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(2323061,24);
manlo <= conv_std_logic_vector(49429697,28);
exponent <= conv_std_logic_vector(502,11);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(11329181,24);
manlo <= conv_std_logic_vector(50166358,28);
exponent <= conv_std_logic_vector(500,11);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(3902315,24);
manlo <= conv_std_logic_vector(102248985,28);
exponent <= conv_std_logic_vector(499,11);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(13653081,24);
manlo <= conv_std_logic_vector(212703346,28);
exponent <= conv_std_logic_vector(497,11);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5612145,24);
manlo <= conv_std_logic_vector(239735388,28);
exponent <= conv_std_logic_vector(496,11);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(16169127,24);
manlo <= conv_std_logic_vector(205528034,28);
exponent <= conv_std_logic_vector(494,11);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7463349,24);
manlo <= conv_std_logic_vector(17797346,28);
exponent <= conv_std_logic_vector(493,11);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(1057995,24);
manlo <= conv_std_logic_vector(16251369,28);
exponent <= conv_std_logic_vector(492,11);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(9467613,24);
manlo <= conv_std_logic_vector(244949044,28);
exponent <= conv_std_logic_vector(490,11);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(2532650,24);
manlo <= conv_std_logic_vector(194268012,28);
exponent <= conv_std_logic_vector(489,11);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(11637595,24);
manlo <= conv_std_logic_vector(246328755,28);
exponent <= conv_std_logic_vector(487,11);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(4129234,24);
manlo <= conv_std_logic_vector(69393408,28);
exponent <= conv_std_logic_vector(486,11);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(13986996,24);
manlo <= conv_std_logic_vector(255528468,28);
exponent <= conv_std_logic_vector(484,11);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5857826,24);
manlo <= conv_std_logic_vector(251701587,28);
exponent <= conv_std_logic_vector(483,11);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(16530651,24);
manlo <= conv_std_logic_vector(211310789,28);
exponent <= conv_std_logic_vector(481,11);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7729343,24);
manlo <= conv_std_logic_vector(154707528,28);
exponent <= conv_std_logic_vector(480,11);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(1253702,24);
manlo <= conv_std_logic_vector(237283577,28);
exponent <= conv_std_logic_vector(479,11);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(9755601,24);
manlo <= conv_std_logic_vector(121155884,28);
exponent <= conv_std_logic_vector(477,11);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(2744540,24);
manlo <= conv_std_logic_vector(30442277,28);
exponent <= conv_std_logic_vector(476,11);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(11949394,24);
manlo <= conv_std_logic_vector(246622503,28);
exponent <= conv_std_logic_vector(474,11);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(4358643,24);
manlo <= conv_std_logic_vector(38405425,28);
exponent <= conv_std_logic_vector(473,11);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(14324576,24);
manlo <= conv_std_logic_vector(53935566,28);
exponent <= conv_std_logic_vector(471,11);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6106203,24);
manlo <= conv_std_logic_vector(233166714,28);
exponent <= conv_std_logic_vector(470,11);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(59463,24);
manlo <= conv_std_logic_vector(114545214,28);
exponent <= conv_std_logic_vector(469,11);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7998256,24);
manlo <= conv_std_logic_vector(234808364,28);
exponent <= conv_std_logic_vector(467,11);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(1451558,24);
manlo <= conv_std_logic_vector(62230667,28);
exponent <= conv_std_logic_vector(466,11);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(10046749,24);
manlo <= conv_std_logic_vector(29683609,28);
exponent <= conv_std_logic_vector(464,11);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(2958754,24);
manlo <= conv_std_logic_vector(158313814,28);
exponent <= conv_std_logic_vector(463,11);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(12264615,24);
manlo <= conv_std_logic_vector(87551554,28);
exponent <= conv_std_logic_vector(461,11);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(4590569,24);
manlo <= conv_std_logic_vector(96025360,28);
exponent <= conv_std_logic_vector(460,11);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(14665859,24);
manlo <= conv_std_logic_vector(200220878,28);
exponent <= conv_std_logic_vector(458,11);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6357306,24);
manlo <= conv_std_logic_vector(71997608,28);
exponent <= conv_std_logic_vector(457,11);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(244214,24);
manlo <= conv_std_logic_vector(66463607,28);
exponent <= conv_std_logic_vector(456,11);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(8270120,24);
manlo <= conv_std_logic_vector(265669912,28);
exponent <= conv_std_logic_vector(454,11);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(1651584,24);
manlo <= conv_std_logic_vector(179638473,28);
exponent <= conv_std_logic_vector(453,11);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(10341091,24);
manlo <= conv_std_logic_vector(152092530,28);
exponent <= conv_std_logic_vector(451,11);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(3175319,24);
manlo <= conv_std_logic_vector(178838140,28);
exponent <= conv_std_logic_vector(450,11);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(12583294,24);
manlo <= conv_std_logic_vector(183442082,28);
exponent <= conv_std_logic_vector(448,11);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(4825040,24);
manlo <= conv_std_logic_vector(141040370,28);
exponent <= conv_std_logic_vector(447,11);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(15010888,24);
manlo <= conv_std_logic_vector(62934477,28);
exponent <= conv_std_logic_vector(445,11);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6611164,24);
manlo <= conv_std_logic_vector(11633311,28);
exponent <= conv_std_logic_vector(444,11);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(430992,24);
manlo <= conv_std_logic_vector(96770068,28);
exponent <= conv_std_logic_vector(443,11);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8544968,24);
manlo <= conv_std_logic_vector(80768180,28);
exponent <= conv_std_logic_vector(441,11);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(1853806,24);
manlo <= conv_std_logic_vector(5288079,28);
exponent <= conv_std_logic_vector(440,11);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(10638663,24);
manlo <= conv_std_logic_vector(235213815,28);
exponent <= conv_std_logic_vector(438,11);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(3394261,24);
manlo <= conv_std_logic_vector(36557939,28);
exponent <= conv_std_logic_vector(437,11);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(12905470,24);
manlo <= conv_std_logic_vector(253900977,28);
exponent <= conv_std_logic_vector(435,11);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(5062084,24);
manlo <= conv_std_logic_vector(153603034,28);
exponent <= conv_std_logic_vector(434,11);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(15359702,24);
manlo <= conv_std_logic_vector(204098933,28);
exponent <= conv_std_logic_vector(432,11);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6867807,24);
manlo <= conv_std_logic_vector(115170312,28);
exponent <= conv_std_logic_vector(431,11);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(619820,24);
manlo <= conv_std_logic_vector(2986045,28);
exponent <= conv_std_logic_vector(430,11);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8822831,24);
manlo <= conv_std_logic_vector(145826716,28);
exponent <= conv_std_logic_vector(428,11);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(2058246,24);
manlo <= conv_std_logic_vector(98876593,28);
exponent <= conv_std_logic_vector(427,11);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(10939501,24);
manlo <= conv_std_logic_vector(129141213,28);
exponent <= conv_std_logic_vector(425,11);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(3615605,24);
manlo <= conv_std_logic_vector(20427716,28);
exponent <= conv_std_logic_vector(424,11);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(13231182,24);
manlo <= conv_std_logic_vector(130335695,28);
exponent <= conv_std_logic_vector(422,11);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(5301729,24);
manlo <= conv_std_logic_vector(196124198,28);
exponent <= conv_std_logic_vector(421,11);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(15712344,24);
manlo <= conv_std_logic_vector(233039482,28);
exponent <= conv_std_logic_vector(419,11);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(7127266,24);
manlo <= conv_std_logic_vector(266329205,28);
exponent <= conv_std_logic_vector(418,11);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(810719,24);
manlo <= conv_std_logic_vector(185030259,28);
exponent <= conv_std_logic_vector(417,11);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(9103743,24);
manlo <= conv_std_logic_vector(217685905,28);
exponent <= conv_std_logic_vector(415,11);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(2264930,24);
manlo <= conv_std_logic_vector(17303531,28);
exponent <= conv_std_logic_vector(414,11);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(11243640,24);
manlo <= conv_std_logic_vector(56799625,28);
exponent <= conv_std_logic_vector(412,11);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(3839377,24);
manlo <= conv_std_logic_vector(227776580,28);
exponent <= conv_std_logic_vector(411,11);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(13560468,24);
manlo <= conv_std_logic_vector(25616516,28);
exponent <= conv_std_logic_vector(409,11);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(5544004,24);
manlo <= conv_std_logic_vector(145740137,28);
exponent <= conv_std_logic_vector(408,11);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(16068856,24);
manlo <= conv_std_logic_vector(149889545,28);
exponent <= conv_std_logic_vector(406,11);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(7389573,24);
manlo <= conv_std_logic_vector(170431948,28);
exponent <= conv_std_logic_vector(405,11);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(1003714,24);
manlo <= conv_std_logic_vector(35324999,28);
exponent <= conv_std_logic_vector(404,11);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(9387738,24);
manlo <= conv_std_logic_vector(150667400,28);
exponent <= conv_std_logic_vector(402,11);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(2473881,24);
manlo <= conv_std_logic_vector(194497484,28);
exponent <= conv_std_logic_vector(401,11);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(11551116,24);
manlo <= conv_std_logic_vector(78219737,28);
exponent <= conv_std_logic_vector(399,11);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(4065606,24);
manlo <= conv_std_logic_vector(28280174,28);
exponent <= conv_std_logic_vector(398,11);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(13893366,24);
manlo <= conv_std_logic_vector(266881350,28);
exponent <= conv_std_logic_vector(396,11);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(5788937,24);
manlo <= conv_std_logic_vector(232096008,28);
exponent <= conv_std_logic_vector(395,11);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(16429280,24);
manlo <= conv_std_logic_vector(78498076,28);
exponent <= conv_std_logic_vector(393,11);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(7654758,24);
manlo <= conv_std_logic_vector(160696217,28);
exponent <= conv_std_logic_vector(392,11);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(1198826,24);
manlo <= conv_std_logic_vector(87006684,28);
exponent <= conv_std_logic_vector(391,11);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(9674849,24);
manlo <= conv_std_logic_vector(166079254,28);
exponent <= conv_std_logic_vector(389,11);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(2685126,24);
manlo <= conv_std_logic_vector(63154951,28);
exponent <= conv_std_logic_vector(388,11);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(11861966,24);
manlo <= conv_std_logic_vector(91696135,28);
exponent <= conv_std_logic_vector(386,11);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(4294316,24);
manlo <= conv_std_logic_vector(212296424,28);
exponent <= conv_std_logic_vector(385,11);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(14229918,24);
manlo <= conv_std_logic_vector(223047784,28);
exponent <= conv_std_logic_vector(383,11);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(6036558,24);
manlo <= conv_std_logic_vector(232962025,28);
exponent <= conv_std_logic_vector(382,11);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(8221,24);
manlo <= conv_std_logic_vector(133893557,28);
exponent <= conv_std_logic_vector(381,11);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7922853,24);
manlo <= conv_std_logic_vector(125492404,28);
exponent <= conv_std_logic_vector(379,11);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(1396079,24);
manlo <= conv_std_logic_vector(135612572,28);
exponent <= conv_std_logic_vector(378,11);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9965111,24);
manlo <= conv_std_logic_vector(47990958,28);
exponent <= conv_std_logic_vector(376,11);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(2898688,24);
manlo <= conv_std_logic_vector(203019642,28);
exponent <= conv_std_logic_vector(375,11);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(12176227,24);
manlo <= conv_std_logic_vector(103393586,28);
exponent <= conv_std_logic_vector(373,11);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(4525537,24);
manlo <= conv_std_logic_vector(38936964,28);
exponent <= conv_std_logic_vector(372,11);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(14570163,24);
manlo <= conv_std_logic_vector(185128905,28);
exponent <= conv_std_logic_vector(370,11);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(6286897,24);
manlo <= conv_std_logic_vector(12037044,28);
exponent <= conv_std_logic_vector(369,11);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(192410,24);
manlo <= conv_std_logic_vector(9691196,28);
exponent <= conv_std_logic_vector(368,11);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(8193890,24);
manlo <= conv_std_logic_vector(46224319,28);
exponent <= conv_std_logic_vector(366,11);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(1595497,24);
manlo <= conv_std_logic_vector(45130080,28);
exponent <= conv_std_logic_vector(365,11);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(10258557,24);
manlo <= conv_std_logic_vector(218068546,28);
exponent <= conv_std_logic_vector(363,11);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(3114594,24);
manlo <= conv_std_logic_vector(194203222,28);
exponent <= conv_std_logic_vector(362,11);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(12493936,24);
manlo <= conv_std_logic_vector(228530713,28);
exponent <= conv_std_logic_vector(360,11);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(4759294,24);
manlo <= conv_std_logic_vector(189728046,28);
exponent <= conv_std_logic_vector(359,11);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(14914142,24);
manlo <= conv_std_logic_vector(25337562,28);
exponent <= conv_std_logic_vector(357,11);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(6539982,24);
manlo <= conv_std_logic_vector(56762382,28);
exponent <= conv_std_logic_vector(356,11);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(378619,24);
manlo <= conv_std_logic_vector(186677702,28);
exponent <= conv_std_logic_vector(355,11);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(8467900,24);
manlo <= conv_std_logic_vector(266785510,28);
exponent <= conv_std_logic_vector(353,11);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(1797103,24);
manlo <= conv_std_logic_vector(17183357,28);
exponent <= conv_std_logic_vector(352,11);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(10555224,24);
manlo <= conv_std_logic_vector(126067134,28);
exponent <= conv_std_logic_vector(350,11);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(3332869,24);
manlo <= conv_std_logic_vector(228611260,28);
exponent <= conv_std_logic_vector(349,11);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(12815132,24);
manlo <= conv_std_logic_vector(155705738,28);
exponent <= conv_std_logic_vector(347,11);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(4995617,24);
manlo <= conv_std_logic_vector(85136440,28);
exponent <= conv_std_logic_vector(346,11);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(15261895,24);
manlo <= conv_std_logic_vector(3688335,28);
exponent <= conv_std_logic_vector(344,11);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(6795844,24);
manlo <= conv_std_logic_vector(137097782,28);
exponent <= conv_std_logic_vector(343,11);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(566872,24);
manlo <= conv_std_logic_vector(175764875,28);
exponent <= conv_std_logic_vector(342,11);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(8744918,24);
manlo <= conv_std_logic_vector(152414052,28);
exponent <= conv_std_logic_vector(340,11);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(2000921,24);
manlo <= conv_std_logic_vector(54921723,28);
exponent <= conv_std_logic_vector(339,11);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(10855146,24);
manlo <= conv_std_logic_vector(129996510,28);
exponent <= conv_std_logic_vector(337,11);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(3553540,24);
manlo <= conv_std_logic_vector(37023540,28);
exponent <= conv_std_logic_vector(336,11);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(13139852,24);
manlo <= conv_std_logic_vector(221848100,28);
exponent <= conv_std_logic_vector(334,11);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(5234533,24);
manlo <= conv_std_logic_vector(32943194,28);
exponent <= conv_std_logic_vector(333,11);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(15613463,24);
manlo <= conv_std_logic_vector(232436445,28);
exponent <= conv_std_logic_vector(331,11);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7054514,24);
manlo <= conv_std_logic_vector(111791498,28);
exponent <= conv_std_logic_vector(330,11);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(757191,24);
manlo <= conv_std_logic_vector(90062360,28);
exponent <= conv_std_logic_vector(329,11);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(9024975,24);
manlo <= conv_std_logic_vector(238219590,28);
exponent <= conv_std_logic_vector(327,11);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(2206975,24);
manlo <= conv_std_logic_vector(232222812,28);
exponent <= conv_std_logic_vector(326,11);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(11158359,24);
manlo <= conv_std_logic_vector(155073518,28);
exponent <= conv_std_logic_vector(324,11);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(3776631,24);
manlo <= conv_std_logic_vector(232102510,28);
exponent <= conv_std_logic_vector(323,11);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(13468136,24);
manlo <= conv_std_logic_vector(71264246,28);
exponent <= conv_std_logic_vector(321,11);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(5476070,24);
manlo <= conv_std_logic_vector(155401688,28);
exponent <= conv_std_logic_vector(320,11);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(15968890,24);
manlo <= conv_std_logic_vector(140531032,28);
exponent <= conv_std_logic_vector(318,11);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7316022,24);
manlo <= conv_std_logic_vector(197790036,28);
exponent <= conv_std_logic_vector(317,11);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(949598,24);
manlo <= conv_std_logic_vector(108723575,28);
exponent <= conv_std_logic_vector(316,11);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(9308106,24);
manlo <= conv_std_logic_vector(82754530,28);
exponent <= conv_std_logic_vector(314,11);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(2415291,24);
manlo <= conv_std_logic_vector(157597766,28);
exponent <= conv_std_logic_vector(313,11);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(11464899,24);
manlo <= conv_std_logic_vector(231735034,28);
exponent <= conv_std_logic_vector(311,11);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(4002171,24);
manlo <= conv_std_logic_vector(161749904,28);
exponent <= conv_std_logic_vector(310,11);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(13800021,24);
manlo <= conv_std_logic_vector(267486845,28);
exponent <= conv_std_logic_vector(308,11);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(5720258,24);
manlo <= conv_std_logic_vector(121711942,28);
exponent <= conv_std_logic_vector(307,11);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(16328217,24);
manlo <= conv_std_logic_vector(85566619,28);
exponent <= conv_std_logic_vector(305,11);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7580400,24);
manlo <= conv_std_logic_vector(165916765,28);
exponent <= conv_std_logic_vector(304,11);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(1144116,24);
manlo <= conv_std_logic_vector(209234965,28);
exponent <= conv_std_logic_vector(303,11);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(9594343,24);
manlo <= conv_std_logic_vector(148128653,28);
exponent <= conv_std_logic_vector(301,11);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(2625893,24);
manlo <= conv_std_logic_vector(48717694,28);
exponent <= conv_std_logic_vector(300,11);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(11774803,24);
manlo <= conv_std_logic_vector(228357100,28);
exponent <= conv_std_logic_vector(298,11);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(4230186,24);
manlo <= conv_std_logic_vector(57439900,28);
exponent <= conv_std_logic_vector(297,11);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(14135549,24);
manlo <= conv_std_logic_vector(147041206,28);
exponent <= conv_std_logic_vector(295,11);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(5967125,24);
manlo <= conv_std_logic_vector(222682176,28);
exponent <= conv_std_logic_vector(294,11);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(16691487,24);
manlo <= conv_std_logic_vector(12959237,28);
exponent <= conv_std_logic_vector(292,11);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(7847679,24);
manlo <= conv_std_logic_vector(147174066,28);
exponent <= conv_std_logic_vector(291,11);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(1340769,24);
manlo <= conv_std_logic_vector(168148656,28);
exponent <= conv_std_logic_vector(290,11);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(9883721,24);
manlo <= conv_std_logic_vector(190474495,28);
exponent <= conv_std_logic_vector(288,11);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(2838805,24);
manlo <= conv_std_logic_vector(196335986,28);
exponent <= conv_std_logic_vector(287,11);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(12088108,24);
manlo <= conv_std_logic_vector(120857634,28);
exponent <= conv_std_logic_vector(285,11);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(4460702,24);
manlo <= conv_std_logic_vector(229771569,28);
exponent <= conv_std_logic_vector(284,11);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(14474758,24);
manlo <= conv_std_logic_vector(236628147,28);
exponent <= conv_std_logic_vector(282,11);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(6216702,24);
manlo <= conv_std_logic_vector(29481361,28);
exponent <= conv_std_logic_vector(281,11);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(140763,24);
manlo <= conv_std_logic_vector(131310533,28);
exponent <= conv_std_logic_vector(280,11);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8117891,24);
manlo <= conv_std_logic_vector(96879140,28);
exponent <= conv_std_logic_vector(278,11);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(1539580,24);
manlo <= conv_std_logic_vector(98694067,28);
exponent <= conv_std_logic_vector(277,11);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(10176275,24);
manlo <= conv_std_logic_vector(66343668,28);
exponent <= conv_std_logic_vector(275,11);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(3054054,24);
manlo <= conv_std_logic_vector(159783892,28);
exponent <= conv_std_logic_vector(274,11);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(12404850,24);
manlo <= conv_std_logic_vector(262311967,28);
exponent <= conv_std_logic_vector(272,11);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(4693748,24);
manlo <= conv_std_logic_vector(264030756,28);
exponent <= conv_std_logic_vector(271,11);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(14817690,24);
manlo <= conv_std_logic_vector(106917994,28);
exponent <= conv_std_logic_vector(269,11);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(6469017,24);
manlo <= conv_std_logic_vector(5191992,28);
exponent <= conv_std_logic_vector(268,11);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(326406,24);
manlo <= conv_std_logic_vector(114083215,28);
exponent <= conv_std_logic_vector(267,11);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8391068,24);
manlo <= conv_std_logic_vector(64117214,28);
exponent <= conv_std_logic_vector(265,11);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(1740572,24);
manlo <= conv_std_logic_vector(183091279,28);
exponent <= conv_std_logic_vector(264,11);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(10472039,24);
manlo <= conv_std_logic_vector(2244224,28);
exponent <= conv_std_logic_vector(262,11);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(3271665,24);
manlo <= conv_std_logic_vector(109958542,28);
exponent <= conv_std_logic_vector(261,11);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(12725069,24);
manlo <= conv_std_logic_vector(41968573,28);
exponent <= conv_std_logic_vector(259,11);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(4929352,24);
manlo <= conv_std_logic_vector(94809674,28);
exponent <= conv_std_logic_vector(258,11);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(15164384,24);
manlo <= conv_std_logic_vector(252890425,28);
exponent <= conv_std_logic_vector(256,11);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(6724100,24);
manlo <= conv_std_logic_vector(163583158,28);
exponent <= conv_std_logic_vector(255,11);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(514086,24);
manlo <= conv_std_logic_vector(118679222,28);
exponent <= conv_std_logic_vector(254,11);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8667242,24);
manlo <= conv_std_logic_vector(192770478,28);
exponent <= conv_std_logic_vector(252,11);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(1943770,24);
manlo <= conv_std_logic_vector(136437165,28);
exponent <= conv_std_logic_vector(251,11);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(10771048,24);
manlo <= conv_std_logic_vector(58883744,28);
exponent <= conv_std_logic_vector(249,11);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(3491664,24);
manlo <= conv_std_logic_vector(24836209,28);
exponent <= conv_std_logic_vector(248,11);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(13048801,24);
manlo <= conv_std_logic_vector(33938829,28);
exponent <= conv_std_logic_vector(246,11);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(5167541,24);
manlo <= conv_std_logic_vector(6894318,28);
exponent <= conv_std_logic_vector(245,11);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(15514883,24);
manlo <= conv_std_logic_vector(216092120,28);
exponent <= conv_std_logic_vector(243,11);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(6981983,24);
manlo <= conv_std_logic_vector(70071320,28);
exponent <= conv_std_logic_vector(242,11);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(703825,24);
manlo <= conv_std_logic_vector(239890498,28);
exponent <= conv_std_logic_vector(241,11);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8946447,24);
manlo <= conv_std_logic_vector(185687386,28);
exponent <= conv_std_logic_vector(239,11);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(2149198,24);
manlo <= conv_std_logic_vector(12777107,28);
exponent <= conv_std_logic_vector(238,11);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11073338,24);
manlo <= conv_std_logic_vector(132295567,28);
exponent <= conv_std_logic_vector(236,11);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(3714076,24);
manlo <= conv_std_logic_vector(227171857,28);
exponent <= conv_std_logic_vector(235,11);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(13376085,24);
manlo <= conv_std_logic_vector(119368169,28);
exponent <= conv_std_logic_vector(233,11);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(5408343,24);
manlo <= conv_std_logic_vector(99290689,28);
exponent <= conv_std_logic_vector(232,11);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(15869228,24);
manlo <= conv_std_logic_vector(196569651,28);
exponent <= conv_std_logic_vector(230,11);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(7242695,24);
manlo <= conv_std_logic_vector(184868911,28);
exponent <= conv_std_logic_vector(229,11);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(895647,24);
manlo <= conv_std_logic_vector(101480846,28);
exponent <= conv_std_logic_vector(228,11);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(9228716,24);
manlo <= conv_std_logic_vector(111040654,28);
exponent <= conv_std_logic_vector(226,11);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(2356879,24);
manlo <= conv_std_logic_vector(205878747,28);
exponent <= conv_std_logic_vector(225,11);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(11378945,24);
manlo <= conv_std_logic_vector(223412824,28);
exponent <= conv_std_logic_vector(223,11);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(3938930,24);
manlo <= conv_std_logic_vector(43159582,28);
exponent <= conv_std_logic_vector(222,11);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(13706961,24);
manlo <= conv_std_logic_vector(24539717,28);
exponent <= conv_std_logic_vector(220,11);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(5651788,24);
manlo <= conv_std_logic_vector(17696328,28);
exponent <= conv_std_logic_vector(219,11);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(16227461,24);
manlo <= conv_std_logic_vector(248897772,28);
exponent <= conv_std_logic_vector(217,11);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(7506268,24);
manlo <= conv_std_logic_vector(253353585,28);
exponent <= conv_std_logic_vector(216,11);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(1089573,24);
manlo <= conv_std_logic_vector(199085712,28);
exponent <= conv_std_logic_vector(215,11);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(9514082,24);
manlo <= conv_std_logic_vector(134954983,28);
exponent <= conv_std_logic_vector(213,11);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(2566840,24);
manlo <= conv_std_logic_vector(107836942,28);
exponent <= conv_std_logic_vector(212,11);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(11687906,24);
manlo <= conv_std_logic_vector(170784064,28);
exponent <= conv_std_logic_vector(210,11);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(4166250,24);
manlo <= conv_std_logic_vector(219198631,28);
exponent <= conv_std_logic_vector(209,11);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(14041467,24);
manlo <= conv_std_logic_vector(127426909,28);
exponent <= conv_std_logic_vector(207,11);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(5897904,24);
manlo <= conv_std_logic_vector(29159081,28);
exponent <= conv_std_logic_vector(206,11);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(16589626,24);
manlo <= conv_std_logic_vector(15093248,28);
exponent <= conv_std_logic_vector(204,11);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(7772734,24);
manlo <= conv_std_logic_vector(112367334,28);
exponent <= conv_std_logic_vector(203,11);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(1285628,24);
manlo <= conv_std_logic_vector(21894417,28);
exponent <= conv_std_logic_vector(202,11);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9802579,24);
manlo <= conv_std_logic_vector(254146435,28);
exponent <= conv_std_logic_vector(200,11);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(2779104,24);
manlo <= conv_std_logic_vector(257348234,28);
exponent <= conv_std_logic_vector(199,11);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12000257,24);
manlo <= conv_std_logic_vector(188607876,28);
exponent <= conv_std_logic_vector(197,11);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(4396065,24);
manlo <= conv_std_logic_vector(238395052,28);
exponent <= conv_std_logic_vector(196,11);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(14379644,24);
manlo <= conv_std_logic_vector(116776141,28);
exponent <= conv_std_logic_vector(194,11);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(6146720,24);
manlo <= conv_std_logic_vector(217697734,28);
exponent <= conv_std_logic_vector(193,11);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(89274,24);
manlo <= conv_std_logic_vector(34078121,28);
exponent <= conv_std_logic_vector(192,11);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(8042123,24);
manlo <= conv_std_logic_vector(228091050,28);
exponent <= conv_std_logic_vector(190,11);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(1483833,24);
manlo <= conv_std_logic_vector(200872250,28);
exponent <= conv_std_logic_vector(189,11);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(10094243,24);
manlo <= conv_std_logic_vector(28573613,28);
exponent <= conv_std_logic_vector(187,11);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(2993698,24);
manlo <= conv_std_logic_vector(193026703,28);
exponent <= conv_std_logic_vector(186,11);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12316036,24);
manlo <= conv_std_logic_vector(62602992,28);
exponent <= conv_std_logic_vector(184,11);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(4628402,24);
manlo <= conv_std_logic_vector(200475490,28);
exponent <= conv_std_logic_vector(183,11);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(14721532,24);
manlo <= conv_std_logic_vector(67122338,28);
exponent <= conv_std_logic_vector(181,11);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(6398267,24);
manlo <= conv_std_logic_vector(216803728,28);
exponent <= conv_std_logic_vector(180,11);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(274352,24);
manlo <= conv_std_logic_vector(17200594,28);
exponent <= conv_std_logic_vector(179,11);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(8314469,24);
manlo <= conv_std_logic_vector(86446456,28);
exponent <= conv_std_logic_vector(177,11);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(1684214,24);
manlo <= conv_std_logic_vector(93587914,28);
exponent <= conv_std_logic_vector(176,11);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(10389106,24);
manlo <= conv_std_logic_vector(193148951,28);
exponent <= conv_std_logic_vector(174,11);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(3210647,24);
manlo <= conv_std_logic_vector(64824977,28);
exponent <= conv_std_logic_vector(173,11);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(12635279,24);
manlo <= conv_std_logic_vector(224939505,28);
exponent <= conv_std_logic_vector(171,11);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(4863289,24);
manlo <= conv_std_logic_vector(17355920,28);
exponent <= conv_std_logic_vector(170,11);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(15067171,24);
manlo <= conv_std_logic_vector(171641236,28);
exponent <= conv_std_logic_vector(168,11);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(6652575,24);
manlo <= conv_std_logic_vector(15694991,28);
exponent <= conv_std_logic_vector(167,11);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(461460,24);
manlo <= conv_std_logic_vector(236949593,28);
exponent <= conv_std_logic_vector(166,11);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(8589803,24);
manlo <= conv_std_logic_vector(73170085,28);
exponent <= conv_std_logic_vector(164,11);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(1886793,24);
manlo <= conv_std_logic_vector(200887360,28);
exponent <= conv_std_logic_vector(163,11);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(10687205,24);
manlo <= conv_std_logic_vector(242930225,28);
exponent <= conv_std_logic_vector(161,11);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(3429976,24);
manlo <= conv_std_logic_vector(97980458,28);
exponent <= conv_std_logic_vector(160,11);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(12958026,24);
manlo <= conv_std_logic_vector(144828568,28);
exponent <= conv_std_logic_vector(158,11);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(5100752,24);
manlo <= conv_std_logic_vector(219332721,28);
exponent <= conv_std_logic_vector(157,11);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(15416603,24);
manlo <= conv_std_logic_vector(206580322,28);
exponent <= conv_std_logic_vector(155,11);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(6909672,24);
manlo <= conv_std_logic_vector(228709240,28);
exponent <= conv_std_logic_vector(154,11);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(650622,24);
manlo <= conv_std_logic_vector(232984198,28);
exponent <= conv_std_logic_vector(153,11);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(8868158,24);
manlo <= conv_std_logic_vector(132673062,28);
exponent <= conv_std_logic_vector(151,11);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(2091596,24);
manlo <= conv_std_logic_vector(20173170,28);
exponent <= conv_std_logic_vector(150,11);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(10988576,24);
manlo <= conv_std_logic_vector(44856082,28);
exponent <= conv_std_logic_vector(148,11);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(3651712,24);
manlo <= conv_std_logic_vector(56970522,28);
exponent <= conv_std_logic_vector(147,11);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13284314,24);
manlo <= conv_std_logic_vector(208786223,28);
exponent <= conv_std_logic_vector(145,11);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(5340822,24);
manlo <= conv_std_logic_vector(76928898,28);
exponent <= conv_std_logic_vector(144,11);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(15769870,24);
manlo <= conv_std_logic_vector(69445892,28);
exponent <= conv_std_logic_vector(142,11);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(7169591,24);
manlo <= conv_std_logic_vector(217224162,28);
exponent <= conv_std_logic_vector(141,11);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(841860,24);
manlo <= conv_std_logic_vector(147476782,28);
exponent <= conv_std_logic_vector(140,11);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9149568,24);
manlo <= conv_std_logic_vector(37524984,28);
exponent <= conv_std_logic_vector(138,11);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(2298645,24);
manlo <= conv_std_logic_vector(193659590,28);
exponent <= conv_std_logic_vector(137,11);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(11293253,24);
manlo <= conv_std_logic_vector(107316618,28);
exponent <= conv_std_logic_vector(135,11);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(3875881,24);
manlo <= conv_std_logic_vector(51654059,28);
exponent <= conv_std_logic_vector(134,11);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13614183,24);
manlo <= conv_std_logic_vector(111249634,28);
exponent <= conv_std_logic_vector(132,11);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(5583526,24);
manlo <= conv_std_logic_vector(17717412,28);
exponent <= conv_std_logic_vector(131,11);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(16127013,24);
manlo <= conv_std_logic_vector(48769099,28);
exponent <= conv_std_logic_vector(129,11);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(7432362,24);
manlo <= conv_std_logic_vector(238120049,28);
exponent <= conv_std_logic_vector(128,11);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(1035196,24);
manlo <= conv_std_logic_vector(188962402,28);
exponent <= conv_std_logic_vector(127,11);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9434065,24);
manlo <= conv_std_logic_vector(194820226,28);
exponent <= conv_std_logic_vector(125,11);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(2507967,24);
manlo <= conv_std_logic_vector(93233285,28);
exponent <= conv_std_logic_vector(124,11);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(11601273,24);
manlo <= conv_std_logic_vector(239123672,28);
exponent <= conv_std_logic_vector(122,11);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(4102510,24);
manlo <= conv_std_logic_vector(1244898,28);
exponent <= conv_std_logic_vector(121,11);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(13947671,24);
manlo <= conv_std_logic_vector(197996828,28);
exponent <= conv_std_logic_vector(119,11);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(5828893,24);
manlo <= conv_std_logic_vector(16622593,28);
exponent <= conv_std_logic_vector(118,11);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(16488075,24);
manlo <= conv_std_logic_vector(20144764,28);
exponent <= conv_std_logic_vector(116,11);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(7698017,24);
manlo <= conv_std_logic_vector(102592250,28);
exponent <= conv_std_logic_vector(115,11);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(1230654,24);
manlo <= conv_std_logic_vector(96196092,28);
exponent <= conv_std_logic_vector(114,11);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(9721685,24);
manlo <= conv_std_logic_vector(36636777,28);
exponent <= conv_std_logic_vector(112,11);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(2719585,24);
manlo <= conv_std_logic_vector(237160861,28);
exponent <= conv_std_logic_vector(111,11);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(11912674,24);
manlo <= conv_std_logic_vector(87541902,28);
exponent <= conv_std_logic_vector(109,11);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(4331625,24);
manlo <= conv_std_logic_vector(172036325,28);
exponent <= conv_std_logic_vector(108,11);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14284819,24);
manlo <= conv_std_logic_vector(125225503,28);
exponent <= conv_std_logic_vector(106,11);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(6076952,24);
manlo <= conv_std_logic_vector(133715238,28);
exponent <= conv_std_logic_vector(105,11);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(37941,24);
manlo <= conv_std_logic_vector(126448851,28);
exponent <= conv_std_logic_vector(104,11);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(7966586,24);
manlo <= conv_std_logic_vector(250893596,28);
exponent <= conv_std_logic_vector(102,11);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(1428256,24);
manlo <= conv_std_logic_vector(212630882,28);
exponent <= conv_std_logic_vector(101,11);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10012460,24);
manlo <= conv_std_logic_vector(168603206,28);
exponent <= conv_std_logic_vector(99,11);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(2933526,24);
manlo <= conv_std_logic_vector(143402282,28);
exponent <= conv_std_logic_vector(98,11);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(12227491,24);
manlo <= conv_std_logic_vector(213203509,28);
exponent <= conv_std_logic_vector(96,11);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(4563255,24);
manlo <= conv_std_logic_vector(104522224,28);
exponent <= conv_std_logic_vector(95,11);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14625666,24);
manlo <= conv_std_logic_vector(203000190,28);
exponent <= conv_std_logic_vector(93,11);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(6327733,24);
manlo <= conv_std_logic_vector(246711469,28);
exponent <= conv_std_logic_vector(92,11);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(222456,24);
manlo <= conv_std_logic_vector(34640152,28);
exponent <= conv_std_logic_vector(91,11);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(8238103,24);
manlo <= conv_std_logic_vector(142733230,28);
exponent <= conv_std_logic_vector(89,11);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(1628027,24);
manlo <= conv_std_logic_vector(144984792,28);
exponent <= conv_std_logic_vector(88,11);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10306426,24);
manlo <= conv_std_logic_vector(223510234,28);
exponent <= conv_std_logic_vector(86,11);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(3149814,24);
manlo <= conv_std_logic_vector(209464872,28);
exponent <= conv_std_logic_vector(85,11);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(12545763,24);
manlo <= conv_std_logic_vector(212245812,28);
exponent <= conv_std_logic_vector(83,11);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(4797426,24);
manlo <= conv_std_logic_vector(224882259,28);
exponent <= conv_std_logic_vector(82,11);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14970254,24);
manlo <= conv_std_logic_vector(54358776,28);
exponent <= conv_std_logic_vector(80,11);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(6581267,24);
manlo <= conv_std_logic_vector(51917314,28);
exponent <= conv_std_logic_vector(79,11);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(408995,24);
manlo <= conv_std_logic_vector(130890803,28);
exponent <= conv_std_logic_vector(78,11);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(8512599,24);
manlo <= conv_std_logic_vector(137347476,28);
exponent <= conv_std_logic_vector(76,11);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(1829990,24);
manlo <= conv_std_logic_vector(106170554,28);
exponent <= conv_std_logic_vector(75,11);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10603618,24);
manlo <= conv_std_logic_vector(204595238,28);
exponent <= conv_std_logic_vector(73,11);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(3368476,24);
manlo <= conv_std_logic_vector(102605239,28);
exponent <= conv_std_logic_vector(72,11);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(12867528,24);
manlo <= conv_std_logic_vector(59687307,28);
exponent <= conv_std_logic_vector(70,11);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(5034167,24);
manlo <= conv_std_logic_vector(235251142,28);
exponent <= conv_std_logic_vector(69,11);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15318622,24);
manlo <= conv_std_logic_vector(227223140,28);
exponent <= conv_std_logic_vector(67,11);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(6837582,24);
manlo <= conv_std_logic_vector(138925467,28);
exponent <= conv_std_logic_vector(66,11);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(597581,24);
manlo <= conv_std_logic_vector(205088968,28);
exponent <= conv_std_logic_vector(65,11);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(8790107,24);
manlo <= conv_std_logic_vector(152356460,28);
exponent <= conv_std_logic_vector(63,11);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(2034169,24);
manlo <= conv_std_logic_vector(110749946,28);
exponent <= conv_std_logic_vector(62,11);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10904071,24);
manlo <= conv_std_logic_vector(218226183,28);
exponent <= conv_std_logic_vector(60,11);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(3589537,24);
manlo <= conv_std_logic_vector(102830143,28);
exponent <= conv_std_logic_vector(59,11);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(13192823,24);
manlo <= conv_std_logic_vector(110639602,28);
exponent <= conv_std_logic_vector(57,11);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(5273506,24);
manlo <= conv_std_logic_vector(188352155,28);
exponent <= conv_std_logic_vector(56,11);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15670814,24);
manlo <= conv_std_logic_vector(48227643,28);
exponent <= conv_std_logic_vector(54,11);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(7096710,24);
manlo <= conv_std_logic_vector(112532514,28);
exponent <= conv_std_logic_vector(53,11);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(788237,24);
manlo <= conv_std_logic_vector(112565412,28);
exponent <= conv_std_logic_vector(52,11);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(9070660,24);
manlo <= conv_std_logic_vector(201680253,28);
exponent <= conv_std_logic_vector(50,11);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(2240588,24);
manlo <= conv_std_logic_vector(244138286,28);
exponent <= conv_std_logic_vector(49,11);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(11207821,24);
manlo <= conv_std_logic_vector(206597824,28);
exponent <= conv_std_logic_vector(47,11);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(3813024,24);
manlo <= conv_std_logic_vector(29987310,28);
exponent <= conv_std_logic_vector(46,11);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(13521688,24);
manlo <= conv_std_logic_vector(27790821,28);
exponent <= conv_std_logic_vector(44,11);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(5515471,24);
manlo <= conv_std_logic_vector(219963166,28);
exponent <= conv_std_logic_vector(43,11);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(16026870,24);
manlo <= conv_std_logic_vector(39964772,28);
exponent <= conv_std_logic_vector(41,11);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(7358681,24);
manlo <= conv_std_logic_vector(204327682,28);
exponent <= conv_std_logic_vector(40,11);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(980985,24);
manlo <= conv_std_logic_vector(43247066,28);
exponent <= conv_std_logic_vector(39,11);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(9354292,24);
manlo <= conv_std_logic_vector(128160132,28);
exponent <= conv_std_logic_vector(37,11);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(2449273,24);
manlo <= conv_std_logic_vector(126511008,28);
exponent <= conv_std_logic_vector(36,11);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(11514904,24);
manlo <= conv_std_logic_vector(217311246,28);
exponent <= conv_std_logic_vector(34,11);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(4038963,24);
manlo <= conv_std_logic_vector(49913566,28);
exponent <= conv_std_logic_vector(33,11);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(13854161,24);
manlo <= conv_std_logic_vector(124821568,28);
exponent <= conv_std_logic_vector(31,11);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(5760092,24);
manlo <= conv_std_logic_vector(12957085,28);
exponent <= conv_std_logic_vector(30,11);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16386833,24);
manlo <= conv_std_logic_vector(43278038,28);
exponent <= conv_std_logic_vector(28,11);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(7623527,24);
manlo <= conv_std_logic_vector(199937734,28);
exponent <= conv_std_logic_vector(27,11);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(1175847,24);
manlo <= conv_std_logic_vector(253947561,28);
exponent <= conv_std_logic_vector(26,11);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(9641036,24);
manlo <= conv_std_logic_vector(141497796,28);
exponent <= conv_std_logic_vector(24,11);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(2660247,24);
manlo <= conv_std_logic_vector(255766959,28);
exponent <= conv_std_logic_vector(23,11);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11825357,24);
manlo <= conv_std_logic_vector(136095046,28);
exponent <= conv_std_logic_vector(21,11);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(4267381,24);
manlo <= conv_std_logic_vector(138414926,28);
exponent <= conv_std_logic_vector(20,11);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(14190283,24);
manlo <= conv_std_logic_vector(25479908,28);
exponent <= conv_std_logic_vector(18,11);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(6007396,24);
manlo <= conv_std_logic_vector(140400514,28);
exponent <= conv_std_logic_vector(17,11);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16750746,24);
manlo <= conv_std_logic_vector(23924155,28);
exponent <= conv_std_logic_vector(15,11);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(7891279,24);
manlo <= conv_std_logic_vector(245330892,28);
exponent <= conv_std_logic_vector(14,11);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(1372848,24);
manlo <= conv_std_logic_vector(263794815,28);
exponent <= conv_std_logic_vector(13,11);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(9930927,24);
manlo <= conv_std_logic_vector(14029030,28);
exponent <= conv_std_logic_vector(11,11);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(2873537,24);
manlo <= conv_std_logic_vector(129274844,28);
exponent <= conv_std_logic_vector(10,11);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(12139216,24);
manlo <= conv_std_logic_vector(224845565,28);
exponent <= conv_std_logic_vector(8,11);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(4498306,24);
manlo <= conv_std_logic_vector(82126943,28);
exponent <= conv_std_logic_vector(7,11);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(14530093,24);
manlo <= conv_std_logic_vector(7024665,28);
exponent <= conv_std_logic_vector(5,11);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(6257414,24);
manlo <= conv_std_logic_vector(187437029,28);
exponent <= conv_std_logic_vector(4,11);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(170718,24);
manlo <= conv_std_logic_vector(36971864,28);
exponent <= conv_std_logic_vector(3,11);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(8161970,24);
manlo <= conv_std_logic_vector(42518955,28);
exponent <= conv_std_logic_vector(1,11);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(1572011,24);
manlo <= conv_std_logic_vector(197150320,28);
exponent <= conv_std_logic_vector(0,11);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_log.vhd
|
10
|
10521
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** DP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 DP LN() ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 27 + 7*DoubleSpeed + ***
--*** RoundConvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, RoundConvert = 0 : 27 ***
--*** DoubleSpeed = 1, RoundConvert = 0 : 34 ***
--*** DoubleSpeed = 0, RoundConvert = 1 : 28 ***
--*** DoubleSpeed = 1, RoundConvert = 1 : 36 ***
--*** ***
--***************************************************
ENTITY dp_log IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_log;
ARCHITECTURE rtl OF dp_log IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
constant coredepth : positive := 26 + 7*doublespeed;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component dp_ln_core
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: dp_ln_core
GENERIC MAP (doublespeed=>doublespeed,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
gra: IF (roundconvert = 0) GENERATE
norndout: dp_lnnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_lnrndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_mul54usb.vhd
|
10
|
3839
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54USB.VHD ***
--*** ***
--*** Function: 4/5/6 pipeline stage unsigned ***
--*** 54 bit multiplier (behavioral) ***
--*** ***
--*** 24/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 31/01/08 ML see below ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul54usb IS
GENERIC (
latency : positive := 5; -- 4/5/6
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
prune : integer := 0 -- 0 = pruned multiplier, 1 = normal multiplier
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54usb;
ARCHITECTURE rtl OF fp_mul54usb IS
constant delaydepth : integer := latency - 2;
type muldelfftype IS ARRAY (delaydepth DOWNTO 1) OF STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal muldelff : muldelfftype;
signal mulnode : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal mulonenode, multwonode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multhrnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 72 GENERATE
zerovec(k) <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 108 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO delaydepth LOOP
FOR j IN 1 TO 72 LOOP
muldelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= mulnode;
muldelff(1)(72 DOWNTO 1) <= mulff(108 DOWNTO 37);
FOR k IN 2 TO delaydepth LOOP
muldelff(k)(72 DOWNTO 1) <= muldelff(k-1)(72 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- full multiplier
gpa: IF (prune = 1) GENERATE
mulonenode <= zerovec(54 DOWNTO 1);
multwonode <= zerovec(54 DOWNTO 1);
multhrnode <= zerovec(72 DOWNTO 1);
mulnode <= aaff * bbff;
END GENERATE;
-- pruned multiplier (18x18 LSB contribution missing)
gpb: IF (prune = 0) GENERATE
mulonenode <= aaff(18 DOWNTO 1) * bbff(54 DOWNTO 19);
multwonode <= bbff(18 DOWNTO 1) * aaff(54 DOWNTO 19);
multhrnode <= aaff(54 DOWNTO 19) * bbff(54 DOWNTO 19);
mulnode <= (multhrnode & zerovec(36 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & mulonenode & zerovec(18 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & multwonode & zerovec(18 DOWNTO 1));
END GENERATE;
cc <= muldelff(delaydepth)(72 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_scmul3236.vhd
|
10
|
4216
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
mit
|
fujy/2D-Image-Filtering-on-FPGA
|
Project_with_state_machine/FlipFlop_tb.vhd
|
2
|
2494
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:17 12/13/2015
-- Design Name:
-- Module Name: /home/student/workspace_Xilinx/lena1/FlipFlop_tb.vhd
-- Project Name: lena1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: FlipFlop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY FlipFlop_tb IS
END FlipFlop_tb;
ARCHITECTURE behavior OF FlipFlop_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FlipFlop
PORT(
D : IN std_logic_vector(7 downto 0);
Q : OUT std_logic_vector(7 downto 0);
CLK : IN std_logic;
EN : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal EN : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal Q : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FlipFlop PORT MAP (
D => D,
Q => Q,
CLK => CLK,
EN => EN,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
EN <= '1';
D <= x"FF";
wait for clk_period * 20;
assert false report "NONE. End of your simulation." severity failure;
end process;
END;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_sqr.vhd
|
10
|
9456
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_castdtoy.vhd
|
10
|
9123
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- double <=> internal double
ENTITY hcc_castdtoy IS
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtoy;
ARCHITECTURE rtl OF hcc_castdtoy IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (53+11*target DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentff : exponentfftype;
signal satdelff, zipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- ieee754: sign (64), 8 exponent (63:53), 52 mantissa (52:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(13:1)
-- multiplier, divider : (SIGN)('1')(52:1), exponent(13:1)
-- (multiplier & divider use unsigned numbers, sign packed with input)
gza: IF (roundconvert = 1) GENERATE
gzb: FOR k IN 1 TO 53+11*target GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
-- if exponent = 1023 => saturate, if 0 => 0
satnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
gexpa: FOR k IN 1 TO 11 GENERATE
expnode(k) <= (aaff(k+52) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(12) <= satnode;
expnode(13) <= '0';
--**************************************
--*** direct to multipier or divider ***
--**************************************
gmda: IF (target = 0) GENERATE
-- already in "01"&mantissa format used by multiplier and divider
--fracnode <= aaff(64) & '1' & aaff(52 DOWNTO 1);
-- 13/07/09
fracnode(54) <= aaff(64);
fracnode(53) <= NOT(zipnode);
fracnode(52 DOWNTO 1) <= aaff(52 DOWNTO 1);
gmdb: IF (outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gmdc: IF (outputpipe = 1) GENERATE
pmda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 67 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fracnode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
END GENERATE;
--***********************
--*** internal format ***
--***********************
gxa: IF (target = 1) GENERATE
fracnode(64) <= aaff(64);
fracnode(63) <= aaff(64);
fracnode(62) <= aaff(64);
fracnode(61) <= aaff(64);
fracnode(60) <= aaff(64);
--fracnode(59) <= NOT(aaff(64)); -- '1' XOR sign
-- 13/07/09
fracnode(59) <= aaff(64) XOR NOT(zipnode);
gfa: FOR k IN 1 TO 52 GENERATE
fracnode(k+6)<= (aaff(k) XOR aaff(64));
END GENERATE;
gfb: FOR k IN 1 TO 6 GENERATE
fracnode(k)<= aaff(64); -- '0' XOR sign
END GENERATE;
--*** OUTPUT STAGE(S) ***
gsa: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gsb: IF (outputpipe = 1 AND
((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0))) GENERATE
gsc: IF (roundconvert = 0) GENERATE
mantissanode <= fracnode;
END GENERATE;
gsd: IF (roundconvert = 1) GENERATE
mantissanode <= fracnode + (zerovec(63 DOWNTO 1) & aaff(64));
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= mantissanode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gse: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsf: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
prcb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
END LOOP;
satdelff <= "00";
zipdelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentff(1)(13 DOWNTO 1) <= expnode;
exponentff(2)(13 DOWNTO 1) <= exponentff(1)(13 DOWNTO 1);
satdelff(1) <= satnode;
satdelff(2) <= satdelff(1);
zipdelff(1) <= zipnode;
zipdelff(2) <= zipdelff(1);
END IF;
END IF;
END PROCESS;
cc <= mantissanode & exponentff(2)(13 DOWNTO 1);
ccsat <= satdelff(2);
cczip <= zipdelff(2);
END GENERATE;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_castdtoy.vhd
|
10
|
9123
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- double <=> internal double
ENTITY hcc_castdtoy IS
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtoy;
ARCHITECTURE rtl OF hcc_castdtoy IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (53+11*target DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentff : exponentfftype;
signal satdelff, zipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- ieee754: sign (64), 8 exponent (63:53), 52 mantissa (52:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(13:1)
-- multiplier, divider : (SIGN)('1')(52:1), exponent(13:1)
-- (multiplier & divider use unsigned numbers, sign packed with input)
gza: IF (roundconvert = 1) GENERATE
gzb: FOR k IN 1 TO 53+11*target GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
-- if exponent = 1023 => saturate, if 0 => 0
satnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
gexpa: FOR k IN 1 TO 11 GENERATE
expnode(k) <= (aaff(k+52) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(12) <= satnode;
expnode(13) <= '0';
--**************************************
--*** direct to multipier or divider ***
--**************************************
gmda: IF (target = 0) GENERATE
-- already in "01"&mantissa format used by multiplier and divider
--fracnode <= aaff(64) & '1' & aaff(52 DOWNTO 1);
-- 13/07/09
fracnode(54) <= aaff(64);
fracnode(53) <= NOT(zipnode);
fracnode(52 DOWNTO 1) <= aaff(52 DOWNTO 1);
gmdb: IF (outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gmdc: IF (outputpipe = 1) GENERATE
pmda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 67 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fracnode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
END GENERATE;
--***********************
--*** internal format ***
--***********************
gxa: IF (target = 1) GENERATE
fracnode(64) <= aaff(64);
fracnode(63) <= aaff(64);
fracnode(62) <= aaff(64);
fracnode(61) <= aaff(64);
fracnode(60) <= aaff(64);
--fracnode(59) <= NOT(aaff(64)); -- '1' XOR sign
-- 13/07/09
fracnode(59) <= aaff(64) XOR NOT(zipnode);
gfa: FOR k IN 1 TO 52 GENERATE
fracnode(k+6)<= (aaff(k) XOR aaff(64));
END GENERATE;
gfb: FOR k IN 1 TO 6 GENERATE
fracnode(k)<= aaff(64); -- '0' XOR sign
END GENERATE;
--*** OUTPUT STAGE(S) ***
gsa: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gsb: IF (outputpipe = 1 AND
((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0))) GENERATE
gsc: IF (roundconvert = 0) GENERATE
mantissanode <= fracnode;
END GENERATE;
gsd: IF (roundconvert = 1) GENERATE
mantissanode <= fracnode + (zerovec(63 DOWNTO 1) & aaff(64));
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= mantissanode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gse: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsf: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
prcb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
END LOOP;
satdelff <= "00";
zipdelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentff(1)(13 DOWNTO 1) <= expnode;
exponentff(2)(13 DOWNTO 1) <= exponentff(1)(13 DOWNTO 1);
satdelff(1) <= satnode;
satdelff(2) <= satdelff(1);
zipdelff(1) <= zipnode;
zipdelff(2) <= zipdelff(1);
END IF;
END IF;
END PROCESS;
cc <= mantissanode & exponentff(2)(13 DOWNTO 1);
ccsat <= satdelff(2);
cczip <= zipdelff(2);
END GENERATE;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_alufp1x_sv.vhd
|
10
|
12097
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** 04/05/10 - optimized structure ***
--*** 15/10/10 - bug in shiftcheckbit ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aanode, bbnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal addsubctlff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aanode <= aaff;
bbnode <= bbff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aanode <= aa;
bbnode <= bb;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3+shiftspeed LOOP
addsubctlff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addsubctlff(1) <= addsubnode;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubctlff(k) <= addsubctlff(k-1);
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aanode(k+10) AND NOT(switch)) OR (bbnode(k+10) AND switch);
mantissarightff(k) <= (bbnode(k+10) AND NOT(switch)) OR (aanode(k+10) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aanode(k) AND NOT(switch)) OR (bbnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= addsubnode AND switch;
invertrightff(1) <= addsubnode AND NOT(switch);
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
alucarrybitnode <= addsubctlff(2+shiftspeed);
subexponentone <= aanode(10 DOWNTO 1) - bbnode(10 DOWNTO 1);
subexponenttwo <= bbnode(10 DOWNTO 1) - aanode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
-- 15/10/10 - was down to exponentshiftff(5) - zeroed any shift >= 16. Old design was ok because it
-- used shiftcheck subtract 31, not caught because unlikely to cause differences for small designs
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_mullongs.vhd
|
10
|
5869
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGS.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** synthesizable ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongs IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongs;
ARCHITECTURE syn OF hcc_mullongs IS
signal mulnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gsa: IF (unsigned = 0) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
gua: IF (unsigned = 1) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
mulcc <= mulnode(32 DOWNTO 1);
END syn;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_mullongs.vhd
|
10
|
5869
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGS.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** synthesizable ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongs IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongs;
ARCHITECTURE syn OF hcc_mullongs IS
signal mulnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gsa: IF (unsigned = 0) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
gua: IF (unsigned = 1) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
mulcc <= mulnode(32 DOWNTO 1);
END syn;
|
mit
|
tjyrz/vhdl_fft
|
determ_adc.vhd
|
3
|
3567
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity determ_adc is
generic (
N : positive := 16;
DA_RESET_DELAY: positive
);
port(
CLK1, spi_sck_i, conv_i: in std_logic;
spi_miso_o: out std_logic
);
end determ_adc;
---------------------------------------------------
architecture Behavioral of determ_adc is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (3 downto 0) := "0000";
begin
if(cnt1_Q = DA_RESET_DELAY) then
currcount := "0000";
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
di_i <= "0" & std_logic_vector(currcount) & "00000000" & "111";
when "0010" =>
next_s_read_state <= "0011";
currcount := currcount + 1;
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_castytol.vhd
|
10
|
6849
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOL.VHD ***
--*** ***
--*** Function: Cast Internal Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytol IS
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytol;
ARCHITECTURE rtl OF hcc_castytol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_lsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
midpoint <= conv_std_logic_vector (1054,13);
maxpoint <= conv_std_logic_vector (1118,13);
minpoint <= conv_std_logic_vector (1022,13);
leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point
rightshiftnum <= midpoint - aa(13 DOWNTO 1);
-- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre
leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate
rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero
selectleftbit <= rightshiftnum(13);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(13));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13);
gsa: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gsb: IF (normspeed > 1) GENERATE
sftlp: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus(64 DOWNTO 33);
rightshiftbusff <= rightshiftbus(64 DOWNTO 33);
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_cntuscomb64.vhd
|
10
|
6369
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSCOMB64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuscomb64 IS
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuscomb64;
ARCHITECTURE rtl of hcc_cntuscomb64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_lsft64x6.vhd
|
10
|
4113
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Left Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64x6 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64x6;
ARCHITECTURE rtl OF dp_lsft64x6 IS
signal leftone, lefttwo, leftthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
leftone(1) <= inbus(1) AND NOT(shift(2)) AND NOT(shift(1));
leftone(2) <= (inbus(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(1) AND NOT(shift(2)) AND shift(1));
leftone(3) <= (inbus(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(2) AND NOT(shift(2)) AND shift(1)) OR
(inbus(1) AND shift(2) AND NOT(shift(1)));
gla: FOR k IN 4 TO 64 GENERATE
leftone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k-1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k-2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k-3) AND shift(2) AND shift(1));
END GENERATE;
glb: FOR k IN 1 TO 4 GENERATE
lefttwo(k) <= leftone(k) AND NOT(shift(4)) AND NOT(shift(3));
END GENERATE;
glc: FOR k IN 5 TO 8 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gld: FOR k IN 9 TO 12 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(leftone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gle: FOR k IN 13 TO 64 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(leftone(k-8) AND shift(4) AND NOT(shift(3))) OR
(leftone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glf: FOR k IN 1 TO 16 GENERATE
leftthr(k) <= lefttwo(k) AND NOT(shift(6)) AND NOT(shift(5));
END GENERATE;
glg: FOR k IN 17 TO 32 GENERATE
leftthr(k) <= (lefttwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(lefttwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glh: FOR k IN 33 TO 48 GENERATE
leftthr(k) <= (lefttwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(lefttwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(lefttwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
gli: FOR k IN 49 TO 64 GENERATE
leftthr(k) <= (lefttwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(lefttwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(lefttwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(lefttwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
outbus <= leftthr;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_castltod.vhd
|
10
|
3294
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOD.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castltod;
ARCHITECTURE rtl OF hcc_castltod IS
signal fit : STD_LOGIC;
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
yvector(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
yvector(77 DOWNTO 73) <= "00000";
END GENERATE;
yvector(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
yvector(k) <= '0';
END GENERATE;
yvector(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
core: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_invsqr_est.vhd
|
10
|
6478
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse Root ***
--*** ***
--*** Used by both single and double inverse ***
--*** square root cores ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse square root of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_invsqr_est;
ARCHITECTURE rtl OF fp_invsqr_est IS
type smalldelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type largedelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal twodelff : smalldelfftype;
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal ziplutdelff : largedelfftype;
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal invrootff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_invsqr_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_invsqr_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 9 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= radicand(18 DOWNTO 10);
two <= radicand(9 DOWNTO 1);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 20 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 18 LOOP
invrootff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
onelutff <= onelut;
ziplutff <= ziplut;
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invrootff <= ziplutdelff(2)(20 DOWNTO 1) - (zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
upper: fp_invsqr_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_invsqr_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
--**************
--*** OUTPUT ***
--**************
invroot <= invrootff(20 DOWNTO 3);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_ln_s5.vhd
|
10
|
195654
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_s5
-- VHDL created on Wed Feb 27 15:13:10 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1248
entity fp_ln_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (22 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (7 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (24 downto 0);
signal postPEMul_uid43_fpLogETest_a : std_logic_vector (24 downto 0);
signal postPEMul_uid43_fpLogETest_b : std_logic_vector (25 downto 0);
signal postPEMul_uid43_fpLogETest_s1 : std_logic_vector (50 downto 0);
signal postPEMul_uid43_fpLogETest_pr : SIGNED (50 downto 0);
signal postPEMul_uid43_fpLogETest_q : std_logic_vector (50 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (34 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (34 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(56 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(56 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(56 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (8 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (22 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(36 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(33 downto 0);
signal zs_uid113_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal mO_uid116_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0);
signal zs_uid121_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid133_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q : std_logic_vector (47 downto 0);
signal leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q : std_logic_vector (2 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid98_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid99_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q : std_logic_vector (25 downto 0);
signal reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q : std_logic_vector (5 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (33 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q : std_logic_vector (22 downto 0);
signal ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q : std_logic_vector (0 downto 0);
signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q : std_logic_vector (41 downto 0);
signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q : std_logic_vector (25 downto 0);
signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q : std_logic_vector (9 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q : std_logic_vector (57 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q : std_logic_vector (22 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (41 downto 0);
signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (25 downto 0);
signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (9 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q : std_logic_vector (57 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (23 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (31 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (34 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (22 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (22 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(31 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(31 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(8 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(8 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (8 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (8 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(7 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(7 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(24 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(24 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (24 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (24 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(57 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(57 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (57 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (57 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(9 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(9 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (9 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (9 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (37 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid120_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid120_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid126_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid126_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid138_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid138_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (20 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (20 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (50 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (29 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (35 downto 0);
signal leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b : std_logic_vector (23 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (14 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (14 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (23 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (22 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (31 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (22 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (8 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (2 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (8 downto 0);
signal rVStage_uid114_countZ_uid54_fpLogETest_in : std_logic_vector (57 downto 0);
signal rVStage_uid114_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid117_countZ_uid54_fpLogETest_in : std_logic_vector (25 downto 0);
signal vStage_uid117_countZ_uid54_fpLogETest_b : std_logic_vector (25 downto 0);
signal X41dto0_uid152_normVal_uid55_fpLogETest_in : std_logic_vector (41 downto 0);
signal X41dto0_uid152_normVal_uid55_fpLogETest_b : std_logic_vector (41 downto 0);
signal X9dto0_uid158_normVal_uid55_fpLogETest_in : std_logic_vector (9 downto 0);
signal X9dto0_uid158_normVal_uid55_fpLogETest_b : std_logic_vector (9 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (7 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (36 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (34 downto 0);
signal rVStage_uid122_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid122_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid124_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid124_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid128_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid128_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid130_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid130_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid140_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid140_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid142_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid142_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in : std_logic_vector (55 downto 0);
signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b : std_logic_vector (55 downto 0);
signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b : std_logic_vector (54 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (56 downto 0);
signal lowRangeB_uid102_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid102_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid103_natLogPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid103_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid108_natLogPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid108_natLogPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid109_natLogPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid109_natLogPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid100_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid100_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal cStage_uid118_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid132_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid132_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal FullSumAB56_uid50_fpLogETest_in : std_logic_vector (56 downto 0);
signal FullSumAB56_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid104_natLogPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid110_natLogPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_q : std_logic_vector (31 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal rVStage_uid134_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid134_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid136_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid136_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid146_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid146_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal s1_uid102_uid105_natLogPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid108_uid111_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (56 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (23 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (32 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (25 downto 0);
signal r_uid148_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (33 downto 0);
signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in : std_logic_vector (45 downto 0);
signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b : std_logic_vector (45 downto 0);
signal leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
begin
--xIn(GPIN,3)@0
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(30 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(30 downto 23);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(22 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(22 downto 0);
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(22 downto 15);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0(REG,194)@0
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid99_natLogTabGen_lutmem(DUALMEM,192)@1
memoryC2_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q;
memoryC2_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
width_b => 13,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC2_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid99_natLogTabGen_lutmem_ia
);
memoryC2_uid99_natLogTabGen_lutmem_q <= memoryC2_uid99_natLogTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1(REG,196)@3
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= memoryC2_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a(DELAY,244)@0
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg(DELAY,451)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@3
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q(14 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(14 downto 0);
--yT1_uid100_natLogPolyEval(BITSELECT,99)@3
yT1_uid100_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid100_natLogPolyEval_b <= yT1_uid100_natLogPolyEval_in(14 downto 2);
--reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0(REG,195)@3
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= yT1_uid100_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid185_pT1_uid101_natLogPolyEval(MULT,184)@4
prodXY_uid185_pT1_uid101_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_a),14)) * SIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_b);
prodXY_uid185_pT1_uid101_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_a <= (others => '0');
prodXY_uid185_pT1_uid101_natLogPolyEval_b <= (others => '0');
prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_a <= reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q;
prodXY_uid185_pT1_uid101_natLogPolyEval_b <= reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q;
prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid185_pT1_uid101_natLogPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid185_pT1_uid101_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_q <= prodXY_uid185_pT1_uid101_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval(BITSELECT,185)@7
prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in <= prodXY_uid185_pT1_uid101_natLogPolyEval_q;
prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in(25 downto 12);
--highBBits_uid103_natLogPolyEval(BITSELECT,102)@7
highBBits_uid103_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b;
highBBits_uid103_natLogPolyEval_b <= highBBits_uid103_natLogPolyEval_in(13 downto 1);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a(DELAY,409)@1
ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg(DELAY,482)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid98_natLogTabGen_lutmem(DUALMEM,191)@5
memoryC1_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid98_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q;
memoryC1_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC1_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid98_natLogTabGen_lutmem_ia
);
memoryC1_uid98_natLogTabGen_lutmem_q <= memoryC1_uid98_natLogTabGen_lutmem_iq(20 downto 0);
--sumAHighB_uid104_natLogPolyEval(ADD,103)@7
sumAHighB_uid104_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid98_natLogTabGen_lutmem_q(20)) & memoryC1_uid98_natLogTabGen_lutmem_q);
sumAHighB_uid104_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid103_natLogPolyEval_b(12)) & highBBits_uid103_natLogPolyEval_b);
sumAHighB_uid104_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid104_natLogPolyEval_a) + SIGNED(sumAHighB_uid104_natLogPolyEval_b));
sumAHighB_uid104_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_o(21 downto 0);
--lowRangeB_uid102_natLogPolyEval(BITSELECT,101)@7
lowRangeB_uid102_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b(0 downto 0);
lowRangeB_uid102_natLogPolyEval_b <= lowRangeB_uid102_natLogPolyEval_in(0 downto 0);
--s1_uid102_uid105_natLogPolyEval(BITJOIN,104)@7
s1_uid102_uid105_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_q & lowRangeB_uid102_natLogPolyEval_b;
--reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1(REG,199)@7
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= s1_uid102_uid105_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,447)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor(LOGICAL,504)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg(REG,502)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena(REG,505)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd(LOGICAL,506)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg(DELAY,496)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt(COUNTER,498)
-- every=1, low=0, high=1, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i,1));
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg(REG,499)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux(MUX,500)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem(DUALMEM,497)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0(REG,198)@7
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid188_pT2_uid107_natLogPolyEval(MULT,187)@8
prodXY_uid188_pT2_uid107_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_a),16)) * SIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_b);
prodXY_uid188_pT2_uid107_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_a <= (others => '0');
prodXY_uid188_pT2_uid107_natLogPolyEval_b <= (others => '0');
prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_a <= reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q;
prodXY_uid188_pT2_uid107_natLogPolyEval_b <= reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q;
prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid188_pT2_uid107_natLogPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid188_pT2_uid107_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_q <= prodXY_uid188_pT2_uid107_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval(BITSELECT,188)@11
prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in <= prodXY_uid188_pT2_uid107_natLogPolyEval_q;
prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in(37 downto 14);
--highBBits_uid109_natLogPolyEval(BITSELECT,108)@11
highBBits_uid109_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b;
highBBits_uid109_natLogPolyEval_b <= highBBits_uid109_natLogPolyEval_in(23 downto 2);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor(LOGICAL,479)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top(CONSTANT,475)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q <= "0101";
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp(LOGICAL,476)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q <= "1" when ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a = ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b else "0";
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg(REG,477)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena(REG,480)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd(LOGICAL,481)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt(COUNTER,471)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg(REG,472)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux(MUX,473)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem(DUALMEM,470)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 6,
width_b => 9,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia
);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg(DELAY,469)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,190)@9
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(30 downto 0);
--sumAHighB_uid110_natLogPolyEval(ADD,109)@11
sumAHighB_uid110_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => memoryC0_uid97_natLogTabGen_lutmem_q(30)) & memoryC0_uid97_natLogTabGen_lutmem_q);
sumAHighB_uid110_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid109_natLogPolyEval_b(21)) & highBBits_uid109_natLogPolyEval_b);
sumAHighB_uid110_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_natLogPolyEval_a) + SIGNED(sumAHighB_uid110_natLogPolyEval_b));
sumAHighB_uid110_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_o(31 downto 0);
--lowRangeB_uid108_natLogPolyEval(BITSELECT,107)@11
lowRangeB_uid108_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b(1 downto 0);
lowRangeB_uid108_natLogPolyEval_b <= lowRangeB_uid108_natLogPolyEval_in(1 downto 0);
--s2_uid108_uid111_natLogPolyEval(BITJOIN,110)@11
s2_uid108_uid111_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_q & lowRangeB_uid108_natLogPolyEval_b;
--peOR_uid37_fpLogETest(BITSELECT,36)@11
peOR_uid37_fpLogETest_in <= s2_uid108_uid111_natLogPolyEval_q(32 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(32 downto 7);
--reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1(REG,201)@11
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= peOR_uid37_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor(LOGICAL,462)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q <= not (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a or ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b);
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top(CONSTANT,458)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q <= "01000";
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp(LOGICAL,459)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q <= "1" when ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a = ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b else "0";
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg(REG,460)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena(REG,463)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd(LOGICAL,464)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b <= en;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a and ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@0
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((22 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@0
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & frac_uid19_fpLogETest_b);
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(24 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@0
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & frac_uid19_fpLogETest_b;
--multTermOne_uid42_fpLogETest(MUX,41)@0
multTermOne_uid42_fpLogETest_s <= c_uid31_fpLogETest_q;
multTermOne_uid42_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multTermOne_uid42_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= sEz_uid41_fpLogETest_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt(COUNTER,454)
-- every=1, low=0, high=8, step=1, init=1
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i = 7 THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i - 8;
ELSE
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i,4));
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg(REG,455)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux(MUX,456)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s <= en;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux: PROCESS (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem(DUALMEM,453)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 <= areset;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia <= multTermOne_uid42_fpLogETest_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 4,
numwords_a => 9,
width_b => 25,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq,
address_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa,
data_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia
);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq(24 downto 0);
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg(DELAY,452)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q, xout => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest(MULT,42)@12
postPEMul_uid43_fpLogETest_pr <= SIGNED(postPEMul_uid43_fpLogETest_a) * SIGNED(postPEMul_uid43_fpLogETest_b);
postPEMul_uid43_fpLogETest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a <= (others => '0');
postPEMul_uid43_fpLogETest_b <= (others => '0');
postPEMul_uid43_fpLogETest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q;
postPEMul_uid43_fpLogETest_b <= reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q;
postPEMul_uid43_fpLogETest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_q <= postPEMul_uid43_fpLogETest_s1;
END IF;
END IF;
END PROCESS;
--highBBits_uid47_fpLogETest(BITSELECT,46)@15
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_q;
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(50 downto 21);
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "00000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,448)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,444)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "01011";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,445)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,446)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,449)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,450)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 10 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 11;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,4));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,441)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,442)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,439)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= expX_uid6_fpLogETest_b;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(7 downto 0);
--e_uid29_fpLogETest(SUB,28)@13
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(8 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@13
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--p0_uid93_constMult(LOOKUP,92)@13
p0_uid93_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p0_uid93_constMult_q <= "0000000000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (xv0_uid90_constMult_b) IS
WHEN "000000" => p0_uid93_constMult_q <= "0000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "0000001011000101110010000110000000";
WHEN "000010" => p0_uid93_constMult_q <= "0000010110001011100100001100000000";
WHEN "000011" => p0_uid93_constMult_q <= "0000100001010001010110010010000000";
WHEN "000100" => p0_uid93_constMult_q <= "0000101100010111001000011000000000";
WHEN "000101" => p0_uid93_constMult_q <= "0000110111011100111010011110000000";
WHEN "000110" => p0_uid93_constMult_q <= "0001000010100010101100100100000000";
WHEN "000111" => p0_uid93_constMult_q <= "0001001101101000011110101010000000";
WHEN "001000" => p0_uid93_constMult_q <= "0001011000101110010000110000000000";
WHEN "001001" => p0_uid93_constMult_q <= "0001100011110100000010110110000000";
WHEN "001010" => p0_uid93_constMult_q <= "0001101110111001110100111100000000";
WHEN "001011" => p0_uid93_constMult_q <= "0001111001111111100111000010000000";
WHEN "001100" => p0_uid93_constMult_q <= "0010000101000101011001001000000000";
WHEN "001101" => p0_uid93_constMult_q <= "0010010000001011001011001110000000";
WHEN "001110" => p0_uid93_constMult_q <= "0010011011010000111101010100000000";
WHEN "001111" => p0_uid93_constMult_q <= "0010100110010110101111011010000000";
WHEN "010000" => p0_uid93_constMult_q <= "0010110001011100100001100000000000";
WHEN "010001" => p0_uid93_constMult_q <= "0010111100100010010011100110000000";
WHEN "010010" => p0_uid93_constMult_q <= "0011000111101000000101101100000000";
WHEN "010011" => p0_uid93_constMult_q <= "0011010010101101110111110010000000";
WHEN "010100" => p0_uid93_constMult_q <= "0011011101110011101001111000000000";
WHEN "010101" => p0_uid93_constMult_q <= "0011101000111001011011111110000000";
WHEN "010110" => p0_uid93_constMult_q <= "0011110011111111001110000100000000";
WHEN "010111" => p0_uid93_constMult_q <= "0011111111000101000000001010000000";
WHEN "011000" => p0_uid93_constMult_q <= "0100001010001010110010010000000000";
WHEN "011001" => p0_uid93_constMult_q <= "0100010101010000100100010110000000";
WHEN "011010" => p0_uid93_constMult_q <= "0100100000010110010110011100000000";
WHEN "011011" => p0_uid93_constMult_q <= "0100101011011100001000100010000000";
WHEN "011100" => p0_uid93_constMult_q <= "0100110110100001111010101000000000";
WHEN "011101" => p0_uid93_constMult_q <= "0101000001100111101100101110000000";
WHEN "011110" => p0_uid93_constMult_q <= "0101001100101101011110110100000000";
WHEN "011111" => p0_uid93_constMult_q <= "0101010111110011010000111010000000";
WHEN "100000" => p0_uid93_constMult_q <= "0101100010111001000011000000000000";
WHEN "100001" => p0_uid93_constMult_q <= "0101101101111110110101000110000000";
WHEN "100010" => p0_uid93_constMult_q <= "0101111001000100100111001100000000";
WHEN "100011" => p0_uid93_constMult_q <= "0110000100001010011001010010000000";
WHEN "100100" => p0_uid93_constMult_q <= "0110001111010000001011011000000000";
WHEN "100101" => p0_uid93_constMult_q <= "0110011010010101111101011110000000";
WHEN "100110" => p0_uid93_constMult_q <= "0110100101011011101111100100000000";
WHEN "100111" => p0_uid93_constMult_q <= "0110110000100001100001101010000000";
WHEN "101000" => p0_uid93_constMult_q <= "0110111011100111010011110000000000";
WHEN "101001" => p0_uid93_constMult_q <= "0111000110101101000101110110000000";
WHEN "101010" => p0_uid93_constMult_q <= "0111010001110010110111111100000000";
WHEN "101011" => p0_uid93_constMult_q <= "0111011100111000101010000010000000";
WHEN "101100" => p0_uid93_constMult_q <= "0111100111111110011100001000000000";
WHEN "101101" => p0_uid93_constMult_q <= "0111110011000100001110001110000000";
WHEN "101110" => p0_uid93_constMult_q <= "0111111110001010000000010100000000";
WHEN "101111" => p0_uid93_constMult_q <= "1000001001001111110010011010000000";
WHEN "110000" => p0_uid93_constMult_q <= "1000010100010101100100100000000000";
WHEN "110001" => p0_uid93_constMult_q <= "1000011111011011010110100110000000";
WHEN "110010" => p0_uid93_constMult_q <= "1000101010100001001000101100000000";
WHEN "110011" => p0_uid93_constMult_q <= "1000110101100110111010110010000000";
WHEN "110100" => p0_uid93_constMult_q <= "1001000000101100101100111000000000";
WHEN "110101" => p0_uid93_constMult_q <= "1001001011110010011110111110000000";
WHEN "110110" => p0_uid93_constMult_q <= "1001010110111000010001000100000000";
WHEN "110111" => p0_uid93_constMult_q <= "1001100001111110000011001010000000";
WHEN "111000" => p0_uid93_constMult_q <= "1001101101000011110101010000000000";
WHEN "111001" => p0_uid93_constMult_q <= "1001111000001001100111010110000000";
WHEN "111010" => p0_uid93_constMult_q <= "1010000011001111011001011100000000";
WHEN "111011" => p0_uid93_constMult_q <= "1010001110010101001011100010000000";
WHEN "111100" => p0_uid93_constMult_q <= "1010011001011010111101101000000000";
WHEN "111101" => p0_uid93_constMult_q <= "1010100100100000101111101110000000";
WHEN "111110" => p0_uid93_constMult_q <= "1010101111100110100001110100000000";
WHEN "111111" => p0_uid93_constMult_q <= "1010111010101100010011111010000000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "0000000000000000000000000000000000";
END CASE;
END IF;
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@13
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(8 downto 6);
--p1_uid92_constMult(LOOKUP,91)@13
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (xv1_uid91_constMult_b) IS
WHEN "000" => p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
WHEN "001" => p1_uid92_constMult_q <= "0001011000101110010000110000000000000";
WHEN "010" => p1_uid92_constMult_q <= "0010110001011100100001100000000000000";
WHEN "011" => p1_uid92_constMult_q <= "0100001010001010110010010000000000000";
WHEN "100" => p1_uid92_constMult_q <= "1010011101000110111101000000000000000";
WHEN "101" => p1_uid92_constMult_q <= "1011110101110101001101110000000000000";
WHEN "110" => p1_uid92_constMult_q <= "1101001110100011011110100000000000000";
WHEN "111" => p1_uid92_constMult_q <= "1110100111010001101111010000000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
END CASE;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@14
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid92_constMult_q(36)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(37 downto 0);
--sR_uid95_constMult(BITSELECT,94)@14
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(36 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(36 downto 2);
--ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b(DELAY,254)@0
ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid45_fpLogETest(MUX,44)@14
addTermOne_uid45_fpLogETest_s <= ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= sR_uid95_constMult_b;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@15
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid45_fpLogETest_q(34)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid47_fpLogETest_b(29)) & highBBits_uid47_fpLogETest_b);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(35 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@15
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_q(20 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(20 downto 0);
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@15
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & lowRangeB_uid46_fpLogETest_b;
--FullSumAB56_uid50_fpLogETest(BITSELECT,49)@15
FullSumAB56_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB56_uid50_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_in(56 downto 56);
--notC_uid71_fpLogETest(LOGICAL,70)@15
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@15
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a(DELAY,285)@0
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRC1_uid73_fpLogETest(LOGICAL,72)@15
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRC1_uid73_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRC1_uid73_fpLogETest_q <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
END IF;
END PROCESS;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "00000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
exc_R_uid27_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
exc_R_uid27_fpLogETest_q <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a(DELAY,290)@1
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRC11_uid74_fpLogETest(LOGICAL,73)@16
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,220)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a(DELAY,292)@1
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid75_fpLogETest(LOGICAL,74)@16
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(31 downto 31);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a(DELAY,294)@0
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@15
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q;
InvExcRNaN_uid76_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid76_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid76_fpLogETest_q <= not InvExcRNaN_uid76_fpLogETest_a;
END IF;
END PROCESS;
--signRFull_uid77_fpLogETest(LOGICAL,76)@16
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,307)@16
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid113_countZ_uid54_fpLogETest(CONSTANT,112)
zs_uid113_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,266)@15
ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB56_uid50_fpLogETest_b, xout => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@15
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((56 downto 1 => FullSumAB56_uid50_fpLogETest_b(0)) & FullSumAB56_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
finalSumOneComp_uid52_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
finalSumOneComp_uid52_fpLogETest_q <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
END IF;
END PROCESS;
--finalSumAbs_uid53_fpLogETest(ADD,52)@16
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((57 downto 57 => finalSumOneComp_uid52_fpLogETest_q(56)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((57 downto 1 => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(57 downto 0);
--rVStage_uid114_countZ_uid54_fpLogETest(BITSELECT,113)@16
rVStage_uid114_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid114_countZ_uid54_fpLogETest_b <= rVStage_uid114_countZ_uid54_fpLogETest_in(57 downto 26);
--reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1(REG,202)@16
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= rVStage_uid114_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid115_countZ_uid54_fpLogETest(LOGICAL,114)@17
vCount_uid115_countZ_uid54_fpLogETest_a <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q;
vCount_uid115_countZ_uid54_fpLogETest_b <= zs_uid113_countZ_uid54_fpLogETest_q;
vCount_uid115_countZ_uid54_fpLogETest_q <= "1" when vCount_uid115_countZ_uid54_fpLogETest_a = vCount_uid115_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f(DELAY,366)@17
ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid115_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid121_countZ_uid54_fpLogETest(CONSTANT,120)
zs_uid121_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid117_countZ_uid54_fpLogETest(BITSELECT,116)@16
vStage_uid117_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(25 downto 0);
vStage_uid117_countZ_uid54_fpLogETest_b <= vStage_uid117_countZ_uid54_fpLogETest_in(25 downto 0);
--mO_uid116_countZ_uid54_fpLogETest(CONSTANT,115)
mO_uid116_countZ_uid54_fpLogETest_q <= "111111";
--cStage_uid118_countZ_uid54_fpLogETest(BITJOIN,117)@16
cStage_uid118_countZ_uid54_fpLogETest_q <= vStage_uid117_countZ_uid54_fpLogETest_b & mO_uid116_countZ_uid54_fpLogETest_q;
--reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3(REG,204)@16
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= cStage_uid118_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid120_countZ_uid54_fpLogETest(MUX,119)@17
vStagei_uid120_countZ_uid54_fpLogETest_s <= vCount_uid115_countZ_uid54_fpLogETest_q;
vStagei_uid120_countZ_uid54_fpLogETest: PROCESS (vStagei_uid120_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q, reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid120_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid120_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid122_countZ_uid54_fpLogETest(BITSELECT,121)@17
rVStage_uid122_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q;
rVStage_uid122_countZ_uid54_fpLogETest_b <= rVStage_uid122_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1(REG,205)@17
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= rVStage_uid122_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid123_countZ_uid54_fpLogETest(LOGICAL,122)@18
vCount_uid123_countZ_uid54_fpLogETest_a <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q;
vCount_uid123_countZ_uid54_fpLogETest_b <= zs_uid121_countZ_uid54_fpLogETest_q;
vCount_uid123_countZ_uid54_fpLogETest_q <= "1" when vCount_uid123_countZ_uid54_fpLogETest_a = vCount_uid123_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e(DELAY,365)@18
ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid123_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid124_countZ_uid54_fpLogETest(BITSELECT,123)@17
vStage_uid124_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid124_countZ_uid54_fpLogETest_b <= vStage_uid124_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3(REG,207)@17
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= vStage_uid124_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid126_countZ_uid54_fpLogETest(MUX,125)@18
vStagei_uid126_countZ_uid54_fpLogETest_s <= vCount_uid123_countZ_uid54_fpLogETest_q;
vStagei_uid126_countZ_uid54_fpLogETest: PROCESS (vStagei_uid126_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q, reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid126_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid126_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid128_countZ_uid54_fpLogETest(BITSELECT,127)@18
rVStage_uid128_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q;
rVStage_uid128_countZ_uid54_fpLogETest_b <= rVStage_uid128_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid129_countZ_uid54_fpLogETest(LOGICAL,128)@18
vCount_uid129_countZ_uid54_fpLogETest_a <= rVStage_uid128_countZ_uid54_fpLogETest_b;
vCount_uid129_countZ_uid54_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
vCount_uid129_countZ_uid54_fpLogETest_q <= "1" when vCount_uid129_countZ_uid54_fpLogETest_a = vCount_uid129_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3(REG,211)@18
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= vCount_uid129_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--zs_uid133_countZ_uid54_fpLogETest(CONSTANT,132)
zs_uid133_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid130_countZ_uid54_fpLogETest(BITSELECT,129)@18
vStage_uid130_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid130_countZ_uid54_fpLogETest_b <= vStage_uid130_countZ_uid54_fpLogETest_in(7 downto 0);
--vStagei_uid132_countZ_uid54_fpLogETest(MUX,131)@18
vStagei_uid132_countZ_uid54_fpLogETest_s <= vCount_uid129_countZ_uid54_fpLogETest_q;
vStagei_uid132_countZ_uid54_fpLogETest: PROCESS (vStagei_uid132_countZ_uid54_fpLogETest_s, en, rVStage_uid128_countZ_uid54_fpLogETest_b, vStage_uid130_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid132_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid132_countZ_uid54_fpLogETest_q <= rVStage_uid128_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid132_countZ_uid54_fpLogETest_q <= vStage_uid130_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid132_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid134_countZ_uid54_fpLogETest(BITSELECT,133)@18
rVStage_uid134_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q;
rVStage_uid134_countZ_uid54_fpLogETest_b <= rVStage_uid134_countZ_uid54_fpLogETest_in(7 downto 4);
--reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1(REG,208)@18
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= rVStage_uid134_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid135_countZ_uid54_fpLogETest(LOGICAL,134)@19
vCount_uid135_countZ_uid54_fpLogETest_a <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q;
vCount_uid135_countZ_uid54_fpLogETest_b <= zs_uid133_countZ_uid54_fpLogETest_q;
vCount_uid135_countZ_uid54_fpLogETest_q <= "1" when vCount_uid135_countZ_uid54_fpLogETest_a = vCount_uid135_countZ_uid54_fpLogETest_b else "0";
--vStage_uid136_countZ_uid54_fpLogETest(BITSELECT,135)@18
vStage_uid136_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid136_countZ_uid54_fpLogETest_b <= vStage_uid136_countZ_uid54_fpLogETest_in(3 downto 0);
--reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3(REG,210)@18
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= vStage_uid136_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid138_countZ_uid54_fpLogETest(MUX,137)@19
vStagei_uid138_countZ_uid54_fpLogETest_s <= vCount_uid135_countZ_uid54_fpLogETest_q;
vStagei_uid138_countZ_uid54_fpLogETest: PROCESS (vStagei_uid138_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q, reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid138_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid138_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid140_countZ_uid54_fpLogETest(BITSELECT,139)@19
rVStage_uid140_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q;
rVStage_uid140_countZ_uid54_fpLogETest_b <= rVStage_uid140_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid141_countZ_uid54_fpLogETest(LOGICAL,140)@19
vCount_uid141_countZ_uid54_fpLogETest_a <= rVStage_uid140_countZ_uid54_fpLogETest_b;
vCount_uid141_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid141_countZ_uid54_fpLogETest_q <= "1" when vCount_uid141_countZ_uid54_fpLogETest_a = vCount_uid141_countZ_uid54_fpLogETest_b else "0";
--vStage_uid142_countZ_uid54_fpLogETest(BITSELECT,141)@19
vStage_uid142_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid142_countZ_uid54_fpLogETest_b <= vStage_uid142_countZ_uid54_fpLogETest_in(1 downto 0);
--vStagei_uid144_countZ_uid54_fpLogETest(MUX,143)@19
vStagei_uid144_countZ_uid54_fpLogETest_s <= vCount_uid141_countZ_uid54_fpLogETest_q;
vStagei_uid144_countZ_uid54_fpLogETest: PROCESS (vStagei_uid144_countZ_uid54_fpLogETest_s, en, rVStage_uid140_countZ_uid54_fpLogETest_b, vStage_uid142_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid144_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid144_countZ_uid54_fpLogETest_q <= rVStage_uid140_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid144_countZ_uid54_fpLogETest_q <= vStage_uid142_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid144_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_countZ_uid54_fpLogETest(BITSELECT,145)@19
rVStage_uid146_countZ_uid54_fpLogETest_in <= vStagei_uid144_countZ_uid54_fpLogETest_q;
rVStage_uid146_countZ_uid54_fpLogETest_b <= rVStage_uid146_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid147_countZ_uid54_fpLogETest(LOGICAL,146)@19
vCount_uid147_countZ_uid54_fpLogETest_a <= rVStage_uid146_countZ_uid54_fpLogETest_b;
vCount_uid147_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid147_countZ_uid54_fpLogETest_q <= "1" when vCount_uid147_countZ_uid54_fpLogETest_a = vCount_uid147_countZ_uid54_fpLogETest_b else "0";
--r_uid148_countZ_uid54_fpLogETest(BITJOIN,147)@19
r_uid148_countZ_uid54_fpLogETest_q <= ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q & ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q & reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q & vCount_uid135_countZ_uid54_fpLogETest_q & vCount_uid141_countZ_uid54_fpLogETest_q & vCount_uid147_countZ_uid54_fpLogETest_q;
--reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1(REG,218)@19
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= r_uid148_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010001001";
--expRExt_uid57_fpLogETest(SUB,56)@20
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("0000" & reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q);
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(9 downto 0);
--LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest(BITSELECT,179)@20
LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(54 downto 0);
LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in(54 downto 0);
--leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest(CONSTANT,178)
leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q <= "000";
--leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest(BITJOIN,180)@20
leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b & leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q;
--LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest(BITSELECT,176)@20
LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(55 downto 0);
LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in(55 downto 0);
--leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest(BITJOIN,177)@20
leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b & z2_uid40_fpLogETest_q;
--LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest(BITSELECT,173)@20
LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(56 downto 0);
LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in(56 downto 0);
--leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest(BITJOIN,174)@20
leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b & GND_q;
--X9dto0_uid158_normVal_uid55_fpLogETest(BITSELECT,157)@16
X9dto0_uid158_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(9 downto 0);
X9dto0_uid158_normVal_uid55_fpLogETest_b <= X9dto0_uid158_normVal_uid55_fpLogETest_in(9 downto 0);
--ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg(DELAY,467)
ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => X9dto0_uid158_normVal_uid55_fpLogETest_b, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b(DELAY,371)@16
ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 2 )
PORT MAP ( xin => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest(CONSTANT,156)
leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest(BITJOIN,158)@19
leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q <= ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q & leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q;
--ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg(DELAY,466)
ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => vStage_uid117_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b(DELAY,369)@16
ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 26, depth => 2 )
PORT MAP ( xin => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest(BITJOIN,155)@19
leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q <= ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q & zs_uid113_countZ_uid54_fpLogETest_q;
--X41dto0_uid152_normVal_uid55_fpLogETest(BITSELECT,151)@16
X41dto0_uid152_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(41 downto 0);
X41dto0_uid152_normVal_uid55_fpLogETest_b <= X41dto0_uid152_normVal_uid55_fpLogETest_in(41 downto 0);
--ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg(DELAY,465)
ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => X41dto0_uid152_normVal_uid55_fpLogETest_b, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b(DELAY,368)@16
ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 42, depth => 2 )
PORT MAP ( xin => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest(BITJOIN,152)@19
leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q <= ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q & zs_uid121_countZ_uid54_fpLogETest_q;
--ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg(DELAY,468)
ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c(DELAY,374)@16
ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 58, depth => 2 )
PORT MAP ( xin => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest(BITSELECT,159)@19
leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q;
leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in(5 downto 4);
--leftShiftStage0_uid161_normVal_uid55_fpLogETest(MUX,160)@19
leftShiftStage0_uid161_normVal_uid55_fpLogETest_s <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid161_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid161_normVal_uid55_fpLogETest_s, en, ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q, leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q, leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage0_uid161_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q;
WHEN "01" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest(BITSELECT,168)@19
LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(45 downto 0);
LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in(45 downto 0);
--leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest(CONSTANT,167)
leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q <= "000000000000";
--leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest(BITJOIN,169)@19
leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5(REG,216)@19
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest(BITSELECT,165)@19
LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(49 downto 0);
LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in(49 downto 0);
--leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest(BITJOIN,166)@19
leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b & cstAllZWE_uid14_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4(REG,215)@19
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest(BITSELECT,162)@19
LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(53 downto 0);
LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in(53 downto 0);
--leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest(BITJOIN,163)@19
leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b & zs_uid133_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3(REG,214)@19
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2(REG,213)@19
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest(BITSELECT,170)@19
leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(3 downto 0);
leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1(REG,212)@19
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid172_normVal_uid55_fpLogETest(MUX,171)@20
leftShiftStage1_uid172_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid172_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid172_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid172_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest(BITSELECT,181)@19
leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(1 downto 0);
leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1(REG,217)@19
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid183_normVal_uid55_fpLogETest(MUX,182)@20
leftShiftStage2_uid183_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q;
leftShiftStage2_uid183_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid183_normVal_uid55_fpLogETest_s, en, leftShiftStage1_uid172_normVal_uid55_fpLogETest_q, leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid183_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q;
WHEN "01" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@20
fracR_uid58_fpLogETest_in <= leftShiftStage2_uid183_normVal_uid55_fpLogETest_q(56 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(56 downto 33);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@20
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,219)@20
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@21
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(34 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@21
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(31 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(31 downto 24);
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor(LOGICAL,493)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q <= not (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a or ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b);
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top(CONSTANT,489)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q <= "010001";
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp(LOGICAL,490)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q <= "1" when ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a = ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b else "0";
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg(REG,491)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena(REG,494)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd(LOGICAL,495)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b <= en;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a and ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg(DELAY,483)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid78_fpLogETest_q, xout => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt(COUNTER,485)
-- every=1, low=0, high=17, step=1, init=1
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i = 16 THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i - 17;
ELSE
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i,5));
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg(REG,486)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux(MUX,487)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s <= en;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux: PROCESS (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem(DUALMEM,484)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 <= areset;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq,
address_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa,
data_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia
);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq(2 downto 0);
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,193)@20
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid79_fpLogETest(LOOKUP,78)@21
excREnc_uid79_fpLogETest: PROCESS (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@21
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, expR_uid62_fpLogETest_b, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= expR_uid62_fpLogETest_b;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "00000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@21
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(23 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(23 downto 1);
--fracRPostExc_uid83_fpLogETest(MUX,82)@21
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, fracR_uid61_fpLogETest_b, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= fracR_uid61_fpLogETest_b;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@21
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@21
q <= RLn_uid88_fpLogETest_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_ln_s5.vhd
|
10
|
195654
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_s5
-- VHDL created on Wed Feb 27 15:13:10 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1248
entity fp_ln_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (22 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (7 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (24 downto 0);
signal postPEMul_uid43_fpLogETest_a : std_logic_vector (24 downto 0);
signal postPEMul_uid43_fpLogETest_b : std_logic_vector (25 downto 0);
signal postPEMul_uid43_fpLogETest_s1 : std_logic_vector (50 downto 0);
signal postPEMul_uid43_fpLogETest_pr : SIGNED (50 downto 0);
signal postPEMul_uid43_fpLogETest_q : std_logic_vector (50 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (34 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (34 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(56 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(56 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(56 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (8 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (22 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(36 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(33 downto 0);
signal zs_uid113_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal mO_uid116_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0);
signal zs_uid121_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid133_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q : std_logic_vector (47 downto 0);
signal leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q : std_logic_vector (2 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid185_pT1_uid101_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid188_pT2_uid107_natLogPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid98_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid98_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid99_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid99_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q : std_logic_vector (25 downto 0);
signal reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q : std_logic_vector (57 downto 0);
signal reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q : std_logic_vector (5 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (33 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q : std_logic_vector (22 downto 0);
signal ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q : std_logic_vector (0 downto 0);
signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q : std_logic_vector (41 downto 0);
signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q : std_logic_vector (25 downto 0);
signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q : std_logic_vector (9 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q : std_logic_vector (57 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q : std_logic_vector (22 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (41 downto 0);
signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (25 downto 0);
signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (9 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q : std_logic_vector (57 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (23 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (31 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (34 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (34 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (22 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (22 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(31 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(31 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(8 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(8 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (8 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (8 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(7 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(7 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(24 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(24 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (24 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (24 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(57 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(57 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (57 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (57 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(9 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(9 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (9 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (9 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (37 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid115_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid120_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid120_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid123_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid126_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid126_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid135_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid138_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid138_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (20 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (20 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (50 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (29 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (35 downto 0);
signal leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b : std_logic_vector (23 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (14 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (14 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (23 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (22 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (31 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (22 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (8 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (2 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (8 downto 0);
signal rVStage_uid114_countZ_uid54_fpLogETest_in : std_logic_vector (57 downto 0);
signal rVStage_uid114_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid117_countZ_uid54_fpLogETest_in : std_logic_vector (25 downto 0);
signal vStage_uid117_countZ_uid54_fpLogETest_b : std_logic_vector (25 downto 0);
signal X41dto0_uid152_normVal_uid55_fpLogETest_in : std_logic_vector (41 downto 0);
signal X41dto0_uid152_normVal_uid55_fpLogETest_b : std_logic_vector (41 downto 0);
signal X9dto0_uid158_normVal_uid55_fpLogETest_in : std_logic_vector (9 downto 0);
signal X9dto0_uid158_normVal_uid55_fpLogETest_b : std_logic_vector (9 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (7 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (36 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (34 downto 0);
signal rVStage_uid122_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid122_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid124_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid124_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid128_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid128_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid130_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid130_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid140_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid140_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid142_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid142_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in : std_logic_vector (55 downto 0);
signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b : std_logic_vector (55 downto 0);
signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b : std_logic_vector (54 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (56 downto 0);
signal lowRangeB_uid102_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid102_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid103_natLogPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid103_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid108_natLogPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid108_natLogPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid109_natLogPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid109_natLogPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid100_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid100_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal cStage_uid118_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid129_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid132_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid132_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid141_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal FullSumAB56_uid50_fpLogETest_in : std_logic_vector (56 downto 0);
signal FullSumAB56_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid104_natLogPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid104_natLogPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid110_natLogPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid110_natLogPolyEval_q : std_logic_vector (31 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal rVStage_uid134_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid134_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid136_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid136_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid146_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid146_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal s1_uid102_uid105_natLogPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid108_uid111_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid147_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (56 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (23 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (32 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (25 downto 0);
signal r_uid148_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (33 downto 0);
signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in : std_logic_vector (45 downto 0);
signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b : std_logic_vector (45 downto 0);
signal leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
signal leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0);
begin
--xIn(GPIN,3)@0
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(30 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(30 downto 23);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(22 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(22 downto 0);
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(22 downto 15);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0(REG,194)@0
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid99_natLogTabGen_lutmem(DUALMEM,192)@1
memoryC2_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q;
memoryC2_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
width_b => 13,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC2_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid99_natLogTabGen_lutmem_ia
);
memoryC2_uid99_natLogTabGen_lutmem_q <= memoryC2_uid99_natLogTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1(REG,196)@3
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= memoryC2_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a(DELAY,244)@0
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg(DELAY,451)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@3
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q(14 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(14 downto 0);
--yT1_uid100_natLogPolyEval(BITSELECT,99)@3
yT1_uid100_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid100_natLogPolyEval_b <= yT1_uid100_natLogPolyEval_in(14 downto 2);
--reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0(REG,195)@3
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= yT1_uid100_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid185_pT1_uid101_natLogPolyEval(MULT,184)@4
prodXY_uid185_pT1_uid101_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_a),14)) * SIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_b);
prodXY_uid185_pT1_uid101_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_a <= (others => '0');
prodXY_uid185_pT1_uid101_natLogPolyEval_b <= (others => '0');
prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_a <= reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q;
prodXY_uid185_pT1_uid101_natLogPolyEval_b <= reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q;
prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid185_pT1_uid101_natLogPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid185_pT1_uid101_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid185_pT1_uid101_natLogPolyEval_q <= prodXY_uid185_pT1_uid101_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval(BITSELECT,185)@7
prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in <= prodXY_uid185_pT1_uid101_natLogPolyEval_q;
prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in(25 downto 12);
--highBBits_uid103_natLogPolyEval(BITSELECT,102)@7
highBBits_uid103_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b;
highBBits_uid103_natLogPolyEval_b <= highBBits_uid103_natLogPolyEval_in(13 downto 1);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a(DELAY,409)@1
ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg(DELAY,482)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid98_natLogTabGen_lutmem(DUALMEM,191)@5
memoryC1_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid98_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q;
memoryC1_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC1_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid98_natLogTabGen_lutmem_ia
);
memoryC1_uid98_natLogTabGen_lutmem_q <= memoryC1_uid98_natLogTabGen_lutmem_iq(20 downto 0);
--sumAHighB_uid104_natLogPolyEval(ADD,103)@7
sumAHighB_uid104_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid98_natLogTabGen_lutmem_q(20)) & memoryC1_uid98_natLogTabGen_lutmem_q);
sumAHighB_uid104_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid103_natLogPolyEval_b(12)) & highBBits_uid103_natLogPolyEval_b);
sumAHighB_uid104_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid104_natLogPolyEval_a) + SIGNED(sumAHighB_uid104_natLogPolyEval_b));
sumAHighB_uid104_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_o(21 downto 0);
--lowRangeB_uid102_natLogPolyEval(BITSELECT,101)@7
lowRangeB_uid102_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b(0 downto 0);
lowRangeB_uid102_natLogPolyEval_b <= lowRangeB_uid102_natLogPolyEval_in(0 downto 0);
--s1_uid102_uid105_natLogPolyEval(BITJOIN,104)@7
s1_uid102_uid105_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_q & lowRangeB_uid102_natLogPolyEval_b;
--reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1(REG,199)@7
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= s1_uid102_uid105_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,447)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor(LOGICAL,504)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg(REG,502)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena(REG,505)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd(LOGICAL,506)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg(DELAY,496)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt(COUNTER,498)
-- every=1, low=0, high=1, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i,1));
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg(REG,499)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux(MUX,500)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem(DUALMEM,497)
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0(REG,198)@7
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid188_pT2_uid107_natLogPolyEval(MULT,187)@8
prodXY_uid188_pT2_uid107_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_a),16)) * SIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_b);
prodXY_uid188_pT2_uid107_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_a <= (others => '0');
prodXY_uid188_pT2_uid107_natLogPolyEval_b <= (others => '0');
prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_a <= reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q;
prodXY_uid188_pT2_uid107_natLogPolyEval_b <= reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q;
prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid188_pT2_uid107_natLogPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid188_pT2_uid107_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid188_pT2_uid107_natLogPolyEval_q <= prodXY_uid188_pT2_uid107_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval(BITSELECT,188)@11
prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in <= prodXY_uid188_pT2_uid107_natLogPolyEval_q;
prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in(37 downto 14);
--highBBits_uid109_natLogPolyEval(BITSELECT,108)@11
highBBits_uid109_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b;
highBBits_uid109_natLogPolyEval_b <= highBBits_uid109_natLogPolyEval_in(23 downto 2);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor(LOGICAL,479)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top(CONSTANT,475)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q <= "0101";
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp(LOGICAL,476)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q <= "1" when ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a = ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b else "0";
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg(REG,477)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena(REG,480)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd(LOGICAL,481)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt(COUNTER,471)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg(REG,472)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux(MUX,473)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem(DUALMEM,470)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q;
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 6,
width_b => 9,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia
);
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg(DELAY,469)
ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,190)@9
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(30 downto 0);
--sumAHighB_uid110_natLogPolyEval(ADD,109)@11
sumAHighB_uid110_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => memoryC0_uid97_natLogTabGen_lutmem_q(30)) & memoryC0_uid97_natLogTabGen_lutmem_q);
sumAHighB_uid110_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid109_natLogPolyEval_b(21)) & highBBits_uid109_natLogPolyEval_b);
sumAHighB_uid110_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_natLogPolyEval_a) + SIGNED(sumAHighB_uid110_natLogPolyEval_b));
sumAHighB_uid110_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_o(31 downto 0);
--lowRangeB_uid108_natLogPolyEval(BITSELECT,107)@11
lowRangeB_uid108_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b(1 downto 0);
lowRangeB_uid108_natLogPolyEval_b <= lowRangeB_uid108_natLogPolyEval_in(1 downto 0);
--s2_uid108_uid111_natLogPolyEval(BITJOIN,110)@11
s2_uid108_uid111_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_q & lowRangeB_uid108_natLogPolyEval_b;
--peOR_uid37_fpLogETest(BITSELECT,36)@11
peOR_uid37_fpLogETest_in <= s2_uid108_uid111_natLogPolyEval_q(32 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(32 downto 7);
--reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1(REG,201)@11
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= peOR_uid37_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor(LOGICAL,462)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q <= not (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a or ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b);
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top(CONSTANT,458)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q <= "01000";
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp(LOGICAL,459)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q <= "1" when ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a = ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b else "0";
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg(REG,460)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena(REG,463)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd(LOGICAL,464)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b <= en;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a and ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@0
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((22 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@0
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & frac_uid19_fpLogETest_b);
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(24 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@0
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & frac_uid19_fpLogETest_b;
--multTermOne_uid42_fpLogETest(MUX,41)@0
multTermOne_uid42_fpLogETest_s <= c_uid31_fpLogETest_q;
multTermOne_uid42_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multTermOne_uid42_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= sEz_uid41_fpLogETest_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt(COUNTER,454)
-- every=1, low=0, high=8, step=1, init=1
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i = 7 THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i - 8;
ELSE
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i,4));
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg(REG,455)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux(MUX,456)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s <= en;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux: PROCESS (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem(DUALMEM,453)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 <= areset;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia <= multTermOne_uid42_fpLogETest_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q;
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 4,
numwords_a => 9,
width_b => 25,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq,
address_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa,
data_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia
);
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq(24 downto 0);
--ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg(DELAY,452)
ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q, xout => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest(MULT,42)@12
postPEMul_uid43_fpLogETest_pr <= SIGNED(postPEMul_uid43_fpLogETest_a) * SIGNED(postPEMul_uid43_fpLogETest_b);
postPEMul_uid43_fpLogETest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a <= (others => '0');
postPEMul_uid43_fpLogETest_b <= (others => '0');
postPEMul_uid43_fpLogETest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q;
postPEMul_uid43_fpLogETest_b <= reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q;
postPEMul_uid43_fpLogETest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_q <= postPEMul_uid43_fpLogETest_s1;
END IF;
END IF;
END PROCESS;
--highBBits_uid47_fpLogETest(BITSELECT,46)@15
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_q;
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(50 downto 21);
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "00000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,448)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,444)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "01011";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,445)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,446)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,449)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,450)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 10 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 11;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,4));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,441)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,442)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,439)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= expX_uid6_fpLogETest_b;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(7 downto 0);
--e_uid29_fpLogETest(SUB,28)@13
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(8 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@13
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--p0_uid93_constMult(LOOKUP,92)@13
p0_uid93_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p0_uid93_constMult_q <= "0000000000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (xv0_uid90_constMult_b) IS
WHEN "000000" => p0_uid93_constMult_q <= "0000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "0000001011000101110010000110000000";
WHEN "000010" => p0_uid93_constMult_q <= "0000010110001011100100001100000000";
WHEN "000011" => p0_uid93_constMult_q <= "0000100001010001010110010010000000";
WHEN "000100" => p0_uid93_constMult_q <= "0000101100010111001000011000000000";
WHEN "000101" => p0_uid93_constMult_q <= "0000110111011100111010011110000000";
WHEN "000110" => p0_uid93_constMult_q <= "0001000010100010101100100100000000";
WHEN "000111" => p0_uid93_constMult_q <= "0001001101101000011110101010000000";
WHEN "001000" => p0_uid93_constMult_q <= "0001011000101110010000110000000000";
WHEN "001001" => p0_uid93_constMult_q <= "0001100011110100000010110110000000";
WHEN "001010" => p0_uid93_constMult_q <= "0001101110111001110100111100000000";
WHEN "001011" => p0_uid93_constMult_q <= "0001111001111111100111000010000000";
WHEN "001100" => p0_uid93_constMult_q <= "0010000101000101011001001000000000";
WHEN "001101" => p0_uid93_constMult_q <= "0010010000001011001011001110000000";
WHEN "001110" => p0_uid93_constMult_q <= "0010011011010000111101010100000000";
WHEN "001111" => p0_uid93_constMult_q <= "0010100110010110101111011010000000";
WHEN "010000" => p0_uid93_constMult_q <= "0010110001011100100001100000000000";
WHEN "010001" => p0_uid93_constMult_q <= "0010111100100010010011100110000000";
WHEN "010010" => p0_uid93_constMult_q <= "0011000111101000000101101100000000";
WHEN "010011" => p0_uid93_constMult_q <= "0011010010101101110111110010000000";
WHEN "010100" => p0_uid93_constMult_q <= "0011011101110011101001111000000000";
WHEN "010101" => p0_uid93_constMult_q <= "0011101000111001011011111110000000";
WHEN "010110" => p0_uid93_constMult_q <= "0011110011111111001110000100000000";
WHEN "010111" => p0_uid93_constMult_q <= "0011111111000101000000001010000000";
WHEN "011000" => p0_uid93_constMult_q <= "0100001010001010110010010000000000";
WHEN "011001" => p0_uid93_constMult_q <= "0100010101010000100100010110000000";
WHEN "011010" => p0_uid93_constMult_q <= "0100100000010110010110011100000000";
WHEN "011011" => p0_uid93_constMult_q <= "0100101011011100001000100010000000";
WHEN "011100" => p0_uid93_constMult_q <= "0100110110100001111010101000000000";
WHEN "011101" => p0_uid93_constMult_q <= "0101000001100111101100101110000000";
WHEN "011110" => p0_uid93_constMult_q <= "0101001100101101011110110100000000";
WHEN "011111" => p0_uid93_constMult_q <= "0101010111110011010000111010000000";
WHEN "100000" => p0_uid93_constMult_q <= "0101100010111001000011000000000000";
WHEN "100001" => p0_uid93_constMult_q <= "0101101101111110110101000110000000";
WHEN "100010" => p0_uid93_constMult_q <= "0101111001000100100111001100000000";
WHEN "100011" => p0_uid93_constMult_q <= "0110000100001010011001010010000000";
WHEN "100100" => p0_uid93_constMult_q <= "0110001111010000001011011000000000";
WHEN "100101" => p0_uid93_constMult_q <= "0110011010010101111101011110000000";
WHEN "100110" => p0_uid93_constMult_q <= "0110100101011011101111100100000000";
WHEN "100111" => p0_uid93_constMult_q <= "0110110000100001100001101010000000";
WHEN "101000" => p0_uid93_constMult_q <= "0110111011100111010011110000000000";
WHEN "101001" => p0_uid93_constMult_q <= "0111000110101101000101110110000000";
WHEN "101010" => p0_uid93_constMult_q <= "0111010001110010110111111100000000";
WHEN "101011" => p0_uid93_constMult_q <= "0111011100111000101010000010000000";
WHEN "101100" => p0_uid93_constMult_q <= "0111100111111110011100001000000000";
WHEN "101101" => p0_uid93_constMult_q <= "0111110011000100001110001110000000";
WHEN "101110" => p0_uid93_constMult_q <= "0111111110001010000000010100000000";
WHEN "101111" => p0_uid93_constMult_q <= "1000001001001111110010011010000000";
WHEN "110000" => p0_uid93_constMult_q <= "1000010100010101100100100000000000";
WHEN "110001" => p0_uid93_constMult_q <= "1000011111011011010110100110000000";
WHEN "110010" => p0_uid93_constMult_q <= "1000101010100001001000101100000000";
WHEN "110011" => p0_uid93_constMult_q <= "1000110101100110111010110010000000";
WHEN "110100" => p0_uid93_constMult_q <= "1001000000101100101100111000000000";
WHEN "110101" => p0_uid93_constMult_q <= "1001001011110010011110111110000000";
WHEN "110110" => p0_uid93_constMult_q <= "1001010110111000010001000100000000";
WHEN "110111" => p0_uid93_constMult_q <= "1001100001111110000011001010000000";
WHEN "111000" => p0_uid93_constMult_q <= "1001101101000011110101010000000000";
WHEN "111001" => p0_uid93_constMult_q <= "1001111000001001100111010110000000";
WHEN "111010" => p0_uid93_constMult_q <= "1010000011001111011001011100000000";
WHEN "111011" => p0_uid93_constMult_q <= "1010001110010101001011100010000000";
WHEN "111100" => p0_uid93_constMult_q <= "1010011001011010111101101000000000";
WHEN "111101" => p0_uid93_constMult_q <= "1010100100100000101111101110000000";
WHEN "111110" => p0_uid93_constMult_q <= "1010101111100110100001110100000000";
WHEN "111111" => p0_uid93_constMult_q <= "1010111010101100010011111010000000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "0000000000000000000000000000000000";
END CASE;
END IF;
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@13
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(8 downto 6);
--p1_uid92_constMult(LOOKUP,91)@13
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (xv1_uid91_constMult_b) IS
WHEN "000" => p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
WHEN "001" => p1_uid92_constMult_q <= "0001011000101110010000110000000000000";
WHEN "010" => p1_uid92_constMult_q <= "0010110001011100100001100000000000000";
WHEN "011" => p1_uid92_constMult_q <= "0100001010001010110010010000000000000";
WHEN "100" => p1_uid92_constMult_q <= "1010011101000110111101000000000000000";
WHEN "101" => p1_uid92_constMult_q <= "1011110101110101001101110000000000000";
WHEN "110" => p1_uid92_constMult_q <= "1101001110100011011110100000000000000";
WHEN "111" => p1_uid92_constMult_q <= "1110100111010001101111010000000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "0000000000000000000000000000000000000";
END CASE;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@14
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid92_constMult_q(36)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(37 downto 0);
--sR_uid95_constMult(BITSELECT,94)@14
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(36 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(36 downto 2);
--ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b(DELAY,254)@0
ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid45_fpLogETest(MUX,44)@14
addTermOne_uid45_fpLogETest_s <= ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= sR_uid95_constMult_b;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@15
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid45_fpLogETest_q(34)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid47_fpLogETest_b(29)) & highBBits_uid47_fpLogETest_b);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(35 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@15
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_q(20 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(20 downto 0);
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@15
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & lowRangeB_uid46_fpLogETest_b;
--FullSumAB56_uid50_fpLogETest(BITSELECT,49)@15
FullSumAB56_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB56_uid50_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_in(56 downto 56);
--notC_uid71_fpLogETest(LOGICAL,70)@15
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@15
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a(DELAY,285)@0
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRC1_uid73_fpLogETest(LOGICAL,72)@15
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRC1_uid73_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRC1_uid73_fpLogETest_q <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
END IF;
END PROCESS;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "00000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
exc_R_uid27_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
exc_R_uid27_fpLogETest_q <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a(DELAY,290)@1
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRC11_uid74_fpLogETest(LOGICAL,73)@16
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,220)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a(DELAY,292)@1
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid75_fpLogETest(LOGICAL,74)@16
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(31 downto 31);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a(DELAY,294)@0
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@15
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q;
InvExcRNaN_uid76_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid76_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid76_fpLogETest_q <= not InvExcRNaN_uid76_fpLogETest_a;
END IF;
END PROCESS;
--signRFull_uid77_fpLogETest(LOGICAL,76)@16
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,307)@16
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid113_countZ_uid54_fpLogETest(CONSTANT,112)
zs_uid113_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,266)@15
ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB56_uid50_fpLogETest_b, xout => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@15
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((56 downto 1 => FullSumAB56_uid50_fpLogETest_b(0)) & FullSumAB56_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
finalSumOneComp_uid52_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
finalSumOneComp_uid52_fpLogETest_q <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
END IF;
END PROCESS;
--finalSumAbs_uid53_fpLogETest(ADD,52)@16
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((57 downto 57 => finalSumOneComp_uid52_fpLogETest_q(56)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((57 downto 1 => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(57 downto 0);
--rVStage_uid114_countZ_uid54_fpLogETest(BITSELECT,113)@16
rVStage_uid114_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid114_countZ_uid54_fpLogETest_b <= rVStage_uid114_countZ_uid54_fpLogETest_in(57 downto 26);
--reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1(REG,202)@16
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= rVStage_uid114_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid115_countZ_uid54_fpLogETest(LOGICAL,114)@17
vCount_uid115_countZ_uid54_fpLogETest_a <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q;
vCount_uid115_countZ_uid54_fpLogETest_b <= zs_uid113_countZ_uid54_fpLogETest_q;
vCount_uid115_countZ_uid54_fpLogETest_q <= "1" when vCount_uid115_countZ_uid54_fpLogETest_a = vCount_uid115_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f(DELAY,366)@17
ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid115_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid121_countZ_uid54_fpLogETest(CONSTANT,120)
zs_uid121_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid117_countZ_uid54_fpLogETest(BITSELECT,116)@16
vStage_uid117_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(25 downto 0);
vStage_uid117_countZ_uid54_fpLogETest_b <= vStage_uid117_countZ_uid54_fpLogETest_in(25 downto 0);
--mO_uid116_countZ_uid54_fpLogETest(CONSTANT,115)
mO_uid116_countZ_uid54_fpLogETest_q <= "111111";
--cStage_uid118_countZ_uid54_fpLogETest(BITJOIN,117)@16
cStage_uid118_countZ_uid54_fpLogETest_q <= vStage_uid117_countZ_uid54_fpLogETest_b & mO_uid116_countZ_uid54_fpLogETest_q;
--reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3(REG,204)@16
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= cStage_uid118_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid120_countZ_uid54_fpLogETest(MUX,119)@17
vStagei_uid120_countZ_uid54_fpLogETest_s <= vCount_uid115_countZ_uid54_fpLogETest_q;
vStagei_uid120_countZ_uid54_fpLogETest: PROCESS (vStagei_uid120_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q, reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid120_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid120_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid122_countZ_uid54_fpLogETest(BITSELECT,121)@17
rVStage_uid122_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q;
rVStage_uid122_countZ_uid54_fpLogETest_b <= rVStage_uid122_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1(REG,205)@17
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= rVStage_uid122_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid123_countZ_uid54_fpLogETest(LOGICAL,122)@18
vCount_uid123_countZ_uid54_fpLogETest_a <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q;
vCount_uid123_countZ_uid54_fpLogETest_b <= zs_uid121_countZ_uid54_fpLogETest_q;
vCount_uid123_countZ_uid54_fpLogETest_q <= "1" when vCount_uid123_countZ_uid54_fpLogETest_a = vCount_uid123_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e(DELAY,365)@18
ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid123_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid124_countZ_uid54_fpLogETest(BITSELECT,123)@17
vStage_uid124_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid124_countZ_uid54_fpLogETest_b <= vStage_uid124_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3(REG,207)@17
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= vStage_uid124_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid126_countZ_uid54_fpLogETest(MUX,125)@18
vStagei_uid126_countZ_uid54_fpLogETest_s <= vCount_uid123_countZ_uid54_fpLogETest_q;
vStagei_uid126_countZ_uid54_fpLogETest: PROCESS (vStagei_uid126_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q, reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid126_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid126_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid128_countZ_uid54_fpLogETest(BITSELECT,127)@18
rVStage_uid128_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q;
rVStage_uid128_countZ_uid54_fpLogETest_b <= rVStage_uid128_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid129_countZ_uid54_fpLogETest(LOGICAL,128)@18
vCount_uid129_countZ_uid54_fpLogETest_a <= rVStage_uid128_countZ_uid54_fpLogETest_b;
vCount_uid129_countZ_uid54_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
vCount_uid129_countZ_uid54_fpLogETest_q <= "1" when vCount_uid129_countZ_uid54_fpLogETest_a = vCount_uid129_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3(REG,211)@18
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= vCount_uid129_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--zs_uid133_countZ_uid54_fpLogETest(CONSTANT,132)
zs_uid133_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid130_countZ_uid54_fpLogETest(BITSELECT,129)@18
vStage_uid130_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid130_countZ_uid54_fpLogETest_b <= vStage_uid130_countZ_uid54_fpLogETest_in(7 downto 0);
--vStagei_uid132_countZ_uid54_fpLogETest(MUX,131)@18
vStagei_uid132_countZ_uid54_fpLogETest_s <= vCount_uid129_countZ_uid54_fpLogETest_q;
vStagei_uid132_countZ_uid54_fpLogETest: PROCESS (vStagei_uid132_countZ_uid54_fpLogETest_s, en, rVStage_uid128_countZ_uid54_fpLogETest_b, vStage_uid130_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid132_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid132_countZ_uid54_fpLogETest_q <= rVStage_uid128_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid132_countZ_uid54_fpLogETest_q <= vStage_uid130_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid132_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid134_countZ_uid54_fpLogETest(BITSELECT,133)@18
rVStage_uid134_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q;
rVStage_uid134_countZ_uid54_fpLogETest_b <= rVStage_uid134_countZ_uid54_fpLogETest_in(7 downto 4);
--reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1(REG,208)@18
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= rVStage_uid134_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid135_countZ_uid54_fpLogETest(LOGICAL,134)@19
vCount_uid135_countZ_uid54_fpLogETest_a <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q;
vCount_uid135_countZ_uid54_fpLogETest_b <= zs_uid133_countZ_uid54_fpLogETest_q;
vCount_uid135_countZ_uid54_fpLogETest_q <= "1" when vCount_uid135_countZ_uid54_fpLogETest_a = vCount_uid135_countZ_uid54_fpLogETest_b else "0";
--vStage_uid136_countZ_uid54_fpLogETest(BITSELECT,135)@18
vStage_uid136_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid136_countZ_uid54_fpLogETest_b <= vStage_uid136_countZ_uid54_fpLogETest_in(3 downto 0);
--reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3(REG,210)@18
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= vStage_uid136_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid138_countZ_uid54_fpLogETest(MUX,137)@19
vStagei_uid138_countZ_uid54_fpLogETest_s <= vCount_uid135_countZ_uid54_fpLogETest_q;
vStagei_uid138_countZ_uid54_fpLogETest: PROCESS (vStagei_uid138_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q, reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid138_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid138_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid140_countZ_uid54_fpLogETest(BITSELECT,139)@19
rVStage_uid140_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q;
rVStage_uid140_countZ_uid54_fpLogETest_b <= rVStage_uid140_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid141_countZ_uid54_fpLogETest(LOGICAL,140)@19
vCount_uid141_countZ_uid54_fpLogETest_a <= rVStage_uid140_countZ_uid54_fpLogETest_b;
vCount_uid141_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid141_countZ_uid54_fpLogETest_q <= "1" when vCount_uid141_countZ_uid54_fpLogETest_a = vCount_uid141_countZ_uid54_fpLogETest_b else "0";
--vStage_uid142_countZ_uid54_fpLogETest(BITSELECT,141)@19
vStage_uid142_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid142_countZ_uid54_fpLogETest_b <= vStage_uid142_countZ_uid54_fpLogETest_in(1 downto 0);
--vStagei_uid144_countZ_uid54_fpLogETest(MUX,143)@19
vStagei_uid144_countZ_uid54_fpLogETest_s <= vCount_uid141_countZ_uid54_fpLogETest_q;
vStagei_uid144_countZ_uid54_fpLogETest: PROCESS (vStagei_uid144_countZ_uid54_fpLogETest_s, en, rVStage_uid140_countZ_uid54_fpLogETest_b, vStage_uid142_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid144_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid144_countZ_uid54_fpLogETest_q <= rVStage_uid140_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid144_countZ_uid54_fpLogETest_q <= vStage_uid142_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid144_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_countZ_uid54_fpLogETest(BITSELECT,145)@19
rVStage_uid146_countZ_uid54_fpLogETest_in <= vStagei_uid144_countZ_uid54_fpLogETest_q;
rVStage_uid146_countZ_uid54_fpLogETest_b <= rVStage_uid146_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid147_countZ_uid54_fpLogETest(LOGICAL,146)@19
vCount_uid147_countZ_uid54_fpLogETest_a <= rVStage_uid146_countZ_uid54_fpLogETest_b;
vCount_uid147_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid147_countZ_uid54_fpLogETest_q <= "1" when vCount_uid147_countZ_uid54_fpLogETest_a = vCount_uid147_countZ_uid54_fpLogETest_b else "0";
--r_uid148_countZ_uid54_fpLogETest(BITJOIN,147)@19
r_uid148_countZ_uid54_fpLogETest_q <= ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q & ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q & reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q & vCount_uid135_countZ_uid54_fpLogETest_q & vCount_uid141_countZ_uid54_fpLogETest_q & vCount_uid147_countZ_uid54_fpLogETest_q;
--reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1(REG,218)@19
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= r_uid148_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010001001";
--expRExt_uid57_fpLogETest(SUB,56)@20
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("0000" & reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q);
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(9 downto 0);
--LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest(BITSELECT,179)@20
LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(54 downto 0);
LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in(54 downto 0);
--leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest(CONSTANT,178)
leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q <= "000";
--leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest(BITJOIN,180)@20
leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b & leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q;
--LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest(BITSELECT,176)@20
LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(55 downto 0);
LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in(55 downto 0);
--leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest(BITJOIN,177)@20
leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b & z2_uid40_fpLogETest_q;
--LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest(BITSELECT,173)@20
LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(56 downto 0);
LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in(56 downto 0);
--leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest(BITJOIN,174)@20
leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b & GND_q;
--X9dto0_uid158_normVal_uid55_fpLogETest(BITSELECT,157)@16
X9dto0_uid158_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(9 downto 0);
X9dto0_uid158_normVal_uid55_fpLogETest_b <= X9dto0_uid158_normVal_uid55_fpLogETest_in(9 downto 0);
--ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg(DELAY,467)
ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => X9dto0_uid158_normVal_uid55_fpLogETest_b, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b(DELAY,371)@16
ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 2 )
PORT MAP ( xin => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest(CONSTANT,156)
leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest(BITJOIN,158)@19
leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q <= ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q & leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q;
--ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg(DELAY,466)
ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => vStage_uid117_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b(DELAY,369)@16
ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 26, depth => 2 )
PORT MAP ( xin => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest(BITJOIN,155)@19
leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q <= ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q & zs_uid113_countZ_uid54_fpLogETest_q;
--X41dto0_uid152_normVal_uid55_fpLogETest(BITSELECT,151)@16
X41dto0_uid152_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(41 downto 0);
X41dto0_uid152_normVal_uid55_fpLogETest_b <= X41dto0_uid152_normVal_uid55_fpLogETest_in(41 downto 0);
--ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg(DELAY,465)
ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => X41dto0_uid152_normVal_uid55_fpLogETest_b, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b(DELAY,368)@16
ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 42, depth => 2 )
PORT MAP ( xin => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest(BITJOIN,152)@19
leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q <= ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q & zs_uid121_countZ_uid54_fpLogETest_q;
--ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg(DELAY,468)
ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c(DELAY,374)@16
ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 58, depth => 2 )
PORT MAP ( xin => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest(BITSELECT,159)@19
leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q;
leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in(5 downto 4);
--leftShiftStage0_uid161_normVal_uid55_fpLogETest(MUX,160)@19
leftShiftStage0_uid161_normVal_uid55_fpLogETest_s <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid161_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid161_normVal_uid55_fpLogETest_s, en, ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q, leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q, leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage0_uid161_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q;
WHEN "01" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest(BITSELECT,168)@19
LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(45 downto 0);
LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in(45 downto 0);
--leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest(CONSTANT,167)
leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q <= "000000000000";
--leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest(BITJOIN,169)@19
leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5(REG,216)@19
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest(BITSELECT,165)@19
LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(49 downto 0);
LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in(49 downto 0);
--leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest(BITJOIN,166)@19
leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b & cstAllZWE_uid14_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4(REG,215)@19
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest(BITSELECT,162)@19
LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(53 downto 0);
LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in(53 downto 0);
--leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest(BITJOIN,163)@19
leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b & zs_uid133_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3(REG,214)@19
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2(REG,213)@19
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest(BITSELECT,170)@19
leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(3 downto 0);
leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1(REG,212)@19
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid172_normVal_uid55_fpLogETest(MUX,171)@20
leftShiftStage1_uid172_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid172_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid172_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid172_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest(BITSELECT,181)@19
leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(1 downto 0);
leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1(REG,217)@19
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid183_normVal_uid55_fpLogETest(MUX,182)@20
leftShiftStage2_uid183_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q;
leftShiftStage2_uid183_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid183_normVal_uid55_fpLogETest_s, en, leftShiftStage1_uid172_normVal_uid55_fpLogETest_q, leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid183_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q;
WHEN "01" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@20
fracR_uid58_fpLogETest_in <= leftShiftStage2_uid183_normVal_uid55_fpLogETest_q(56 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(56 downto 33);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@20
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,219)@20
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@21
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(34 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@21
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(31 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(31 downto 24);
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor(LOGICAL,493)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q <= not (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a or ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b);
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top(CONSTANT,489)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q <= "010001";
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp(LOGICAL,490)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q <= "1" when ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a = ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b else "0";
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg(REG,491)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena(REG,494)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd(LOGICAL,495)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b <= en;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a and ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg(DELAY,483)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid78_fpLogETest_q, xout => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt(COUNTER,485)
-- every=1, low=0, high=17, step=1, init=1
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i = 16 THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i - 17;
ELSE
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i,5));
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg(REG,486)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux(MUX,487)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s <= en;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux: PROCESS (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem(DUALMEM,484)
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 <= areset;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q;
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq,
address_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa,
data_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia
);
ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq(2 downto 0);
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,193)@20
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid79_fpLogETest(LOOKUP,78)@21
excREnc_uid79_fpLogETest: PROCESS (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@21
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, expR_uid62_fpLogETest_b, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= expR_uid62_fpLogETest_b;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "00000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@21
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(23 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(23 downto 1);
--fracRPostExc_uid83_fpLogETest(MUX,82)@21
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, fracR_uid61_fpLogETest_b, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= fracR_uid61_fpLogETest_b;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@21
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@21
q <= RLn_uid88_fpLogETest_q;
end normal;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_lnlut8.vhd
|
10
|
50006
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_lnlut8.vhd
|
10
|
50006
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_exprnd.vhd
|
10
|
7830
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPRND.VHD ***
--*** ***
--*** Function: FP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exprnd;
ARCHITECTURE rtl OF fp_exprnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_sqrt_double_s5.vhd
|
10
|
321991
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sqrt_double_s5
-- VHDL created on Tue Apr 9 15:17:30 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sqrt_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sqrt_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0);
signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0);
signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0);
signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0);
signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0);
signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0);
signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0);
signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0);
signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0);
signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0);
signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0);
signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0);
signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0);
signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0);
signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0);
signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0);
signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0);
signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0);
signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0);
signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0);
signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b;
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= a;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63);
--cstAllZWE_uid11_fpSqrtTest(CONSTANT,10)
cstAllZWE_uid11_fpSqrtTest_q <= "00000000000";
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= a(62 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52);
--expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0
expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q;
expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0";
--negZero_uid56_fpSqrtTest(LOGICAL,55)@0
negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427)
-- every=1, low=0, high=24, step=1, init=1
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24;
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5));
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q)
BEGIN
CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS
WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 25,
width_b => 1,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq,
address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa,
data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia
);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0);
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b;
--cstAllOWE_uid9_fpSqrtTest(CONSTANT,8)
cstAllOWE_uid9_fpSqrtTest_q <= "11111111111";
--sBiasM1_uid28_fpSqrtTest(CONSTANT,27)
sBiasM1_uid28_fpSqrtTest_q <= "01111111110";
--expOddSig_uid29_fpSqrtTest(ADD,28)@0
expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q);
expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b));
expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0);
--expROdd_uid30_fpSqrtTest(BITSELECT,29)@0
expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q;
expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1);
--sBias_uid25_fpSqrtTest(CONSTANT,24)
sBias_uid25_fpSqrtTest_q <= "01111111111";
--expEvenSig_uid26_fpSqrtTest(ADD,25)@0
expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q);
expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b));
expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0);
--expREven_uid27_fpSqrtTest(BITSELECT,26)@0
expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q;
expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1);
--expX0_uid31_fpSqrtTest(BITSELECT,30)@0
expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0
expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b;
expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a;
--expRMux_uid33_fpSqrtTest(MUX,32)@0
expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q;
expRMux_uid33_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid33_fpSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid33_fpSqrtTest_s IS
WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b;
WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1
ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0
ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid10_fpSqrtTest(CONSTANT,9)
cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000";
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= a(51 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0);
--fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0
fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q;
fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0";
--InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0
InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q;
InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a;
--expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0
expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q;
expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0";
--exc_N_uid20_fpSqrtTest(LOGICAL,19)@0
exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b;
--InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0
InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q;
InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a;
--exc_I_uid18_fpSqrtTest(LOGICAL,17)@0
exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b;
--InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0
InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a;
--InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0
InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a;
--exc_R_uid24_fpSqrtTest(LOGICAL,23)@0
exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c;
--minReg_uid42_fpSqrtTest(LOGICAL,41)@0
minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q;
minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--minInf_uid43_fpSqrtTest(LOGICAL,42)@0
minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1
excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q;
excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c;
--InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0
InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a;
--inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0
inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b;
inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--join_uid45_fpSqrtTest(BITJOIN,44)@1
join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q;
--fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1
fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q;
--fracSel_uid47_fpSqrtTest(LOOKUP,46)@1
fracSel_uid47_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracSel_uid47_fpSqrtTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (fracSelIn_uid46_fpSqrtTest_q) IS
WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid47_fpSqrtTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid51_fpSqrtTest(MUX,50)@2
expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q;
expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid51_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q;
WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401)
-- every=1, low=0, high=23, step=1, init=1
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23;
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5));
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 24,
width_b => 11,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0);
--fracNaN_uid52_fpSqrtTest(CONSTANT,51)
fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0
fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b;
fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45);
--addrTable_uid36_fpSqrtTest(BITJOIN,35)@0
addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b;
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1
memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q;
memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq,
address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa,
data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia
);
memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398)
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3
FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0);
FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0);
--yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3
yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28);
--reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b);
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16);
--highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7
highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b;
highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4
memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q;
memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 8,
numwords_a => 256,
width_b => 24,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq,
address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa,
data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia
);
memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0);
--reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7
sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b);
sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b));
sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0);
--lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7
lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7
s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b;
--reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b);
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3
yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21);
--reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1));
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0);
--prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b);
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50));
END IF;
END IF;
END PROCESS;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23);
--highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11
highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b;
highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8
memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 8,
numwords_a => 256,
width_b => 33,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq,
address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa,
data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia
);
memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0);
--reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11
sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b);
sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b));
sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0);
--lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11
lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0);
--s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11
s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b;
--reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3
yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516)
-- every=1, low=0, high=5, step=1, init=1
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5;
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3));
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 3,
numwords_a => 6,
width_b => 33,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0);
--reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b);
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68));
END IF;
END IF;
END PROCESS;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34);
--highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15
highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b;
highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529)
-- every=1, low=0, high=8, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12
memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15
sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b);
sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b));
sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0);
--lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15
lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0);
--s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15
s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b;
--yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24);
--reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=9, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 10,
width_b => 45,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15
yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q;
yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5);
--xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0);
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15
pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0);
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0);
--spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15
spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b;
--pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15
pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22);
--reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2);
--highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b;
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6);
--yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15);
--reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13);
--reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b);
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b));
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0);
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0);
--add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19
add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b;
--R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0);
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17);
--reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503)
-- every=1, low=0, high=12, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 13,
width_b => 8,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16
memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 8,
numwords_a => 256,
width_b => 9,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0);
--reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16
memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid64_sqrtTableGenerator(BITJOIN,63)@19
os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q;
--rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92)
rndBit_uid93_sqrtPolynomialEvaluator_q <= "01";
--cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19
cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20
ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q);
ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q);
ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b));
ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0);
--s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20
s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q;
s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490)
-- every=1, low=0, high=14, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 15,
width_b => 45,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0);
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b));
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0);
--prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0);
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44);
--highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26
highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b;
highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2);
--reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464)
-- every=1, low=0, high=19, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23
memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23
memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid61_sqrtTableGenerator(BITJOIN,60)@26
os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q;
--reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27
sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b));
sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0);
--lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26
lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0);
--reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27
s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q;
--fracR_uid39_fpSqrtTest(BITSELECT,38)@27
fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0);
fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5);
--reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 24,
width_b => 2,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq,
address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa,
data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia
);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid55_fpSqrtTest(MUX,54)@28
fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q;
fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q)
BEGIN
CASE fracRPostExc_uid55_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q;
WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28
RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q;
--xOut(GPOUT,4)@28
q <= RSqrt_uid57_fpSqrtTest_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_atan.vhd
|
10
|
17028
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATAN.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ArcTangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
-- slight improvement when "roundbit" is used i.e. round up from
-- X.4999 - exact number of bits to be used needs to be tweaked
ENTITY fp_atan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_atan;
ARCHITECTURE rtl OF fp_atan IS
constant coredepth : positive := 12;
constant b_precision : positive := 10;
type exponentinfftype IS ARRAY (coredepth-2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type exponenttopfftype IS ARRAY (coredepth-3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type mantissabpfftype IS ARRAY (2*coredepth+10 DOWNTO 1) OF STD_LOGIC_VECTOR (23 DOWNTO 1); -- SPR: 380600
type termfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi_over_two : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delinputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topquotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topquotientnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal exponentoffset : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentinff : exponentinfftype;
signal idselectff : STD_LOGIC_VECTOR (2*coredepth+10 DOWNTO 1); -- SPR: 380600
signal pathselectff : STD_LOGIC_VECTOR (2*coredepth+9 DOWNTO 1);
signal exponenttopff : exponenttopfftype;
signal forward_shiftff, inverse_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal a_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_fixedpointbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pathcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal ab_plusone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2*coredepth+11 DOWNTO 1);
signal mantissabpff : mantissabpfftype; -- SPR: 380600
signal atantermff : termfftype;
signal large_atanff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal small_mantissa, small_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal large_mantissa, large_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mux_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal small_count, small_countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal small_overflowbus, large_overflowbus : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal small_overflowff, large_overflowff : STD_LOGIC;
signal mux_overflow : STD_LOGIC;
signal roundbit : STD_LOGIC;
signal mantissa_roundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissa_bypass : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponent_outff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_exponent_adjust, large_exponent_adjust : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponent_adjust, exponent_adjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- SPR: 380600
signal expinzero : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero : STD_LOGIC;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_atanlut
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pi_over_two <= x"C90FDAA22"; -- 1.57...
--*** Invert Input ***
inputnumber <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>inputnumber,
quotient=>topquotient);
exponentoffset <= conv_std_logic_vector (127,10);
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-2 LOOP
FOR j IN 1 TO 8 LOOP
exponentinff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2*coredepth+9 LOOP
pathselectff(k) <= '0';
END LOOP;
-- SPR: 380600
FOR k IN 1 TO 2*coredepth+10 LOOP
idselectff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-3 LOOP
FOR j IN 1 TO 10 LOOP
exponenttopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 10 LOOP
forward_shiftff(k) <= '0';
inverse_shiftff(k) <= '0';
a_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
a_fixedpointff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff(1)(8 DOWNTO 1) <= exponentin;
FOR k IN 2 TO coredepth-2 LOOP
exponentinff(k)(8 DOWNTO 1) <= exponentinff(k-1)(8 DOWNTO 1);
END LOOP;
pathselectff(1) <= pathcheck(9);
FOR k IN 2 TO 2*coredepth+9 LOOP
pathselectff(k) <= pathselectff(k-1);
END LOOP;
-- SPR: 380600
idselectff(1) <= expzero;
FOR k IN 2 TO 2*coredepth+10 LOOP
idselectff(k) <= idselectff(k-1);
END LOOP;
-- exponent for inverse, used when exponent > 126
exponenttopff(1)(10 DOWNTO 1) <= exponentoffset - ("00" & exponentinff(1)(8 DOWNTO 1));
exponenttopff(2)(10 DOWNTO 1) <= exponenttopff(1)(10 DOWNTO 1) + exponentoffset;
exponenttopff(3)(10 DOWNTO 1) <= exponenttopff(2)(10 DOWNTO 1) - 1;
-- inverse always less than 1, decrement exponent
FOR k IN 4 TO coredepth-3 LOOP
exponenttopff(k)(10 DOWNTO 1) <= exponenttopff(k-1)(10 DOWNTO 1);
END LOOP;
forward_shiftff <= "0001111111" - ("00" & exponentinff(coredepth-2)(8 DOWNTO 1));
inverse_shiftff <= "0001111111" - exponenttopff(coredepth-3)(10 DOWNTO 1);
FOR k IN 1 TO 6 LOOP
a_shiftff(k) <= (forward_shiftff(k) AND NOT(pathselectff(coredepth-2))) OR
(inverse_shiftff(k) AND pathselectff(coredepth-2));
END LOOP;
a_fixedpointff <= a_fixedpointbus;
END IF;
END IF;
END PROCESS;
-- if <=126 (<= 0.999999), use atan(x) path, else use (pi/2-atan(1/x)) path
pathcheck <= "001111110" - ('0' & exponentinff(1)(8 DOWNTO 1));
cdma: fp_del
GENERIC MAP (width=>36,pipes=>coredepth) -- 12 for inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>inputnumber,
cc=>delinputnumber);
topquotientnumber <= topquotient(35 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 36 GENERATE
a_mantissanode(k) <= (delinputnumber(k) AND NOT(pathselectff(coredepth-1))) OR
(topquotientnumber(k) AND pathselectff(coredepth-1));
END GENERATE;
casr: fp_rsft36
PORT MAP (inbus=>a_mantissanode,shift=>a_shiftff(6 DOWNTO 1),
outbus=>a_fixedpointbus);
a_fixedpoint <= a_fixedpointff;
b_fixedpoint <= a_fixedpointff(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1);
c_fixedpoint <= a_fixedpointff(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1);
cmone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,
pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>a_fixedpoint,databb=>b_fixedpoint,
result=>ab_fixedpoint);
ab_plusone <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value
invtwo: fp_inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>ab_plusone,
quotient=>denominator);
cdc: fp_del
GENERIC MAP (width=>36,pipes=>coredepth+3) -- inv_core and 3 for 36*36 mult
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>c_fixedpoint,
cc=>numerator);
cmtwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,
pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>numerator,databb=>denominator,
result=>addterm);
b_address <= a_fixedpoint(36 DOWNTO 37-b_precision);
clut: fp_atanlut
PORT MAP (add=>b_address,
data=>lutterm);
cdlut: fp_del
GENERIC MAP (width=>36,pipes=>18) -- 12 for inv_core and 3 for 36*36 mult
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>lutterm,
cc=>dellutterm);
pimo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2*coredepth+11 LOOP
signff(k) <= '0';
END LOOP;
-- SPR: 380600
FOR k IN 1 TO 2*coredepth+10 LOOP
FOR j IN 1 TO 23 LOOP
mantissabpff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 36 LOOP
atantermff(1)(k) <= '0';
atantermff(2)(k) <= '0';
large_atanff(k) <= '0';
small_mantissaff(k) <= '0';
large_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
small_countff(k) <= '0';
END LOOP;
small_overflowff <= '0';
large_overflowff <= '0';
FOR k IN 1 TO 23 LOOP
mantissa_roundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponent_outff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
mantissabpff(1)(23 DOWNTO 1) <= mantissain(23 DOWNTO 1);
FOR k IN 2 TO 2*coredepth+11 LOOP
signff(k) <= signff(k-1);
END LOOP;
-- SPR: 380600
FOR k IN 2 TO 2*coredepth+10 LOOP
mantissabpff(k)(23 DOWNTO 1) <= mantissabpff(k-1)(23 DOWNTO 1);
END LOOP;
atantermff(1)(36 DOWNTO 1) <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10));
atantermff(2)(36 DOWNTO 1) <= atantermff(1)(36 DOWNTO 1);
-- always in the range 0.78 to pi/2
large_atanff(36 DOWNTO 1) <= pi_over_two - atantermff(1)(36 DOWNTO 1);
small_countff <= small_count;
large_mantissaff <= large_mantissa;
small_mantissaff <= small_mantissa;
small_overflowff <= small_overflowbus(24);
large_overflowff <= large_overflowbus(24);
exponent_adjustff <= exponent_adjust;
--mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + mux_mantissa(12);
mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + roundbit;
exponent_outff <= "01111111" - exponent_adjustff + mux_overflow;
END IF;
END IF;
END PROCESS;
roundbit <= mux_mantissa(12) OR
(mux_mantissa(11) AND mux_mantissa(10) AND mux_mantissa(9) AND mux_mantissa(8) AND
mux_mantissa(7) AND mux_mantissa(6) AND mux_mantissa(5) AND mux_mantissa(4) AND
mux_mantissa(3) AND mux_mantissa(2));
ccsat: fp_clz36
PORT MAP (mantissa=>atantermff(1)(36 DOWNTO 1),
leading=>small_count);
cssat: fp_lsft36
PORT MAP (inbus=>atantermff(2)(36 DOWNTO 1),shift=>small_countff,
outbus=>small_mantissa);
small_overflowbus(1) <= small_mantissa(12);
gova: FOR k IN 2 TO 24 GENERATE
small_overflowbus(k) <= small_overflowbus(k-1) AND small_mantissa(k+11);
END GENERATE;
glma: FOR k IN 1 TO 35 GENERATE
large_mantissa(k+1) <= (large_atanff(k) AND NOT(large_atanff(36))) OR
(large_atanff(k+1) AND large_atanff(36));
END GENERATE;
large_mantissa(1) <= '0';
large_overflowbus(1) <= large_mantissa(12);
govb: FOR k IN 2 TO 24 GENERATE
large_overflowbus(k) <= large_overflowbus(k-1) AND large_mantissa(k+11);
END GENERATE;
gmma: FOR k IN 1 TO 36 GENERATE
mux_mantissa(k) <= (small_mantissaff(k) AND NOT(pathselectff(2*coredepth+9))) OR
(large_mantissaff(k) AND pathselectff(2*coredepth+9));
END GENERATE;
mux_overflow <= (small_overflowff AND NOT(pathselectff(2*coredepth+9))) OR
(large_overflowff AND pathselectff(2*coredepth+9));
large_exponent_adjust <= "0000000" & NOT(large_atanff(36));
small_exponent_adjust <= "00" & small_countff;
gxa: FOR k IN 1 TO 8 GENERATE
exponent_adjust(k) <= (small_exponent_adjust(k) AND NOT(pathselectff(2*coredepth+8))) OR
(large_exponent_adjust(k) AND pathselectff(2*coredepth+8));
END GENERATE;
-- SPR: 380600
bypass: FOR k IN 1 TO 23 GENERATE
mantissa_bypass(k) <= (mantissa_roundff(k) AND NOT(idselectff(2*coredepth+10))) OR
(mantissabpff(2*coredepth+10)(k) AND idselectff(2*coredepth+10));
END GENERATE;
-- SPR: 380600
expinzero(1) <= exponentinff(1)(1);
gxza: FOR k IN 2 TO 8 GENERATE
expinzero(k) <= expinzero(k-1) OR exponentinff(1)(k);
END GENERATE;
expzero <= NOT(expinzero(8)); -- '0' when zero
--*** OUTPUTS ***
signout <= signff(2*coredepth+11);
exponentout <= (others => '0') when idselectff(2*coredepth+10) = '1' else exponent_outff; -- SPR: 380600
mantissaout <= mantissa_bypass;
end rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/dp_ln_core.vhd
|
10
|
21706
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(e) - CORE ***
--*** ***
--*** DP_LN_CORE.VHD ***
--*** ***
--*** Function: Double Precision LOG (LN) Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII/SIII/SIV Latency = 26 + 7*doublespeed ***
--*** no 54x54 multipliers ***
--***************************************************
ENTITY dp_ln_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_ln_core;
ARCHITECTURE rtl OF dp_ln_core IS
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
--*** INPUT BLOCK ***
signal aamanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal aaexpabsff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal aaexpabs : STD_LOGIC_VECTOR (10 DOWNTO 1);
--*** TABLES ***
signal lutpowaddff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutoneaddff, luttwoaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lutpowmanff, lutonemanff, luttwomanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpff, lutoneexpff, luttwoexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal lutpowmannode, lutonemannode, luttwomannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpnode, lutoneexpnode, luttwoexpnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvnode : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvnode : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal aanum, aanumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invonenum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulonenode : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal mulonenormff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mulonenumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multwonode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwonormff : STD_LOGIC_VECTOR (71 DOWNTO 1);
--*** SERIES ***
signal squaredterm : STD_LOGIC_VECTOR (48 DOWNTO 1);
signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaledterm, scaledtermdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal cubedterm : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal xtermdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal oneplustwoterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal seriesterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaseries : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentseries : STD_LOGIC_VECTOR (11 DOWNTO 1);
--*** ADD LOGS ***
signal zeropow, zeroone, zerotwo : STD_LOGIC;
signal mantissapowernode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissapower : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentpower : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberone, numberonedel : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaaddone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissatwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponenttwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numbertwo, numbertwodel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissaaddtwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddtwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberthr, numberthrdel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissasum : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissasumabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentsum : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissanorm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentnorm : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronorm : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (25+7*doublespeed DOWNTO 1);
component dp_lnlutpow
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut9
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (12 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut18
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (18 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxsub
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_lnadd
GENERIC (
speed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
bbman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnnorm
GENERIC (
speed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
inexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
outman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
outexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
zero : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
ppin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexpabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman; -- level 1
aaexpff <= aaexp; -- level 1
aaexpabsff <= aaexpabs; -- level 2
END IF;
END IF;
END PROCESS;
aaexppos <= ('0' & aaexpff) - "001111111111";
aaexpneg <= "001111111111" - ('0' & aaexpff);
gaba: FOR k IN 1 TO 10 GENERATE
aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(12))) OR (aaexpneg(k) AND aaexppos(12));
END GENERATE;
--******************************************
--*** RANGE REDUCTION THROUGH LUT SERIES ***
--******************************************
plut: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 10 LOOP
lutpowaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
lutoneaddff(k) <= '0';
luttwoaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
lutpowmanff(k) <= '0';
lutonemanff(k) <= '0';
luttwomanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutpowexpff(k) <= '0';
lutoneexpff(k) <= '0';
luttwoexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 12 LOOP
lutoneinvff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
luttwoinvff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lutpowaddff <= aaexpabsff; -- level 3
lutoneaddff <= aamanff(52 DOWNTO 44); -- level 2
luttwoaddff <= mulonenormff(55 DOWNTO 47); -- level 8+speed
lutpowmanff <= lutpowmannode; -- level 4
lutpowexpff <= lutpowexpnode; -- level 4
lutoneinvff <= lutoneinvnode; -- level 3
lutonemanff <= lutonemannode; -- level 3
lutoneexpff <= lutoneexpnode; -- level 3
luttwoinvff <= luttwoinvnode; -- level 9+speed
luttwomanff <= luttwomannode; -- level 9+speed
luttwoexpff <= luttwoexpnode; -- level 9+speed
END IF;
END IF;
END PROCESS;
lutpow: dp_lnlutpow
PORT MAP (add=>lutpowaddff,
logman=>lutpowmannode,logexp=>lutpowexpnode);
lutone: dp_lnlut9
PORT MAP (add=>lutoneaddff,
inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode);
luttwo: dp_lnlut18
PORT MAP (add=>luttwoaddff,
inv=>luttwoinvnode,logman=>luttwomannode,logexp=>luttwoexpnode);
aanum <= '1' & aamanff & '0';
-- level 1 in, level 3 out
delone: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanum,cc=>aanumdel);
invonenum <= lutoneinvff & "000000";
--mulone <= aanum * invone; -- 53*12 = 65
-- level 3 in, level 6+doublespeed out
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>65,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>aanumdel,databb=>invonenum,
result=>mulonenode);
--multwo <= mulonenorm(64 DOWNTO 11) * invtwo; -- 54x18=72
-- level 7+speed in, level 9+speed out
deltwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulonenormff(64 DOWNTO 11),cc=>mulonenumdel);
-- level 9+doublespeed in, level 12+2*doublespeed out
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>72,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulonenumdel,databb=>luttwoinvff,
result=>multwonode);
pmna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- normalize in case input is 1.000000 and inv is 0.5
-- level 7+speed
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(65)) OR
(mulonenode(k) AND NOT(mulonenode(65)));
END LOOP;
-- level 13+2*speed
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= (multwonode(k+1) AND multwonode(72)) OR
(multwonode(k) AND NOT(multwonode(72)));
END LOOP;
END IF;
END IF;
END PROCESS;
--************************************
--*** TAYLOR SERIES OF SMALL RANGE ***
--************************************
-- taylor series expansion of subrange (36 bits)
-- x - x*x/2
-- 16 leading bits, so x*x 16 bits down, +1 bit for 1/2
-- 36 lower bits in multwo(54:19)
--square <= multwonorm(54 DOWNTO 19) * multwonorm(54 DOWNTO 19);
-- level 13+2*doublespeed in, 16+2*doublespeed out
multhr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>48,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 19),databb=>multwonormff(54 DOWNTO 19),
result=>squaredterm);
onethird <= "010101010101010101";
-- level 13+2*doublespeed in, level 15+2*doublespeed out
mulfor: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 37),databb=>onethird,
result=>scaledterm);
--level 15+2*doublespeed in, level 16+2*doublespeed out
delthr: fp_del
GENERIC MAP (width=>18,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>scaledterm,cc=>scaledtermdel);
-- level 16+2*doublespeed in, level 18+2*doublespeed out
mulfiv: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>32,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>squaredterm(48 DOWNTO 31),databb=>scaledtermdel,
result=>cubedterm);
--level 13+2*doublespeed in, level 16+2*doublespeed out
delfor: fp_del
GENERIC MAP (width=>54,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>multwonormff(54 DOWNTO 1),cc=>xtermdel);
-- level 16+2*doublespeed
oneterm <= xtermdel & zerovec(10 DOWNTO 1);
twoterm <= zerovec(17 DOWNTO 1) & squaredterm(48 DOWNTO 2); -- x*x/2
-- level 18+2*doublespeed
thrterm <= zerovec(32 DOWNTO 1) & cubedterm;
--level 16+2*doublespeed in, level 18+2*doublespeed out
tayone: dp_fxsub
GENERIC MAP (width=>64,pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneterm,bb=>twoterm,borrowin=>'1',
cc=>oneplustwoterm);
--level 18+2*doublespeed in, level 19+3*doublespeed out
taytwo: dp_fxadd
GENERIC MAP (width=>64,pipes=>1+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneplustwoterm,bb=>thrterm,carryin=>'0',
cc=>seriesterm);
--mantissaseries <= seriesterm;
mantissaseries <= '0' & seriesterm(64 DOWNTO 2);
exponentseries <= conv_std_logic_vector (1006,11);
--18x18
--cubed <= square(72 DOWNTO 55) * multwonorm(54 DOWNTO 37);
--cubedscale <= cubed(36 DOWNTO 19) * onethird;
--**************************
--*** ADD ALL LOGARITHMS ***
--**************************
zeropow <= lutpowexpff(11) OR lutpowexpff(10) OR lutpowexpff(9) OR
lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR
lutpowexpff(5) OR lutpowexpff(4) OR lutpowexpff(3) OR
lutpowexpff(2) OR lutpowexpff(1);
-- level 4
--mantissapower <= zeropow & lutpowmanff & zerovec(11 DOWNTO 1);
--mantissapower <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
mantissapowernode <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
gmpz: FOR k IN 1 TO 64 GENERATE
mantissapower(k) <= mantissapowernode(k) XOR signff(3);
END GENERATE;
exponentpower <= lutpowexpff;
zeroone <= lutoneexpff(11) OR lutoneexpff(10) OR lutoneexpff(9) OR
lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR
lutoneexpff(5) OR lutoneexpff(4) OR lutoneexpff(3) OR
lutoneexpff(2) OR lutoneexpff(1);
-- level 3
numberone <= zeroone & lutonemanff & lutoneexpff;
-- level 3 in, level 4 out
delfiv: fp_del
GENERIC MAP (width=>64,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberone,cc=>numberonedel);
--mantissaone <= numberonedel(64 DOWNTO 12) & zerovec(11 DOWNTO 1);
mantissaone <= '0' & numberonedel(64 DOWNTO 12) & zerovec(10 DOWNTO 1);
exponentone <= numberonedel(11 DOWNTO 1);
-- level 4 in, level 10 out
addone: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissapower,aaexp=>exponentpower,
bbman=>mantissaone,bbexp=>exponentone,
ccman=>mantissaaddone,ccexp=>exponentaddone);
zerotwo <= luttwoexpff(11) OR luttwoexpff(10) OR luttwoexpff(9) OR
luttwoexpff(8) OR luttwoexpff(7) OR luttwoexpff(6) OR
luttwoexpff(5) OR luttwoexpff(4) OR luttwoexpff(3) OR
luttwoexpff(2) OR luttwoexpff(1);
-- level 9+doublespeed
--mantissatwo <= zerotwo & luttwomanff & zerovec(11 DOWNTO 1);
mantissatwo <= '0' & zerotwo & luttwomanff & zerovec(10 DOWNTO 1);
exponenttwo <= luttwoexpff;
numbertwo <= mantissatwo & exponenttwo;
gasa: IF (doublespeed = 0) GENERATE
delsix: fp_del
GENERIC MAP (width=>75,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numbertwo,cc=>numbertwodel);
END GENERATE;
gasb: IF (doublespeed = 1) GENERATE
numbertwodel <= numbertwo;
END GENERATE;
-- level 10 in, level 16 out
addtwo: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaaddone,aaexp=>exponentaddone,
bbman=>numbertwodel(75 DOWNTO 12),bbexp=>numbertwodel(11 DOWNTO 1),
ccman=>mantissaaddtwo,ccexp=>exponentaddtwo);
numberthr <= mantissaaddtwo & exponentaddtwo;
-- level 16 in, level 19+3*doublespeed out
delsev: fp_del
GENERIC MAP (width=>75,pipes=>3+3*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberthr,cc=>numberthrdel);
-- level 19+3*doublespeed in, level 23+5*doublespeed out
addthr: dp_lnadd
GENERIC MAP (speed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaseries,aaexp=>exponentseries,
bbman=>numberthrdel(75 DOWNTO 12),bbexp=>numberthrdel(11 DOWNTO 1),
ccman=>mantissasum,ccexp=>exponentsum);
gmsa: FOR k IN 1 TO 64 GENERATE
mantissasumabs(k) <= mantissasum(k) XOR signff(22+5*doublespeed);
END GENERATE;
-- level 23+5*doublespeed in, level 26+7*doublespeed out
norm: dp_lnnorm
GENERIC MAP (speed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inman=>mantissasumabs,inexp=>exponentsum,
outman=>mantissanorm,outexp=>exponentnorm,
zero=>zeronorm);
psgna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+7*doublespeed LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signff(1) <= aaexppos(12);
FOR k IN 2 TO 25+7*doublespeed LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END PROCESS;
--***************
--*** OUTPUTS ***
--***************
ccman <= mantissanorm(63 DOWNTO 11);
ccexp <= exponentnorm;
ccsgn <= signff(25+7*doublespeed);
zeroout <= zeronorm;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_mul54usb.vhd
|
10
|
2644
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USB.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 31/01/08 ML see below ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- 31/01/08 - output right shifted so same as synthesable core
-- (now "001X" >= 2, "0001X" < 2
ENTITY hcc_mul54usb IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54usb;
ARCHITECTURE rtl OF hcc_mul54usb IS
constant normtype : integer := 0;
type muldelfftype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (72 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal muldelff : muldelfftype;
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 108 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
FOR j IN 1 TO 72 LOOP
muldelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= aaff * bbff;
muldelff(1)(72 DOWNTO 1) <= mulff(108 DOWNTO 37);
FOR k IN 2 TO 4 LOOP
muldelff(k)(72 DOWNTO 1) <= muldelff(k-1)(72 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= muldelff(4)(72 DOWNTO 9);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_cordic_atan1.vhd
|
10
|
5033
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_ATAN1.VHD ***
--*** ***
--*** Function: ATAN Values Table for SIN and ***
--*** COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_atan1 IS
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_atan1;
ARCHITECTURE sft OF fp_cordic_atan1 IS
type atantype IS ARRAY (48 DOWNTO 1) OF STD_LOGIC_VECTOR (48 DOWNTO 1);
signal atannum : atantype;
BEGIN
-- "00" + 46 bits
atannum(1)(48 DOWNTO 1) <= x"3243F6A8885A";
atannum(2)(48 DOWNTO 1) <= x"1DAC670561BB";
atannum(3)(48 DOWNTO 1) <= x"0FADBAFC9640";
atannum(4)(48 DOWNTO 1) <= x"07F56EA6AB0C";
atannum(5)(48 DOWNTO 1) <= x"03FEAB76E5A0";
atannum(6)(48 DOWNTO 1) <= x"01FFD55BBA97";
atannum(7)(48 DOWNTO 1) <= x"00FFFAAADDDC";
atannum(8)(48 DOWNTO 1) <= x"007FFF5556EF";
atannum(9)(48 DOWNTO 1) <= x"003FFFEAAAB7";
atannum(10)(48 DOWNTO 1) <= x"001FFFFD5556";
atannum(11)(48 DOWNTO 1) <= x"000FFFFFAAAB";
atannum(12)(48 DOWNTO 1) <= x"0007FFFFF555";
atannum(13)(48 DOWNTO 1) <= x"0003FFFFFEAB";
atannum(14)(48 DOWNTO 1) <= x"0001FFFFFFD5";
atannum(15)(48 DOWNTO 1) <= x"0000FFFFFFFB";
atannum(16)(48 DOWNTO 1) <= x"00007FFFFFFF";
atannum(17)(48 DOWNTO 1) <= x"000040000000";
atannum(18)(48 DOWNTO 1) <= x"000020000000";
atannum(19)(48 DOWNTO 1) <= x"000010000000";
atannum(20)(48 DOWNTO 1) <= x"000008000000";
atannum(21)(48 DOWNTO 1) <= x"000004000000";
atannum(22)(48 DOWNTO 1) <= x"000002000000";
atannum(23)(48 DOWNTO 1) <= x"000001000000";
atannum(24)(48 DOWNTO 1) <= x"000000800000";
atannum(25)(48 DOWNTO 1) <= x"000000400000";
atannum(26)(48 DOWNTO 1) <= x"000000200000";
atannum(27)(48 DOWNTO 1) <= x"000000100000";
atannum(28)(48 DOWNTO 1) <= x"000000080000";
atannum(29)(48 DOWNTO 1) <= x"000000040000";
atannum(30)(48 DOWNTO 1) <= x"000000020000";
atannum(31)(48 DOWNTO 1) <= x"000000010000";
atannum(32)(48 DOWNTO 1) <= x"000000008000";
atannum(33)(48 DOWNTO 1) <= x"000000004000";
atannum(34)(48 DOWNTO 1) <= x"000000002000";
atannum(35)(48 DOWNTO 1) <= x"000000001000";
atannum(36)(48 DOWNTO 1) <= x"000000000800";
atannum(37)(48 DOWNTO 1) <= x"000000000400";
atannum(38)(48 DOWNTO 1) <= x"000000000200";
atannum(39)(48 DOWNTO 1) <= x"000000000100";
atannum(40)(48 DOWNTO 1) <= x"000000000080";
atannum(41)(48 DOWNTO 1) <= x"000000000040";
atannum(42)(48 DOWNTO 1) <= x"000000000020";
atannum(43)(48 DOWNTO 1) <= x"000000000010";
atannum(44)(48 DOWNTO 1) <= x"000000000008";
atannum(45)(48 DOWNTO 1) <= x"000000000004";
atannum(46)(48 DOWNTO 1) <= x"000000000002";
atannum(47)(48 DOWNTO 1) <= x"000000000001";
atannum(48)(48 DOWNTO 1) <= x"000000000000";
pca: PROCESS (indexbit)
BEGIN
CASE indexbit IS
WHEN '0' => arctan <= atannum(start)(48 DOWNTO 49-width);
WHEN '1' => arctan <= atannum(start+indexpoint)(48-indexpoint DOWNTO 49-indexpoint-width);
WHEN others => arctan <= atannum(48)(width DOWNTO 1);
END CASE;
END PROCESS;
END sft;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_pos.vhd
|
10
|
6915
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT LIBRARY ***
--*** ***
--*** FP_POS.VHD ***
--*** ***
--*** Function: Local Count Leading Zeroes ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_pos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_pos;
ARCHITECTURE rtl of fp_pos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,5);
WHEN "000001" => position <= conv_std_logic_vector(start+5,5);
WHEN "000010" => position <= conv_std_logic_vector(start+4,5);
WHEN "000011" => position <= conv_std_logic_vector(start+4,5);
WHEN "000100" => position <= conv_std_logic_vector(start+3,5);
WHEN "000101" => position <= conv_std_logic_vector(start+3,5);
WHEN "000110" => position <= conv_std_logic_vector(start+3,5);
WHEN "000111" => position <= conv_std_logic_vector(start+3,5);
WHEN "001000" => position <= conv_std_logic_vector(start+2,5);
WHEN "001001" => position <= conv_std_logic_vector(start+2,5);
WHEN "001010" => position <= conv_std_logic_vector(start+2,5);
WHEN "001011" => position <= conv_std_logic_vector(start+2,5);
WHEN "001100" => position <= conv_std_logic_vector(start+2,5);
WHEN "001101" => position <= conv_std_logic_vector(start+2,5);
WHEN "001110" => position <= conv_std_logic_vector(start+2,5);
WHEN "001111" => position <= conv_std_logic_vector(start+2,5);
WHEN "010000" => position <= conv_std_logic_vector(start+1,5);
WHEN "010001" => position <= conv_std_logic_vector(start+1,5);
WHEN "010010" => position <= conv_std_logic_vector(start+1,5);
WHEN "010011" => position <= conv_std_logic_vector(start+1,5);
WHEN "010100" => position <= conv_std_logic_vector(start+1,5);
WHEN "010101" => position <= conv_std_logic_vector(start+1,5);
WHEN "010110" => position <= conv_std_logic_vector(start+1,5);
WHEN "010111" => position <= conv_std_logic_vector(start+1,5);
WHEN "011000" => position <= conv_std_logic_vector(start+1,5);
WHEN "011001" => position <= conv_std_logic_vector(start+1,5);
WHEN "011010" => position <= conv_std_logic_vector(start+1,5);
WHEN "011011" => position <= conv_std_logic_vector(start+1,5);
WHEN "011100" => position <= conv_std_logic_vector(start+1,5);
WHEN "011101" => position <= conv_std_logic_vector(start+1,5);
WHEN "011110" => position <= conv_std_logic_vector(start+1,5);
WHEN "011111" => position <= conv_std_logic_vector(start+1,5);
WHEN "100000" => position <= conv_std_logic_vector(start,5);
WHEN "100001" => position <= conv_std_logic_vector(start,5);
WHEN "100010" => position <= conv_std_logic_vector(start,5);
WHEN "100011" => position <= conv_std_logic_vector(start,5);
WHEN "100100" => position <= conv_std_logic_vector(start,5);
WHEN "100101" => position <= conv_std_logic_vector(start,5);
WHEN "100110" => position <= conv_std_logic_vector(start,5);
WHEN "100111" => position <= conv_std_logic_vector(start,5);
WHEN "101000" => position <= conv_std_logic_vector(start,5);
WHEN "101001" => position <= conv_std_logic_vector(start,5);
WHEN "101010" => position <= conv_std_logic_vector(start,5);
WHEN "101011" => position <= conv_std_logic_vector(start,5);
WHEN "101100" => position <= conv_std_logic_vector(start,5);
WHEN "101101" => position <= conv_std_logic_vector(start,5);
WHEN "101110" => position <= conv_std_logic_vector(start,5);
WHEN "101111" => position <= conv_std_logic_vector(start,5);
WHEN "110000" => position <= conv_std_logic_vector(start,5);
WHEN "110001" => position <= conv_std_logic_vector(start,5);
WHEN "110010" => position <= conv_std_logic_vector(start,5);
WHEN "110011" => position <= conv_std_logic_vector(start,5);
WHEN "110100" => position <= conv_std_logic_vector(start,5);
WHEN "110101" => position <= conv_std_logic_vector(start,5);
WHEN "110110" => position <= conv_std_logic_vector(start,5);
WHEN "110111" => position <= conv_std_logic_vector(start,5);
WHEN "111000" => position <= conv_std_logic_vector(start,5);
WHEN "111001" => position <= conv_std_logic_vector(start,5);
WHEN "111010" => position <= conv_std_logic_vector(start,5);
WHEN "111011" => position <= conv_std_logic_vector(start,5);
WHEN "111100" => position <= conv_std_logic_vector(start,5);
WHEN "111101" => position <= conv_std_logic_vector(start,5);
WHEN "111110" => position <= conv_std_logic_vector(start,5);
WHEN "111111" => position <= conv_std_logic_vector(start,5);
WHEN others => position <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dotProduct64_dut_sv.vhd
|
10
|
54182
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from dotProduct64_dut
-- VHDL created on Fri Oct 19 16:38:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.dotProduct64_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/SJ/nightly/12.1/173/w64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of dotProduct64_dut is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
-- dotProduct64_dut_prim component declaration
-- inputs
-- N/C
-- N/C
-- N/C
-- N/C
-- valid_s <= v_s, width=1, real=0
-- channel_s <= c_s, width=8, real=0
-- datain_a_00 <= datain_a_00, width=32, real=1
-- datain_a_01 <= datain_a_01, width=32, real=1
-- datain_a_02 <= datain_a_02, width=32, real=1
-- datain_a_03 <= datain_a_03, width=32, real=1
-- datain_a_04 <= datain_a_04, width=32, real=1
-- datain_a_05 <= datain_a_05, width=32, real=1
-- datain_a_06 <= datain_a_06, width=32, real=1
-- datain_a_07 <= datain_a_07, width=32, real=1
-- datain_a_08 <= datain_a_08, width=32, real=1
-- datain_a_09 <= datain_a_09, width=32, real=1
-- datain_a_10 <= datain_a_10, width=32, real=1
-- datain_a_11 <= datain_a_11, width=32, real=1
-- datain_a_12 <= datain_a_12, width=32, real=1
-- datain_a_13 <= datain_a_13, width=32, real=1
-- datain_a_14 <= datain_a_14, width=32, real=1
-- datain_a_15 <= datain_a_15, width=32, real=1
-- datain_a_16 <= datain_a_16, width=32, real=1
-- datain_a_17 <= datain_a_17, width=32, real=1
-- datain_a_18 <= datain_a_18, width=32, real=1
-- datain_a_19 <= datain_a_19, width=32, real=1
-- datain_a_20 <= datain_a_20, width=32, real=1
-- datain_a_21 <= datain_a_21, width=32, real=1
-- datain_a_22 <= datain_a_22, width=32, real=1
-- datain_a_23 <= datain_a_23, width=32, real=1
-- datain_a_24 <= datain_a_24, width=32, real=1
-- datain_a_25 <= datain_a_25, width=32, real=1
-- datain_a_26 <= datain_a_26, width=32, real=1
-- datain_a_27 <= datain_a_27, width=32, real=1
-- datain_a_28 <= datain_a_28, width=32, real=1
-- datain_a_29 <= datain_a_29, width=32, real=1
-- datain_a_30 <= datain_a_30, width=32, real=1
-- datain_a_31 <= datain_a_31, width=32, real=1
-- datain_a_32 <= datain_a_32, width=32, real=1
-- datain_a_33 <= datain_a_33, width=32, real=1
-- datain_a_34 <= datain_a_34, width=32, real=1
-- datain_a_35 <= datain_a_35, width=32, real=1
-- datain_a_36 <= datain_a_36, width=32, real=1
-- datain_a_37 <= datain_a_37, width=32, real=1
-- datain_a_38 <= datain_a_38, width=32, real=1
-- datain_a_39 <= datain_a_39, width=32, real=1
-- datain_a_40 <= datain_a_40, width=32, real=1
-- datain_a_41 <= datain_a_41, width=32, real=1
-- datain_a_42 <= datain_a_42, width=32, real=1
-- datain_a_43 <= datain_a_43, width=32, real=1
-- datain_a_44 <= datain_a_44, width=32, real=1
-- datain_a_45 <= datain_a_45, width=32, real=1
-- datain_a_46 <= datain_a_46, width=32, real=1
-- datain_a_47 <= datain_a_47, width=32, real=1
-- datain_a_48 <= datain_a_48, width=32, real=1
-- datain_a_49 <= datain_a_49, width=32, real=1
-- datain_a_50 <= datain_a_50, width=32, real=1
-- datain_a_51 <= datain_a_51, width=32, real=1
-- datain_a_52 <= datain_a_52, width=32, real=1
-- datain_a_53 <= datain_a_53, width=32, real=1
-- datain_a_54 <= datain_a_54, width=32, real=1
-- datain_a_55 <= datain_a_55, width=32, real=1
-- datain_a_56 <= datain_a_56, width=32, real=1
-- datain_a_57 <= datain_a_57, width=32, real=1
-- datain_a_58 <= datain_a_58, width=32, real=1
-- datain_a_59 <= datain_a_59, width=32, real=1
-- datain_a_60 <= datain_a_60, width=32, real=1
-- datain_a_61 <= datain_a_61, width=32, real=1
-- datain_a_62 <= datain_a_62, width=32, real=1
-- datain_a_63 <= datain_a_63, width=32, real=1
-- datain_b_00 <= datain_b_00, width=32, real=1
-- datain_b_01 <= datain_b_01, width=32, real=1
-- datain_b_02 <= datain_b_02, width=32, real=1
-- datain_b_03 <= datain_b_03, width=32, real=1
-- datain_b_04 <= datain_b_04, width=32, real=1
-- datain_b_05 <= datain_b_05, width=32, real=1
-- datain_b_06 <= datain_b_06, width=32, real=1
-- datain_b_07 <= datain_b_07, width=32, real=1
-- datain_b_08 <= datain_b_08, width=32, real=1
-- datain_b_09 <= datain_b_09, width=32, real=1
-- datain_b_10 <= datain_b_10, width=32, real=1
-- datain_b_11 <= datain_b_11, width=32, real=1
-- datain_b_12 <= datain_b_12, width=32, real=1
-- datain_b_13 <= datain_b_13, width=32, real=1
-- datain_b_14 <= datain_b_14, width=32, real=1
-- datain_b_15 <= datain_b_15, width=32, real=1
-- datain_b_16 <= datain_b_16, width=32, real=1
-- datain_b_17 <= datain_b_17, width=32, real=1
-- datain_b_18 <= datain_b_18, width=32, real=1
-- datain_b_19 <= datain_b_19, width=32, real=1
-- datain_b_20 <= datain_b_20, width=32, real=1
-- datain_b_21 <= datain_b_21, width=32, real=1
-- datain_b_22 <= datain_b_22, width=32, real=1
-- datain_b_23 <= datain_b_23, width=32, real=1
-- datain_b_24 <= datain_b_24, width=32, real=1
-- datain_b_25 <= datain_b_25, width=32, real=1
-- datain_b_26 <= datain_b_26, width=32, real=1
-- datain_b_27 <= datain_b_27, width=32, real=1
-- datain_b_28 <= datain_b_28, width=32, real=1
-- datain_b_29 <= datain_b_29, width=32, real=1
-- datain_b_30 <= datain_b_30, width=32, real=1
-- datain_b_31 <= datain_b_31, width=32, real=1
-- datain_b_32 <= datain_b_32, width=32, real=1
-- datain_b_33 <= datain_b_33, width=32, real=1
-- datain_b_34 <= datain_b_34, width=32, real=1
-- datain_b_35 <= datain_b_35, width=32, real=1
-- datain_b_36 <= datain_b_36, width=32, real=1
-- datain_b_37 <= datain_b_37, width=32, real=1
-- datain_b_38 <= datain_b_38, width=32, real=1
-- datain_b_39 <= datain_b_39, width=32, real=1
-- datain_b_40 <= datain_b_40, width=32, real=1
-- datain_b_41 <= datain_b_41, width=32, real=1
-- datain_b_42 <= datain_b_42, width=32, real=1
-- datain_b_43 <= datain_b_43, width=32, real=1
-- datain_b_44 <= datain_b_44, width=32, real=1
-- datain_b_45 <= datain_b_45, width=32, real=1
-- datain_b_46 <= datain_b_46, width=32, real=1
-- datain_b_47 <= datain_b_47, width=32, real=1
-- datain_b_48 <= datain_b_48, width=32, real=1
-- datain_b_49 <= datain_b_49, width=32, real=1
-- datain_b_50 <= datain_b_50, width=32, real=1
-- datain_b_51 <= datain_b_51, width=32, real=1
-- datain_b_52 <= datain_b_52, width=32, real=1
-- datain_b_53 <= datain_b_53, width=32, real=1
-- datain_b_54 <= datain_b_54, width=32, real=1
-- datain_b_55 <= datain_b_55, width=32, real=1
-- datain_b_56 <= datain_b_56, width=32, real=1
-- datain_b_57 <= datain_b_57, width=32, real=1
-- datain_b_58 <= datain_b_58, width=32, real=1
-- datain_b_59 <= datain_b_59, width=32, real=1
-- datain_b_60 <= datain_b_60, width=32, real=1
-- datain_b_61 <= datain_b_61, width=32, real=1
-- datain_b_62 <= datain_b_62, width=32, real=1
-- datain_b_63 <= datain_b_63, width=32, real=1
-- outputs
-- N/C
-- N/C
-- vout_s => dotProduct64_dut_prim_vout_s, width=1, real=0
-- cout_s => dotProduct64_dut_prim_cout_s, width=8, real=0
-- dout_s => dotProduct64_dut_prim_dout_s, width=32, real=1
component dotProduct64_dut_prim is
port (
valid_s : in std_logic_vector(0 downto 0);
channel_s : in std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
vout_s : out std_logic_vector(0 downto 0);
cout_s : out std_logic_vector(7 downto 0);
dout_s : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
signal dotProduct64_dut_prim_valid_s : std_logic_vector (0 downto 0);
signal dotProduct64_dut_prim_channel_s : std_logic_vector (7 downto 0);
signal dotProduct64_dut_prim_datain_a_00 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_01 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_02 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_03 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_04 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_05 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_06 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_07 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_08 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_09 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_10 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_11 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_12 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_13 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_14 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_15 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_16 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_17 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_18 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_19 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_20 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_21 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_22 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_23 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_24 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_25 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_26 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_27 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_28 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_29 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_30 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_31 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_32 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_33 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_34 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_35 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_36 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_37 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_38 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_39 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_40 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_41 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_42 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_43 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_44 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_45 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_46 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_47 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_48 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_49 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_50 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_51 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_52 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_53 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_54 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_55 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_56 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_57 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_58 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_59 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_60 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_61 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_62 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_a_63 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_00 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_01 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_02 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_03 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_04 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_05 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_06 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_07 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_08 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_09 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_10 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_11 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_12 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_13 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_14 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_15 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_16 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_17 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_18 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_19 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_20 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_21 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_22 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_23 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_24 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_25 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_26 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_27 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_28 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_29 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_30 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_31 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_32 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_33 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_34 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_35 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_36 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_37 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_38 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_39 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_40 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_41 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_42 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_43 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_44 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_45 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_46 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_47 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_48 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_49 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_50 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_51 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_52 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_53 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_54 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_55 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_56 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_57 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_58 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_59 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_60 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_61 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_62 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_datain_b_63 : std_logic_vector (31 downto 0);
signal dotProduct64_dut_prim_vout_s : std_logic_vector (0 downto 0);
signal dotProduct64_dut_prim_cout_s : std_logic_vector (7 downto 0);
signal dotProduct64_dut_prim_dout_s : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--u63_datain_b_auto(GPIN,131)
--u62_datain_b_auto(GPIN,130)
--u61_datain_b_auto(GPIN,129)
--u60_datain_b_auto(GPIN,128)
--u59_datain_b_auto(GPIN,127)
--u58_datain_b_auto(GPIN,126)
--u57_datain_b_auto(GPIN,125)
--u56_datain_b_auto(GPIN,124)
--u55_datain_b_auto(GPIN,123)
--u54_datain_b_auto(GPIN,122)
--u53_datain_b_auto(GPIN,121)
--u52_datain_b_auto(GPIN,120)
--u51_datain_b_auto(GPIN,119)
--u50_datain_b_auto(GPIN,118)
--u49_datain_b_auto(GPIN,117)
--u48_datain_b_auto(GPIN,116)
--u47_datain_b_auto(GPIN,115)
--u46_datain_b_auto(GPIN,114)
--u45_datain_b_auto(GPIN,113)
--u44_datain_b_auto(GPIN,112)
--u43_datain_b_auto(GPIN,111)
--u42_datain_b_auto(GPIN,110)
--u41_datain_b_auto(GPIN,109)
--u40_datain_b_auto(GPIN,108)
--u39_datain_b_auto(GPIN,107)
--u38_datain_b_auto(GPIN,106)
--u37_datain_b_auto(GPIN,105)
--u36_datain_b_auto(GPIN,104)
--u35_datain_b_auto(GPIN,103)
--u34_datain_b_auto(GPIN,102)
--u33_datain_b_auto(GPIN,101)
--u32_datain_b_auto(GPIN,100)
--u31_datain_b_auto(GPIN,99)
--u30_datain_b_auto(GPIN,98)
--u29_datain_b_auto(GPIN,97)
--u28_datain_b_auto(GPIN,96)
--u27_datain_b_auto(GPIN,95)
--u26_datain_b_auto(GPIN,94)
--u25_datain_b_auto(GPIN,93)
--u24_datain_b_auto(GPIN,92)
--u23_datain_b_auto(GPIN,91)
--u22_datain_b_auto(GPIN,90)
--u21_datain_b_auto(GPIN,89)
--u20_datain_b_auto(GPIN,88)
--u19_datain_b_auto(GPIN,87)
--u18_datain_b_auto(GPIN,86)
--u17_datain_b_auto(GPIN,85)
--u16_datain_b_auto(GPIN,84)
--u15_datain_b_auto(GPIN,83)
--u14_datain_b_auto(GPIN,82)
--u13_datain_b_auto(GPIN,81)
--u12_datain_b_auto(GPIN,80)
--u11_datain_b_auto(GPIN,79)
--u10_datain_b_auto(GPIN,78)
--u9_datain_b_auto(GPIN,77)
--u8_datain_b_auto(GPIN,76)
--u7_datain_b_auto(GPIN,75)
--u6_datain_b_auto(GPIN,74)
--u5_datain_b_auto(GPIN,73)
--u4_datain_b_auto(GPIN,72)
--u3_datain_b_auto(GPIN,71)
--u2_datain_b_auto(GPIN,70)
--u1_datain_b_auto(GPIN,69)
--u0_datain_b_auto(GPIN,68)
--u63_datain_a_auto(GPIN,67)
--u62_datain_a_auto(GPIN,66)
--u61_datain_a_auto(GPIN,65)
--u60_datain_a_auto(GPIN,64)
--u59_datain_a_auto(GPIN,63)
--u58_datain_a_auto(GPIN,62)
--u57_datain_a_auto(GPIN,61)
--u56_datain_a_auto(GPIN,60)
--u55_datain_a_auto(GPIN,59)
--u54_datain_a_auto(GPIN,58)
--u53_datain_a_auto(GPIN,57)
--u52_datain_a_auto(GPIN,56)
--u51_datain_a_auto(GPIN,55)
--u50_datain_a_auto(GPIN,54)
--u49_datain_a_auto(GPIN,53)
--u48_datain_a_auto(GPIN,52)
--u47_datain_a_auto(GPIN,51)
--u46_datain_a_auto(GPIN,50)
--u45_datain_a_auto(GPIN,49)
--u44_datain_a_auto(GPIN,48)
--u43_datain_a_auto(GPIN,47)
--u42_datain_a_auto(GPIN,46)
--u41_datain_a_auto(GPIN,45)
--u40_datain_a_auto(GPIN,44)
--u39_datain_a_auto(GPIN,43)
--u38_datain_a_auto(GPIN,42)
--u37_datain_a_auto(GPIN,41)
--u36_datain_a_auto(GPIN,40)
--u35_datain_a_auto(GPIN,39)
--u34_datain_a_auto(GPIN,38)
--u33_datain_a_auto(GPIN,37)
--u32_datain_a_auto(GPIN,36)
--u31_datain_a_auto(GPIN,35)
--u30_datain_a_auto(GPIN,34)
--u29_datain_a_auto(GPIN,33)
--u28_datain_a_auto(GPIN,32)
--u27_datain_a_auto(GPIN,31)
--u26_datain_a_auto(GPIN,30)
--u25_datain_a_auto(GPIN,29)
--u24_datain_a_auto(GPIN,28)
--u23_datain_a_auto(GPIN,27)
--u22_datain_a_auto(GPIN,26)
--u21_datain_a_auto(GPIN,25)
--u20_datain_a_auto(GPIN,24)
--u19_datain_a_auto(GPIN,23)
--u18_datain_a_auto(GPIN,22)
--u17_datain_a_auto(GPIN,21)
--u16_datain_a_auto(GPIN,20)
--u15_datain_a_auto(GPIN,19)
--u14_datain_a_auto(GPIN,18)
--u13_datain_a_auto(GPIN,17)
--u12_datain_a_auto(GPIN,16)
--u11_datain_a_auto(GPIN,15)
--u10_datain_a_auto(GPIN,14)
--u9_datain_a_auto(GPIN,13)
--u8_datain_a_auto(GPIN,12)
--u7_datain_a_auto(GPIN,11)
--u6_datain_a_auto(GPIN,10)
--u5_datain_a_auto(GPIN,9)
--u4_datain_a_auto(GPIN,8)
--u3_datain_a_auto(GPIN,7)
--u2_datain_a_auto(GPIN,6)
--u1_datain_a_auto(GPIN,5)
--u0_datain_a_auto(GPIN,4)
--c_auto(GPIN,2)
--v_auto(GPIN,134)
--dotProduct64_dut_prim(BLACKBOX,133)
dotProduct64_dut_prim_valid_s <= v_s;
dotProduct64_dut_prim_channel_s <= c_s;
dotProduct64_dut_prim_datain_a_00 <= datain_a_00;
dotProduct64_dut_prim_datain_a_01 <= datain_a_01;
dotProduct64_dut_prim_datain_a_02 <= datain_a_02;
dotProduct64_dut_prim_datain_a_03 <= datain_a_03;
dotProduct64_dut_prim_datain_a_04 <= datain_a_04;
dotProduct64_dut_prim_datain_a_05 <= datain_a_05;
dotProduct64_dut_prim_datain_a_06 <= datain_a_06;
dotProduct64_dut_prim_datain_a_07 <= datain_a_07;
dotProduct64_dut_prim_datain_a_08 <= datain_a_08;
dotProduct64_dut_prim_datain_a_09 <= datain_a_09;
dotProduct64_dut_prim_datain_a_10 <= datain_a_10;
dotProduct64_dut_prim_datain_a_11 <= datain_a_11;
dotProduct64_dut_prim_datain_a_12 <= datain_a_12;
dotProduct64_dut_prim_datain_a_13 <= datain_a_13;
dotProduct64_dut_prim_datain_a_14 <= datain_a_14;
dotProduct64_dut_prim_datain_a_15 <= datain_a_15;
dotProduct64_dut_prim_datain_a_16 <= datain_a_16;
dotProduct64_dut_prim_datain_a_17 <= datain_a_17;
dotProduct64_dut_prim_datain_a_18 <= datain_a_18;
dotProduct64_dut_prim_datain_a_19 <= datain_a_19;
dotProduct64_dut_prim_datain_a_20 <= datain_a_20;
dotProduct64_dut_prim_datain_a_21 <= datain_a_21;
dotProduct64_dut_prim_datain_a_22 <= datain_a_22;
dotProduct64_dut_prim_datain_a_23 <= datain_a_23;
dotProduct64_dut_prim_datain_a_24 <= datain_a_24;
dotProduct64_dut_prim_datain_a_25 <= datain_a_25;
dotProduct64_dut_prim_datain_a_26 <= datain_a_26;
dotProduct64_dut_prim_datain_a_27 <= datain_a_27;
dotProduct64_dut_prim_datain_a_28 <= datain_a_28;
dotProduct64_dut_prim_datain_a_29 <= datain_a_29;
dotProduct64_dut_prim_datain_a_30 <= datain_a_30;
dotProduct64_dut_prim_datain_a_31 <= datain_a_31;
dotProduct64_dut_prim_datain_a_32 <= datain_a_32;
dotProduct64_dut_prim_datain_a_33 <= datain_a_33;
dotProduct64_dut_prim_datain_a_34 <= datain_a_34;
dotProduct64_dut_prim_datain_a_35 <= datain_a_35;
dotProduct64_dut_prim_datain_a_36 <= datain_a_36;
dotProduct64_dut_prim_datain_a_37 <= datain_a_37;
dotProduct64_dut_prim_datain_a_38 <= datain_a_38;
dotProduct64_dut_prim_datain_a_39 <= datain_a_39;
dotProduct64_dut_prim_datain_a_40 <= datain_a_40;
dotProduct64_dut_prim_datain_a_41 <= datain_a_41;
dotProduct64_dut_prim_datain_a_42 <= datain_a_42;
dotProduct64_dut_prim_datain_a_43 <= datain_a_43;
dotProduct64_dut_prim_datain_a_44 <= datain_a_44;
dotProduct64_dut_prim_datain_a_45 <= datain_a_45;
dotProduct64_dut_prim_datain_a_46 <= datain_a_46;
dotProduct64_dut_prim_datain_a_47 <= datain_a_47;
dotProduct64_dut_prim_datain_a_48 <= datain_a_48;
dotProduct64_dut_prim_datain_a_49 <= datain_a_49;
dotProduct64_dut_prim_datain_a_50 <= datain_a_50;
dotProduct64_dut_prim_datain_a_51 <= datain_a_51;
dotProduct64_dut_prim_datain_a_52 <= datain_a_52;
dotProduct64_dut_prim_datain_a_53 <= datain_a_53;
dotProduct64_dut_prim_datain_a_54 <= datain_a_54;
dotProduct64_dut_prim_datain_a_55 <= datain_a_55;
dotProduct64_dut_prim_datain_a_56 <= datain_a_56;
dotProduct64_dut_prim_datain_a_57 <= datain_a_57;
dotProduct64_dut_prim_datain_a_58 <= datain_a_58;
dotProduct64_dut_prim_datain_a_59 <= datain_a_59;
dotProduct64_dut_prim_datain_a_60 <= datain_a_60;
dotProduct64_dut_prim_datain_a_61 <= datain_a_61;
dotProduct64_dut_prim_datain_a_62 <= datain_a_62;
dotProduct64_dut_prim_datain_a_63 <= datain_a_63;
dotProduct64_dut_prim_datain_b_00 <= datain_b_00;
dotProduct64_dut_prim_datain_b_01 <= datain_b_01;
dotProduct64_dut_prim_datain_b_02 <= datain_b_02;
dotProduct64_dut_prim_datain_b_03 <= datain_b_03;
dotProduct64_dut_prim_datain_b_04 <= datain_b_04;
dotProduct64_dut_prim_datain_b_05 <= datain_b_05;
dotProduct64_dut_prim_datain_b_06 <= datain_b_06;
dotProduct64_dut_prim_datain_b_07 <= datain_b_07;
dotProduct64_dut_prim_datain_b_08 <= datain_b_08;
dotProduct64_dut_prim_datain_b_09 <= datain_b_09;
dotProduct64_dut_prim_datain_b_10 <= datain_b_10;
dotProduct64_dut_prim_datain_b_11 <= datain_b_11;
dotProduct64_dut_prim_datain_b_12 <= datain_b_12;
dotProduct64_dut_prim_datain_b_13 <= datain_b_13;
dotProduct64_dut_prim_datain_b_14 <= datain_b_14;
dotProduct64_dut_prim_datain_b_15 <= datain_b_15;
dotProduct64_dut_prim_datain_b_16 <= datain_b_16;
dotProduct64_dut_prim_datain_b_17 <= datain_b_17;
dotProduct64_dut_prim_datain_b_18 <= datain_b_18;
dotProduct64_dut_prim_datain_b_19 <= datain_b_19;
dotProduct64_dut_prim_datain_b_20 <= datain_b_20;
dotProduct64_dut_prim_datain_b_21 <= datain_b_21;
dotProduct64_dut_prim_datain_b_22 <= datain_b_22;
dotProduct64_dut_prim_datain_b_23 <= datain_b_23;
dotProduct64_dut_prim_datain_b_24 <= datain_b_24;
dotProduct64_dut_prim_datain_b_25 <= datain_b_25;
dotProduct64_dut_prim_datain_b_26 <= datain_b_26;
dotProduct64_dut_prim_datain_b_27 <= datain_b_27;
dotProduct64_dut_prim_datain_b_28 <= datain_b_28;
dotProduct64_dut_prim_datain_b_29 <= datain_b_29;
dotProduct64_dut_prim_datain_b_30 <= datain_b_30;
dotProduct64_dut_prim_datain_b_31 <= datain_b_31;
dotProduct64_dut_prim_datain_b_32 <= datain_b_32;
dotProduct64_dut_prim_datain_b_33 <= datain_b_33;
dotProduct64_dut_prim_datain_b_34 <= datain_b_34;
dotProduct64_dut_prim_datain_b_35 <= datain_b_35;
dotProduct64_dut_prim_datain_b_36 <= datain_b_36;
dotProduct64_dut_prim_datain_b_37 <= datain_b_37;
dotProduct64_dut_prim_datain_b_38 <= datain_b_38;
dotProduct64_dut_prim_datain_b_39 <= datain_b_39;
dotProduct64_dut_prim_datain_b_40 <= datain_b_40;
dotProduct64_dut_prim_datain_b_41 <= datain_b_41;
dotProduct64_dut_prim_datain_b_42 <= datain_b_42;
dotProduct64_dut_prim_datain_b_43 <= datain_b_43;
dotProduct64_dut_prim_datain_b_44 <= datain_b_44;
dotProduct64_dut_prim_datain_b_45 <= datain_b_45;
dotProduct64_dut_prim_datain_b_46 <= datain_b_46;
dotProduct64_dut_prim_datain_b_47 <= datain_b_47;
dotProduct64_dut_prim_datain_b_48 <= datain_b_48;
dotProduct64_dut_prim_datain_b_49 <= datain_b_49;
dotProduct64_dut_prim_datain_b_50 <= datain_b_50;
dotProduct64_dut_prim_datain_b_51 <= datain_b_51;
dotProduct64_dut_prim_datain_b_52 <= datain_b_52;
dotProduct64_dut_prim_datain_b_53 <= datain_b_53;
dotProduct64_dut_prim_datain_b_54 <= datain_b_54;
dotProduct64_dut_prim_datain_b_55 <= datain_b_55;
dotProduct64_dut_prim_datain_b_56 <= datain_b_56;
dotProduct64_dut_prim_datain_b_57 <= datain_b_57;
dotProduct64_dut_prim_datain_b_58 <= datain_b_58;
dotProduct64_dut_prim_datain_b_59 <= datain_b_59;
dotProduct64_dut_prim_datain_b_60 <= datain_b_60;
dotProduct64_dut_prim_datain_b_61 <= datain_b_61;
dotProduct64_dut_prim_datain_b_62 <= datain_b_62;
dotProduct64_dut_prim_datain_b_63 <= datain_b_63;
thedotProduct64_dut_prim : dotProduct64_dut_prim port map (
valid_s => dotProduct64_dut_prim_valid_s,
channel_s => dotProduct64_dut_prim_channel_s,
datain_a_00 => dotProduct64_dut_prim_datain_a_00,
datain_a_01 => dotProduct64_dut_prim_datain_a_01,
datain_a_02 => dotProduct64_dut_prim_datain_a_02,
datain_a_03 => dotProduct64_dut_prim_datain_a_03,
datain_a_04 => dotProduct64_dut_prim_datain_a_04,
datain_a_05 => dotProduct64_dut_prim_datain_a_05,
datain_a_06 => dotProduct64_dut_prim_datain_a_06,
datain_a_07 => dotProduct64_dut_prim_datain_a_07,
datain_a_08 => dotProduct64_dut_prim_datain_a_08,
datain_a_09 => dotProduct64_dut_prim_datain_a_09,
datain_a_10 => dotProduct64_dut_prim_datain_a_10,
datain_a_11 => dotProduct64_dut_prim_datain_a_11,
datain_a_12 => dotProduct64_dut_prim_datain_a_12,
datain_a_13 => dotProduct64_dut_prim_datain_a_13,
datain_a_14 => dotProduct64_dut_prim_datain_a_14,
datain_a_15 => dotProduct64_dut_prim_datain_a_15,
datain_a_16 => dotProduct64_dut_prim_datain_a_16,
datain_a_17 => dotProduct64_dut_prim_datain_a_17,
datain_a_18 => dotProduct64_dut_prim_datain_a_18,
datain_a_19 => dotProduct64_dut_prim_datain_a_19,
datain_a_20 => dotProduct64_dut_prim_datain_a_20,
datain_a_21 => dotProduct64_dut_prim_datain_a_21,
datain_a_22 => dotProduct64_dut_prim_datain_a_22,
datain_a_23 => dotProduct64_dut_prim_datain_a_23,
datain_a_24 => dotProduct64_dut_prim_datain_a_24,
datain_a_25 => dotProduct64_dut_prim_datain_a_25,
datain_a_26 => dotProduct64_dut_prim_datain_a_26,
datain_a_27 => dotProduct64_dut_prim_datain_a_27,
datain_a_28 => dotProduct64_dut_prim_datain_a_28,
datain_a_29 => dotProduct64_dut_prim_datain_a_29,
datain_a_30 => dotProduct64_dut_prim_datain_a_30,
datain_a_31 => dotProduct64_dut_prim_datain_a_31,
datain_a_32 => dotProduct64_dut_prim_datain_a_32,
datain_a_33 => dotProduct64_dut_prim_datain_a_33,
datain_a_34 => dotProduct64_dut_prim_datain_a_34,
datain_a_35 => dotProduct64_dut_prim_datain_a_35,
datain_a_36 => dotProduct64_dut_prim_datain_a_36,
datain_a_37 => dotProduct64_dut_prim_datain_a_37,
datain_a_38 => dotProduct64_dut_prim_datain_a_38,
datain_a_39 => dotProduct64_dut_prim_datain_a_39,
datain_a_40 => dotProduct64_dut_prim_datain_a_40,
datain_a_41 => dotProduct64_dut_prim_datain_a_41,
datain_a_42 => dotProduct64_dut_prim_datain_a_42,
datain_a_43 => dotProduct64_dut_prim_datain_a_43,
datain_a_44 => dotProduct64_dut_prim_datain_a_44,
datain_a_45 => dotProduct64_dut_prim_datain_a_45,
datain_a_46 => dotProduct64_dut_prim_datain_a_46,
datain_a_47 => dotProduct64_dut_prim_datain_a_47,
datain_a_48 => dotProduct64_dut_prim_datain_a_48,
datain_a_49 => dotProduct64_dut_prim_datain_a_49,
datain_a_50 => dotProduct64_dut_prim_datain_a_50,
datain_a_51 => dotProduct64_dut_prim_datain_a_51,
datain_a_52 => dotProduct64_dut_prim_datain_a_52,
datain_a_53 => dotProduct64_dut_prim_datain_a_53,
datain_a_54 => dotProduct64_dut_prim_datain_a_54,
datain_a_55 => dotProduct64_dut_prim_datain_a_55,
datain_a_56 => dotProduct64_dut_prim_datain_a_56,
datain_a_57 => dotProduct64_dut_prim_datain_a_57,
datain_a_58 => dotProduct64_dut_prim_datain_a_58,
datain_a_59 => dotProduct64_dut_prim_datain_a_59,
datain_a_60 => dotProduct64_dut_prim_datain_a_60,
datain_a_61 => dotProduct64_dut_prim_datain_a_61,
datain_a_62 => dotProduct64_dut_prim_datain_a_62,
datain_a_63 => dotProduct64_dut_prim_datain_a_63,
datain_b_00 => dotProduct64_dut_prim_datain_b_00,
datain_b_01 => dotProduct64_dut_prim_datain_b_01,
datain_b_02 => dotProduct64_dut_prim_datain_b_02,
datain_b_03 => dotProduct64_dut_prim_datain_b_03,
datain_b_04 => dotProduct64_dut_prim_datain_b_04,
datain_b_05 => dotProduct64_dut_prim_datain_b_05,
datain_b_06 => dotProduct64_dut_prim_datain_b_06,
datain_b_07 => dotProduct64_dut_prim_datain_b_07,
datain_b_08 => dotProduct64_dut_prim_datain_b_08,
datain_b_09 => dotProduct64_dut_prim_datain_b_09,
datain_b_10 => dotProduct64_dut_prim_datain_b_10,
datain_b_11 => dotProduct64_dut_prim_datain_b_11,
datain_b_12 => dotProduct64_dut_prim_datain_b_12,
datain_b_13 => dotProduct64_dut_prim_datain_b_13,
datain_b_14 => dotProduct64_dut_prim_datain_b_14,
datain_b_15 => dotProduct64_dut_prim_datain_b_15,
datain_b_16 => dotProduct64_dut_prim_datain_b_16,
datain_b_17 => dotProduct64_dut_prim_datain_b_17,
datain_b_18 => dotProduct64_dut_prim_datain_b_18,
datain_b_19 => dotProduct64_dut_prim_datain_b_19,
datain_b_20 => dotProduct64_dut_prim_datain_b_20,
datain_b_21 => dotProduct64_dut_prim_datain_b_21,
datain_b_22 => dotProduct64_dut_prim_datain_b_22,
datain_b_23 => dotProduct64_dut_prim_datain_b_23,
datain_b_24 => dotProduct64_dut_prim_datain_b_24,
datain_b_25 => dotProduct64_dut_prim_datain_b_25,
datain_b_26 => dotProduct64_dut_prim_datain_b_26,
datain_b_27 => dotProduct64_dut_prim_datain_b_27,
datain_b_28 => dotProduct64_dut_prim_datain_b_28,
datain_b_29 => dotProduct64_dut_prim_datain_b_29,
datain_b_30 => dotProduct64_dut_prim_datain_b_30,
datain_b_31 => dotProduct64_dut_prim_datain_b_31,
datain_b_32 => dotProduct64_dut_prim_datain_b_32,
datain_b_33 => dotProduct64_dut_prim_datain_b_33,
datain_b_34 => dotProduct64_dut_prim_datain_b_34,
datain_b_35 => dotProduct64_dut_prim_datain_b_35,
datain_b_36 => dotProduct64_dut_prim_datain_b_36,
datain_b_37 => dotProduct64_dut_prim_datain_b_37,
datain_b_38 => dotProduct64_dut_prim_datain_b_38,
datain_b_39 => dotProduct64_dut_prim_datain_b_39,
datain_b_40 => dotProduct64_dut_prim_datain_b_40,
datain_b_41 => dotProduct64_dut_prim_datain_b_41,
datain_b_42 => dotProduct64_dut_prim_datain_b_42,
datain_b_43 => dotProduct64_dut_prim_datain_b_43,
datain_b_44 => dotProduct64_dut_prim_datain_b_44,
datain_b_45 => dotProduct64_dut_prim_datain_b_45,
datain_b_46 => dotProduct64_dut_prim_datain_b_46,
datain_b_47 => dotProduct64_dut_prim_datain_b_47,
datain_b_48 => dotProduct64_dut_prim_datain_b_48,
datain_b_49 => dotProduct64_dut_prim_datain_b_49,
datain_b_50 => dotProduct64_dut_prim_datain_b_50,
datain_b_51 => dotProduct64_dut_prim_datain_b_51,
datain_b_52 => dotProduct64_dut_prim_datain_b_52,
datain_b_53 => dotProduct64_dut_prim_datain_b_53,
datain_b_54 => dotProduct64_dut_prim_datain_b_54,
datain_b_55 => dotProduct64_dut_prim_datain_b_55,
datain_b_56 => dotProduct64_dut_prim_datain_b_56,
datain_b_57 => dotProduct64_dut_prim_datain_b_57,
datain_b_58 => dotProduct64_dut_prim_datain_b_58,
datain_b_59 => dotProduct64_dut_prim_datain_b_59,
datain_b_60 => dotProduct64_dut_prim_datain_b_60,
datain_b_61 => dotProduct64_dut_prim_datain_b_61,
datain_b_62 => dotProduct64_dut_prim_datain_b_62,
datain_b_63 => dotProduct64_dut_prim_datain_b_63,
vout_s => dotProduct64_dut_prim_vout_s,
cout_s => dotProduct64_dut_prim_cout_s,
dout_s => dotProduct64_dut_prim_dout_s,
clk => clk,
areset => areset,
h_areset => h_areset
);
--cout_auto(GPOUT,3)
cout_s <= dotProduct64_dut_prim_cout_s;
--dout_auto(GPOUT,132)
dout_s <= dotProduct64_dut_prim_dout_s;
--vout_auto(GPOUT,135)
vout_s <= dotProduct64_dut_prim_vout_s;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_exp2_double_s5.vhd
|
10
|
562595
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_sum36x18.vhd
|
10
|
18695
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_castxtof.vhd
|
10
|
11513
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOF.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 9&10 of expnode to check zero & max ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--******************************************************************************
ENTITY hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtof;
ARCHITECTURE rtl OF hcc_castxtof IS
-- latency = 5 if normspeed = 1
-- latency = 7 if normspeed = 2 (extra pipe in normusgn3236 and output stage)
type exptopfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type expbotfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal count : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal absnode, absroundnode, absff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : expbotfftype;
signal roundoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal satff, zipff : STD_LOGIC_VECTOR (3+normspeed DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2+2*normspeed DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal preexpnode, expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal mantissaroundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
signal ccsgn : STD_LOGIC;
signal aaexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (23 DOWNTO 1);
component hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
absff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
roundoverflowff <= '0';
FOR k IN 1 TO 3+normspeed LOOP --27/05/09
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2+2*normspeed LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
absff <= absnode + absroundnode;
fracoutff <= fracout;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
-- add 4 because of maximum 4 bits wordgrowth in X mantissa
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) + "0000000100";
exptopff(3)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1) - ("0000" & count);
roundoverflowff <= roundoverflow(24);
satff(1) <= aasat;
FOR k IN 2 TO 3+normspeed LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO 3+normspeed LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(mantissa+10);
FOR k IN 2 TO 2+2*normspeed LOOP
signff(k) <= signff(k-1);
END LOOP;
zeronumberff(1) <= NOT(zeronumber(mantissa));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsa: IF (normspeed = 1) GENERATE
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode; -- 27/05/09
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= mantissanode(k) AND NOT(zeromantissanode);
END LOOP;
END IF;
END IF;
END PROCESS;
preexpnode <= exptopff(3)(10 DOWNTO 1);
END GENERATE;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsb: IF (normspeed = 2) GENERATE
pnb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
expbotff(1)(10 DOWNTO 1) <= "0000000000";
expbotff(2)(10 DOWNTO 1) <= "0000000000";
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaroundff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(1)(10 DOWNTO 1) <= exptopff(3)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expnode;
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expbotff(2)(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
mantissaroundff <= mantissanode;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END IF;
END PROCESS;
preexpnode <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
-- round absolute value any way - need register on input of cntusgn
gaa: FOR k IN 1 TO mantissa GENERATE
absnode(k) <= aaff(k+10) XOR aaff(mantissa+10);
END GENERATE;
absroundnode <= zerovec(mantissa-1 DOWNTO 1) & aaff(mantissa+10);
zeronumber(1) <= absff(1);
gzma: FOR k IN 2 TO mantissa GENERATE
zeronumber(k) <= zeronumber(k-1) OR absff(k);
END GENERATE;
core: hcc_normusgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absff(mantissa DOWNTO 1),countout=>count,
fracout=>fracout);
roundoverflow(1) <= fracout(7);
gna: FOR k IN 2 TO 24 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+6);
END GENERATE;
expnode <= preexpnode(10 DOWNTO 1) + ("000000000" & roundoverflowff);
-- always round single output (round to nearest even - 27/05/09)
roundbit <= (fracoutff(mantissa-24) AND fracoutff(mantissa-25)) OR
(NOT(fracoutff(mantissa-24)) AND fracoutff(mantissa-25) AND
(fracoutff(mantissa-26) OR fracoutff(mantissa-27) OR fracoutff(mantissa-28)));
-- always round single output
mantissanode <= fracoutff(mantissa-2 DOWNTO mantissa-24) +
(zerovec(22 DOWNTO 1) & roundbit);
-- 29/06/09 - look at all of expnode, not just lower 8 bits to get zero or max
zeroexpnode <= NOT(expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR
expnode(6) OR expnode(5) OR expnode(4) OR
expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(10)) AND NOT(expnode(9)) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 24/03/09 - zeroexpnode, maxexpnode also zeros mantissa (SRC bug)
zeromantissanode <= roundoverflowff OR zeroexpnode OR maxexpnode OR
expnode(9) OR expnode(10) OR
zipff(3+normspeed) OR satff(3+normspeed) OR
zeronumberff(1+normspeed);
zeroexponentnode <= zeroexpnode OR expnode(10) OR
zipff(3+normspeed) OR zeronumberff(1+normspeed);
maxexponentnode <= maxexpnode OR (expnode(9) AND NOT(expnode(10))) OR satff(3+normspeed);
--*** OUTPUTS ***
cc(32) <= signff(2+2*normspeed);
cc(31 DOWNTO 24) <= exponentff;
cc(23 DOWNTO 1) <= mantissaff(23 DOWNTO 1);
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccsgn <= signff(2+2*normspeed);
ccexp <= exponentff;
ccman <= mantissaff(23 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_package.vhd
|
10
|
12965
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - removed divides (now a library ***
--*** function ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 0; -- 0 = none, 1 = scale
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 0 -- 1 = to another double muliplier (s/1u52/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castytox IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_package.vhd
|
10
|
12965
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - removed divides (now a library ***
--*** function ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 0; -- 0 = none, 1 = scale
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 0 -- 1 = to another double muliplier (s/1u52/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castytox IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_sinpi_s5.vhd
|
10
|
314232
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_castltox.vhd
|
10
|
3526
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOX.VHD ***
--*** ***
--*** Function: Cast Long to Internal Single ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltox IS
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltox;
ARCHITECTURE rtl OF hcc_castltox IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
ccsat <= '0';
cczip <= '0';
END rtl;
|
mit
|
CamelClarkson/MIPS
|
MIPS_Design/Src/32x32_Mem.vhd
|
2
|
10087
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity Reg_Depth. This is the 32-bit memory/depth at each address of the register
entity Reg_Depth is
Port (
i_Clk : in std_logic; --Input clock
i_Data : in std_logic_vector(31 downto 0); --Input Data
i_Rst : in std_logic; --Input Reset (Active High)
i_w_en : in std_logic; --Read/Write enable
i_rA_sel : in std_logic; --Select bit for tri state buffer for data A
i_rB_sel : in std_logic; --Select bit for tri state buffer for Data B
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Reg_Depth;
architecture structural of Reg_Depth is
--Declares the RFC component
component RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end component;
begin
--Instatiates 32 RFCs that control the memory. 32 of them are instatiated because there are 32-bits at each depth
--because they are 1 bit each. 32 bit values are routed to i_data, R_sel_A, and R_sel_B to select which data is outputted,
--or written to.
Inst_RFC31: RFC
port map(
iClk => i_Clk, --Input Clock
i_Rst => i_Rst, --asynchronous reset
w_sel => i_w_en, --Read/Write enable
i_data => i_Data(31),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(31),
B => o_Data_B(31)
);
Inst_RFC30: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(30),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(30),
B => o_Data_B(30)
);
Inst_RFC29: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(29),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(29),
B => o_Data_B(29)
);
Inst_RFC28: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(28),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(28),
B => o_Data_B(28)
);
Inst_RFC27: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(27),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(27),
B => o_Data_B(27)
);
Inst_RFC26: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(26),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(26),
B => o_Data_B(26)
);
Inst_RFC25: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(25),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(25),
B => o_Data_B(25)
);
Inst_RFC24: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(24),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(24),
B => o_Data_B(24)
);
Inst_RFC23: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(23),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(23),
B => o_Data_B(23)
);
Inst_RFC22: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(22),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(22),
B => o_Data_B(22)
);
Inst_RFC21: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(21),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(21),
B => o_Data_B(21)
);
Inst_RFC20: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(20),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(20),
B => o_Data_B(20)
);
Inst_RFC19: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(19),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(19),
B => o_Data_B(19)
);
Inst_RFC18: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(18),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(18),
B => o_Data_B(18)
);
Inst_RFC17: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(17),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(17),
B => o_Data_B(17)
);
Inst_RFC16: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(16),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(16),
B => o_Data_B(16)
);
Inst_RFC15: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(15),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(15),
B => o_Data_B(15)
);
Inst_RFC14: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(14),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(14),
B => o_Data_B(14)
);
Inst_RFC13: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(13),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(13),
B => o_Data_B(13)
);
Inst_RFC12: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(12),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(12),
B => o_Data_B(12)
);
Inst_RFC11: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(11),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(11),
B => o_Data_B(11)
);
Inst_RFC10: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(10),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(10),
B => o_Data_B(10)
);
Inst_RFC9: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(9),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(9),
B => o_Data_B(9)
);
Inst_RFC8: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(8),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(8),
B => o_Data_B(8)
);
Inst_RFC7: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(7),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(7),
B => o_Data_B(7)
);
Inst_RFC6: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(6),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(6),
B => o_Data_B(6)
);
Inst_RFC5: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(5),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(5),
B => o_Data_B(5)
);
Inst_RFC4: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(4),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(4),
B => o_Data_B(4)
);
Inst_RFC3: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(3),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(3),
B => o_Data_B(3)
);
Inst_RFC2: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(2),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(2),
B => o_Data_B(2)
);
Inst_RFC1: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(1),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(1),
B => o_Data_B(1)
);
Inst_RFC0: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(0),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(0),
B => o_Data_B(0)
);
end structural;
|
mit
|
CamelClarkson/MIPS
|
MIPS_Design/Src/Register.vhd
|
2
|
10074
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downto 0);
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Register32X32;
architecture Behavioral of Register32X32 is
component Reg_Depth is
Port (
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic;
i_rA_sel : in std_logic;
i_rB_sel : in std_logic;
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end component;
begin
Inst_Reg_Depth31: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(31),
i_rA_sel => i_rA_sel(31),
i_rB_sel => i_rB_sel(31),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth30: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(30),
i_rA_sel => i_rA_sel(30),
i_rB_sel => i_rB_sel(30),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth29: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(29),
i_rA_sel => i_rA_sel(29),
i_rB_sel => i_rB_sel(29),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth28: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(28),
i_rA_sel => i_rA_sel(28),
i_rB_sel => i_rB_sel(28),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth27: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(27),
i_rA_sel => i_rA_sel(27),
i_rB_sel => i_rB_sel(27),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth26: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(26),
i_rA_sel => i_rA_sel(26),
i_rB_sel => i_rB_sel(26),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth25: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(25),
i_rA_sel => i_rA_sel(25),
i_rB_sel => i_rB_sel(25),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth24: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(24),
i_rA_sel => i_rA_sel(24),
i_rB_sel => i_rB_sel(24),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth23: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(23),
i_rA_sel => i_rA_sel(23),
i_rB_sel => i_rB_sel(23),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth22: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(22),
i_rA_sel => i_rA_sel(22),
i_rB_sel => i_rB_sel(22),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth21: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(21),
i_rA_sel => i_rA_sel(21),
i_rB_sel => i_rB_sel(21),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth20: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(20),
i_rA_sel => i_rA_sel(20),
i_rB_sel => i_rB_sel(20),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth19: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(19),
i_rA_sel => i_rA_sel(19),
i_rB_sel => i_rB_sel(19),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth18: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(18),
i_rA_sel => i_rA_sel(18),
i_rB_sel => i_rB_sel(18),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth17: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(17),
i_rA_sel => i_rA_sel(17),
i_rB_sel => i_rB_sel(17),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth16: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(16),
i_rA_sel => i_rA_sel(16),
i_rB_sel => i_rB_sel(16),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth15: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(15),
i_rA_sel => i_rA_sel(15),
i_rB_sel => i_rB_sel(15),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth14: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(14),
i_rA_sel => i_rA_sel(14),
i_rB_sel => i_rB_sel(14),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth13: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(13),
i_rA_sel => i_rA_sel(13),
i_rB_sel => i_rB_sel(13),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth12: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(12),
i_rA_sel => i_rA_sel(12),
i_rB_sel => i_rB_sel(12),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth11: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(11),
i_rA_sel => i_rA_sel(11),
i_rB_sel => i_rB_sel(11),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth10: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(10),
i_rA_sel => i_rA_sel(10),
i_rB_sel => i_rB_sel(10),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth9: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(9),
i_rA_sel => i_rA_sel(9),
i_rB_sel => i_rB_sel(9),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth8: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(8),
i_rA_sel => i_rA_sel(8),
i_rB_sel => i_rB_sel(8),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth7: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(7),
i_rA_sel => i_rA_sel(7),
i_rB_sel => i_rB_sel(7),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth6: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(6),
i_rA_sel => i_rA_sel(6),
i_rB_sel => i_rB_sel(6),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth5: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(5),
i_rA_sel => i_rA_sel(5),
i_rB_sel => i_rB_sel(5),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth4: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(4),
i_rA_sel => i_rA_sel(4),
i_rB_sel => i_rB_sel(4),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth3: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(3),
i_rA_sel => i_rA_sel(3),
i_rB_sel => i_rB_sel(3),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth2: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(2),
i_rA_sel => i_rA_sel(2),
i_rB_sel => i_rB_sel(2),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth1: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(1),
i_rA_sel => i_rA_sel(1),
i_rB_sel => i_rB_sel(1),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth0: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(0),
i_rA_sel => i_rA_sel(0),
i_rB_sel => i_rB_sel(0),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
end Behavioral;
|
mit
|
CamelClarkson/MIPS
|
MIPS_Design/Src/RFC.vhd
|
2
|
1440
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end RFC;
architecture Behavioral of RFC is
--Declares signals in processing the input logic
signal d_in : std_logic;
signal q_out : std_logic;
--Declares the D Flip Flop to be used
component DFlipFlop is
Port (
iClk : in std_logic;
D : in std_logic;
iRst : in std_logic;
Q : out std_logic
);
end component;
begin
--Instatiates the component D Flip Flop
inst_DFlipFlop: DFlipFlop
port map(
iClk => iClk,
D => d_in,
iRst => i_Rst,
Q => q_out
);
--Creates input logic to the D Flip Flop, which is the d_in for the flip flop
d_in <= (w_sel AND i_data) OR (not(w_sel) AND q_out);
--Creates a tri state buffer based on the select bit. If the either of the select bits are high, the entity outputs data
A <= q_out when (R_sel_A = '1') else 'Z';
B <= q_out when (R_sel_B = '1') else 'Z';
end Behavioral;
|
mit
|
CamelClarkson/MIPS
|
ALU_Control/source/ALU_Ctrl_top.vhd
|
2
|
1935
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU_Ctrl_top is
Port (
Op5 : in STD_LOGIC; -- input of the ALU ctrl module
Op4 : in STD_LOGIC; -- input of the ALU ctrl module
Op3 : in STD_LOGIC; -- input of the ALU ctrl module
Op2 : in STD_LOGIC; -- input of the ALU ctrl module
Op1 : in STD_LOGIC; -- input of the ALU ctrl module
Op0 : in STD_LOGIC; -- input of the ALU ctrl module
RegDst : out STD_LOGIC; -- output the ALU ctrl module
ALUSrc : out STD_LOGIC; -- output the ALU ctrl module
MemtoReg : out STD_LOGIC; -- output the ALU ctrl module
RegWrite : out STD_LOGIC; -- output the ALU ctrl module
MemRead : out STD_LOGIC; -- output the ALU ctrl module
MemWrite : out STD_LOGIC; -- output the ALU ctrl module
Branch : out STD_LOGIC; -- output the ALU ctrl module
ALUOp1 : out STD_LOGIC; -- output the ALU ctrl module
ALUOp0 : out STD_LOGIC -- output the ALU ctrl module
);
end ALU_Ctrl_top;
architecture Behavioral of ALU_Ctrl_top is
signal R_format : std_logic;
signal lw : std_logic;
signal sw : std_logic;
signal beq : std_logic;
begin
R_format <= ( (not(Op5)) and (not(Op4)) and (not(Op3)) and (not(Op2)) and (not(Op1)) and (not(Op0)) );
lw <= ( (Op5) and (not(Op4)) and (not(Op3)) and (not(Op2)) and (Op1) and (Op0) );
sw <= ( (Op5) and (not(Op4)) and (Op3) and (not(Op2)) and (Op1) and (Op0) );
beq <= ( (not(Op5)) and (not(Op4)) and (not(Op3)) and (Op2) and (not(Op1)) and (not(Op0)) );
RegDst <= R_format;
ALUSrc <= lw or sw;
MemtoReg <= lw;
RegWrite <= R_format or lw;
MemRead <= lw;
MemWrite <= sw;
Branch <= beq;
ALUOp1 <= R_format;
ALUOp0 <= beq;
end Behavioral;
|
mit
|
CamelClarkson/MIPS
|
CarryinAnd.vhd
|
2
|
1295
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:22:08 PM
-- Design Name:
-- Module Name: CarryinAnd - CIA_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CarryinAnd is
Port (
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
C0 : out STD_LOGIC);
end CarryinAnd;
architecture CIA_Func of CarryinAnd is
begin
C0 <= P2 and P1;
end CIA_Func;
|
mit
|
CamelClarkson/MIPS
|
MIPS_Design/Src/AE.vhd
|
2
|
1705
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:11:31 PM
-- Design Name:
-- Module Name: AE - AE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AE is
Port (
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end AE;
architecture AE_Func of AE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
begin
-- P1(P2 xor B)
Temp1 <= P2 and P1 and (not B);
Temp2 <= (not P2) and P1 and B;
Y <= Temp1 or Temp2;
end AE_Func;
|
mit
|
CamelClarkson/MIPS
|
MIPS_Design/Src/mux.vhd
|
1
|
383
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_32bit is
port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (31 downto 0);
B: in STD_LOGIC_VECTOR (31 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
);
end mux_32bit;
architecture Behavioral of mux_32bit is
begin
OUTPUT <= A when (SEL = '0') else B;
end Behavioral;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd
|
6
|
57638
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_stbs_set_nodre.vhd
|
18
|
43117
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd
|
30
|
22280
|
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
use proc_sys_reset_v5_0.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0.SEQUENCE
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
mit
|
VisionistInc/advent-of-code-2016
|
rawjoe/18/sol_tb.vhdl
|
1
|
1514
|
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use std.textio.all;
-- A testbench has no ports.
entity sol_tb is
end sol_tb;
architecture behav of sol_tb is
-- Declaration of the component that will be instantiated.
component sol
port ( clk : in std_logic;
rst : in std_logic;
rows : out integer;
safe : out integer);
end component;
-- Specifies which entity is bound with the component.
for sol_0: sol use entity work.sol;
signal clk : std_logic;
signal rst : std_logic;
signal rows : integer;
signal safe : integer;
begin
-- Component instantiation.
sol_0: sol port map (clk => clk, rst => rst, rows => rows, safe => safe);
-- This process does the real job.
process
begin
rst <= '1';
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
rst <= '0';
L1: loop
if rows = 40 then
report "After 40 rows numSafe = " & integer'image(safe);
end if;
if rows = 400000 then
report "After 400000 rows numSafe = " & integer'image(safe);
exit L1;
end if;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
|
mit
|
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