repo_name
stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
1.04M
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stringclasses 15
values |
|---|---|---|---|---|---|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_Pro/zpu_config.vhd
|
14
|
2691
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/zpuino_uart.vhd
|
13
|
6945
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/zpuino_uart.vhd
|
13
|
6945
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_One_250k/zpuinopkg.vhd
|
26
|
21269
|
--
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/board_Papilio_Pro/zpuinopkg.vhd
|
26
|
21269
|
--
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/sid_voice.vhd
|
13
|
28809
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
olgam-/chaoticScan
|
vhdl/ramImage.vhd
|
1
|
924
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ramImage is
generic (
N : integer := 14 -- here 14 because 2^14 = 128 * 128
);
port
(
clk : in std_logic;
rst : in std_logic;
data : in std_logic_vector(7 downto 0);
write_address : in std_logic_vector(N - 1 downto 0);
read_address : in std_logic_vector(N - 1 downto 0);
we : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end ramImage;
architecture rtl of ramImage is
type RAM is array(0 to (2 ** N - 1)) of std_logic_vector(7 downto 0);
signal ram_block : RAM;
begin
process (clk,rst)
begin
if (rst = '1') then
for i in 0 to (2 ** N - 1) loop
ram_block(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if (we = '1') then
ram_block(to_integer(unsigned(write_address))) <= data;
end if;
q <= ram_block(to_integer(unsigned(read_address)));
end if;
end process;
end rtl;
|
mit
|
hubertokf/VHDL-Fast-Adders
|
RCA/8bits/RCA/Soma1.vhd
|
8
|
341
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val2);
END strc_Soma ;
|
mit
|
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/altpll0.vhd
|
1
|
18727
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
locked <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 4,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire6,
areset => areset,
clk => sub_wire0,
locked => sub_wire4
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_inst.vhd
|
1
|
1535
|
component ghrd_10as066n2_dipsw_pio is
port (
clk : in std_logic := 'X'; -- clk
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
irq : out std_logic; -- irq
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component ghrd_10as066n2_dipsw_pio;
u0 : component ghrd_10as066n2_dipsw_pio
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_port => CONNECTED_TO_in_port, -- external_connection.export
irq => CONNECTED_TO_irq, -- irq.irq
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
address => CONNECTED_TO_address, -- s1.address
write_n => CONNECTED_TO_write_n, -- .write_n
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
);
|
mit
|
hubertokf/VHDL-Fast-Adders
|
CLAH/CLA2bits/8bits/CLAH8bits/Reg1Bit.vhd
|
14
|
470
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg1Bit is
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end Reg1Bit;
architecture strc_Reg1Bit of Reg1Bit is
signal Temp: std_logic;
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= '0';
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg1Bit;
|
mit
|
hubertokf/VHDL-Fast-Adders
|
RCA/32bits/RCA/Reg1Bit.vhd
|
14
|
470
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg1Bit is
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end Reg1Bit;
architecture strc_Reg1Bit of Reg1Bit is
signal Temp: std_logic;
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= '0';
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg1Bit;
|
mit
|
hubertokf/VHDL-Fast-Adders
|
CSA/16bits/CSA16bits/Reg1Bit.vhd
|
14
|
470
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg1Bit is
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end Reg1Bit;
architecture strc_Reg1Bit of Reg1Bit is
signal Temp: std_logic;
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= '0';
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg1Bit;
|
mit
|
lfmunoz/vhdl
|
ip_blocks/sip_spi/fmc408_stellar_cmd.vhd
|
1
|
11370
|
--------------------------------------------------------------------------------
-- file name : fmc408_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -fmc408_stellar_cmd
-- arch_itecture - arch_fmc408_stellar_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- specify libraries.
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------------------------
-- entity declaration
--------------------------------------------------------------------------------
entity fmc408_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port
(
reset :in std_logic;
--command if
clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
--register interface
clk_reg :in std_logic; --register interface is synchronous to this clock
out_reg :out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val :out std_logic; --the out_reg has valid data (pulse)
out_reg_addr :out std_logic_vector(27 downto 0);--out register address
in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val :in std_logic; --pulse to indicate requested register is valid
in_reg_req :out std_logic; --pulse to request data
in_reg_addr :out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_out_val :out std_logic;
mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val :in std_logic --pulse to indicate mailbox is valid
);
end entity fmc408_stellar_cmd ;
--------------------------------------------------------------------------------
-- arch_itecture declaration
--------------------------------------------------------------------------------
architecture arch_fmc408_stellar_cmd of fmc408_stellar_cmd is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0";
constant cmd_rd :std_logic_vector(3 downto 0) :=x"2";
constant cmd_wr :std_logic_vector(3 downto 0) :=x"1";
constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4";
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal register_wr :std_logic;
signal register_rd :std_logic;
signal out_cmd_val_sig :std_logic;
signal in_reg_addr_sig :std_logic_vector(27 downto 0):=(others=>'0');
signal mbx_in_val_sig :std_logic;
signal mbx_received :std_logic;
signal mbx_out_val_sig :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end component;
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_wr,
inbusy =>open,
pulseout =>out_reg_val
);
p2p1: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_rd,
inbusy =>open,
pulseout =>in_reg_req
);
p2p2: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>in_reg_val,
inbusy =>open,
pulseout =>out_cmd_val_sig
);
p2p3: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>mbx_in_val,
inbusy =>open,
pulseout =>mbx_in_val_sig
);
p2p4: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg ,
rst =>reset,
pulsein =>mbx_out_val_sig,
inbusy =>open,
pulseout =>mbx_out_val
);
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then
mbx_received <= '1';
elsif( mbx_received ='1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig='1') then
out_cmd(31 downto 0) <=in_reg;
out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr;
out_cmd(63 downto 60)<=cmd_rd_ack;
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd(31 downto 0) <=mbx_in_reg;
out_cmd(59 downto 32)<=start_addr;
out_cmd(63 downto 60)<=cmd_mbx;
else
out_cmd(63 downto 0)<=(others=>'0');
end if;
if (out_cmd_val_sig='1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
out_reg_addr <= in_cmd(59 downto 32)-start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then
mbx_out_reg <= in_cmd(31 downto 0);
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then
mbx_out_val_sig <= '1';
else
mbx_out_val_sig <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
end architecture arch_fmc408_stellar_cmd ; -- of fmc408_stellar_cmd
|
mit
|
hubertokf/VHDL-Fast-Adders
|
CLAH/CLA4bits/16bits/CLAH16bits/CLGB.vhd
|
5
|
288
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB;
|
mit
|
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_inst.vhd
|
1
|
460
|
component ghrd_10as066n2_rst_bdg is
port (
clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_reset : out std_logic -- reset
);
end component ghrd_10as066n2_rst_bdg;
u0 : component ghrd_10as066n2_rst_bdg
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_reset => CONNECTED_TO_in_reset, -- in_reset.reset
out_reset => CONNECTED_TO_out_reset -- out_reset.reset
);
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/explosion/example_design/explosion_prod.vhd
|
1
|
9926
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: explosion_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : explosion.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 50400
-- C_READ_DEPTH_A : 50400
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 50400
-- C_READ_DEPTH_B : 50400
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY explosion_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END explosion_prod;
ARCHITECTURE xilinx OF explosion_prod IS
COMPONENT explosion_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : explosion_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
Luisda199824/ProcesadorMonociclo
|
DataRF_Mux.vhd
|
1
|
696
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DataRF_Mux is
Port ( clk : in STD_LOGIC;
RfSource : in STD_LOGIC_VECTOR (1 downto 0);
DataToMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
DataToReg : out STD_LOGIC_VECTOR (31 downto 0));
end DataRF_Mux;
architecture Behavioral of DataRF_Mux is
begin
process(RfSource, PC)
begin
case RfSource is
when "00" =>
DataToReg <= AluResult;
when "01" =>
DataToReg <= PC;
when "10" =>
DataToReg <= DataToMem;
when others =>
DataToReg <= x"00000000";
end case;
end process;
end Behavioral;
|
mit
|
Luisda199824/ProcesadorMonociclo
|
UnityControl.vhd
|
1
|
4687
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UnityControl is
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
we : out STD_LOGIC;
RFDest : out STD_LOGIC;
WrENMemory : out STD_LOGIC;
ReENMemory : out STD_LOGIC;
RfSource : out STD_LOGIC_VECTOR(1 downto 0);
PcSource : out STD_LOGIC_VECTOR(1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0));
end UnityControl;
architecture Behavioral of UnityControl is
signal nzvc : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin
-- Add 10 000000
-- Sub 10 000100
-- And 10 000001
-- Or 10 000010
-- Xor 10 000011
-- Orn 10 000110
-- Andn 10 000101
-- Xnor 10 000111
-- Addcc 10 010000
-- Subcc 10 010100
-- Addx 10 001000
-- Addxcc 10 011000
-- Subx 10 001100
-- Subxcc 10 011100
-- Orcc 10 010010
-- Andcc 10 010001
-- Xorcc 10 010011
-- Andncc 10 010101
-- Orncc 10 010110
-- Xnorncc 10 010111
-- SLL 10 100101
-- SRL 10 100111
-- Branchs
-- BA 00 1000
-- BN 00 0000
-- BNE 00 1001
-- BE 00 0001
-- BG 00 1010
-- BLE 00 0010
-- BGE 00 1011
-- BL 00 0011
-- BGU 00 1100
-- BLEU 00 0100
-- BCC 00 1101
-- BCS 00 0101
-- BPOS 00 1110
-- BNEG 00 0110
-- BVC 00 1111
-- BVS 00 0111
-- Jump and Link
-- jmpl 10 111000
-- Call 01 disp22
nzvc <= icc;
process(Op, Op3)
begin
case Op is
when "10" =>
case (Op3) is
when "000000" => -- Add
AluOp <= "000000";
when "000100" => -- Sub
AluOp <= "000001";
when "000001" => -- And
AluOp <= "000011";
when "000010" => -- Or
AluOp <= "000010";
when "000011" => -- Xor
AluOp <= "000100";
when "000110" => -- Orn
AluOp <= "000101";
when "000101" => -- Andn
AluOp <= "000110";
when "000111" => -- Xnor
AluOp <= "000111";
when "010000" => -- Addcc
AluOp <= "001000";
when "010100" => -- Subcc
AluOp <= "001001";
when "001000" => -- Addx
AluOp <= "001010";
when "011000" => -- Addxcc
AluOp <= "001011";
when "001100" => -- Subx
AluOp <= "001100";
when "011100" => -- Subxcc
AluOp <= "001101";
when "010010" => -- Orcc
AluOp <= "001110";
when "010001" => -- Andcc
AluOp <= "001111";
when "010011" => -- Xorcc
AluOp <= "010000";
when "010101" => -- Andncc
AluOp <= "010001";
when "010110" => -- Orncc
AluOp <= "010010";
when "010111" => -- Xnorncc
AluOp <= "010011";
when "100101" => -- SLL
AluOp <= "010100";
when "100111" => -- SRL
AluOp <= "010101";
when "111000" => -- Jmpl
AluOp <= "000000";
when others =>
AluOp <= "000000"; -- Error
end case;
if (Op3 = "111000") then
RfSource <= "01";
RFDest <= '1';
PcSource <= "11";
else
RfSource <= "00";
RFDest <= '0';
PcSource <= "00";
end if;
we <= '1';
WrENMemory <= '0';
ReENMemory <= '0';
when "01" => -- Call
we <= '1';
RFDest <= '1';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "01";
PcSource <= "10";
AluOp <= "000000";
when "00" => -- Branch
we <= '0';
RFDest <= '0';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "00";
PcSource(1) <= '0';
case cond is
when "1000" => -- BA
PcSource(0) <= '1';
when "0000" => -- BN
PcSource(0) <= '0';
when "1001" => -- BNE
PcSource(0) <= not nzvc(2);
when "0001" => -- BE
PcSource(0) <= nzvc(2);
when "1010" => -- BG
PcSource(0) <= not (nzvc(2) or (nzvc(3) xor nzvc(1)));
when "0010" => -- BLE
PcSource(0) <= nzvc(2) or (nzvc(3) xor nzvc(1));
when "1011" => -- BGE
PcSource(0) <= not (nzvc(3) xor nzvc(1));
when "0011" => -- BL
PcSource(0) <= nzvc(3) xor nzvc(1);
when "1100" => -- BGU
PcSource(0) <= not (nzvc(0) or nzvc(2));
when "0100" => -- BLEU
PcSource(0) <= nzvc(0) or nzvc(2);
when "1101" => -- BCC
PcSource(0) <= not nzvc(0);
when "0101" => -- BCS
PcSource(0) <= nzvc(0);
when "1110" => -- BPOS
PcSource(0) <= not nzvc(3);
when "0110" => -- BNEG
PcSource(0) <= nzvc(0);
when "1111" => -- BVC
PcSource(0) <= not nzvc(1);
when "0111" => -- BVS
PcSource(0) <= nzvc(1);
when others =>
PcSource(0) <= '0';
end case;
when others =>
we <= '0';
RFDest <= '0';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "00";
PcSource <= "00";
AluOp <= "000000";
end case;
end process;
end Behavioral;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/score/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/explosion/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
capitanov/Stupid_watch
|
src/rtl/chips/cl_timer_data.vhd
|
1
|
16324
|
--------------------------------------------------------------------------------
--
-- Title : cl_timer_data.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Test example for DS1302 timer settings and LCD1602 RAM loading
-- DS1302 -> LCD1602
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity cl_timer_data is
generic (
TIME_SECS : in integer range 0 to 59:=12; --! Seconds
TIME_MINS : in integer range 0 to 59:=35; --! Minutes
TIME_HRS : in integer range 0 to 23:=17; --! Hours
TIME_DTS : in integer range 0 to 30:=13; --! Dates
TIME_MTHS : in integer range 0 to 11:=07; --! Months
TIME_DAYS : in integer range 0 to 59:=17; --! Days
TIME_YRS : in integer range 0 to 99:=16; --! Years
TD : in time := 1 ns --! simulation time;
);
port(
---- Global signals ----
reset : in std_logic; --! asycnchronous reset
clk : in std_logic; --! clock 50 MHz
restart : in std_logic; --! restart timer
---- DS1302 signals ----
addr : out std_logic_vector(7 downto 0); --! address for timer
data_o : out std_logic_vector(7 downto 0); --! input data (to timer)
data_i : in std_logic_vector(7 downto 0); --! output data (from timer)
data_v : in std_logic; --! valid data (from timer)
ready : in std_logic; --! timer is ready for data
enable : out std_logic; --! timer enable
---- LCD1602 signals ----
load_ena : out std_logic; --! enable writing to LCD RAM
load_dat : out std_logic_vector(7 downto 0); --! data to LCD RAM
load_addr : out std_logic_vector(4 downto 0) --! address to LCD RAM
);
end cl_timer_data;
architecture cl_timer_data of cl_timer_data is
signal sec0_lcd : std_logic_vector(3 downto 0);
signal sec1_lcd : std_logic_vector(3 downto 0);
signal min0_lcd : std_logic_vector(3 downto 0);
signal min1_lcd : std_logic_vector(3 downto 0);
signal hrs0_lcd : std_logic_vector(3 downto 0);
signal hrs1_lcd : std_logic_vector(3 downto 0);
signal dts0_lcd : std_logic_vector(3 downto 0);
signal dts1_lcd : std_logic_vector(3 downto 0);
signal mth0_lcd : std_logic_vector(3 downto 0);
signal mth1_lcd : std_logic_vector(3 downto 0);
signal days_lcd : std_logic_vector(3 downto 0);
signal yrs0_lcd : std_logic_vector(3 downto 0);
signal yrs1_lcd : std_logic_vector(3 downto 0);
signal data_rom : std_logic_vector(3 downto 0);
signal time_addr : std_logic_vector(3 downto 0);
signal timer_v : std_logic_vector(3 downto 0);
type tdata_timer is (secs, mins, hours, dates, months, days, years, nulls); --days,
signal time_code : tdata_timer;
signal time_codex : tdata_timer;
signal time_set : std_logic_vector(4 downto 0);
signal time_get : std_logic_vector(3 downto 0);
signal mode : std_logic;
signal timer_conf : std_logic;
signal readyz : std_logic;
signal ena : std_logic;
signal load : std_logic;
signal lcd_addr : std_logic_vector(4 downto 0);
---------------- INTEGER TO STD_LOGIC_VECTOR TO BCD CONVERTER ----------------
constant n : integer:=8;
constant q : integer:=2;
function to_bcd ( bin : std_logic_vector((n-1) downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable j : integer:=1;
variable bcd : std_logic_vector(((4*q)-1) downto 0) := (others => '0');
variable bint : std_logic_vector((n-1) downto 0) := bin;
begin
for i in 0 to n-1 loop -- repeating 8 times.
bcd(((4*q)-1) downto 1) := bcd(((4*q)-2) downto 0); --shifting the bits.
bcd(0) := bint(n-1);
bint((n-1) downto 1) := bint((n-2) downto 0);
bint(0) :='0';
l1: for j in 1 to q loop
if(i < n-1 and bcd(((4*j)-1) downto ((4*j)-4)) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(((4*j)-1) downto ((4*j)-4)) := bcd(((4*j)-1) downto ((4*j)-4)) + "0011";
end if;
end loop l1;
end loop;
return bcd;
end to_bcd;
constant temp_secs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_SECS, 8)); -- Seconds
constant temp_mins : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MINS, 8)); -- Minutes
constant temp_hrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_HRS, 8)); -- Hours
constant temp_dts : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DTS, 8)); -- Dates
constant temp_mths : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MTHS, 8)); -- Months
constant temp_days : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DAYS, 8)); -- Days
constant temp_yrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_YRS, 8)); -- Years
begin
readyz <= not ready after td when rising_edge(clk);
ena <= ready and readyz after td when rising_edge(clk);
enable <= ena when rising_edge(clk);
--addr <= x"8" & time_addr after td when rising_edge(clk);
pr_addr: process(clk, reset) is
begin
if (reset = '0') then
addr <= x"00";
elsif (rising_edge(clk)) then
addr <= x"8" & time_addr after td;
end if;
end process;
load_dat <= x"3" & data_rom after td when rising_edge(clk);
load_addr <= lcd_addr after td when rising_edge(clk);
load_ena <= load after td when rising_edge(clk);
timer_v <= timer_v(2 downto 0) & data_v after td when rising_edge(clk);
---------------- TIMER CONFIGURE DATA ----------------
pr_conf: process(clk, reset) is
begin
if (reset = '0') then
data_o <= x"00";
time_set <= "00000";
timer_conf <= '0';
elsif (rising_edge(clk)) then
if (restart = '0') then
time_set <= "00000" after td;
end if;
timer_conf <= time_set(4) after td;
if (ena = '1') then
if time_set(4) = '0' then
time_set <= time_set + '1' after td;
else
null;
end if;
end if;
case time_set(3 downto 0) is
when x"1" => data_o <= x"00"; -- WP: (7) bit should be '0' to enable writing data
when x"2" => data_o <= temp_yrs;--temp_yrs;
when x"3" => data_o <= temp_days;
when x"4" => data_o <= temp_mths;
when x"5" => data_o <= temp_dts;
when x"6" => data_o <= temp_hrs;
when x"7" => data_o <= temp_mins;
when x"8" => data_o <= temp_secs; -- CH: (7) bit should be '0' to start clocking
when others => data_o <= x"80"; --null;
end case;
end if;
end process;
---------------- TIMER GETTING DATA ----------------
pr_timeget: process(clk, reset) is
begin
if (reset = '0') then
time_get <= x"0";
mode <= '1';
elsif (rising_edge(clk)) then
if ((ena = '1') and (timer_conf = '1')) then
time_get <= time_get + '1' after td;
mode <= not mode after td;
end if;
end if;
end process;
pr_rom_load: process(clk, reset) is
begin
if (reset = '0') then
load <= '0';
elsif (rising_edge(clk)) then
if (timer_conf = '0') then
load <= '0' after td;
else
load <= timer_v(3) after td;
end if;
end if;
end process;
---------------- TIMER READING DATA ----------------
pr_readback: process(clk, reset) is
begin
if (reset = '0') then
time_addr <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
time_addr <= x"0" after td;
end if;
if (timer_conf = '0') then
case time_set(3 downto 0) is
when x"1" => time_addr <= x"E"; -- set write protect
when x"2" => time_addr <= x"C"; -- year
when x"3" => time_addr <= x"A"; -- day
when x"4" => time_addr <= x"8"; -- month
when x"5" => time_addr <= x"6"; -- date
when x"6" => time_addr <= x"4"; -- hour
when x"7" => time_addr <= x"2"; -- minute
when x"8" => time_addr <= x"0"; -- second
when others => time_addr <= x"E";
end case;
else
case time_get is
when x"1" | x"2" => time_addr <= x"D"; -- year
when x"3" | x"4" => time_addr <= x"B"; -- day
when x"5" | x"6" => time_addr <= x"9"; -- month
when x"7" | x"8" => time_addr <= x"7"; -- date
when x"9" | x"A" => time_addr <= x"5"; -- hour
when x"B" | x"C" => time_addr <= x"3"; -- minute
when x"D" | x"E" => time_addr <= x"1"; -- second
when others => null;
end case;
end if;
end if;
end process;
---------------- TIMER CODES ----------------
time_codex <= secs when time_addr(3 downto 1) = "000" else
mins when time_addr(3 downto 1) = "001" else
hours when time_addr(3 downto 1) = "010" else
dates when time_addr(3 downto 1) = "011" else
months when time_addr(3 downto 1) = "100" else
days when time_addr(3 downto 1) = "101" else
years when time_addr(3 downto 1) = "110" else
nulls;
time_code <= time_codex after td when rising_edge(clk);
---------------- TIMER WRITE ROM ----------------
pr_data_rom: process(clk, reset) is
begin
if (reset = '0') then
data_rom <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
data_rom <= x"0" after td;
end if;
if (timer_v(2) = '1') then
case time_code is
when secs =>
if mode = '0' then
lcd_addr <= "11100" after td;
data_rom <= sec0_lcd after td;
else
lcd_addr <= "11011" after td;
data_rom <= sec1_lcd after td;
end if;
when mins =>
if mode = '0' then
lcd_addr <= "11001" after td;
data_rom <= min0_lcd after td;
else
lcd_addr <= "11000" after td;
data_rom <= min1_lcd after td;
end if;
when hours =>
if mode = '0' then
lcd_addr <= "10110" after td;
data_rom <= hrs0_lcd after td;
else
lcd_addr <= "10101" after td;
data_rom <= hrs1_lcd after td;
end if;
when dates =>
if mode = '0' then
lcd_addr <= "00110" after td;
data_rom <= dts0_lcd after td;
else
lcd_addr <= "00101" after td;
data_rom <= dts1_lcd after td;
end if;
when months =>
if mode = '0' then
lcd_addr <= "01001" after td;
data_rom <= mth0_lcd after td;
else
lcd_addr <= "01000" after td;
data_rom <= mth1_lcd after td;
end if;
-- when days =>
-- data_rom <= days_lcd after td;
when years =>
if mode = '0' then
lcd_addr <= "01100" after td;
data_rom <= yrs0_lcd after td;
else
lcd_addr <= "01011" after td;
data_rom <= yrs1_lcd after td;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
---------------- SECONDS LSB ----------------
pr_conv_sec0: process(clk, reset) is
begin
if (reset = '0') then
sec0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
sec0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- SECONDS MSB ----------------
pr_conv_sec1: process(clk, reset) is
begin
if (reset = '0') then
sec1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
case data_i(6 downto 4) is
when "000" => sec1_lcd <= x"0" after td;
when "001" => sec1_lcd <= x"1" after td;
when "010" => sec1_lcd <= x"2" after td;
when "011" => sec1_lcd <= x"3" after td;
when "100" => sec1_lcd <= x"4" after td;
when "101" => sec1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MINUTES LSB ----------------
pr_conv_min0: process(clk, reset) is
begin
if (reset = '0') then
min0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
min0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MINUTES MSB ----------------
pr_conv_min1: process(clk, reset) is
begin
if (reset = '0') then
min1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
case data_i(6 downto 4) is
when "000" => min1_lcd <= x"0" after td;
when "001" => min1_lcd <= x"1" after td;
when "010" => min1_lcd <= x"2" after td;
when "011" => min1_lcd <= x"3" after td;
when "100" => min1_lcd <= x"4" after td;
when "101" => min1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DATES LSB ----------------
pr_conv_dts0: process(clk, reset) is
begin
if (reset = '0') then
dts0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
dts0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- DATES MSB ----------------
pr_conv_dts1: process(clk, reset) is
begin
if (reset = '0') then
dts1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
case data_i(5 downto 4) is
when "00" => dts1_lcd <= x"0" after td;
when "01" => dts1_lcd <= x"1" after td;
when "10" => dts1_lcd <= x"2" after td;
when "11" => dts1_lcd <= x"3" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MONTHS LSB ----------------
pr_conv_mth0: process(clk, reset) is
begin
if (reset = '0') then
mth0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
mth0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MONTHS MSB ----------------
pr_conv_mth1: process(clk, reset) is
begin
if (reset = '0') then
mth1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
case data_i(4) is
when '0' => mth1_lcd <= x"0" after td;
when '1' => mth1_lcd <= x"1" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DAYS ----------------
pr_conv_days: process(clk, reset) is
begin
if (reset = '0') then
days_lcd <= x"0";
elsif (rising_edge(clk)) then
if (time_code = days) then
case data_i(2 downto 0) is
when "000" => days_lcd <= x"1" after td;
when "001" => days_lcd <= x"2" after td;
when "010" => days_lcd <= x"3" after td;
when "011" => days_lcd <= x"4" after td;
when "100" => days_lcd <= x"5" after td;
when "101" => days_lcd <= x"6" after td;
when "110" => days_lcd <= x"7" after td;
--when "111" => days_lcd <= x"7" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- HOURS LSB ----------------
pr_conv_hrs: process(clk, reset) is
begin
if (reset = '0') then
hrs0_lcd <= x"0";
hrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = hours)) then
hrs0_lcd <= data_i(3 downto 0) after td;
hrs1_lcd <= data_i(7 downto 4) after td;
end if;
end if;
end process;
---------------- YEARS LSB ----------------
pr_conv_yrs: process(clk, reset) is
begin
if (reset = '0') then
yrs0_lcd <= x"0";
yrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = years)) then
yrs0_lcd <= data_i(3 downto 0) after td;
yrs1_lcd <= data_i(7 downto 4) after td;
-- case data_i(3 downto 0) is
-- when x"0" => yrs0_lcd <= x"0" after td;
-- when x"1" => yrs0_lcd <= x"1" after td;
-- when x"2" => yrs0_lcd <= x"2" after td;
-- when x"3" => yrs0_lcd <= x"3" after td;
-- when x"4" => yrs0_lcd <= x"4" after td;
-- when x"5" => yrs0_lcd <= x"5" after td;
-- when x"6" => yrs0_lcd <= x"6" after td;
-- when x"7" => yrs0_lcd <= x"7" after td;
-- when x"8" => yrs0_lcd <= x"8" after td;
-- when x"9" => yrs0_lcd <= x"9" after td;
-- when others => null;
-- end case;
-- case data_i(7 downto 4) is
-- when x"0" => yrs1_lcd <= x"0" after td;
-- when x"1" => yrs1_lcd <= x"1" after td;
-- when x"2" => yrs1_lcd <= x"2" after td;
-- when x"3" => yrs1_lcd <= x"3" after td;
-- when x"4" => yrs1_lcd <= x"4" after td;
-- when x"5" => yrs1_lcd <= x"5" after td;
-- when x"6" => yrs1_lcd <= x"6" after td;
-- when x"7" => yrs1_lcd <= x"7" after td;
-- when x"8" => yrs1_lcd <= x"8" after td;
-- when x"9" => yrs1_lcd <= x"9" after td;
-- when others => null;
-- end case;
end if;
end if;
end process;
end cl_timer_data;
|
mit
|
pdt/ttask
|
test/xilinx-ise/lib/my_lib/sim/or_gate_test.vhdl
|
1
|
874
|
--
-- or_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
entity or_gate_test is
end entity;
architecture sim of or_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity work.or_gate port map (
a => a,
b => b,
c => c
);
test : process
begin
report "Starting or_gate test";
wait for 1 us;
assert c = '0' report "Error, output should be '0'";
a <= '1';
wait for 1 us;
assert c = '1' report "Error, output should be '1'";
b <= '1';
wait for 1 us;
assert c = '1' report "Error, output should be '1'";
a <= '0';
wait for 1 us;
assert c = '1' report "Error, output should be '1'";
report "Completed or_gate test";
wait;
end process;
end;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/police/simulation/addr_gen.vhd
|
101
|
4409
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/side/simulation/addr_gen.vhd
|
101
|
4409
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
zxcmehran/FPGADisplay-ipcore
|
hdl/vhdl/DisplayOut.vhd
|
1
|
3016
|
--
--
-- FPGA Display Handler IP Core By Mehran Ahadi (http://mehran.ahadi.me)
-- This IP allows you to draw shapes and print texts on VGA screen.
-- Copyright (C) 2015-2016 Mehran Ahadi
-- This work is released under MIT License.
--
-- VGA Signal Generator File
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DisplayOut is
Generic (
w_pixels: integer;
w_fp: integer;
w_synch: integer;
w_bp: integer;
w_syncval: std_logic;
h_pixels: integer;
h_fp: integer;
h_synch: integer;
h_bp: integer;
h_syncval: std_logic
);
Port (
PIXEL_CLK :in STD_LOGIC;
COMP_SYNCH : out STD_LOGIC;
OUT_BLANK_Z : out STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
R : out STD_LOGIC_VECTOR(7 downto 0);
G : out STD_LOGIC_VECTOR(7 downto 0);
B : out STD_LOGIC_VECTOR(7 downto 0);
MEMORY_ADDRESS: OUT std_logic_VECTOR(19 downto 0);
MEMORY_OUT: IN std_logic_VECTOR(0 downto 0)
);
end DisplayOut;
architecture Behavioral of DisplayOut is
constant w_total : integer := w_pixels + w_fp + w_synch + w_bp;
constant h_total : integer := h_pixels + h_fp + h_synch + h_bp;
begin
COMP_SYNCH <= '0'; -- Disable "sync on green"
R <= (others => MEMORY_OUT(0));
G <= (others => MEMORY_OUT(0));
B <= (others => MEMORY_OUT(0));
process(PIXEL_CLK)
variable clk_x: integer range 0 to w_total - 1 := 0;
variable clk_y: integer range 0 to h_total - 1 := 0;
variable clk_xy: STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000"; -- 1048576 = 2 ^ 20 as we have 20 bits.
begin
if PIXEL_CLK'event and PIXEL_CLK='1' then
-- VGA Signals
if clk_x < w_pixels + w_fp or clk_x >= w_pixels + w_fp + w_synch then
HSYNC <= not w_syncval; -- not on synch location
else
HSYNC <= w_syncval; -- on synch location
end if;
if clk_y < h_pixels + h_fp or clk_y >= h_pixels + h_fp + h_synch then
VSYNC <= not h_syncval; -- not on synch location
else
VSYNC <= h_syncval; -- on synch location
end if;
if clk_x >= w_pixels or clk_y >= h_pixels then
OUT_BLANK_Z <= '0';
else
OUT_BLANK_Z <= '1';
end if;
-- Increment coordinate counters
if clk_x < w_total - 1 then
clk_x := clk_x + 1;
else
clk_x := 0;
if clk_y < h_total - 1 then
clk_y := clk_y + 1;
else
clk_y := 0;
end if;
end if;
-- Let it be one clock ahead
if clk_x = w_pixels - 1 then
if clk_y < h_pixels - 1 then
clk_xy (19 downto 10) := clk_xy (19 downto 10) + 1;
clk_xy (9 downto 0) := "0000000000";
elsif clk_y = h_total - 1 then
clk_xy := "00000000000000000000";
end if;
elsif clk_x < w_pixels - 1 then
-- add up
clk_xy := clk_xy + '1';
end if;
MEMORY_ADDRESS <= clk_xy;
end if;
end process;
end Behavioral;
|
mit
|
pdt/ttask
|
test/fpga-sim/lib/my_lib/rtl/or_gate.vhdl
|
4
|
262
|
--
-- or_gate.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
entity or_gate is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic
);
end entity or_gate;
architecture rtl of or_gate is
begin
c <= a or b;
end;
|
mit
|
Luisda199824/ProcesadorMonociclo
|
Mux32B.vhd
|
1
|
492
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux32B is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
Sc : in STD_LOGIC;
MuxOut : out STD_LOGIC_VECTOR (31 downto 0));
end Mux32B;
architecture Behavioral of Mux32B is
begin
process (A, B, Sc)
begin
if (Sc = '0') then
MuxOut <= A;
else
MuxOut <= B;
end if;
end process;
end Behavioral;
|
mit
|
IamVNIE/Hardware-Security
|
DES CryptoCore/src/test_benches/DES_Encrypt_Testbench.vhd
|
2
|
5647
|
--******************************************************************************
-- Copyright (c) 2016 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2017
-- Design Name:
-- Module Name: DES_ENCRYPT Testbench.vhd
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined Design and txt_util.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
LIBRARY ieee;
Use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
ENTITY DES_testBench IS
END DES_testBench;
ARCHITECTURE behavior OF DES_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DES_CRYPTO_CORE --desCryptoCore
PORT(
reset : IN std_logic;
EN : IN std_logic;
clk : IN std_logic;
DES_IN : IN std_logic_vector(63 downto 0);
USER_KEY : IN std_logic_vector(63 downto 0);
DES_OUT : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
COMPONENT DES IS
PORT(
PT : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
KIN: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
CT: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RST: IN STD_LOGIC;
CLK: IN STD_LOGIC;
TEST_MODE: IN STD_LOGIC;
SCAN_OUT : OUT STD_LOGIC);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal EN : std_logic := '0';
signal clk : std_logic := '0';
signal DES_IN : std_logic_vector(63 downto 0) := (others => '0');
signal USER_KEY : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal DES_OUT : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal ERROR,ERRORD: integer :=0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DES_CRYPTO_CORE PORT MAP (
reset => reset,
EN => EN,
clk => clk,
DES_IN => DES_IN,
USER_KEY => USER_KEY,
DES_OUT => DES_OUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
readcmd: process
file CryptoCore_TestVectors: TEXT;
variable file_line: Line;
variable test_vector_key_in: std_logic_vector (63 downto 0);
variable test_vector_din: std_logic_vector (63 downto 0);
variable test_vector_expected_dout : std_logic_vector (63 downto 0);
Begin
reset <= '1';
USER_KEY <= (others => '0');
DES_IN <= (others => '0');
En <= '1';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
reset <= '0';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
print ("DES Test#1 has begun.");
FILE_OPEN (CryptoCore_TestVectors, "../src/test_vectors/DES_TV_Triplets_NBS.txt", READ_MODE); --In case of problems, use absolute path
loop
If endfile (CryptoCore_TestVectors) then
exit;
End If;
readline (CryptoCore_TestVectors, file_line);
hread (file_line, test_vector_key_in);
hread (file_line, test_vector_din);
hread (file_line, test_vector_expected_dout);
USER_KEY <= test_vector_key_in;
-- din_vld_T <= '1'; --# When Designs have din and key valid use this
-- Key_vld <= '1';
DES_IN <= test_vector_din;
wait until rising_edge (clk);
-- din_vld_T <= '0';
-- wait until dout_rdy_T = '1'; --# When Designs have dout use this to get the result
wait for 20*clk_period; -- Currently DES takes 19 clock cycles to complete processing
wait until rising_edge (clk);
If DES_OUT /= test_vector_expected_dout then
print ("***ERROR: test vector failed to compare"); ERROR<=ERROR+1;
print ((" Expected PT: ") & hstr (test_vector_expected_dout (63 downto 0)) & (" Received PT: ") & hstr (DES_OUT (63 downto 0)));
End If;
End loop;
print ("Test#1 completed");
print ("");
print ("");
if ERROR=0 then
print ("All tests complete- PASS");
else
print (("All tests complete 4 Decrypt - FAIL --> Total ERRORS=") & integer'image(ERROR));
end if;
wait;
end process;
END;
|
mit
|
Luisda199824/ProcesadorMonociclo
|
Sparcv8Monocycle.vhd
|
1
|
165
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sparcv8Monocycle is
end Sparcv8Monocycle;
architecture Behavioral of Sparcv8Monocycle is
begin
end Behavioral;
|
mit
|
capitanov/Stupid_watch
|
src/rtl/chips/rtl_lcd1602.vhd
|
1
|
6446
|
-------------------------------------------------------------------------------
--
-- Title : rtl_lcd1602
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Controller for LCD Display LCD1602
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rtl_lcd1602 is
generic (
TD : in time; --! simulation time;
DIV_SCL : in integer --! clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; --! system frequency (50 MHz)
rstn : in std_logic; --! '0' - negative reset
-- main interface
start : in std_logic; --! start
data_ena : in std_logic; --! data enable (S)
data_int : in std_logic_vector(7 downto 0); --! data Tx
data_sel : in std_logic; --! select: '0' - data, '1' - command
data_rw : in std_logic; --! data write: write - '0', read - '1'
lcd_ready : out std_logic; --! ready for data
lcd_init : out std_logic; --! lcd initialization complete
-- lcd1602 interface
lcd_dt : out std_logic_vector(7 downto 0); --! lcd data
lcd_en : out std_logic; --! lcd clock enable
lcd_rw : out std_logic; --! lcd r/w: write - '0', read - '1'
lcd_rs : out std_logic --! lcd set: command - '0', data - '1'
);
end rtl_lcd1602;
architecture rtl_lcd1602 of rtl_lcd1602 is
signal clk_r : std_logic;
--signal clk_f : std_logic;
signal clk_z : std_logic;
signal clk_low : std_logic;
signal cnt_div : integer range 0 to DIV_SCL:=0;
type fsm_stage is (RDY_START, INIT, WAITING, DATA, DATA_WAIT, COM, COM_WAIT);
signal STM_OP : fsm_stage;
signal busy : std_logic;
signal en : std_logic;
signal rw : std_logic;
signal rs : std_logic;
signal dt : std_logic_vector(7 downto 0);
signal lcd_cnt : std_logic_vector(2 downto 0);
signal lcd_initr : std_logic;
--signal clk_rise : std_logic;
signal clk_en : std_logic;
begin
-- clk_div generator:
pr_cnt_div: process(clk50m, rstn) is
begin
if (rstn = '0') then
cnt_div <= 0;
clk_low <= '0';
elsif (rising_edge(clk50m)) then
if (cnt_div = DIV_SCL) then
cnt_div <= 0 after td;
clk_low <= not clk_low after td;
else
cnt_div <= cnt_div + 1 after td;
end if;
end if;
end process;
-- clk rising/falling
clk_z <= clk_low after td when rising_edge(clk50m);
clk_r <= (not clk_z) and clk_low after td when rising_edge(clk50m);
--clk_f <= (not clk_low) and clk_z after td when rising_edge(clk50m);
-- lcd_output data
--lcd_initr <= '0' when (rstn = '0') else lcd_cnt(2);
lcd_init <= lcd_initr after td when rising_edge(clk50m);
lcd_ready <= busy after td when rising_edge(clk50m);
lcd_dt <= dt after td when rising_edge(clk50m);
lcd_en <= en after td when rising_edge(clk50m);
lcd_rw <= rw after td when rising_edge(clk50m);
lcd_rs <= rs after td when rising_edge(clk50m);
pr_en_clk: process(clk50m, rstn) is
begin
if (rstn = '0') then
en <= '0';
elsif (rising_edge(clk50m)) then
if (clk_en = '1') then
if (clk_r = '1') then
en <= not en after td;
end if;
else
en <= '0' after td;
end if;
end if;
end process;
--clk_rise <= (clk_f and (not en)) after td when rising_edge(clk50m);
pr_fsm_operation: process(clk50m, rstn) is
variable cnt1: std_logic_vector(4 downto 0):="00000";
begin
if (rstn = '0') then
busy <= '0';
rs <= '0';
rw <= '0';
dt <= x"00";
clk_en <= '0';
lcd_initr <= '0';
lcd_cnt <= "000";
STM_OP <= RDY_START;
elsif (rising_edge(clk50m)) then
case STM_OP is
when RDY_START =>
cnt1 := "11111";
lcd_initr <= '0' after td;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
if ((start = '1') and (clk_r = '1')) then
STM_OP <= INIT after td;
clk_en <= '1' after td;
end if;
when INIT =>
if (clk_r = '1') then
rs <= '0' after td;
rw <= '0' after td;
STM_OP <= WAITING after td;
if lcd_cnt = "001" then
if (lcd_initr = '0') then
dt <= x"01" after td;
else
dt <= x"00" after td;
end if;
elsif lcd_cnt = "010" then
dt <= x"38" after td;
elsif lcd_cnt = "011" then
dt <= x"0C" after td;
elsif lcd_cnt = "100" then
dt <= x"06" after td;
else
null;
end if;
end if;
when WAITING =>
if (clk_r = '1') then
if lcd_cnt(2) = '1' then
STM_OP <= DATA after td;
busy <= '1' after td;
lcd_initr <= '1' after td;
else
lcd_cnt <= lcd_cnt + '1' after td;
STM_OP <= INIT after td;
end if;
end if;
when DATA_WAIT =>
if (clk_r = '1') then
busy <= '0' after td;
STM_OP <= COM after td;
end if;
when DATA =>
if (clk_r = '1') then
if (data_ena = '1') then
busy <= '0' after td;
rs <= '1' after td;
rw <= data_rw after td;
dt <= data_int after td;
STM_OP <= DATA_WAIT after td;
end if;
end if;
when COM_WAIT =>
if (clk_r = '1') then
STM_OP <= INIT after td;
end if;
when COM =>
if (clk_r = '1') then
if (cnt1 < "11111") then
cnt1 := cnt1 + 1;
else
cnt1 := "00000";
end if;
if (cnt1(4) = '0') then
dt <= "10000000" + cnt1 after td;
else
dt <= "10110000" + cnt1 after td;--80H
end if;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
STM_OP <= COM_WAIT after td;
end if;
end case;
end if;
end process;
end rtl_lcd1602;
|
mit
|
Yuriu5/MiniBlaze
|
test/Simu/tb_ALU.vhd
|
1
|
11316
|
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : tb_ALU
-- Date : 07/07/2016
--
-- Description : TestBench for Arithmetic Logic Unit
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ALU_pkg.all;
use work.data_pkg.all;
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_ALU is
generic (
runner_cfg : string
);
end tb_ALU;
architecture simu of tb_ALU is
---------------------------
-- Component declaration
component ALU
generic(
DATA_WIDTH : natural := 32
);
port(
param_i : in t_param_alu;
carry_i : in std_logic;
operandA_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandB_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandD_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
status_o : out t_status_alu_out
);
end component;
---------------------------
-- Constant declaration
constant DWIDTH : integer range 0 to 63 := 32;
constant PERIOD_CLK : time := 10 ns;
constant input_file : string := "test2.hex";
---------------------------
-- Signal declaration
signal clk : std_logic := '0';
signal s_param : t_param_alu := c_param_alu_null;
signal s_carry : std_logic := '0';
signal s_operandA : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal s_operandB : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal s_operandD : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal s_status : t_status_alu_out := c_status_alu_out_null;
type fsm_test is (st_start, st_test_1, st_test_2, st_test_3, st_end);
signal r_fsm_test : fsm_test := st_start;
signal r_count : unsigned(31 downto 0) := (others => '0');
signal r_set : std_logic := '0';
signal r_error : std_logic := '0';
signal r_ack_test : std_logic := '0';
signal r_start_test : std_logic := '0';
signal r_do_test : fsm_test := st_start;
begin
clk <= not clk after PERIOD_CLK/2;
i_dut : ALU
generic map(
DATA_WIDTH => DWIDTH
)
port map(
param_i => s_param,
carry_i => s_carry,
operandA_i => s_operandA,
operandB_i => s_operandB,
operandD_o => s_operandD,
status_o => s_status
);
main : process
begin
test_runner_setup(runner,runner_cfg);
while test_suite loop
if run("test_1") then
wait until rising_edge(clk);
r_start_test <= '1';
r_do_test <= st_test_1;
wait until rising_edge(clk);
r_start_test <= '0';
wait until r_ack_test = '1' and rising_edge(clk);
elsif run("test_2") then
wait until rising_edge(clk);
r_start_test <= '1';
r_do_test <= st_test_2;
wait until rising_edge(clk);
r_start_test <= '0';
wait until r_ack_test = '1' and rising_edge(clk);
elsif run("test_random") then
wait until rising_edge(clk);
r_start_test <= '1';
r_do_test <= st_test_3;
wait until rising_edge(clk);
r_start_test <= '0';
wait until r_ack_test = '1' and rising_edge(clk);
end if;
end loop;
test_runner_cleanup(runner);
end process;
p_test : process(clk)
begin
if rising_edge(clk) then
r_ack_test <= '0';
case r_fsm_test is
when st_start =>
if r_start_test = '1' then
r_fsm_test <= r_do_test;
end if;
r_count <= (others => '0');
r_set <= '1';
r_error <= '0';
when st_test_1 => -- PassThrough
-- Generation control
if r_count = 16 then
r_count <= (others => '0');
r_fsm_test <= r_fsm_test;
else
r_count <= r_count + 1;
s_param.operation <= OP_PTA;
s_param.ctrl_op.keepCarry <= '0';
s_param.ctrl_op.negOperandA <= '0';
s_param.ctrl_op.negOperandB <= '0';
s_param.ctrl_op.whichCarry <= CARRY_INPUT;
s_param.ctrl_op.ctrlShift <= LEFT_SHIFT;
s_carry <= not s_carry;
s_operandA <= std_logic_vector(resize(r_count, DWIDTH));
s_operandB <= std_logic_vector(resize(r_count+4, DWIDTH));
end if;
-- Check data
if is_zero(s_operandA) = '0' then
if (unsigned(s_operandD) /= (unsigned(s_operandA))) or (s_status.carry /= '0') then
ASSERT false report "Test 1 failure" severity failure;
end if;
end if;
r_ack_test <= '1';
when st_test_2 => -- Add
s_param.operation <= OP_ADD;
s_param.ctrl_op.keepCarry <= '0';
s_param.ctrl_op.negOperandA <= '0';
s_param.ctrl_op.negOperandB <= '0';
s_param.ctrl_op.whichCarry <= CARRY_INPUT;
s_param.ctrl_op.ctrlShift <= LEFT_SHIFT;
s_carry <= '0';
s_operandA <= x"7fffffff";
s_operandB <= x"0000ffff";
r_count <= r_count + 1;
if r_count /= 0 then
r_fsm_test <= r_fsm_test;
r_count <= (others => '0');
if s_operandD /= x"8000FFFE" then
assert false report "Test 2 failure" severity failure;
end if;
end if;
r_ack_test <= '1';
when st_test_3 => -- Random
if r_count < data_in'length then
if r_set = '1' then
s_operandA <= data_in(to_integer(r_count)).operandA;
s_operandB <= data_in(to_integer(r_count)).operandB;
s_param.operation <= data_in(to_integer(r_count)).operation;
s_param.ctrl_op.keepCarry <= data_in(to_integer(r_count)).keepCarry;
s_param.ctrl_op.negOperandA <= data_in(to_integer(r_count)).negOpA;
s_param.ctrl_op.negOperandB <= data_in(to_integer(r_count)).negOpB;
s_param.ctrl_op.whichCarry <= data_in(to_integer(r_count)).carry_type;
s_param.ctrl_op.ctrlShift <= data_in(to_integer(r_count)).shift_type;
s_carry <= data_in(to_integer(r_count)).carry_in;
r_set <= '0';
r_error <= '0';
else
if data_in(to_integer(r_count)).operandD /= s_operandD then
assert false report "Test 3 failure operandD : " & integer'image(to_integer(r_count)) severity failure;
end if;
if data_in(to_integer(r_count)).carry_out /= s_status.carry then
r_error <= '1';
assert false report "Test 3 failure Carry out: " & integer'image(to_integer(r_count)) severity failure;
end if;
if data_in(to_integer(r_count)).zero /= s_status.zero then
r_error <= '1';
assert false report "Test 3 failure Zero: " & integer'image(to_integer(r_count)) severity failure;
end if;
if data_in(to_integer(r_count)).negative /= s_status.negative then
r_error <= '1';
assert false report "Test 3 failure Negative: " & integer'image(to_integer(r_count)) severity failure;
end if;
if data_in(to_integer(r_count)).overflow /= s_status.overflow then
r_error <= '1';
end if;
r_set <= '1';
r_count <= r_count + 1;
end if;
else
r_ack_test <= '1';
r_fsm_test <= st_start;
end if;
when st_end => null;
when others => null;
end case;
end if;
end process;
end simu;
|
mit
|
Luisda199824/ProcesadorMonociclo
|
Tb_Procesador2.vhd
|
1
|
1066
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_Procesador2 IS
END Tb_Procesador2;
ARCHITECTURE behavior OF Tb_Procesador2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT unionModulos
PORT(
clk : IN std_logic;
rst : IN std_logic;
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: unionModulos PORT MAP (
clk => clk,
rst => rst,
salida => salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 10 ns;
rst <= '0';
wait;
end process;
END;
|
mit
|
IamVNIE/Hardware-Security
|
DES CryptoCore/src/DES_TOP_FILE.vhd
|
2
|
6235
|
--******************************************************************************
-- Copyright (c) 2017 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
----------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: DES_TOP_FILE - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY FPGAs
-- Tool versions: ISE, Vivado
-- Description: Implements DES - Complete Structural Modelling
--
-- Dependencies: Modules :-> XP- Expansion; DESXOR1,DESXOR2 - XOR; S1..S8 - S-Boxes;
-- PP - Permutation; REG32 - 32 bit register
-- Files :-> xp.vhd,desxor1.vhd,desxor2.vhd, s1.vhd...s8.vhd,pp.vhd
-- reg32.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DES_CRYPTO_CORE is port
(
reset : in std_logic;
EN : in STD_LOGIC;
clk : in std_logic;
DES_IN: in STD_LOGIC_VECTOR (63 downto 0);
USER_KEY: in STD_LOGIC_VECTOR (63 downto 0);
DES_OUT: out STD_LOGIC_VECTOR (63 downto 0)
);
end DES_CRYPTO_CORE;
architecture behavior of DES_CRYPTO_CORE is
--Cypher Text & Key Initialization
-----------------For Encoding ------------------------------
--signal ct : std_logic_vector(1 TO 64):=x"1234567890abcdef";
--signal key : std_logic_vector(1 TO 64):=x"abbcccddddeeeeef";
---------------- For Decoding -------------------------------
signal ct : std_logic_vector(1 TO 64);
signal key : std_logic_vector(1 TO 64);
signal pt : std_logic_vector(1 TO 64);
signal pt1:STD_LOGIC_VECTOR(64 downto 0);
signal k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: std_logic_vector(1 to 48);
signal
l0xa,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x
: std_logic_vector(1 to 32);
signal
r0xa,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x
: std_logic_vector(1 to 32);
component keysched
port (
key : in std_logic_vector(1 to 64);EN,CLK: in std_logic;
k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: out std_logic_vector(1 to 48)
);
end component;
component ip
port (
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end component;
component roundfunc
port (
clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32);
k : in std_logic_vector(1 to 48);
lo,ro : out std_logic_vector(1 to 32)
);
end component;
component fp
port (
l,r : in std_logic_vector(1 to 32);
pt : out std_logic_vector(1 to 64)
);
end component;
begin
process(CLK,RESET)
begin
if reset='1' then
DES_OUT<=(OTHERS=>'0');
ct<=(OTHERS=>'0');
key<=(OTHERS=>'0');
elsif rising_edge(CLK) then
DES_OUT<=pt;
ct<=DES_IN;
key<=USER_KEY;
end if;
end process;
keyscheduling: keysched port map ( key=>key,EN=>EN, CLK=>CLK,
k1x=>k1x, k2x=>k2x, k3x=>k3x, k4x=>k4x,
k5x=>k5x, k6x=>k6x, k7x=>k7x, k8x=>k8x,
k9x=>k9x, k10x=>k10x, k11x=>k11x, k12x=>k12x,
k13x=>k13x,k14x=>k14x, k15x=>k15x, k16x=>k16x );
iperm: ip port map ( ct=>ct, l0x=>l0xa, r0x=>r0xa );
round1: roundfunc port map ( clk=>clk, reset=>reset, li=>l0xa, ri=>r0xa, k=>k1x, lo=>l1x, ro=>r1x );
round2: roundfunc port map ( clk=>clk, reset=>reset, li=>l1x, ri=>r1x, k=>k2x, lo=>l2x, ro=>r2x );
round3: roundfunc port map ( clk=>clk, reset=>reset, li=>l2x, ri=>r2x, k=>k3x, lo=>l3x, ro=>r3x );
round4: roundfunc port map ( clk=>clk, reset=>reset, li=>l3x, ri=>r3x, k=>k4x, lo=>l4x, ro=>r4x );
round5: roundfunc port map ( clk=>clk, reset=>reset, li=>l4x, ri=>r4x, k=>k5x, lo=>l5x, ro=>r5x );
round6: roundfunc port map ( clk=>clk, reset=>reset, li=>l5x, ri=>r5x, k=>k6x, lo=>l6x, ro=>r6x );
round7: roundfunc port map ( clk=>clk, reset=>reset, li=>l6x, ri=>r6x, k=>k7x, lo=>l7x, ro=>r7x );
round8: roundfunc port map ( clk=>clk, reset=>reset, li=>l7x, ri=>r7x, k=>k8x, lo=>l8x, ro=>r8x );
round9: roundfunc port map ( clk=>clk, reset=>reset, li=>l8x, ri=>r8x, k=>k9x, lo=>l9x, ro=>r9x );
round10: roundfunc port map ( clk=>clk, reset=>reset, li=>l9x, ri=>r9x, k=>k10x, lo=>l10x, ro=>r10x );
round11: roundfunc port map ( clk=>clk, reset=>reset, li=>l10x, ri=>r10x, k=>k11x, lo=>l11x, ro=>r11x );
round12: roundfunc port map ( clk=>clk, reset=>reset, li=>l11x, ri=>r11x, k=>k12x, lo=>l12x, ro=>r12x );
round13: roundfunc port map ( clk=>clk, reset=>reset, li=>l12x, ri=>r12x, k=>k13x, lo=>l13x, ro=>r13x );
round14: roundfunc port map ( clk=>clk, reset=>reset, li=>l13x, ri=>r13x, k=>k14x, lo=>l14x, ro=>r14x );
round15: roundfunc port map ( clk=>clk, reset=>reset, li=>l14x, ri=>r14x, k=>k15x, lo=>l15x, ro=>r15x );
round16: roundfunc port map ( clk=>clk, reset=>reset, li=>l15x, ri=>r15x, k=>k16x, lo=>l16x, ro=>r16x );
fperm: fp port map ( l=>r16x, r=>l16x, pt=>pt );
end behavior;
|
mit
|
Yuriu5/MiniBlaze
|
test/Simu/tb_generic_hdl_fifo.vhd
|
1
|
11671
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_generic_hdl_fifo is
generic (
runner_cfg : string
);
end tb_generic_hdl_fifo;
architecture simu of tb_generic_hdl_fifo is
component generic_hdl_fifo is
generic (
G_DEPTH_LOG2 : integer := 4; -- Depth is equal to 2^(G_DEPTH_LOG2)
G_WIDTH : integer := 8
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- Data
data_wr : in std_logic_vector(G_WIDTH-1 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
data_rd : out std_logic_vector(G_WIDTH-1 downto 0);
rd_valid : out std_logic;
-- Status
nb_data : out std_logic_vector(G_DEPTH_LOG2 downto 0);
empty : out std_logic;
full : out std_logic
);
end component;
constant C_DEPTH : integer := 4;
constant C_WIDTH : integer := 16;
constant C_PERIOD : time := 8 ns;
signal s_zero : std_logic_vector(C_WIDTH-1 downto 0) := (others => '0');
signal s_one : std_logic_vector(C_WIDTH-1 downto 0) := (others => '1');
signal s_test : std_logic_vector(C_WIDTH-1 downto 0);
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal s_data_wr : std_logic_vector(C_WIDTH-1 downto 0) := (others => '0');
signal s_wr_en : std_logic := '0';
signal s_rd_en : std_logic := '0';
signal s_data_rd : std_logic_vector(C_WIDTH-1 downto 0) := (others => '0');
signal s_rd_valid : std_logic := '0';
signal s_nb_data : std_logic_vector(C_DEPTH downto 0) := (others => '0');
signal s_empty : std_logic := '0';
signal s_full : std_logic := '0';
signal r_cnt : unsigned(C_WIDTH-1 downto 0) := (others => '0');
begin
clk <= not clk after C_PERIOD/2;
s_test <= x"CAFE";
i_dut : generic_hdl_fifo
generic map(
G_DEPTH_LOG2 => C_DEPTH,
G_WIDTH => C_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
--
data_wr => s_data_wr,
wr_en => s_wr_en,
rd_en => s_rd_en,
data_rd => s_data_rd,
rd_valid => s_rd_valid,
--
nb_data => s_nb_data,
empty => s_empty,
full => s_full
);
main : process
variable filter : log_filter_t;
begin
checker_init( display_format => verbose,
file_name => join(output_path(runner_cfg), "error.cvs"),
file_format => verbose_csv);
logger_init( display_format => verbose,
file_name => join(output_path(runner_cfg), "log.csv"),
file_format => verbose_csv);
stop_level((debug,verbose), display_handler, filter);
test_runner_setup(runner,runner_cfg);
enable_pass_msg;
enable_pass_msg(file_handler);
enable_pass_msg(display_handler);
while test_suite loop
reset_checker_stat;
wait until rising_edge(clk);
rst_n <= '0';
wait for 10*C_PERIOD;
rst_n <= '1';
wait until rising_edge(clk);
if run("test_during_reset") then
rst_n <= '0';
wait until rising_edge(clk);
check_equal(s_data_wr, s_zero(s_data_wr'left downto 0));
check_equal(s_wr_en, '0');
check_equal(s_rd_en, '0');
check_equal(s_data_rd, s_zero(s_data_rd'left downto 0));
check_equal(s_rd_valid, '0');
check_equal(s_nb_data, s_zero(s_nb_data'left downto 0));
check_equal(s_empty, '1');
check_equal(s_full, '1');
elsif run("test_write_one_word") then
wait until rising_edge(clk);
s_wr_en <= '1';
s_data_wr <= s_test;
check_equal(s_empty, '1');
check_equal(s_nb_data, s_zero(s_nb_data'left downto 0));
wait until rising_edge(clk);
s_wr_en <= '0';
s_rd_en <= '1';
wait until rising_edge(clk);
check_equal(s_nb_data, std_logic_vector(to_unsigned(1,C_DEPTH+1)));
check_equal(s_empty, '0');
s_rd_en <= '0';
wait until rising_edge(clk);
check_equal(s_empty, '1');
check_equal(s_nb_data, s_zero(s_nb_data'left downto 0));
check_equal(s_data_rd, s_test);
check_equal(s_rd_valid, '1');
wait until rising_edge(clk);
check_equal(s_rd_valid, '0');
elsif run("test_after_reset") then
check_equal(s_data_wr, s_zero(s_data_wr'left downto 0));
check_equal(s_wr_en, '0');
check_equal(s_rd_en, '0');
check_equal(s_data_rd, s_zero(s_data_rd'left downto 0));
check_equal(s_rd_valid, '0');
check_equal(s_nb_data, s_zero(s_nb_data'left downto 0));
check_equal(s_empty, '1');
check_equal(s_full, '0');
elsif run("write_full_then_read") then
wait until rising_edge(clk);
s_wr_en <= '1';
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
s_data_wr <= std_logic_vector(r_cnt);
wait until rising_edge(clk);
check_equal(s_full, '1');
s_rd_en <= '1';
s_wr_en <= '0';
wait until s_rd_valid = '1' and rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(1,C_WIDTH)), "Should be 1");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(2,C_WIDTH)), "Should be 2");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(3,C_WIDTH)), "Should be 3");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(4,C_WIDTH)), "Should be 4");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(5,C_WIDTH)), "Should be 5");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(6,C_WIDTH)), "Should be 6");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(7,C_WIDTH)), "Should be 7");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(8,C_WIDTH)), "Should be 8");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(9,C_WIDTH)), "Should be 9");
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(10,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(11,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(12,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(13,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(14,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(15,C_WIDTH)));
wait until rising_edge(clk);
check_equal(s_data_rd, std_logic_vector(to_unsigned(16,C_WIDTH)));
wait until rising_edge(clk);
log(to_string(s_nb_data));
s_rd_en <= '0';
check_equal(s_empty, '1');
check_equal(s_rd_valid, '0');
elsif run("read_when_emtpy") then
s_rd_en <= '1';
wait until rising_edge(clk);
s_rd_en <= '0';
wait until rising_edge(clk);
check_equal(s_rd_valid, '0');
check_equal(s_empty, '1');
check_equal(s_nb_data, std_logic_vector(to_unsigned(0,C_DEPTH+1)));
s_wr_en <= '1';
wait until rising_edge(clk);
s_wr_en <= '0';
wait until rising_edge(clk);
check_equal(s_nb_data, std_logic_vector(to_unsigned(1,C_DEPTH+1)));
check_equal(s_empty, '0');
elsif run("write_when_full") then
s_wr_en <= '1';
wait until s_full = '1' and rising_edge(clk);
s_wr_en <= '0';
wait until rising_edge(clk);
check_equal(unsigned(s_nb_data), (to_unsigned(2**C_DEPTH, C_DEPTH+1)), "Should be full");
wait until rising_edge(clk);
s_wr_en <= '1';
wait until rising_edge(clk);
check_equal(unsigned(s_nb_data), (to_unsigned(2**C_DEPTH, C_DEPTH+1)));
s_rd_en <= '1';
wait until rising_edge(clk);
s_rd_en <= '0';
wait until rising_edge(clk);
check_equal(s_rd_valid, '1');
check_equal(unsigned(s_nb_data), (to_unsigned((2**C_DEPTH)-1, C_DEPTH+1)));
check_equal(s_full, '0');
end if;
end loop;
test_runner_cleanup(runner);
end process;
process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
r_cnt <= (others => '0');
else
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
end simu;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/road/simulation/road_synth.vhd
|
1
|
6808
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: road_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY road_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE road_synth_ARCH OF road_synth IS
COMPONENT road_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: road_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
capitanov/Stupid_watch
|
src/rtl/chips/rtl_ds1302.vhd
|
1
|
8690
|
-------------------------------------------------------------------------------
--
-- Title : rtl_ds1302
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : There is a serial interface controller for ds1302 chip.
-- Serial interface has 3 ports (i/o, clk, enable).
-- User interface has 4 ports:
-- data_i - input data, from fpga to chip,
-- data_o - output data, from chip to fpga,
-- addr_i - sets address for read/write,
-- enable - start of operation.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rtl_ds1302 is
generic (
TD : in time; --! simulation time;
DIV_SCL : in integer --! clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; --! system frequency (50 MHz)
rstn : in std_logic; --! negative reset
-- main interface
enable : in std_logic; --! serial start (S)
addr_i : in std_logic_vector(7 downto 0); --! address Tx: 7 bit - always '1', 0 bit - R/W ('0' - write, '1' - read)
data_i : in std_logic_vector(7 downto 0); --! data (Tx)
data_o : out std_logic_vector(7 downto 0); --! data (Rx)
data_v : out std_logic; --! valid Rx
ready : out std_logic; --! ready for data
-- serial interface
ds_data_i : in std_logic; --! serial data input
ds_data_o : out std_logic; --! serial data output
ds_data_t : out std_logic; --! serial data enable
ds_clk : out std_logic; --! serial clock
ds_ena : out std_logic --! clock enable for i2c
);
end rtl_ds1302;
architecture rtl_ds1302 of rtl_ds1302 is
type fsm_serial is ( RDY, START, WAITING, DATA, ADDR,
CLK_RISE, CLK_FALL, CLK_ONE,
WRITE, CLK_WR_R, CLK_WR1, CLK_WR_F,
CLK_RD_R, CLK_RD1, CLK_RD_F, STOP);
signal STM : fsm_serial;
signal dat_s : std_logic;
signal dat_e : std_logic;
signal clk_s : std_logic;
signal clk_r : std_logic;
signal clk_f : std_logic;
signal clk_z : std_logic;
signal cnt : std_logic_vector(3 downto 0);
signal reg_iic : std_logic_vector(7 downto 0);
signal reg_in : std_logic_vector(7 downto 0);
signal clk_low : std_logic;
signal scl_cnt : integer range 0 to DIV_SCL:=0;
signal rdwr : std_logic;
signal data_b : std_logic;
signal data_vl : std_logic;
-- delete this:
--signal ena_cnt : std_logic_vector(12 downto 0);
--signal ena_stw : std_logic;
--signal ena_vld : std_logic:='0';
--signal ena_stwz : std_logic;
--signal ena_stwx : std_logic;
begin
-- test ce inactive time:
--ena_vld <= '1' when (enable = '1') else '0' when (data_vl = '1');
--pr_ce_inactive: process(clk50m, rstn) is
--begin
-- if (rstn = '0') then
-- ena_stw <= '0';
-- ena_cnt <= (others => '0');
-- elsif (rising_edge(clk50m)) then
-- if (ena_vld = '1') then
-- if ena_cnt(12) = '0' then
-- ena_stw <= '0' after td;
-- ena_cnt <= ena_cnt + 1 after td;
-- else
-- ena_stw <= '1' after td;
-- end if;
-- else
-- ena_cnt <= (others => '0') after td;
-- end if;
-- end if;
--end process;
--ena_stwz <= ena_stw after td when rising_edge(clk50m);
--ena_stwx <= (ena_stw and not ena_stwz) after td when rising_edge(clk50m);
rdwr <= addr_i(0);-- after td when rising_edge(clk);
-- clk_low generator:
pr_cnt_serial: process(clk50m, rstn) is
begin
if (rstn = '0') then
scl_cnt <= 0;
clk_low <= '0';
elsif (rising_edge(clk50m)) then
if (scl_cnt = DIV_SCL) then
scl_cnt <= 0 after td;
clk_low <= not clk_low after td;
else
scl_cnt <= scl_cnt + 1 after td;
end if;
end if;
end process;
-- clk rising/falling
clk_z <= clk_low after td when rising_edge(clk50m);
clk_r <= (not clk_z) and clk_low after td when rising_edge(clk50m);
clk_f <= (not clk_low) and clk_z after td when rising_edge(clk50m);
pr_fsm: process(clk50m, rstn) is
begin
if (rstn = '0') then
cnt <= x"0";
clk_s <= '0';
dat_s <= '0';
dat_e <= '0';
ds_ena <= '0';
ready <= '0';
reg_iic <= x"00";
reg_in <= x"00";
data_o <= x"00";
data_vl <= '0';
STM <= RDY;
elsif (rising_edge(clk50m)) then
case (STM) is
when RDY =>
data_vl <= '0' after td;
ds_ena <= '0' after td;
dat_e <= '0' after td;
--if (ena_stwx = '1') then
if (enable = '1') then
STM <= START after td;
end if;
if (clk_r = '1') then--(clk_f = '1') then
--dat_e <= '0' after td;
--ds_ena <= '0' after td;
ready <= '1' after td;
end if;
when START =>
if (clk_r = '1') then
clk_s <= '0' after td;
reg_iic <= addr_i after td;
ready <= '0' after td;
cnt <= x"1" after td;
ds_ena <= '1' after td;
STM <= ADDR after td;
end if;
when ADDR =>
if (clk_f = '1') then
dat_s <= reg_iic(0) after td;
dat_e <= '0' after td;
--ds_ena <= '1' after td;
STM <= CLK_RISE after td;
end if;
when CLK_RISE =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_ONE after td;
end if;
when CLK_ONE =>
if (clk_f = '1') then
reg_iic <= '0' & reg_iic(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_FALL after td;
else
dat_e <= rdwr after td;
--dat_s <= '0' after td;
STM <= WAITING after td;
end if;
end if;
when CLK_FALL =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= ADDR after td;
end if;
when WAITING =>
if (clk_r = '1') then
clk_s <= '0' after td;
if (rdwr = '0') then
reg_iic <= data_i after td;
reg_in <= x"00" after td;
cnt <= x"1" after td;
STM <= WRITE after td;
else
reg_iic <= x"00" after td;
cnt <= x"1" after td;
dat_s <= '0' after td;
--dat_e <= '1' after td;
reg_in <= data_b & reg_in(7 downto 1) after td;
STM <= CLK_RD_R after td;
end if;
end if;
when WRITE =>
if (clk_f = '1') then
dat_s <= reg_iic(0) after td;
STM <= CLK_WR_R after td;
end if;
when CLK_WR_R =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_WR1 after td;
end if;
when CLK_WR1 =>
if (clk_f = '1') then
reg_iic <= '0' & reg_iic(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_WR_F after td;
else
--dat_s <= '0' after td;
dat_e <= '0' after td;
STM <= STOP after td;
end if;
end if;
when CLK_WR_F =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= WRITE after td;
end if;
when CLK_RD_R =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_RD1 after td;
end if;
if (clk_f = '1') then
reg_in <= data_b & reg_in(7 downto 1) after td;
end if;
when CLK_RD1 =>
if (clk_f = '1') then
--reg_in <= data_b & reg_in(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_RD_F after td;
else
--dat_e <= '0' after td;
STM <= STOP after td;
end if;
end if;
when CLK_RD_F =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= CLK_RD_R after td;
end if;
when STOP =>
if (clk_r = '1') then
clk_s <= '0' after td;
reg_iic <= x"00" after td;
reg_in <= x"00" after td;
data_o <= reg_in after td;
--data_vl <= '1' after td;
end if;
if (clk_f = '1') then
data_vl <= '1' after td;
dat_e <= '0' after td;
STM <= RDY after td;
end if;
when others => null;
end case;
end if;
end process;
data_v <= data_vl;
data_b <= ds_data_i;-- when dat_e = '1';
ds_data_o <= dat_s;-- when dat_e = '0' else '0';
ds_data_t <= dat_e;
ds_clk <= clk_s;
end rtl_ds1302;
|
mit
|
pdt/ttask
|
test/fpga-sim/sim/my_fpga_test_count_up.vhdl
|
1
|
1837
|
--
-- my_fpga_test_count_up.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use work.tbmsgs.all;
entity my_fpga_test_count_up is
end entity;
architecture sim of my_fpga_test_count_up is
signal clk : std_logic := '0';
signal n_rst : std_logic := '0';
signal up : std_logic := '0';
signal dn : std_logic := '0';
signal cnt : std_logic_vector(31 downto 0);
signal cnt_1k : std_logic_vector(3 downto 0);
signal in1 : std_logic := '0';
signal in2 : std_logic := '0';
signal out1 : std_logic;
signal out2 : std_logic;
signal done : boolean := false;
begin
uut : entity work.my_fpga port map (
clk => clk,
n_rst => n_rst,
up => up,
dn => dn,
cnt => cnt,
cnt_1k => cnt_1k,
in1 => in1,
in2 => in2,
out1 => out1,
out2 => out2
);
test : process
begin
testcase("my_fpga count up", 2);
wait for 1 us;
n_rst <= '1';
wait for 1 us;
-- check count after 10 clocks
wait until falling_edge(clk);
up <= '1';
for i in 0 to 9 loop
wait until falling_edge(clk);
end loop;
check(cnt = x"0000000a", "cnt should be 0x00000000a");
tested("count up to 10");
-- check count is 1024 after another 1014 clocks
for i in 0 to 1013 loop
wait until falling_edge(clk);
end loop;
check(cnt = x"00000400", "cnt should be 0x000000400");
tested("count up to 1024");
testcase_complete;
done <= true;
wait;
end process;
clk_gen : process
begin
loop
wait for 5 ns;
clk <= not clk;
if done then
exit;
end if;
end loop;
wait;
end process;
end;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/background/simulation/bmg_stim_gen.vhd
|
1
|
12588
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (76799 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"background.mif",
DEFAULT_DATA,
12,
76800);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>76800 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(16 DOWNTO 0) <= READ_ADDR(16 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 76800 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
mit
|
Fairyland0902/BlockyRoads
|
src/BlockyRoads/ipcore_dir/score/simulation/bmg_stim_gen.vhd
|
1
|
12583
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (11999 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"score.mif",
DEFAULT_DATA,
12,
12000);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>12000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 12000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/38a92fb39758d0fa/led_controller_design_rst_ps7_0_100M_0_stub.vhdl
|
1
|
1931
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:41 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : led_controller_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.3";
begin
end;
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Master/POCP/My_Designs/Accum/src/CTRL1.vhd
|
1
|
5439
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ROM
ROM_re: out std_logic;
ROM_addr: out mem_addr;
ROM_dout: in command;
-- RAM
RAM_rw: out std_logic;
RAM_addr: out mem_addr;
RAM_din: out operand;
RAM_dout: in operand;
--datapath
DP_op1: out operand;
DP_ot: out operation;
DP_en: out std_logic;
DP_res: in operand;
DP_zf: in std_logic
);
end CTRL1;
architecture Beh of CTRL1 is
type states is (I, F, D, R, L, SH, S, A, SB, H, JNOTZ, SIN);
-- I - idle
-- F - fetch
-- D - decode
-- R - read
-- L - load
-- SH - shift
-- S - store
-- A - add
-- SB - sub
-- H - halt
-- JNOTZ - jump if zero bit not set
-- SIN - store indirect
signal nxt_state, cur_state: states;
-- instruction register
signal RI: command;
-- instruction counter
signal IC: mem_addr;
-- operation type register
signal RO: operation;
-- memory address register
signal RA: mem_addr;
-- data register
signal RD: operand;
begin
-- synchronous memory
FSM: process(CLK, RST, nxt_state)
begin
if (RST = '1') then
cur_state <= I;
elsif rising_edge(CLK) then
cur_state <= nxt_state;
end if;
end process;
-- Next state
COMB: process(cur_state, start, RO)
begin
case cur_state is
when I =>
if (start = '1') then
nxt_state <= F;
else
nxt_state <= I;
end if;
when F => nxt_state <= D;
when D =>
if (RO = HALT) then
nxt_state <= H;
elsif (RO = STORE) then
nxt_state <= S;
elsif (RO = JNZ) then
nxt_state <= JNOTZ;
elsif (RO = SHIFT) then
nxt_state <= SH;
else
nxt_state <= R;
end if;
when R =>
if (RO = LOAD) then
nxt_state <= L;
elsif (RO = ADD) then
nxt_state <= A;
elsif (RO = SUBT) then
nxt_state <= SB;
elsif (RO = STOREIN) then
nxt_state <= SIN;
else
nxt_state <= I;
end if;
when SIN => nxt_state <= S;
when L | S | A | SB | SH | JNOTZ => nxt_state <= F;
when H => nxt_state <= H;
when others => nxt_state <= I;
end case;
end process;
-- stop signal
PSTOP: process (cur_state)
begin
if (cur_state = H) then
stop <= '1';
else
stop <= '0';
end if;
end process;
-- instruction counter
PMC: process (CLK, RST, cur_state)
begin
if (RST = '1') then
IC <= "00000";
elsif falling_edge(CLK) then
if (cur_state = D) then
IC <= IC + 1;
elsif (cur_state = JNOTZ and DP_ZF = '0') then
IC <= RA;
end if;
end if;
end process;
ROM_addr <= IC;
-- ROM read signal
PROMREAD: process (nxt_state, cur_state)
begin
if (nxt_state = F or cur_state = F) then
ROM_re <= '1';
else
ROM_re <= '0';
end if;
end process;
-- read ROM value and put it into RI
PROMDAT: process (RST, cur_state, ROM_dout)
begin
if (RST = '1') then
RI <= "00000000";
elsif (cur_state = F) then
RI <= ROM_dout;
end if;
end process;
-- RO and RA control
PRORA: process (RST, nxt_state, RI)
begin
if (RST = '1') then
RO <= "000";
RA <= "00000";
elsif (nxt_state = D) then
RO <= RI (7 downto 5);
RA <= RI (4 downto 0);
elsif (nxt_state = SIN) then
RA <= RD (4 downto 0);
end if;
end process;
PRAMST: process (RA)
begin
if (cur_state /= JNOTZ) then
RAM_addr <= RA;
end if;
end process;
-- RAM read/write control
PRAMREAD: process (cur_state)
begin
if (cur_state = S) then
RAM_rw <= '0';
else
RAM_rw <= '1';
end if;
end process;
-- read value from RAM and put it into RD
PRAMDAR: process (cur_state)
begin
if (cur_state = R) then
RD <= RAM_dout;
end if;
end process;
-- move the value from DPATH to RAM input bus
RAM_din <= DP_res;
-- move the value from RD to datapath
DP_op1 <= RD;
-- move RO value to DP operation bus
DP_ot <= RO;
paddsuben: process (cur_state)
begin
if (cur_state = A or cur_state = SB or cur_state = SH or cur_state = L) then
DP_en <= '1';
else
DP_en <= '0';
end if;
end process;
end Beh;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_stub.vhdl
|
1
|
1982
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:42 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : led_controller_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller_design_rst_ps7_0_100M_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end led_controller_design_rst_ps7_0_100M_0;
architecture stub of led_controller_design_rst_ps7_0_100M_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.3";
begin
end;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
16
|
94635
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/387128e4034068b3/zqynq_lab_1_design_processing_system7_0_0_stub.vhdl
|
1
|
5763
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
begin
end;
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Labs/POCP/POCP-4/src/TestBench/LFSR_In_t.vhd
|
1
|
1189
|
library ieee;
use ieee.std_logic_1164.all;
entity LFSR_IN_T is
end LFSR_In_T;
architecture Beh of LFSR_In_T is
component LFSR_In
port (
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 3);
Pout: out std_logic_vector(0 to 3)
);
end component;
signal CLK: std_logic := '0';
signal RST: std_logic := '0';
signal LS: std_logic := '0';
signal Pin: std_logic_vector(0 to 3) := (others => '0');
signal Pout: std_logic_vector(0 to 3);
constant CLK_Period: time := 10 ns;
begin
uut: LFSR_In port map (
CLK => CLK,
RST => RST,
LS => LS,
PIn => Pin,
POut => POut
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
stim_proc: process
begin
wait for CLK_Period;
RST <= '0'; wait for CLK_Period;
RST <= '1'; wait for 2*CLK_Period;
RST <= '0'; wait for CLK_Period;
PIn <= "1011"; wait for CLK_Period;
LS <= '1'; wait for 8*CLK_period;
end process;
end Beh;
configuration TESTBENCH_FOR_lfsr_in of LFSR_IN_T is
for Beh
for UUT : lfsr_in
use entity work.lfsr_in(behavior);
end for;
end for;
end TESTBENCH_FOR_lfsr_in;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/convolve_kernel_fcud.vhd
|
1
|
3164
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 8;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
mit
|
khaledhassan/vhdl-examples
|
adders_1bit/half_adder_tb.vhd
|
1
|
1939
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the half-adder.
library ieee;
use ieee.std_logic_1164.all;
entity half_adder_tb is
end half_adder_tb;
architecture TB of half_adder_tb is
signal a, b, sum, carry : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.half_adder
port map (
a => a,
b => b,
sum => sum,
carry => carry
);
-- Stimulus process
process
begin
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait;
end process;
end TB;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_2/embedded_lab_2.ip_user_files/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/sim/zynq_design_1_axi_bram_ctrl_0_0.vhd
|
2
|
16920
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zynq_design_1_axi_bram_ctrl_0_0_arch;
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Labs/POCP/POCP-6/src/RAM.vhd
|
2
|
1060
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity RAM is
generic(
-- øèíà äàííûõ
m: integer := 2;
-- øèíà àäðåñà
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- øèíà àäðåñà
AB: in std_logic_vector (m-1 downto 0);
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0)
);
end RAM;
architecture Beh of RAM is
-- òèï õðàíèìîãî ñëîâà
subtype word is std_logic_vector (n-1 downto 0);
-- íåïîñðåäñòâåííî òèï õðàíèëèùà äàííûõ
type tram is array (0 to 2**m - 1) of word;
signal sRAM: tram;
signal addrreg: integer range 0 to 2**m - 1;
Begin
addrreg <= CONV_INTEGER(AB);
WRP: process (WR, CLK, addrreg, DB)
begin
if WR = '0' then
if rising_edge(CLK) then
sRAM(addrreg) <= DB;
end if;
end if;
end process;
RDP: process(WR, sRAM, addrreg)
begin
if WR = '1' then
DB <= sRAM (addrreg);
else
DB <= (others => 'Z');
end if;
end process;
end Beh;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/33befe9f7af11a93/ip_design_led_controller_0_0_stub.vhdl
|
1
|
2678
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:09 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.vhdl
-- Design : ip_design_led_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3";
begin
end;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
7
|
143167
|
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`protect end_protected
|
mit
|
dawsonjon/FPGA-TX
|
synthesis/cmod_a7_15/tx/lfsr.vhd
|
3
|
643
|
library ieee;
use ieee.std_logic_1164.all;
entity lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end entity lfsr;
architecture rtl of lfsr is
signal shifter : std_logic_vector(63 downto 0) := init;
begin
process
begin
wait until rising_edge(clk);
if shifter(0) = '1' then
shifter <= ('0' & shifter(63 downto 1)) xor (X"d800000000000000");
else
shifter <= ('0' & shifter(63 downto 1));
end if;
rand <= shifter(63 downto 32) xor shifter(31 downto 0);
end process;
end rtl;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
7
|
103702
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
VHDL_UART/UART_LIB.vhd
|
1
|
949
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TX is
port(
CLK: in std_logic;
START: in std_logic;
BUSY: out std_logic;
DATA: in std_logic_vector(7 downto 0);
TX_LINE: out std_logic
);
end TX;
architecture MAIN of TX is
signal PRSCL: INTEGER range 0 to 5208:=0;
signal INDEX: integer range 0 to 9:=0;
signal DATAFLL: std_logic_vector(9 downto 0);
signal TX_FLG: std_logic:='0';
begin
process(CLK)
begin
if (CLK'event and CLK='1') then
if(TX_FLG='0' and START='1') then
TX_FLG<='1';
BUSY<='1';
DATAFLL(0)<='0';
DATAFLL(9)<='1';
DATAFLL(8 downto 1)<=DATA;
end if;
if (TX_FLG='1') then
if (PRSCL<5207) then
PRSCL <= PRSCL + 1;
else
PRSCL <= 0;
end if;
if (PRSCL=2607) then
TX_LINE<=DATAFLL(INDEX);
if (INDEX<9) then
INDEX <= INDEX + 1;
else
TX_FLG<='0';
BUSY<='0';
INDEX <= 0;
end if;
end if;
end if;
end if;
end process;
end MAIN;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/ip_design_axi_gpio_1_0_stub.vhdl
|
1
|
2478
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/ip_design_axi_gpio_1_0_stub.vhdl
-- Design : ip_design_axi_gpio_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ip_design_axi_gpio_1_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ip_design_axi_gpio_1_0;
architecture stub of ip_design_axi_gpio_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[4:0],gpio2_io_i[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.3";
begin
end;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/synth/ip_design.vhd
|
1
|
177183
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
--Date : Wed Oct 18 15:14:15 2017
--Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
--Command : generate_target ip_design.bd
--Design : ip_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_XB6WOP is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_XB6WOP;
architecture STRUCTURE of m00_couplers_imp_XB6WOP is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1CTDBQ9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_1CTDBQ9;
architecture STRUCTURE of m01_couplers_imp_1CTDBQ9 is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_3J4E14 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_3J4E14;
architecture STRUCTURE of m02_couplers_imp_3J4E14 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1OV3LN4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1OV3LN4;
architecture STRUCTURE of m03_couplers_imp_1OV3LN4 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_14CCC2J is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_14CCC2J;
architecture STRUCTURE of m04_couplers_imp_14CCC2J is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_JKHUF7 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_JKHUF7;
architecture STRUCTURE of m05_couplers_imp_JKHUF7 is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1Q6ZP2D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1Q6ZP2D;
architecture STRUCTURE of s00_couplers_imp_1Q6ZP2D is
component ip_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component ip_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component ip_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_ps7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end ip_design_ps7_0_axi_periph_0;
architecture STRUCTURE of ip_design_ps7_0_axi_periph_0 is
component ip_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component ip_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_ACLK_net : STD_LOGIC;
signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 3 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 3 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_ps7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_ps7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_ps7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_ps7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_ps7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_ps7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_ps7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_ps7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_ps7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_ps7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_ps7_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_ps7_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_ps7_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_ps7_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_ps7_0_axi_periph_WVALID(0);
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_ps7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_ps7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_ps7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_ps7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_ps7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_ps7_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_ps7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_ps7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_ps7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_ps7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_ps7_0_axi_periph_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_ps7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_ps7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_ps7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_ps7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_ps7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_ps7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_ps7_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
m03_couplers_to_ps7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_ps7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_ps7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_ps7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_ps7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_ps7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_ps7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_ps7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_ps7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_ps7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_ps7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_ps7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_ps7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_ps7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_ps7_0_axi_periph_WREADY <= M05_AXI_wready;
ps7_0_axi_periph_ACLK_net <= ACLK;
ps7_0_axi_periph_ARESETN_net <= ARESETN;
ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_XB6WOP
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1CTDBQ9
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_3J4E14
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m02_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m02_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m02_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1OV3LN4
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_14CCC2J
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_JKHUF7
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
s00_couplers: entity work.s00_couplers_imp_1Q6ZP2D
port map (
M_ACLK => ps7_0_axi_periph_ACLK_net,
M_ARESETN => ps7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component ip_design_xbar_0
port map (
aclk => ps7_0_axi_periph_ACLK_net,
aresetn => ps7_0_axi_periph_ARESETN_net,
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(17 downto 3) => NLW_xbar_m_axi_arprot_UNCONNECTED(17 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(17 downto 3) => NLW_xbar_m_axi_awprot_UNCONNECTED(17 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design is
port (
BCLK : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ip_design : entity is "ip_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ip_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=18,numReposBlks=10,numNonXlnxBlks=2,numHierBlks=8,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=2,da_clkrst_cnt=1,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of ip_design : entity is "ip_design.hwdef";
end ip_design;
architecture STRUCTURE of ip_design is
component ip_design_led_controller_0_0 is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component ip_design_led_controller_0_0;
component ip_design_nco_0_0 is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
end component ip_design_nco_0_0;
component ip_design_lms_pcore_0_0 is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
end component ip_design_lms_pcore_0_0;
component ip_design_processing_system7_0_0 is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component ip_design_processing_system7_0_0;
component ip_design_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component ip_design_rst_ps7_0_100M_0;
component ip_design_zed_audio_ctrl_0_0 is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
end component ip_design_zed_audio_ctrl_0_0;
component ip_design_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component ip_design_axi_gpio_0_0;
component ip_design_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ip_design_axi_gpio_1_0;
signal SDATA_I_0_1 : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_1_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_gpio_1_GPIO_TRI_I : STD_LOGIC_VECTOR ( 4 downto 0 );
signal led_controller_0_LEDs_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK1 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal zed_audio_ctrl_0_BCLK : STD_LOGIC;
signal zed_audio_ctrl_0_LRCLK : STD_LOGIC;
signal zed_audio_ctrl_0_SDATA_O : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 CLK.FCLK_CLK1 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME CLK.FCLK_CLK1, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000";
attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of IIC_0_scl_i : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of IIC_0_scl_o : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of IIC_0_scl_t : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of IIC_0_sda_i : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of IIC_0_sda_o : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of IIC_0_sda_t : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of GPIO_tri_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute X_INTERFACE_INFO of GPIO_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute X_INTERFACE_INFO of GPIO_tri_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute X_INTERFACE_INFO of btns_5bits_tri_i : signal is "xilinx.com:interface:gpio:1.0 btns_5bits TRI_I";
attribute X_INTERFACE_INFO of sws_8bits_tri_i : signal is "xilinx.com:interface:gpio:1.0 sws_8bits TRI_I";
begin
BCLK <= zed_audio_ctrl_0_BCLK;
FCLK_CLK1 <= processing_system7_0_FCLK_CLK1;
GPIO_tri_o(1 downto 0) <= axi_gpio_0_GPIO_TRI_O(1 downto 0);
GPIO_tri_t(1 downto 0) <= axi_gpio_0_GPIO_TRI_T(1 downto 0);
IIC_0_scl_o <= processing_system7_0_IIC_0_SCL_O;
IIC_0_scl_t <= processing_system7_0_IIC_0_SCL_T;
IIC_0_sda_o <= processing_system7_0_IIC_0_SDA_O;
IIC_0_sda_t <= processing_system7_0_IIC_0_SDA_T;
LEDs_out(7 downto 0) <= led_controller_0_LEDs_out(7 downto 0);
LRCLK <= zed_audio_ctrl_0_LRCLK;
SDATA_I_0_1 <= SDATA_I;
SDATA_O <= zed_audio_ctrl_0_SDATA_O;
axi_gpio_0_GPIO_TRI_I(1 downto 0) <= GPIO_tri_i(1 downto 0);
axi_gpio_1_GPIO2_TRI_I(7 downto 0) <= sws_8bits_tri_i(7 downto 0);
axi_gpio_1_GPIO_TRI_I(4 downto 0) <= btns_5bits_tri_i(4 downto 0);
processing_system7_0_IIC_0_SCL_I <= IIC_0_scl_i;
processing_system7_0_IIC_0_SDA_I <= IIC_0_sda_i;
axi_gpio_0: component ip_design_axi_gpio_0_0
port map (
gpio_io_i(1 downto 0) => axi_gpio_0_GPIO_TRI_I(1 downto 0),
gpio_io_o(1 downto 0) => axi_gpio_0_GPIO_TRI_O(1 downto 0),
gpio_io_t(1 downto 0) => axi_gpio_0_GPIO_TRI_T(1 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => ps7_0_axi_periph_M04_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_arready => ps7_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => ps7_0_axi_periph_M04_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => ps7_0_axi_periph_M04_AXI_AWADDR(8 downto 0),
s_axi_awready => ps7_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => ps7_0_axi_periph_M04_AXI_AWVALID,
s_axi_bready => ps7_0_axi_periph_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => ps7_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => ps7_0_axi_periph_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => ps7_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => ps7_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => ps7_0_axi_periph_M04_AXI_WVALID
);
axi_gpio_1: component ip_design_axi_gpio_1_0
port map (
gpio2_io_i(7 downto 0) => axi_gpio_1_GPIO2_TRI_I(7 downto 0),
gpio_io_i(4 downto 0) => axi_gpio_1_GPIO_TRI_I(4 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => ps7_0_axi_periph_M05_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_arready => ps7_0_axi_periph_M05_AXI_ARREADY,
s_axi_arvalid => ps7_0_axi_periph_M05_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => ps7_0_axi_periph_M05_AXI_AWADDR(8 downto 0),
s_axi_awready => ps7_0_axi_periph_M05_AXI_AWREADY,
s_axi_awvalid => ps7_0_axi_periph_M05_AXI_AWVALID,
s_axi_bready => ps7_0_axi_periph_M05_AXI_BREADY,
s_axi_bresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_bvalid => ps7_0_axi_periph_M05_AXI_BVALID,
s_axi_rdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_rready => ps7_0_axi_periph_M05_AXI_RREADY,
s_axi_rresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_rvalid => ps7_0_axi_periph_M05_AXI_RVALID,
s_axi_wdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_wready => ps7_0_axi_periph_M05_AXI_WREADY,
s_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s_axi_wvalid => ps7_0_axi_periph_M05_AXI_WVALID
);
led_controller_0: component ip_design_led_controller_0_0
port map (
LEDs_out(7 downto 0) => led_controller_0_LEDs_out(7 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID(0),
s00_axi_bready => ps7_0_axi_periph_M00_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => ps7_0_axi_periph_M00_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => ps7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => ps7_0_axi_periph_M00_AXI_WVALID(0)
);
lms_pcore_0: component ip_design_lms_pcore_0_0
port map (
AXI4_Lite_ACLK => processing_system7_0_FCLK_CLK0,
AXI4_Lite_ARADDR(15 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(15 downto 0),
AXI4_Lite_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
AXI4_Lite_ARREADY => ps7_0_axi_periph_M02_AXI_ARREADY,
AXI4_Lite_ARVALID => ps7_0_axi_periph_M02_AXI_ARVALID(0),
AXI4_Lite_AWADDR(15 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(15 downto 0),
AXI4_Lite_AWREADY => ps7_0_axi_periph_M02_AXI_AWREADY,
AXI4_Lite_AWVALID => ps7_0_axi_periph_M02_AXI_AWVALID(0),
AXI4_Lite_BREADY => ps7_0_axi_periph_M02_AXI_BREADY(0),
AXI4_Lite_BRESP(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
AXI4_Lite_BVALID => ps7_0_axi_periph_M02_AXI_BVALID,
AXI4_Lite_RDATA(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
AXI4_Lite_RREADY => ps7_0_axi_periph_M02_AXI_RREADY(0),
AXI4_Lite_RRESP(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
AXI4_Lite_RVALID => ps7_0_axi_periph_M02_AXI_RVALID,
AXI4_Lite_WDATA(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
AXI4_Lite_WREADY => ps7_0_axi_periph_M02_AXI_WREADY,
AXI4_Lite_WSTRB(3 downto 0) => ps7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
AXI4_Lite_WVALID => ps7_0_axi_periph_M02_AXI_WVALID(0),
IPCORE_CLK => processing_system7_0_FCLK_CLK0,
IPCORE_RESETN => rst_ps7_0_100M_peripheral_aresetn(0)
);
nco_0: component ip_design_nco_0_0
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_AXILiteS_ARADDR(5 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(5 downto 0),
s_axi_AXILiteS_ARREADY => ps7_0_axi_periph_M01_AXI_ARREADY,
s_axi_AXILiteS_ARVALID => ps7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_AXILiteS_AWADDR(5 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(5 downto 0),
s_axi_AXILiteS_AWREADY => ps7_0_axi_periph_M01_AXI_AWREADY,
s_axi_AXILiteS_AWVALID => ps7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_AXILiteS_BREADY => ps7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_AXILiteS_BRESP(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => ps7_0_axi_periph_M01_AXI_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => ps7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_AXILiteS_RRESP(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => ps7_0_axi_periph_M01_AXI_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => ps7_0_axi_periph_M01_AXI_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => ps7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => ps7_0_axi_periph_M01_AXI_WVALID(0)
);
processing_system7_0: component ip_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK1 => processing_system7_0_FCLK_CLK1,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
ps7_0_axi_periph: entity work.ip_design_ps7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => ps7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => ps7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => ps7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => ps7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => ps7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => ps7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => ps7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => ps7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => ps7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => ps7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => ps7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => ps7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => ps7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => ps7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => ps7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => ps7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => ps7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => ps7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => ps7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => ps7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => ps7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => ps7_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => ps7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => ps7_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => ps7_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => ps7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => ps7_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => ps7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => ps7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid(0) => ps7_0_axi_periph_M02_AXI_WVALID(0),
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => ps7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => ps7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => ps7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => ps7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => ps7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => ps7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => ps7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => ps7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => ps7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => ps7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => ps7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => ps7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => ps7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => ps7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => ps7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => ps7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => ps7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => ps7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => ps7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => ps7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => ps7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => ps7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => ps7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => ps7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => ps7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => ps7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => ps7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => ps7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => ps7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => ps7_0_axi_periph_M05_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_ps7_0_100M: component ip_design_rst_ps7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
zed_audio_ctrl_0: component ip_design_zed_audio_ctrl_0_0
port map (
BCLK => zed_audio_ctrl_0_BCLK,
LRCLK => zed_audio_ctrl_0_LRCLK,
SDATA_I => SDATA_I_0_1,
SDATA_O => zed_audio_ctrl_0_SDATA_O,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_ARADDR(31 downto 0) => ps7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
S_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S_AXI_ARREADY => ps7_0_axi_periph_M03_AXI_ARREADY,
S_AXI_ARVALID => ps7_0_axi_periph_M03_AXI_ARVALID,
S_AXI_AWADDR(31 downto 0) => ps7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
S_AXI_AWREADY => ps7_0_axi_periph_M03_AXI_AWREADY,
S_AXI_AWVALID => ps7_0_axi_periph_M03_AXI_AWVALID,
S_AXI_BREADY => ps7_0_axi_periph_M03_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => ps7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
S_AXI_BVALID => ps7_0_axi_periph_M03_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => ps7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
S_AXI_RREADY => ps7_0_axi_periph_M03_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => ps7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
S_AXI_RVALID => ps7_0_axi_periph_M03_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => ps7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
S_AXI_WREADY => ps7_0_axi_periph_M03_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => ps7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => ps7_0_axi_periph_M03_AXI_WVALID
);
end STRUCTURE;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd
|
6
|
57399
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/b19f/hdl/vhdl/lms_pcore_axi_lite.vhd
|
2
|
10041
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_axi_lite
-- Source Path: lms_pcore/lms_pcore_axi_lite
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_axi_lite IS
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END lms_pcore_axi_lite;
ARCHITECTURE rtl OF lms_pcore_axi_lite IS
-- Component Declarations
COMPONENT lms_pcore_addr_decoder
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
data_write : IN std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : IN std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : IN std_logic; -- ufix1
rd_enb : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
data_read : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite_module
PORT( clk : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
data_read : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
data_write : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : OUT std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : OUT std_logic; -- ufix1
rd_enb : OUT std_logic; -- ufix1
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_addr_decoder
USE ENTITY work.lms_pcore_addr_decoder(rtl);
FOR ALL : lms_pcore_axi_lite_module
USE ENTITY work.lms_pcore_axi_lite_module(rtl);
-- Signals
SIGNAL top_data_write : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL top_addr_sel : std_logic_vector(13 DOWNTO 0); -- ufix14
SIGNAL top_wr_enb : std_logic; -- ufix1
SIGNAL top_rd_enb : std_logic; -- ufix1
SIGNAL top_data_read : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL write_x_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL top_reset_internal : std_logic; -- ufix1
BEGIN
u_lms_pcore_addr_decoder_inst : lms_pcore_addr_decoder
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
reset => reset,
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
read_cop_out_ready => read_cop_out_ready, -- ufix1
cop_reg_strobe => cop_reg_strobe, -- ufix1
read_e_k => read_e_k, -- sfix16_En14
data_read => top_data_read, -- ufix32
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k_tmp, -- sfix16_En14
write_d_k => write_d_k_tmp -- sfix16_En14
);
u_lms_pcore_axi_lite_module_inst : lms_pcore_axi_lite_module
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
data_read => top_data_read, -- ufix32
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
reset_internal => top_reset_internal -- ufix1
);
reset_internal <= top_reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
write_x_k <= write_x_k_tmp;
write_d_k <= write_d_k_tmp;
END rtl;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/impl/ip/hdl/vhdl/fir.vhd
|
9
|
14661
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.714000,HLS_SYN_LAT=45,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=329,HLS_SYN_LUT=214}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_187 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_134_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_123_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_206 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_211 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal acc_1_fu_167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal acc_reg_89 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_106_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_102 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_123_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
acc_reg_89_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
acc_reg_89 <= acc_1_fu_167_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
acc_reg_89 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0))) then
data1_reg_114 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
data1_reg_114 <= x;
end if;
end if;
end process;
i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_reg_102 <= i_1_reg_206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_102 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_206 <= grp_fu_123_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_178 <= i_cast_fu_130_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0))) then
tmp_1_reg_187 <= tmp_1_fu_142_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_6_reg_211 <= tmp_6_fu_161_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_134_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
acc_1_fu_167_p2 <= std_logic_vector(unsigned(tmp_6_reg_211) + unsigned(acc_reg_89));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_157_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_123_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_106_p4, i_reg_102)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_123_p0 <= i_reg_102;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_123_p0 <= i_phi_fu_106_p4;
else
grp_fu_123_p0 <= "XXXXX";
end if;
end process;
grp_fu_123_p2 <= std_logic_vector(unsigned(grp_fu_123_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_130_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_102),32));
i_phi_fu_106_p4 <= i_reg_102;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3, tmp_3_fu_148_p1, tmp_4_fu_153_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_148_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_1_reg_187, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_142_p2 <= "1" when (i_reg_102 = ap_const_lv5_0) else "0";
tmp_3_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_123_p2),64));
tmp_4_fu_153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_5_fu_157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_6_fu_161_p0 <= c_q0;
tmp_6_fu_161_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(tmp_6_fu_161_p0) * signed(data1_reg_114))), 32));
tmp_fu_134_p3 <= i_reg_102(4 downto 4);
y <= acc_reg_89;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/aesl_mux_load_7_3_x_s.vhd
|
1
|
21565
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity aesl_mux_load_7_3_x_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
empty_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_EN_A : OUT STD_LOGIC;
empty_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_EN_A : OUT STD_LOGIC;
empty_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_EN_A : OUT STD_LOGIC;
empty_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_EN_A : OUT STD_LOGIC;
empty_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_EN_A : OUT STD_LOGIC;
empty_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_EN_A : OUT STD_LOGIC;
empty_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_EN_A : OUT STD_LOGIC;
empty_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_9 : IN STD_LOGIC_VECTOR (2 downto 0);
empty_10 : IN STD_LOGIC_VECTOR (1 downto 0);
empty : IN STD_LOGIC_VECTOR (2 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of aesl_mux_load_7_3_x_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state2_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter1_tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter2_tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_22_fu_174_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_22_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_21_reg_302 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_22_reg_307 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_23_reg_312 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_24_reg_317 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_25_reg_322 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_26_reg_327 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_27_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_fu_196_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_reg_337 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp4_fu_203_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_342 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_347 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_352 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp10_fu_218_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp10_reg_357 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal tmp_fu_156_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl_fu_164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_cast_fu_152_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_cast1_fu_148_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_168_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp_fu_180_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_185_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp5_fu_223_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp7_fu_228_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp9_fu_234_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_idle_pp0_0to3 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_tmp_15_reg_246 <= tmp_15_reg_246;
ap_reg_pp0_iter1_tmp_22_reg_256 <= tmp_22_reg_256;
tmp_15_reg_246 <= empty_9;
tmp_22_reg_256 <= tmp_22_fu_174_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) then
ap_reg_pp0_iter2_tmp_15_reg_246 <= ap_reg_pp0_iter1_tmp_15_reg_246;
empty_21_reg_302 <= empty_8_Dout_A;
empty_22_reg_307 <= empty_2_Dout_A;
empty_23_reg_312 <= empty_3_Dout_A;
empty_24_reg_317 <= empty_4_Dout_A;
empty_25_reg_322 <= empty_5_Dout_A;
empty_26_reg_327 <= empty_6_Dout_A;
empty_27_reg_332 <= empty_7_Dout_A;
sel_tmp10_reg_357 <= sel_tmp10_fu_218_p2;
sel_tmp3_reg_337 <= sel_tmp3_fu_196_p3;
sel_tmp4_reg_342 <= sel_tmp4_fu_203_p2;
sel_tmp6_reg_347 <= sel_tmp6_fu_208_p2;
sel_tmp8_reg_352 <= sel_tmp8_fu_213_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start));
end process;
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state2_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0 <= ap_start;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to3_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3))) then
ap_idle_pp0_0to3 <= ap_const_logic_1;
else
ap_idle_pp0_0to3 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to3)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to3))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <=
empty_27_reg_332 when (sel_tmp10_reg_357(0) = '1') else
sel_tmp9_fu_234_p3;
empty_2_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_2_Din_A <= ap_const_lv32_0;
empty_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_2_EN_A <= ap_const_logic_1;
else
empty_2_EN_A <= ap_const_logic_0;
end if;
end process;
empty_2_WEN_A <= ap_const_lv4_0;
empty_3_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_3_Din_A <= ap_const_lv32_0;
empty_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_3_EN_A <= ap_const_logic_1;
else
empty_3_EN_A <= ap_const_logic_0;
end if;
end process;
empty_3_WEN_A <= ap_const_lv4_0;
empty_4_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_4_Din_A <= ap_const_lv32_0;
empty_4_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_4_EN_A <= ap_const_logic_1;
else
empty_4_EN_A <= ap_const_logic_0;
end if;
end process;
empty_4_WEN_A <= ap_const_lv4_0;
empty_5_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_5_Din_A <= ap_const_lv32_0;
empty_5_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_5_EN_A <= ap_const_logic_1;
else
empty_5_EN_A <= ap_const_logic_0;
end if;
end process;
empty_5_WEN_A <= ap_const_lv4_0;
empty_6_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_6_Din_A <= ap_const_lv32_0;
empty_6_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_6_EN_A <= ap_const_logic_1;
else
empty_6_EN_A <= ap_const_logic_0;
end if;
end process;
empty_6_WEN_A <= ap_const_lv4_0;
empty_7_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_7_Din_A <= ap_const_lv32_0;
empty_7_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_7_EN_A <= ap_const_logic_1;
else
empty_7_EN_A <= ap_const_logic_0;
end if;
end process;
empty_7_WEN_A <= ap_const_lv4_0;
empty_8_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_8_Din_A <= ap_const_lv32_0;
empty_8_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_8_EN_A <= ap_const_logic_1;
else
empty_8_EN_A <= ap_const_logic_0;
end if;
end process;
empty_8_WEN_A <= ap_const_lv4_0;
p_cast1_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(empty),32));
p_cast_fu_152_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(empty_10),32));
p_shl_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_156_p3),32));
sel_tmp10_fu_218_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_5) else "0";
sel_tmp1_fu_185_p3 <=
empty_22_reg_307 when (sel_tmp_fu_180_p2(0) = '1') else
empty_21_reg_302;
sel_tmp2_fu_191_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_1) else "0";
sel_tmp3_fu_196_p3 <=
empty_23_reg_312 when (sel_tmp2_fu_191_p2(0) = '1') else
sel_tmp1_fu_185_p3;
sel_tmp4_fu_203_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_2) else "0";
sel_tmp5_fu_223_p3 <=
empty_24_reg_317 when (sel_tmp4_reg_342(0) = '1') else
sel_tmp3_reg_337;
sel_tmp6_fu_208_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_3) else "0";
sel_tmp7_fu_228_p3 <=
empty_25_reg_322 when (sel_tmp6_reg_347(0) = '1') else
sel_tmp5_fu_223_p3;
sel_tmp8_fu_213_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_4) else "0";
sel_tmp9_fu_234_p3 <=
empty_26_reg_327 when (sel_tmp8_reg_352(0) = '1') else
sel_tmp7_fu_228_p3;
sel_tmp_fu_180_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_0) else "0";
tmp_21_fu_168_p2 <= std_logic_vector(unsigned(p_shl_fu_164_p1) - unsigned(p_cast_fu_152_p1));
tmp_22_fu_174_p2 <= std_logic_vector(unsigned(p_cast1_fu_148_p1) + unsigned(tmp_21_fu_168_p2));
tmp_fu_156_p3 <= (empty_10 & ap_const_lv3_0);
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_0_5/hdl/vhdl/convolve_kernel_fcud.vhd
|
4
|
3594
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Labs/POCP/POCP-2/src/TestBeanch.vhd
|
1
|
766
|
entity ODD_PARITY_TB is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture
OP_TB_ARCH of ODD_PARITY_TB is
component Parity_Generator1
port(
input_stream : in input;
clk : in std_logic;
parity : out bit);
end component;
signal input_stream : input;
signal clk :std_logic;
signal parity :bit ;
begin
U1: Parity_Generator1 port map (input_stream, clk, parity => parity );
input1 : process (clk)
begin
if clk <= 'U' then clk <= '0' after 1 ns;
else clk <= not clk after 1 ns;
end if;
end process;
input2: process (input_stream)
begin
input_stream <= "10100110" after 1 ns,
"01111100" after 2 ns;
end process;
end OP_TB_ARCH;
configuration cfg_op of ODD_PARITY_TB is
for OP_TB_ARCH
end for;
end cfg_op;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/vhdl/convolve_kernel.vhd
|
1
|
806728
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_A : OUT STD_LOGIC;
bufw_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_A : OUT STD_LOGIC;
bufw_0_Rst_A : OUT STD_LOGIC;
bufw_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_B : OUT STD_LOGIC;
bufw_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_B : OUT STD_LOGIC;
bufw_0_Rst_B : OUT STD_LOGIC;
bufw_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_A : OUT STD_LOGIC;
bufw_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_A : OUT STD_LOGIC;
bufw_1_Rst_A : OUT STD_LOGIC;
bufw_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_B : OUT STD_LOGIC;
bufw_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_B : OUT STD_LOGIC;
bufw_1_Rst_B : OUT STD_LOGIC;
bufw_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_A : OUT STD_LOGIC;
bufw_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_A : OUT STD_LOGIC;
bufw_2_Rst_A : OUT STD_LOGIC;
bufw_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_B : OUT STD_LOGIC;
bufw_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_B : OUT STD_LOGIC;
bufw_2_Rst_B : OUT STD_LOGIC;
bufw_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_A : OUT STD_LOGIC;
bufw_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_A : OUT STD_LOGIC;
bufw_3_Rst_A : OUT STD_LOGIC;
bufw_3_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_B : OUT STD_LOGIC;
bufw_3_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_B : OUT STD_LOGIC;
bufw_3_Rst_B : OUT STD_LOGIC;
bufw_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_A : OUT STD_LOGIC;
bufw_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_A : OUT STD_LOGIC;
bufw_4_Rst_A : OUT STD_LOGIC;
bufw_4_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_B : OUT STD_LOGIC;
bufw_4_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_B : OUT STD_LOGIC;
bufw_4_Rst_B : OUT STD_LOGIC;
bufw_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_A : OUT STD_LOGIC;
bufw_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_A : OUT STD_LOGIC;
bufw_5_Rst_A : OUT STD_LOGIC;
bufw_5_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_B : OUT STD_LOGIC;
bufw_5_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_B : OUT STD_LOGIC;
bufw_5_Rst_B : OUT STD_LOGIC;
bufw_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_A : OUT STD_LOGIC;
bufw_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_A : OUT STD_LOGIC;
bufw_6_Rst_A : OUT STD_LOGIC;
bufw_6_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_B : OUT STD_LOGIC;
bufw_6_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_B : OUT STD_LOGIC;
bufw_6_Rst_B : OUT STD_LOGIC;
bufw_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_A : OUT STD_LOGIC;
bufw_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_A : OUT STD_LOGIC;
bufw_7_Rst_A : OUT STD_LOGIC;
bufw_7_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_B : OUT STD_LOGIC;
bufw_7_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_B : OUT STD_LOGIC;
bufw_7_Rst_B : OUT STD_LOGIC;
bufw_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_A : OUT STD_LOGIC;
bufw_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_A : OUT STD_LOGIC;
bufw_8_Rst_A : OUT STD_LOGIC;
bufw_8_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_B : OUT STD_LOGIC;
bufw_8_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_B : OUT STD_LOGIC;
bufw_8_Rst_B : OUT STD_LOGIC;
bufw_9_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_A : OUT STD_LOGIC;
bufw_9_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_A : OUT STD_LOGIC;
bufw_9_Rst_A : OUT STD_LOGIC;
bufw_9_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_B : OUT STD_LOGIC;
bufw_9_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_B : OUT STD_LOGIC;
bufw_9_Rst_B : OUT STD_LOGIC;
bufw_10_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_A : OUT STD_LOGIC;
bufw_10_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_A : OUT STD_LOGIC;
bufw_10_Rst_A : OUT STD_LOGIC;
bufw_10_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_B : OUT STD_LOGIC;
bufw_10_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_B : OUT STD_LOGIC;
bufw_10_Rst_B : OUT STD_LOGIC;
bufw_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_A : OUT STD_LOGIC;
bufw_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_A : OUT STD_LOGIC;
bufw_11_Rst_A : OUT STD_LOGIC;
bufw_11_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_B : OUT STD_LOGIC;
bufw_11_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_B : OUT STD_LOGIC;
bufw_11_Rst_B : OUT STD_LOGIC;
bufw_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_A : OUT STD_LOGIC;
bufw_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_A : OUT STD_LOGIC;
bufw_12_Rst_A : OUT STD_LOGIC;
bufw_12_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_B : OUT STD_LOGIC;
bufw_12_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_B : OUT STD_LOGIC;
bufw_12_Rst_B : OUT STD_LOGIC;
bufi_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_A : OUT STD_LOGIC;
bufi_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_A : OUT STD_LOGIC;
bufi_0_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_B : OUT STD_LOGIC;
bufi_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_B : OUT STD_LOGIC;
bufi_0_Rst_B : OUT STD_LOGIC;
bufi_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_A : OUT STD_LOGIC;
bufi_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_A : OUT STD_LOGIC;
bufi_1_Rst_A : OUT STD_LOGIC;
bufi_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_B : OUT STD_LOGIC;
bufi_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_B : OUT STD_LOGIC;
bufi_1_Rst_B : OUT STD_LOGIC;
bufi_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_A : OUT STD_LOGIC;
bufi_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_A : OUT STD_LOGIC;
bufi_2_Rst_A : OUT STD_LOGIC;
bufi_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_B : OUT STD_LOGIC;
bufi_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_B : OUT STD_LOGIC;
bufi_2_Rst_B : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
bufo_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_B : OUT STD_LOGIC;
bufo_WEN_B : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_B : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_B : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_B : OUT STD_LOGIC;
bufo_Rst_B : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.384000,HLS_SYN_LAT=5467,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=117,HLS_SYN_FF=72137,HLS_SYN_LUT=50295}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (9 downto 0) := "0000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (9 downto 0) := "0000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (9 downto 0) := "0000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (9 downto 0) := "0001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (9 downto 0) := "0010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (9 downto 0) := "0100000000";
constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (9 downto 0) := "1000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_FFFFFFFFFFFFFFFF : STD_LOGIC_VECTOR (63 downto 0) := "1111111111111111111111111111111111111111111111111111111111111111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv10_2A3 : STD_LOGIC_VECTOR (9 downto 0) := "1010100011";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv8_87 : STD_LOGIC_VECTOR (7 downto 0) := "10000111";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal indvar_flatten1_reg_885 : STD_LOGIC_VECTOR (9 downto 0);
signal i_reg_896 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten_reg_908 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_919 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_reg_931 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_1_fu_1499_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_reg_3141 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state42_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state58_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state74_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal tmp_12_2_fu_1505_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_reg_3146 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_fu_1511_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_reg_3151 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_4_fu_1517_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_reg_3156 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_fu_1523_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_reg_3161 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_fu_1529_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_reg_3166 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_fu_1535_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_reg_3171 : STD_LOGIC_VECTOR (3 downto 0);
signal exitcond_flatten1_fu_1541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next1_fu_1547_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next1_reg_3180 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal i_1_fu_1553_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_3185 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond_flatten_fu_1559_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_3190 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_1565_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_reg_3206 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_op_fu_1571_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_op_reg_3211 : STD_LOGIC_VECTOR (7 downto 0);
signal j_mid_fu_1577_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid_reg_3216 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state19_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state27_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state35_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state43_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state59_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state67_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state75_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_pp0_stage1_11001 : BOOLEAN;
signal tmp_1_mid2_v_fu_1584_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_mid2_v_reg_3225 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_mid_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_mid_reg_3233 : STD_LOGIC_VECTOR (0 downto 0);
signal row_b_mid2_fu_1605_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter1_row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_fu_1613_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_next_reg_3252 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_1633_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_reg_3257 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state20_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state28_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state36_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state44_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state60_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state68_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_pp0_stage2_11001 : BOOLEAN;
signal j_1_fu_1642_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_3264 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_s_fu_1647_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_s_reg_3270 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_fu_1652_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_reg_3276 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_2_fu_1657_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_reg_3281 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_state21_pp0_stage3_iter2 : BOOLEAN;
signal ap_block_state29_pp0_stage3_iter3 : BOOLEAN;
signal ap_block_state37_pp0_stage3_iter4 : BOOLEAN;
signal ap_block_state45_pp0_stage3_iter5 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter6 : BOOLEAN;
signal ap_block_state61_pp0_stage3_iter7 : BOOLEAN;
signal ap_block_state69_pp0_stage3_iter8 : BOOLEAN;
signal ap_block_pp0_stage3_11001 : BOOLEAN;
signal tmp_5_mid2_fu_1662_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_reg_3286 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_fu_1667_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_reg_3294 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_90_fu_1694_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_90_reg_3299 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_3_fu_1706_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_reg_3311 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state14_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_state22_pp0_stage4_iter2 : BOOLEAN;
signal ap_block_state30_pp0_stage4_iter3 : BOOLEAN;
signal ap_block_state38_pp0_stage4_iter4 : BOOLEAN;
signal ap_block_state46_pp0_stage4_iter5 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter6 : BOOLEAN;
signal ap_block_state62_pp0_stage4_iter7 : BOOLEAN;
signal ap_block_state70_pp0_stage4_iter8 : BOOLEAN;
signal ap_block_pp0_stage4_11001 : BOOLEAN;
signal tmp_5_mid2_cast2_fu_1721_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast2_reg_3316 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_6_fu_1727_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_reg_3321 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_1732_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_reg_3326 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_2_mid1_fu_1748_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_mid1_reg_3331 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_130_fu_1753_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_130_reg_3336 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_fu_1758_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_reg_3341 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state15_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_state23_pp0_stage5_iter2 : BOOLEAN;
signal ap_block_state31_pp0_stage5_iter3 : BOOLEAN;
signal ap_block_state39_pp0_stage5_iter4 : BOOLEAN;
signal ap_block_state47_pp0_stage5_iter5 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter6 : BOOLEAN;
signal ap_block_state63_pp0_stage5_iter7 : BOOLEAN;
signal ap_block_state71_pp0_stage5_iter8 : BOOLEAN;
signal ap_block_pp0_stage5_11001 : BOOLEAN;
signal tmp_7_fu_1807_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_7_reg_3356 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_4_mid1_fu_1840_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_mid1_reg_3481 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_fu_1846_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_reg_3486 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_fu_1852_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_reg_3491 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_fu_1858_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_reg_3496 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_210_fu_1876_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_210_reg_3511 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_fu_1881_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_reg_3516 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state16_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_state24_pp0_stage6_iter2 : BOOLEAN;
signal ap_block_state32_pp0_stage6_iter3 : BOOLEAN;
signal ap_block_state40_pp0_stage6_iter4 : BOOLEAN;
signal ap_block_state48_pp0_stage6_iter5 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter6 : BOOLEAN;
signal ap_block_state64_pp0_stage6_iter7 : BOOLEAN;
signal ap_block_state72_pp0_stage6_iter8 : BOOLEAN;
signal ap_block_pp0_stage6_11001 : BOOLEAN;
signal tmp_290_fu_1978_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_290_reg_3616 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_fu_1983_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_reg_3621 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_fu_1988_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_reg_3626 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_fu_1993_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_reg_3631 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state17_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_state25_pp0_stage7_iter2 : BOOLEAN;
signal ap_block_state33_pp0_stage7_iter3 : BOOLEAN;
signal ap_block_state41_pp0_stage7_iter4 : BOOLEAN;
signal ap_block_state49_pp0_stage7_iter5 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter6 : BOOLEAN;
signal ap_block_state65_pp0_stage7_iter7 : BOOLEAN;
signal ap_block_state73_pp0_stage7_iter8 : BOOLEAN;
signal ap_block_pp0_stage7_11001 : BOOLEAN;
signal bufw_0_load_reg_3686 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_reg_3693 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_1_reg_3710 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_reg_3718 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_reg_3735 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_reg_3752 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_1_reg_3759 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_reg_3767 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_1_reg_3774 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_reg_3782 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_1_reg_3789 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_reg_3797 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_1_reg_3804 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_reg_3812 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_1_reg_3819 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_reg_3827 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_1_reg_3834 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_reg_3842 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_1_reg_3849 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_reg_3857 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_1_reg_3864 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_reg_3872 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_1_reg_3879 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_reg_3887 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_1_reg_3894 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_reg_3902 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_1_reg_3909 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_reg_3917 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_1_reg_3924 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_1_reg_3931 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_1_reg_3948 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_1_reg_3965 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_2_reg_4012 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal bufw_1_load_2_reg_4019 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_2_reg_4026 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_2_reg_4033 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_2_reg_4040 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_2_reg_4047 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_2_reg_4054 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_2_reg_4061 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_2_reg_4068 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_2_reg_4075 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_2_reg_4082 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_2_reg_4089 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_2_reg_4096 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_2_reg_4103 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_2_reg_4120 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_2_reg_4137 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_3_reg_4154 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_3_reg_4171 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_3_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_4_reg_4205 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_4_reg_4222 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_4_reg_4239 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_5_reg_4256 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_5_reg_4273 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_5_reg_4290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_333_fu_2022_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_333_reg_4307 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_0_load_6_reg_4327 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_6_reg_4344 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_6_reg_4361 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_7_reg_4378 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_7_reg_4395 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_7_reg_4412 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_350_reg_4449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_reg_4454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_reg_4459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_reg_4464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_4469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_4474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_reg_4479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_4484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_reg_4489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_37_reg_4494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_40_reg_4499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_reg_4504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_reg_4509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_fu_2109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_reg_4514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_4519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_reg_4524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_reg_4529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_reg_4534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_reg_4539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_68_reg_4544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_4549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_reg_4554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_reg_4559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_reg_4564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_reg_4569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_86_reg_4574 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_353_reg_4589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_reg_4594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_96_reg_4599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_reg_4604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_102_reg_4609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_105_reg_4614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_108_reg_4619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_111_reg_4624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_114_reg_4629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_117_reg_4634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_120_reg_4639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_123_reg_4644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_126_reg_4649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_fu_2145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_reg_4654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_133_reg_4659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_136_reg_4664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_139_reg_4669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_142_reg_4674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_145_reg_4679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_148_reg_4684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_151_reg_4689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_154_reg_4694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_157_reg_4699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_160_reg_4704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_163_reg_4709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_166_reg_4714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_fu_2149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_reg_4719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_173_reg_4724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_176_reg_4729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_179_reg_4734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_182_reg_4739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_185_reg_4744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_188_reg_4749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_191_reg_4754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_194_reg_4759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_197_reg_4764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_reg_4769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_203_reg_4774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_206_reg_4779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_fu_2153_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_reg_4784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_reg_4789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_216_reg_4794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_219_reg_4799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_222_reg_4804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_reg_4809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_reg_4814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_reg_4819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_234_reg_4824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_237_reg_4829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_reg_4834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_243_reg_4839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_246_reg_4844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_349_reg_4849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_reg_4859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_reg_4869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_reg_4879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_reg_4889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_reg_4899 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_reg_4909 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_reg_4919 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_reg_4929 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_reg_4939 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_s_reg_4949 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_reg_4959 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_reg_4969 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_reg_4979 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_reg_4984 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_reg_4989 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_reg_4994 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_reg_4999 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_reg_5004 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_reg_5009 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_reg_5014 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_reg_5019 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_reg_5024 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_s_reg_5029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_reg_5034 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_reg_5039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_fu_2157_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_reg_5044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_253_reg_5049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_256_reg_5054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_259_reg_5059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_262_reg_5064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_265_reg_5069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_268_reg_5074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_271_reg_5079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_274_reg_5084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_277_reg_5089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_280_reg_5094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_283_reg_5099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_286_reg_5104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_fu_2161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_reg_5109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_293_reg_5114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_296_reg_5119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_299_reg_5124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_302_reg_5129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_305_reg_5134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_308_reg_5139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_311_reg_5144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_314_reg_5149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_317_reg_5154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_320_reg_5159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_323_reg_5164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_326_reg_5169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_2165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_2169_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_2173_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_2177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_2181_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_fu_2193_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_fu_2197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_2201_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_41_fu_2205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_44_fu_2209_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_fu_2213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_2221_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_2225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_2229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_2233_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_2237_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_2241_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_2245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_2249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_2253_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_2257_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_84_fu_2261_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_2265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_reg_5369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_reg_5374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_reg_5379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_reg_5384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_reg_5389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_reg_5394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_reg_5399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_reg_5404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_reg_5409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_reg_5414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_s_reg_5419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_reg_5424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_reg_5429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_reg_5434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_reg_5439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_reg_5444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_reg_5449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_reg_5454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_reg_5459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_reg_5464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_reg_5469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_reg_5474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_reg_5479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_s_reg_5484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_reg_5489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_reg_5494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_2269_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_94_fu_2273_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_97_fu_2277_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_100_fu_2281_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_103_fu_2285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_106_fu_2289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_109_fu_2293_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_112_fu_2297_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_115_fu_2301_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_118_fu_2305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_121_fu_2309_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_124_fu_2313_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_127_fu_2317_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_131_fu_2321_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_134_fu_2325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_137_fu_2329_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_140_fu_2333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_143_fu_2337_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_146_fu_2341_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_149_fu_2345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_152_fu_2349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_155_fu_2353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_158_fu_2357_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_161_fu_2361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_164_fu_2365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_167_fu_2369_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_reg_5694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_reg_5699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_reg_5704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_reg_5709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_reg_5714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_reg_5719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_reg_5724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_reg_5729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_reg_5734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_reg_5739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_s_reg_5744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_reg_5749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_reg_5754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_reg_5759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_reg_5764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_reg_5769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_reg_5774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_reg_5779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_reg_5784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_reg_5789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_reg_5794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_reg_5799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_reg_5804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_s_reg_5809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_reg_5814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_reg_5819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_171_fu_2373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_174_fu_2377_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_177_fu_2381_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_180_fu_2385_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_183_fu_2389_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_186_fu_2393_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_189_fu_2397_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_192_fu_2401_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_195_fu_2405_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_198_fu_2409_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_201_fu_2413_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_204_fu_2417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_207_fu_2421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_fu_2425_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_214_fu_2429_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_fu_2433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_220_fu_2437_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_223_fu_2441_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_fu_2445_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_229_fu_2449_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_fu_2453_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_235_fu_2457_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_238_fu_2461_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_241_fu_2465_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_244_fu_2469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_247_fu_2473_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_reg_6019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_reg_6024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_reg_6034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_reg_6039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_reg_6044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_reg_6049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_reg_6054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_reg_6064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_s_reg_6069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_reg_6074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_reg_6079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_reg_6084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_reg_6089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_reg_6094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_reg_6104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_reg_6114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_reg_6119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_reg_6124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_s_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_251_fu_2477_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_254_fu_2481_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_257_fu_2485_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_260_fu_2489_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_263_fu_2493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_266_fu_2497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_269_fu_2501_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_272_fu_2505_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_275_fu_2509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_278_fu_2513_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_281_fu_2517_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_284_fu_2521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_287_fu_2525_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_291_fu_2529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_294_fu_2533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_297_fu_2537_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_300_fu_2541_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_303_fu_2545_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_306_fu_2549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_309_fu_2553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_312_fu_2557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_315_fu_2561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_318_fu_2565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_321_fu_2569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_324_fu_2573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_327_fu_2577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_351_reg_7059 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal grp_fu_947_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_1_reg_7064 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_reg_7069 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_reg_7074 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_reg_7079 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_reg_7084 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_reg_7089 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_reg_7094 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_reg_7099 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_reg_7104 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_s_reg_7109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_reg_7114 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_reg_7119 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_reg_7124 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_reg_7129 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_reg_7134 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_reg_7139 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_reg_7144 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_reg_7149 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_reg_7154 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_reg_7159 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_reg_7164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_reg_7169 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_s_reg_7174 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_reg_7179 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_reg_7184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_reg_7189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_reg_7194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_reg_7199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_reg_7204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_reg_7209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_reg_7214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_reg_7219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_reg_7224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_reg_7229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_reg_7234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_s_reg_7239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_reg_7244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_reg_7249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_reg_7254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_reg_7259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_reg_7264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_reg_7269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_reg_7274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_reg_7279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_reg_7284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_reg_7289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_reg_7294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_reg_7299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_s_reg_7304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_reg_7309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_reg_7314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_reg_7319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_reg_7324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_reg_7329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_reg_7334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_reg_7339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_reg_7344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_reg_7349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_reg_7354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_reg_7359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_reg_7364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_s_reg_7369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_reg_7374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_reg_7379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_reg_7384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_reg_7389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_reg_7394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_reg_7399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_reg_7404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_reg_7409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_reg_7414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_reg_7419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_reg_7424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_reg_7429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_s_reg_7434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_reg_7439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_reg_7444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_reg_7449 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_20_6_1_reg_7454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_reg_7459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_reg_7464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_reg_7469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_reg_7474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_reg_7479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_reg_7484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_reg_7489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_reg_7494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_s_reg_7499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_reg_7504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_reg_7509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_reg_7514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_reg_7519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_reg_7524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_reg_7529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_reg_7534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_reg_7539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_reg_7544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_reg_7549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_reg_7554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_reg_7559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_s_reg_7564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_reg_7569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_reg_7574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_1_reg_7579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal tmp_20_0_1_1_reg_7584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_1_reg_7589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_1_reg_7594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_1_reg_7599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_1_reg_7604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_1_reg_7609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_1_reg_7614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_1_reg_7619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_1_reg_7624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_1_reg_7629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_1_reg_7634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_1_reg_7639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_1_reg_7644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_1_reg_7649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_1_reg_7654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_1_reg_7659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_1_reg_7664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_1_reg_7669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_1_reg_7674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_1_reg_7679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_1_reg_7684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_1_reg_7689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_1_reg_7694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_1_reg_7699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_1_reg_7704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_1_reg_7709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_1_reg_7714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_1_reg_7719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_1_reg_7724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_1_reg_7729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_1_reg_7734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_1_reg_7739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_1_reg_7744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_1_reg_7749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_1_reg_7754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_1_reg_7759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_1_reg_7764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_1_reg_7769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_1_reg_7774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_1_reg_7779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_1_reg_7784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_1_reg_7789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_1_reg_7794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_1_reg_7799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_1_reg_7804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_1_reg_7809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_1_reg_7814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_1_reg_7819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_1_reg_7824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_1_reg_7829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_1_reg_7834 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_1_reg_7839 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_1_reg_7844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_1_reg_7849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_1_reg_7854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_1_reg_7859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_1_reg_7864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_1_reg_7869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_1_reg_7874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_1_reg_7879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_1_reg_7884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_1_reg_7889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_1_reg_7894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_1_reg_7899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_1_reg_7904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_1_reg_7909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_1_reg_7914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_1_reg_7919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_1_reg_7924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_1_reg_7929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_1_reg_7934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_1_reg_7939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_1_reg_7944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_1_reg_7949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_1_reg_7954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_1_reg_7959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_1_reg_7964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_1_reg_7969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_1_1_reg_7974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_1_reg_7979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_1_reg_7984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_1_reg_7989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_1_reg_7994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_1_reg_7999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_1_reg_8004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_1_reg_8009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_1_reg_8014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_1_reg_8019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_1_reg_8024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_1_reg_8029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_1_reg_8034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal tmp_20_7_1_1_reg_8039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_1_reg_8044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_1_reg_8049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_1_reg_8054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_1_reg_8059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_1_reg_8064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_1_reg_8069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_1_reg_8074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_1_reg_8079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_1_reg_8084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_1_reg_8089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_1_reg_8094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_2_reg_8099 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal tmp_20_0_1_2_reg_8104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_2_reg_8109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_2_reg_8114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_2_reg_8119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_2_reg_8124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_2_reg_8129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_2_reg_8134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_2_reg_8139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_2_reg_8144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_2_reg_8149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_2_reg_8154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_2_reg_8159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_2_reg_8164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_2_reg_8169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_2_reg_8174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_2_reg_8179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_2_reg_8184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_2_reg_8189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_2_reg_8194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_2_reg_8199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_2_reg_8204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_2_reg_8209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_2_reg_8214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_2_reg_8219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_2_reg_8224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_2_reg_8229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_2_reg_8234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_2_reg_8239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_2_reg_8244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_2_reg_8249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_2_reg_8254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_2_reg_8259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_2_reg_8264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_2_reg_8269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_2_reg_8274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_2_reg_8279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_2_reg_8284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_2_reg_8289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_2_reg_8294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_2_reg_8299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_2_reg_8304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_2_reg_8309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_2_reg_8314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_2_reg_8319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_2_reg_8324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_2_reg_8329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_2_reg_8334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_2_reg_8339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_2_reg_8344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_2_reg_8349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_2_reg_8354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_2_reg_8359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_2_reg_8364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_2_reg_8369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_2_reg_8374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_2_reg_8379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_2_reg_8384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_2_reg_8389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_2_reg_8394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_2_reg_8399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_2_reg_8404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_2_reg_8409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_2_reg_8414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_2_reg_8419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_2_reg_8424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_2_reg_8429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_2_reg_8434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_2_reg_8439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_2_reg_8444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_2_reg_8449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_2_reg_8454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_2_reg_8459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_2_reg_8464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_2_reg_8469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_2_reg_8474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_2_reg_8479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_2_reg_8484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_2_reg_8489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal tmp_20_6_1_2_reg_8494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_2_reg_8499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_2_reg_8504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_2_reg_8509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_2_reg_8514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_2_reg_8519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_2_reg_8524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_2_reg_8529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_2_reg_8534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_2_reg_8539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_2_reg_8544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_2_reg_8549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_2_reg_8554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_2_reg_8559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_2_reg_8564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_2_reg_8569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_2_reg_8574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_2_reg_8579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_2_reg_8584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_2_reg_8589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_2_reg_8594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_2_reg_8599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_2_reg_8604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_2_reg_8609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_2_reg_8614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage7_subdone : BOOLEAN;
signal ap_block_pp0_stage1_subdone : BOOLEAN;
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_phi_mux_indvar_flatten1_phi_fu_889_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage0 : BOOLEAN;
signal ap_phi_mux_i_phi_fu_900_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_indvar_flatten_phi_fu_912_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_mux_j_phi_fu_923_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_row_b_phi_fu_935_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_cast_fu_1775_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage5 : BOOLEAN;
signal tmp_8_cast_fu_1791_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_cast_fu_1864_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_335_cast_fu_1870_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_330_cast_fu_1910_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage6 : BOOLEAN;
signal tmp_336_cast_fu_1966_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_337_cast_fu_1972_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_cast_fu_1998_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage7 : BOOLEAN;
signal tmp_339_cast_fu_2004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_340_cast_fu_2010_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_341_cast_fu_2016_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_fu_2029_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage2 : BOOLEAN;
signal tmp_336_fu_2040_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_fu_2054_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage3 : BOOLEAN;
signal tmp_340_fu_2068_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_342_fu_2082_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage4 : BOOLEAN;
signal tmp_344_fu_2096_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_346_fu_2118_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_348_fu_2132_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_2620_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_89_fu_2690_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_129_fu_2760_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_169_fu_2830_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_209_fu_2900_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_249_fu_2970_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_289_fu_3040_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal ap_block_pp0_stage1 : BOOLEAN;
signal tmp_329_fu_3110_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_943_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1255_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1265_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1275_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1285_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1295_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1305_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1315_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1325_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1335_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1345_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1355_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1365_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1375_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1385_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1395_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1405_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1415_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1425_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1435_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1445_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1455_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1465_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1475_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1485_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_6_cast2_fu_1495_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal not_exitcond_flatten_fu_1590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_1600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_1622_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_mid2_cast_fu_1619_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1629_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_mid2_fu_1639_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_1672_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_50_fu_1683_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal p_shl_cast_fu_1679_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal p_shl1_cast_fu_1690_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_1_cast_fu_1700_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast_fu_1724_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_fu_1703_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_13_1_mid_fu_1712_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_1_mid2_fu_1738_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_cast1_fu_1718_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_1_mid2_cast_fu_1744_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_2_mid_fu_1763_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_2_mid2_fu_1814_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_mid1_fu_1824_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid_fu_1769_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid2_fu_1829_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_6_cast2_mid1_fu_1811_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_2_mid2_cast_fu_1820_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_3_mid2_cast_fu_1836_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_4_mid_fu_1886_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_fu_1926_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid_fu_1892_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid2_fu_1936_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid_fu_1898_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid2_fu_1946_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid_fu_1904_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid2_fu_1956_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_cast_fu_1932_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_5_mid2_cast_fu_1942_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_6_mid2_cast_fu_1952_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_7_mid2_cast_fu_1962_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_335_fu_2034_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_337_fu_2049_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_339_fu_2063_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_341_fu_2077_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_343_fu_2091_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_352_fu_2109_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_345_fu_2113_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_347_fu_2127_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_354_fu_2145_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_355_fu_2149_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_356_fu_2153_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_357_fu_2157_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_358_fu_2161_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_48_fu_2617_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_2614_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_2611_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_2608_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_fu_2605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_fu_2602_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_fu_2599_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_2596_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_fu_2593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_2590_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_2587_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_2584_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_2581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_88_fu_2687_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_2684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_82_fu_2681_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_2678_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_2675_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_fu_2672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_70_fu_2669_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_2666_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_64_fu_2663_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_2660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_58_fu_2657_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_fu_2654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_2651_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_128_fu_2757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_125_fu_2754_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_122_fu_2751_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_119_fu_2748_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_116_fu_2745_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_113_fu_2742_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_110_fu_2739_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_107_fu_2736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_104_fu_2733_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_2730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_fu_2727_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_2724_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_92_fu_2721_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_168_fu_2827_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_165_fu_2824_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_162_fu_2821_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_159_fu_2818_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_156_fu_2815_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_153_fu_2812_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_150_fu_2809_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_147_fu_2806_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_144_fu_2803_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_141_fu_2800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_138_fu_2797_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_135_fu_2794_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_132_fu_2791_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_208_fu_2897_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_205_fu_2894_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_202_fu_2891_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_199_fu_2888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_196_fu_2885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_193_fu_2882_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_190_fu_2879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_187_fu_2876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_184_fu_2873_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_181_fu_2870_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_178_fu_2867_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_175_fu_2864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_172_fu_2861_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_248_fu_2967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_245_fu_2964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_242_fu_2961_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_fu_2958_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_236_fu_2955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_fu_2952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_230_fu_2949_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_227_fu_2946_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_224_fu_2943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_221_fu_2940_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_218_fu_2937_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_215_fu_2934_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_212_fu_2931_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_288_fu_3037_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_285_fu_3034_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_282_fu_3031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_279_fu_3028_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_276_fu_3025_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_273_fu_3022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_270_fu_3019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_267_fu_3016_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_264_fu_3013_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_261_fu_3010_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_258_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_255_fu_3004_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_252_fu_3001_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_328_fu_3107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_325_fu_3104_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_322_fu_3101_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_319_fu_3098_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_316_fu_3095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_313_fu_3092_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_310_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_307_fu_3086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_304_fu_3083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_301_fu_3080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_298_fu_3077_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_295_fu_3074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_292_fu_3071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state76 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage2_subdone : BOOLEAN;
signal ap_block_pp0_stage3_subdone : BOOLEAN;
signal ap_block_pp0_stage4_subdone : BOOLEAN;
signal ap_block_pp0_stage5_subdone : BOOLEAN;
signal ap_block_pp0_stage6_subdone : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_943_p0,
din1 => grp_fu_943_p1,
ce => ap_const_logic_1,
dout => grp_fu_943_p2);
convolve_kernel_fbkb_U2 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_947_p0,
din1 => grp_fu_947_p1,
ce => ap_const_logic_1,
dout => grp_fu_947_p2);
convolve_kernel_fbkb_U3 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_951_p0,
din1 => grp_fu_951_p1,
ce => ap_const_logic_1,
dout => grp_fu_951_p2);
convolve_kernel_fbkb_U4 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_955_p0,
din1 => grp_fu_955_p1,
ce => ap_const_logic_1,
dout => grp_fu_955_p2);
convolve_kernel_fbkb_U5 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_959_p0,
din1 => grp_fu_959_p1,
ce => ap_const_logic_1,
dout => grp_fu_959_p2);
convolve_kernel_fbkb_U6 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_963_p0,
din1 => grp_fu_963_p1,
ce => ap_const_logic_1,
dout => grp_fu_963_p2);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_967_p0,
din1 => grp_fu_967_p1,
ce => ap_const_logic_1,
dout => grp_fu_967_p2);
convolve_kernel_fbkb_U8 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_971_p0,
din1 => grp_fu_971_p1,
ce => ap_const_logic_1,
dout => grp_fu_971_p2);
convolve_kernel_fbkb_U9 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_975_p0,
din1 => grp_fu_975_p1,
ce => ap_const_logic_1,
dout => grp_fu_975_p2);
convolve_kernel_fbkb_U10 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_979_p0,
din1 => grp_fu_979_p1,
ce => ap_const_logic_1,
dout => grp_fu_979_p2);
convolve_kernel_fbkb_U11 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_983_p0,
din1 => grp_fu_983_p1,
ce => ap_const_logic_1,
dout => grp_fu_983_p2);
convolve_kernel_fbkb_U12 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_987_p0,
din1 => grp_fu_987_p1,
ce => ap_const_logic_1,
dout => grp_fu_987_p2);
convolve_kernel_fbkb_U13 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_991_p0,
din1 => grp_fu_991_p1,
ce => ap_const_logic_1,
dout => grp_fu_991_p2);
convolve_kernel_fbkb_U14 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_995_p0,
din1 => grp_fu_995_p1,
ce => ap_const_logic_1,
dout => grp_fu_995_p2);
convolve_kernel_fbkb_U15 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_999_p0,
din1 => grp_fu_999_p1,
ce => ap_const_logic_1,
dout => grp_fu_999_p2);
convolve_kernel_fbkb_U16 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1003_p0,
din1 => grp_fu_1003_p1,
ce => ap_const_logic_1,
dout => grp_fu_1003_p2);
convolve_kernel_fbkb_U17 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1007_p0,
din1 => grp_fu_1007_p1,
ce => ap_const_logic_1,
dout => grp_fu_1007_p2);
convolve_kernel_fbkb_U18 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1011_p0,
din1 => grp_fu_1011_p1,
ce => ap_const_logic_1,
dout => grp_fu_1011_p2);
convolve_kernel_fbkb_U19 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1015_p0,
din1 => grp_fu_1015_p1,
ce => ap_const_logic_1,
dout => grp_fu_1015_p2);
convolve_kernel_fbkb_U20 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1019_p0,
din1 => grp_fu_1019_p1,
ce => ap_const_logic_1,
dout => grp_fu_1019_p2);
convolve_kernel_fbkb_U21 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1023_p0,
din1 => grp_fu_1023_p1,
ce => ap_const_logic_1,
dout => grp_fu_1023_p2);
convolve_kernel_fbkb_U22 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1027_p0,
din1 => grp_fu_1027_p1,
ce => ap_const_logic_1,
dout => grp_fu_1027_p2);
convolve_kernel_fbkb_U23 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1031_p0,
din1 => grp_fu_1031_p1,
ce => ap_const_logic_1,
dout => grp_fu_1031_p2);
convolve_kernel_fbkb_U24 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1035_p0,
din1 => grp_fu_1035_p1,
ce => ap_const_logic_1,
dout => grp_fu_1035_p2);
convolve_kernel_fbkb_U25 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1039_p0,
din1 => grp_fu_1039_p1,
ce => ap_const_logic_1,
dout => grp_fu_1039_p2);
convolve_kernel_fbkb_U26 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1043_p0,
din1 => grp_fu_1043_p1,
ce => ap_const_logic_1,
dout => grp_fu_1043_p2);
convolve_kernel_fbkb_U27 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1047_p0,
din1 => grp_fu_1047_p1,
ce => ap_const_logic_1,
dout => grp_fu_1047_p2);
convolve_kernel_fbkb_U28 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1051_p0,
din1 => grp_fu_1051_p1,
ce => ap_const_logic_1,
dout => grp_fu_1051_p2);
convolve_kernel_fbkb_U29 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1055_p0,
din1 => grp_fu_1055_p1,
ce => ap_const_logic_1,
dout => grp_fu_1055_p2);
convolve_kernel_fbkb_U30 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1059_p0,
din1 => grp_fu_1059_p1,
ce => ap_const_logic_1,
dout => grp_fu_1059_p2);
convolve_kernel_fbkb_U31 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1063_p0,
din1 => grp_fu_1063_p1,
ce => ap_const_logic_1,
dout => grp_fu_1063_p2);
convolve_kernel_fbkb_U32 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1067_p0,
din1 => grp_fu_1067_p1,
ce => ap_const_logic_1,
dout => grp_fu_1067_p2);
convolve_kernel_fbkb_U33 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1071_p0,
din1 => grp_fu_1071_p1,
ce => ap_const_logic_1,
dout => grp_fu_1071_p2);
convolve_kernel_fbkb_U34 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1075_p0,
din1 => grp_fu_1075_p1,
ce => ap_const_logic_1,
dout => grp_fu_1075_p2);
convolve_kernel_fbkb_U35 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1079_p0,
din1 => grp_fu_1079_p1,
ce => ap_const_logic_1,
dout => grp_fu_1079_p2);
convolve_kernel_fbkb_U36 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1083_p0,
din1 => grp_fu_1083_p1,
ce => ap_const_logic_1,
dout => grp_fu_1083_p2);
convolve_kernel_fbkb_U37 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1087_p0,
din1 => grp_fu_1087_p1,
ce => ap_const_logic_1,
dout => grp_fu_1087_p2);
convolve_kernel_fbkb_U38 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1091_p0,
din1 => grp_fu_1091_p1,
ce => ap_const_logic_1,
dout => grp_fu_1091_p2);
convolve_kernel_fbkb_U39 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1095_p0,
din1 => grp_fu_1095_p1,
ce => ap_const_logic_1,
dout => grp_fu_1095_p2);
convolve_kernel_fcud_U40 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1099_p0,
din1 => grp_fu_1099_p1,
ce => ap_const_logic_1,
dout => grp_fu_1099_p2);
convolve_kernel_fcud_U41 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1103_p0,
din1 => grp_fu_1103_p1,
ce => ap_const_logic_1,
dout => grp_fu_1103_p2);
convolve_kernel_fcud_U42 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1107_p0,
din1 => grp_fu_1107_p1,
ce => ap_const_logic_1,
dout => grp_fu_1107_p2);
convolve_kernel_fcud_U43 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1111_p0,
din1 => grp_fu_1111_p1,
ce => ap_const_logic_1,
dout => grp_fu_1111_p2);
convolve_kernel_fcud_U44 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1115_p0,
din1 => grp_fu_1115_p1,
ce => ap_const_logic_1,
dout => grp_fu_1115_p2);
convolve_kernel_fcud_U45 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1119_p0,
din1 => grp_fu_1119_p1,
ce => ap_const_logic_1,
dout => grp_fu_1119_p2);
convolve_kernel_fcud_U46 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1123_p0,
din1 => grp_fu_1123_p1,
ce => ap_const_logic_1,
dout => grp_fu_1123_p2);
convolve_kernel_fcud_U47 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1127_p0,
din1 => grp_fu_1127_p1,
ce => ap_const_logic_1,
dout => grp_fu_1127_p2);
convolve_kernel_fcud_U48 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1131_p0,
din1 => grp_fu_1131_p1,
ce => ap_const_logic_1,
dout => grp_fu_1131_p2);
convolve_kernel_fcud_U49 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1135_p0,
din1 => grp_fu_1135_p1,
ce => ap_const_logic_1,
dout => grp_fu_1135_p2);
convolve_kernel_fcud_U50 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1139_p0,
din1 => grp_fu_1139_p1,
ce => ap_const_logic_1,
dout => grp_fu_1139_p2);
convolve_kernel_fcud_U51 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1143_p0,
din1 => grp_fu_1143_p1,
ce => ap_const_logic_1,
dout => grp_fu_1143_p2);
convolve_kernel_fcud_U52 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1147_p0,
din1 => grp_fu_1147_p1,
ce => ap_const_logic_1,
dout => grp_fu_1147_p2);
convolve_kernel_fcud_U53 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1151_p0,
din1 => grp_fu_1151_p1,
ce => ap_const_logic_1,
dout => grp_fu_1151_p2);
convolve_kernel_fcud_U54 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1155_p0,
din1 => grp_fu_1155_p1,
ce => ap_const_logic_1,
dout => grp_fu_1155_p2);
convolve_kernel_fcud_U55 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1159_p0,
din1 => grp_fu_1159_p1,
ce => ap_const_logic_1,
dout => grp_fu_1159_p2);
convolve_kernel_fcud_U56 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1163_p0,
din1 => grp_fu_1163_p1,
ce => ap_const_logic_1,
dout => grp_fu_1163_p2);
convolve_kernel_fcud_U57 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1167_p0,
din1 => grp_fu_1167_p1,
ce => ap_const_logic_1,
dout => grp_fu_1167_p2);
convolve_kernel_fcud_U58 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1171_p0,
din1 => grp_fu_1171_p1,
ce => ap_const_logic_1,
dout => grp_fu_1171_p2);
convolve_kernel_fcud_U59 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1175_p0,
din1 => grp_fu_1175_p1,
ce => ap_const_logic_1,
dout => grp_fu_1175_p2);
convolve_kernel_fcud_U60 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1179_p0,
din1 => grp_fu_1179_p1,
ce => ap_const_logic_1,
dout => grp_fu_1179_p2);
convolve_kernel_fcud_U61 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1183_p0,
din1 => grp_fu_1183_p1,
ce => ap_const_logic_1,
dout => grp_fu_1183_p2);
convolve_kernel_fcud_U62 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1187_p0,
din1 => grp_fu_1187_p1,
ce => ap_const_logic_1,
dout => grp_fu_1187_p2);
convolve_kernel_fcud_U63 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1191_p0,
din1 => grp_fu_1191_p1,
ce => ap_const_logic_1,
dout => grp_fu_1191_p2);
convolve_kernel_fcud_U64 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1195_p0,
din1 => grp_fu_1195_p1,
ce => ap_const_logic_1,
dout => grp_fu_1195_p2);
convolve_kernel_fcud_U65 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1199_p0,
din1 => grp_fu_1199_p1,
ce => ap_const_logic_1,
dout => grp_fu_1199_p2);
convolve_kernel_fcud_U66 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1203_p0,
din1 => grp_fu_1203_p1,
ce => ap_const_logic_1,
dout => grp_fu_1203_p2);
convolve_kernel_fcud_U67 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1207_p0,
din1 => grp_fu_1207_p1,
ce => ap_const_logic_1,
dout => grp_fu_1207_p2);
convolve_kernel_fcud_U68 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1211_p0,
din1 => grp_fu_1211_p1,
ce => ap_const_logic_1,
dout => grp_fu_1211_p2);
convolve_kernel_fcud_U69 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1215_p0,
din1 => grp_fu_1215_p1,
ce => ap_const_logic_1,
dout => grp_fu_1215_p2);
convolve_kernel_fcud_U70 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1219_p0,
din1 => grp_fu_1219_p1,
ce => ap_const_logic_1,
dout => grp_fu_1219_p2);
convolve_kernel_fcud_U71 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1223_p0,
din1 => grp_fu_1223_p1,
ce => ap_const_logic_1,
dout => grp_fu_1223_p2);
convolve_kernel_fcud_U72 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1227_p0,
din1 => grp_fu_1227_p1,
ce => ap_const_logic_1,
dout => grp_fu_1227_p2);
convolve_kernel_fcud_U73 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1231_p0,
din1 => grp_fu_1231_p1,
ce => ap_const_logic_1,
dout => grp_fu_1231_p2);
convolve_kernel_fcud_U74 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1235_p0,
din1 => grp_fu_1235_p1,
ce => ap_const_logic_1,
dout => grp_fu_1235_p2);
convolve_kernel_fcud_U75 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1239_p0,
din1 => grp_fu_1239_p1,
ce => ap_const_logic_1,
dout => grp_fu_1239_p2);
convolve_kernel_fcud_U76 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1243_p0,
din1 => grp_fu_1243_p1,
ce => ap_const_logic_1,
dout => grp_fu_1243_p2);
convolve_kernel_fcud_U77 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1247_p0,
din1 => grp_fu_1247_p1,
ce => ap_const_logic_1,
dout => grp_fu_1247_p2);
convolve_kernel_fcud_U78 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1251_p0,
din1 => grp_fu_1251_p1,
ce => ap_const_logic_1,
dout => grp_fu_1251_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_896_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
i_reg_896 <= tmp_1_mid2_v_reg_3225;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_896 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten1_reg_885_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten1_reg_885 <= indvar_flatten_next1_reg_3180;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_885 <= ap_const_lv10_0;
end if;
end if;
end process;
indvar_flatten_reg_908_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_reg_908 <= indvar_flatten_next_reg_3252;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_908 <= ap_const_lv8_0;
end if;
end if;
end process;
j_reg_919_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
j_reg_919 <= tmp_5_mid2_reg_3286;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_919 <= ap_const_lv3_0;
end if;
end if;
end process;
row_b_reg_931_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
row_b_reg_931 <= row_b_1_reg_3276;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_931 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 <= exitcond_flatten1_reg_3176;
ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter1_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter2_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 <= tmp_19_1_0_1_reg_5244;
ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 <= tmp_19_1_10_1_reg_5344;
ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 <= tmp_19_1_11_1_reg_5354;
ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 <= tmp_19_1_12_1_reg_5364;
ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 <= tmp_19_1_1_1_reg_5254;
ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 <= tmp_19_1_2_1_reg_5264;
ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 <= tmp_19_1_3_1_reg_5274;
ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 <= tmp_19_1_4_1_reg_5284;
ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 <= tmp_19_1_5_1_reg_5294;
ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 <= tmp_19_1_6_1_reg_5304;
ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 <= tmp_19_1_7_1_reg_5314;
ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 <= tmp_19_1_8_1_reg_5324;
ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 <= tmp_19_1_9_1_reg_5334;
ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter3_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter4_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter5_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter6_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter7_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter8_exitcond_flatten1_reg_3176;
exitcond_flatten1_reg_3176 <= exitcond_flatten1_fu_1541_p2;
tmp_12_1_reg_3141 <= tmp_12_1_fu_1499_p2;
tmp_12_2_reg_3146 <= tmp_12_2_fu_1505_p2;
tmp_12_3_reg_3151 <= tmp_12_3_fu_1511_p2;
tmp_12_4_reg_3156 <= tmp_12_4_fu_1517_p2;
tmp_12_5_reg_3161 <= tmp_12_5_fu_1523_p2;
tmp_12_6_reg_3166 <= tmp_12_6_fu_1529_p2;
tmp_12_7_reg_3171 <= tmp_12_7_fu_1535_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
ap_reg_pp0_iter1_row_b_mid2_reg_3245 <= row_b_mid2_reg_3245;
ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 <= tmp_19_2_0_1_reg_5504;
ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 <= tmp_19_2_10_1_reg_5604;
ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 <= tmp_19_2_11_1_reg_5614;
ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 <= tmp_19_2_12_1_reg_5624;
ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 <= tmp_19_2_1_1_reg_5514;
ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 <= tmp_19_2_2_1_reg_5524;
ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 <= tmp_19_2_3_1_reg_5534;
ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 <= tmp_19_2_4_1_reg_5544;
ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 <= tmp_19_2_5_1_reg_5554;
ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 <= tmp_19_2_6_1_reg_5564;
ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 <= tmp_19_2_7_1_reg_5574;
ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 <= tmp_19_2_8_1_reg_5584;
ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 <= tmp_19_2_9_1_reg_5594;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3) <= bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3) <= bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 <= tmp_19_3_0_1_reg_5824;
ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 <= tmp_19_3_10_1_reg_5874;
ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 <= tmp_19_3_11_1_reg_5879;
ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 <= tmp_19_3_12_1_reg_5884;
ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 <= tmp_19_3_1_1_reg_5829;
ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 <= tmp_19_3_2_1_reg_5834;
ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 <= tmp_19_3_3_1_reg_5839;
ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 <= tmp_19_3_4_1_reg_5844;
ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 <= tmp_19_3_5_1_reg_5849;
ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 <= tmp_19_3_6_1_reg_5854;
ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 <= tmp_19_3_7_1_reg_5859;
ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 <= tmp_19_3_8_1_reg_5864;
ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 <= tmp_19_3_9_1_reg_5869;
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3) <= bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3) <= bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 <= tmp_19_4_0_1_reg_6149;
ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 <= tmp_19_4_10_1_reg_6199;
ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 <= tmp_19_4_11_1_reg_6204;
ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 <= tmp_19_4_12_1_reg_6209;
ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 <= tmp_19_4_1_1_reg_6154;
ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 <= tmp_19_4_2_1_reg_6159;
ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 <= tmp_19_4_3_1_reg_6164;
ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 <= tmp_19_4_4_1_reg_6169;
ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 <= tmp_19_4_5_1_reg_6174;
ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 <= tmp_19_4_6_1_reg_6179;
ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 <= tmp_19_4_7_1_reg_6184;
ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 <= tmp_19_4_8_1_reg_6189;
ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 <= tmp_19_4_9_1_reg_6194;
ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 <= tmp_19_5_0_1_reg_6214;
ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 <= tmp_19_5_10_1_reg_6264;
ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 <= tmp_19_5_11_1_reg_6269;
ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 <= tmp_19_5_12_1_reg_6274;
ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 <= tmp_19_5_1_1_reg_6219;
ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 <= tmp_19_5_2_1_reg_6224;
ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 <= tmp_19_5_3_1_reg_6229;
ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 <= tmp_19_5_4_1_reg_6234;
ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 <= tmp_19_5_5_1_reg_6239;
ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 <= tmp_19_5_6_1_reg_6244;
ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 <= tmp_19_5_7_1_reg_6249;
ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 <= tmp_19_5_8_1_reg_6254;
ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 <= tmp_19_5_9_1_reg_6259;
ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 <= tmp_19_6_0_1_reg_6284;
ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 <= tmp_19_6_10_1_reg_6384;
ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 <= tmp_19_6_11_1_reg_6394;
ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 <= tmp_19_6_12_1_reg_6404;
ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 <= tmp_19_6_1_1_reg_6294;
ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 <= tmp_19_6_2_1_reg_6304;
ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 <= tmp_19_6_3_1_reg_6314;
ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 <= tmp_19_6_4_1_reg_6324;
ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 <= tmp_19_6_5_1_reg_6334;
ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 <= tmp_19_6_6_1_reg_6344;
ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 <= tmp_19_6_7_1_reg_6354;
ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 <= tmp_19_6_8_1_reg_6364;
ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 <= tmp_19_6_9_1_reg_6374;
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3) <= bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3) <= bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 <= tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 <= tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 <= tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 <= tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 <= tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 <= tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 <= tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 <= tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 <= tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 <= tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 <= tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 <= tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 <= tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 <= tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 <= tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 <= tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 <= tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 <= tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 <= tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 <= tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 <= tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 <= tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 <= tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 <= tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 <= tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 <= tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 <= tmp_19_7_0_1_reg_6604;
ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 <= tmp_19_7_10_1_reg_6654;
ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 <= tmp_19_7_11_1_reg_6659;
ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 <= tmp_19_7_12_1_reg_6664;
ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 <= tmp_19_7_1_1_reg_6609;
ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 <= tmp_19_7_2_1_reg_6614;
ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 <= tmp_19_7_3_1_reg_6619;
ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 <= tmp_19_7_4_1_reg_6624;
ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 <= tmp_19_7_5_1_reg_6629;
ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 <= tmp_19_7_6_1_reg_6634;
ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 <= tmp_19_7_7_1_reg_6639;
ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 <= tmp_19_7_8_1_reg_6644;
ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 <= tmp_19_7_9_1_reg_6649;
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 <= ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 <= ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 <= ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 <= ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 <= ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 <= ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 <= ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 <= ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 <= ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 <= ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 <= ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 <= ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 <= ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 <= ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 <= ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 <= ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 <= ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 <= ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 <= ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 <= ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 <= ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 <= ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 <= ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 <= ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 <= ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 <= ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3) <= bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3) <= bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 <= tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 <= tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 <= tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 <= tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 <= tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 <= tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 <= tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 <= tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 <= tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 <= tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 <= tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 <= tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 <= tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 <= tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 <= tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 <= tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 <= tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 <= tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 <= tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 <= tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 <= tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 <= tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 <= tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 <= tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 <= tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 <= tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 <= tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 <= tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 <= tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 <= tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 <= tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 <= tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 <= tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 <= tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 <= tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 <= tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 <= tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 <= tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 <= tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 <= ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 <= ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 <= ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 <= ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 <= ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 <= ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 <= ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 <= ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 <= ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 <= ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 <= ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 <= ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 <= ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 <= ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 <= ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 <= ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 <= ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 <= ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 <= ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 <= ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 <= ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 <= ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 <= ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 <= ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 <= ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 <= ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 <= tmp_19_0_0_1_reg_4854;
ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 <= tmp_19_0_10_1_reg_4954;
ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 <= tmp_19_0_11_1_reg_4964;
ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 <= tmp_19_0_12_1_reg_4974;
ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 <= tmp_19_0_1_1_reg_4864;
ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 <= tmp_19_0_2_1_reg_4874;
ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 <= tmp_19_0_3_1_reg_4884;
ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 <= tmp_19_0_4_1_reg_4894;
ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 <= tmp_19_0_5_1_reg_4904;
ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 <= tmp_19_0_6_1_reg_4914;
ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 <= tmp_19_0_7_1_reg_4924;
ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 <= tmp_19_0_8_1_reg_4934;
ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 <= tmp_19_0_9_1_reg_4944;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 <= tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 <= tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 <= tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 <= tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 <= tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 <= tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 <= tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 <= tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 <= tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 <= tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 <= tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 <= tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 <= tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 <= tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 <= tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 <= tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 <= tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 <= tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 <= tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 <= tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 <= tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 <= tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 <= tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 <= tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 <= tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 <= tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 <= tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 <= tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 <= tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 <= tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 <= tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 <= tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 <= tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 <= tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 <= tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 <= tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 <= tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 <= tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 <= tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_load_1_reg_3931 <= bufi_0_Dout_B;
bufi_0_load_reg_3693 <= bufi_0_Dout_A;
bufi_1_load_1_reg_3948 <= bufi_1_Dout_B;
bufi_1_load_reg_3718 <= bufi_1_Dout_A;
bufi_2_load_1_reg_3965 <= bufi_2_Dout_B;
bufi_2_load_reg_3735 <= bufi_2_Dout_A;
bufw_0_load_1_reg_3710 <= bufw_0_Dout_B;
bufw_0_load_reg_3686 <= bufw_0_Dout_A;
bufw_10_load_1_reg_3894 <= bufw_10_Dout_B;
bufw_10_load_reg_3887 <= bufw_10_Dout_A;
bufw_11_load_1_reg_3909 <= bufw_11_Dout_B;
bufw_11_load_reg_3902 <= bufw_11_Dout_A;
bufw_12_load_1_reg_3924 <= bufw_12_Dout_B;
bufw_12_load_reg_3917 <= bufw_12_Dout_A;
bufw_1_load_1_reg_3759 <= bufw_1_Dout_B;
bufw_1_load_reg_3752 <= bufw_1_Dout_A;
bufw_2_load_1_reg_3774 <= bufw_2_Dout_B;
bufw_2_load_reg_3767 <= bufw_2_Dout_A;
bufw_3_load_1_reg_3789 <= bufw_3_Dout_B;
bufw_3_load_reg_3782 <= bufw_3_Dout_A;
bufw_4_load_1_reg_3804 <= bufw_4_Dout_B;
bufw_4_load_reg_3797 <= bufw_4_Dout_A;
bufw_5_load_1_reg_3819 <= bufw_5_Dout_B;
bufw_5_load_reg_3812 <= bufw_5_Dout_A;
bufw_6_load_1_reg_3834 <= bufw_6_Dout_B;
bufw_6_load_reg_3827 <= bufw_6_Dout_A;
bufw_7_load_1_reg_3849 <= bufw_7_Dout_B;
bufw_7_load_reg_3842 <= bufw_7_Dout_A;
bufw_8_load_1_reg_3864 <= bufw_8_Dout_B;
bufw_8_load_reg_3857 <= bufw_8_Dout_A;
bufw_9_load_1_reg_3879 <= bufw_9_Dout_B;
bufw_9_load_reg_3872 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_load_2_reg_4103 <= bufi_0_Dout_A;
bufi_0_load_3_reg_4154 <= bufi_0_Dout_B;
bufi_1_load_2_reg_4120 <= bufi_1_Dout_A;
bufi_1_load_3_reg_4171 <= bufi_1_Dout_B;
bufi_2_load_2_reg_4137 <= bufi_2_Dout_A;
bufi_2_load_3_reg_4188 <= bufi_2_Dout_B;
bufw_0_load_2_reg_4012 <= bufw_0_Dout_A;
bufw_10_load_2_reg_4082 <= bufw_10_Dout_A;
bufw_11_load_2_reg_4089 <= bufw_11_Dout_A;
bufw_12_load_2_reg_4096 <= bufw_12_Dout_A;
bufw_1_load_2_reg_4019 <= bufw_1_Dout_A;
bufw_2_load_2_reg_4026 <= bufw_2_Dout_A;
bufw_3_load_2_reg_4033 <= bufw_3_Dout_A;
bufw_4_load_2_reg_4040 <= bufw_4_Dout_A;
bufw_5_load_2_reg_4047 <= bufw_5_Dout_A;
bufw_6_load_2_reg_4054 <= bufw_6_Dout_A;
bufw_7_load_2_reg_4061 <= bufw_7_Dout_A;
bufw_8_load_2_reg_4068 <= bufw_8_Dout_A;
bufw_9_load_2_reg_4075 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
bufi_0_load_4_reg_4205 <= bufi_0_Dout_A;
bufi_0_load_5_reg_4256 <= bufi_0_Dout_B;
bufi_1_load_4_reg_4222 <= bufi_1_Dout_A;
bufi_1_load_5_reg_4273 <= bufi_1_Dout_B;
bufi_2_load_4_reg_4239 <= bufi_2_Dout_A;
bufi_2_load_5_reg_4290 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufi_0_load_6_reg_4327 <= bufi_0_Dout_A;
bufi_0_load_7_reg_4378 <= bufi_0_Dout_B;
bufi_1_load_6_reg_4344 <= bufi_1_Dout_A;
bufi_1_load_7_reg_4395 <= bufi_1_Dout_B;
bufi_2_load_6_reg_4361 <= bufi_2_Dout_A;
bufi_2_load_7_reg_4412 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_addr_1_reg_4322(7 downto 3) <= tmp_336_fu_2040_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_reg_4317(7 downto 3) <= tmp_334_fu_2029_p1(8 - 1 downto 0)(7 downto 3);
tmp_333_reg_4307(7 downto 3) <= tmp_333_fu_2022_p3(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_addr_2_reg_4429(7 downto 3) <= tmp_338_fu_2054_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_3_reg_4434(7 downto 3) <= tmp_340_fu_2068_p3(8 - 1 downto 0)(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_addr_4_reg_4439(7 downto 3) <= tmp_342_fu_2082_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_5_reg_4444(7 downto 3) <= tmp_344_fu_2096_p3(8 - 1 downto 0)(7 downto 3);
tmp_350_reg_4449 <= tmp_350_fu_2105_p1;
tmp_352_reg_4514 <= tmp_352_fu_2109_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_addr_6_reg_4579(7 downto 3) <= tmp_346_fu_2118_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_7_reg_4584(7 downto 3) <= tmp_348_fu_2132_p3(8 - 1 downto 0)(7 downto 3);
tmp_353_reg_4589 <= tmp_353_fu_2141_p1;
tmp_354_reg_4654 <= tmp_354_fu_2145_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
exitcond_flatten_reg_3190 <= exitcond_flatten_fu_1559_p2;
i_1_reg_3185 <= i_1_fu_1553_p2;
indvar_flatten_op_reg_3211 <= indvar_flatten_op_fu_1571_p2;
tmp_5_reg_3206 <= tmp_5_fu_1565_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_next1_reg_3180 <= indvar_flatten_next1_fu_1547_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next_reg_3252 <= indvar_flatten_next_fu_1613_p3;
tmp_1_mid2_v_reg_3225 <= tmp_1_mid2_v_fu_1584_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
j_1_reg_3264 <= j_1_fu_1642_p2;
tmp_1_reg_3257 <= tmp_1_fu_1633_p2;
tmp_s_reg_3270 <= tmp_s_fu_1647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
j_mid_reg_3216 <= j_mid_fu_1577_p3;
row_b_mid2_reg_3245 <= row_b_mid2_fu_1605_p3;
tmp_7_mid_reg_3233 <= tmp_7_mid_fu_1595_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
row_b_1_reg_3276 <= row_b_1_fu_1652_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_102_reg_4609 <= grp_fu_1285_p1(159 downto 128);
tmp_105_reg_4614 <= grp_fu_1295_p1(191 downto 160);
tmp_108_reg_4619 <= grp_fu_1305_p1(223 downto 192);
tmp_111_reg_4624 <= grp_fu_1315_p1(255 downto 224);
tmp_114_reg_4629 <= grp_fu_1325_p1(287 downto 256);
tmp_117_reg_4634 <= grp_fu_1335_p1(319 downto 288);
tmp_120_reg_4639 <= grp_fu_1345_p1(351 downto 320);
tmp_123_reg_4644 <= grp_fu_1355_p1(383 downto 352);
tmp_126_reg_4649 <= grp_fu_1365_p1(415 downto 384);
tmp_133_reg_4659 <= grp_fu_1375_p1(63 downto 32);
tmp_136_reg_4664 <= grp_fu_1385_p1(95 downto 64);
tmp_139_reg_4669 <= grp_fu_1395_p1(127 downto 96);
tmp_142_reg_4674 <= grp_fu_1405_p1(159 downto 128);
tmp_145_reg_4679 <= grp_fu_1415_p1(191 downto 160);
tmp_148_reg_4684 <= grp_fu_1425_p1(223 downto 192);
tmp_151_reg_4689 <= grp_fu_1435_p1(255 downto 224);
tmp_154_reg_4694 <= grp_fu_1445_p1(287 downto 256);
tmp_157_reg_4699 <= grp_fu_1455_p1(319 downto 288);
tmp_160_reg_4704 <= grp_fu_1465_p1(351 downto 320);
tmp_163_reg_4709 <= grp_fu_1475_p1(383 downto 352);
tmp_166_reg_4714 <= grp_fu_1485_p1(415 downto 384);
tmp_93_reg_4594 <= grp_fu_1255_p1(63 downto 32);
tmp_96_reg_4599 <= grp_fu_1265_p1(95 downto 64);
tmp_99_reg_4604 <= grp_fu_1275_p1(127 downto 96);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_12_1_mid1_reg_3294 <= tmp_12_1_mid1_fu_1667_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_12_2_mid1_reg_3331 <= tmp_12_2_mid1_fu_1748_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_12_4_mid1_reg_3481 <= tmp_12_4_mid1_fu_1840_p2;
tmp_12_5_mid1_reg_3486 <= tmp_12_5_mid1_fu_1846_p2;
tmp_12_6_mid1_reg_3491 <= tmp_12_6_mid1_fu_1852_p2;
tmp_12_7_mid1_reg_3496 <= tmp_12_7_mid1_fu_1858_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_130_reg_3336 <= tmp_130_fu_1753_p2;
tmp_170_reg_3341 <= tmp_170_fu_1758_p2;
tmp_3_reg_3311 <= tmp_3_fu_1706_p2;
tmp_5_mid2_cast2_reg_3316(2 downto 0) <= tmp_5_mid2_cast2_fu_1721_p1(2 downto 0);
tmp_6_reg_3321 <= tmp_6_fu_1727_p2;
tmp_8_reg_3326 <= tmp_8_fu_1732_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_13_reg_4454 <= grp_fu_1255_p1(63 downto 32);
tmp_16_reg_4459 <= grp_fu_1265_p1(95 downto 64);
tmp_19_reg_4464 <= grp_fu_1275_p1(127 downto 96);
tmp_22_reg_4469 <= grp_fu_1285_p1(159 downto 128);
tmp_25_reg_4474 <= grp_fu_1295_p1(191 downto 160);
tmp_28_reg_4479 <= grp_fu_1305_p1(223 downto 192);
tmp_31_reg_4484 <= grp_fu_1315_p1(255 downto 224);
tmp_34_reg_4489 <= grp_fu_1325_p1(287 downto 256);
tmp_37_reg_4494 <= grp_fu_1335_p1(319 downto 288);
tmp_40_reg_4499 <= grp_fu_1345_p1(351 downto 320);
tmp_43_reg_4504 <= grp_fu_1355_p1(383 downto 352);
tmp_46_reg_4509 <= grp_fu_1365_p1(415 downto 384);
tmp_53_reg_4519 <= grp_fu_1375_p1(63 downto 32);
tmp_56_reg_4524 <= grp_fu_1385_p1(95 downto 64);
tmp_59_reg_4529 <= grp_fu_1395_p1(127 downto 96);
tmp_62_reg_4534 <= grp_fu_1405_p1(159 downto 128);
tmp_65_reg_4539 <= grp_fu_1415_p1(191 downto 160);
tmp_68_reg_4544 <= grp_fu_1425_p1(223 downto 192);
tmp_71_reg_4549 <= grp_fu_1435_p1(255 downto 224);
tmp_74_reg_4554 <= grp_fu_1445_p1(287 downto 256);
tmp_77_reg_4559 <= grp_fu_1455_p1(319 downto 288);
tmp_80_reg_4564 <= grp_fu_1465_p1(351 downto 320);
tmp_83_reg_4569 <= grp_fu_1475_p1(383 downto 352);
tmp_86_reg_4574 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_173_reg_4724 <= grp_fu_1255_p1(63 downto 32);
tmp_176_reg_4729 <= grp_fu_1265_p1(95 downto 64);
tmp_179_reg_4734 <= grp_fu_1275_p1(127 downto 96);
tmp_182_reg_4739 <= grp_fu_1285_p1(159 downto 128);
tmp_185_reg_4744 <= grp_fu_1295_p1(191 downto 160);
tmp_188_reg_4749 <= grp_fu_1305_p1(223 downto 192);
tmp_191_reg_4754 <= grp_fu_1315_p1(255 downto 224);
tmp_194_reg_4759 <= grp_fu_1325_p1(287 downto 256);
tmp_197_reg_4764 <= grp_fu_1335_p1(319 downto 288);
tmp_200_reg_4769 <= grp_fu_1345_p1(351 downto 320);
tmp_203_reg_4774 <= grp_fu_1355_p1(383 downto 352);
tmp_206_reg_4779 <= grp_fu_1365_p1(415 downto 384);
tmp_213_reg_4789 <= grp_fu_1375_p1(63 downto 32);
tmp_216_reg_4794 <= grp_fu_1385_p1(95 downto 64);
tmp_219_reg_4799 <= grp_fu_1395_p1(127 downto 96);
tmp_222_reg_4804 <= grp_fu_1405_p1(159 downto 128);
tmp_225_reg_4809 <= grp_fu_1415_p1(191 downto 160);
tmp_228_reg_4814 <= grp_fu_1425_p1(223 downto 192);
tmp_231_reg_4819 <= grp_fu_1435_p1(255 downto 224);
tmp_234_reg_4824 <= grp_fu_1445_p1(287 downto 256);
tmp_237_reg_4829 <= grp_fu_1455_p1(319 downto 288);
tmp_240_reg_4834 <= grp_fu_1465_p1(351 downto 320);
tmp_243_reg_4839 <= grp_fu_1475_p1(383 downto 352);
tmp_246_reg_4844 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_19_0_0_1_reg_4854 <= grp_fu_1103_p2;
tmp_19_0_10_1_reg_4954 <= grp_fu_1183_p2;
tmp_19_0_10_reg_4959 <= grp_fu_1187_p2;
tmp_19_0_11_1_reg_4964 <= grp_fu_1191_p2;
tmp_19_0_11_reg_4969 <= grp_fu_1195_p2;
tmp_19_0_12_1_reg_4974 <= grp_fu_1199_p2;
tmp_19_0_1_1_reg_4864 <= grp_fu_1111_p2;
tmp_19_0_1_reg_4859 <= grp_fu_1107_p2;
tmp_19_0_2_1_reg_4874 <= grp_fu_1119_p2;
tmp_19_0_2_reg_4869 <= grp_fu_1115_p2;
tmp_19_0_3_1_reg_4884 <= grp_fu_1127_p2;
tmp_19_0_3_reg_4879 <= grp_fu_1123_p2;
tmp_19_0_4_1_reg_4894 <= grp_fu_1135_p2;
tmp_19_0_4_reg_4889 <= grp_fu_1131_p2;
tmp_19_0_5_1_reg_4904 <= grp_fu_1143_p2;
tmp_19_0_5_reg_4899 <= grp_fu_1139_p2;
tmp_19_0_6_1_reg_4914 <= grp_fu_1151_p2;
tmp_19_0_6_reg_4909 <= grp_fu_1147_p2;
tmp_19_0_7_1_reg_4924 <= grp_fu_1159_p2;
tmp_19_0_7_reg_4919 <= grp_fu_1155_p2;
tmp_19_0_8_1_reg_4934 <= grp_fu_1167_p2;
tmp_19_0_8_reg_4929 <= grp_fu_1163_p2;
tmp_19_0_9_1_reg_4944 <= grp_fu_1175_p2;
tmp_19_0_9_reg_4939 <= grp_fu_1171_p2;
tmp_19_0_s_reg_4949 <= grp_fu_1179_p2;
tmp_19_1_10_reg_5034 <= grp_fu_1247_p2;
tmp_19_1_11_reg_5039 <= grp_fu_1251_p2;
tmp_19_1_1_reg_4984 <= grp_fu_1207_p2;
tmp_19_1_2_reg_4989 <= grp_fu_1211_p2;
tmp_19_1_3_reg_4994 <= grp_fu_1215_p2;
tmp_19_1_4_reg_4999 <= grp_fu_1219_p2;
tmp_19_1_5_reg_5004 <= grp_fu_1223_p2;
tmp_19_1_6_reg_5009 <= grp_fu_1227_p2;
tmp_19_1_7_reg_5014 <= grp_fu_1231_p2;
tmp_19_1_8_reg_5019 <= grp_fu_1235_p2;
tmp_19_1_9_reg_5024 <= grp_fu_1239_p2;
tmp_19_1_reg_4979 <= grp_fu_1203_p2;
tmp_19_1_s_reg_5029 <= grp_fu_1243_p2;
tmp_253_reg_5049 <= grp_fu_1255_p1(63 downto 32);
tmp_256_reg_5054 <= grp_fu_1265_p1(95 downto 64);
tmp_259_reg_5059 <= grp_fu_1275_p1(127 downto 96);
tmp_262_reg_5064 <= grp_fu_1285_p1(159 downto 128);
tmp_265_reg_5069 <= grp_fu_1295_p1(191 downto 160);
tmp_268_reg_5074 <= grp_fu_1305_p1(223 downto 192);
tmp_271_reg_5079 <= grp_fu_1315_p1(255 downto 224);
tmp_274_reg_5084 <= grp_fu_1325_p1(287 downto 256);
tmp_277_reg_5089 <= grp_fu_1335_p1(319 downto 288);
tmp_280_reg_5094 <= grp_fu_1345_p1(351 downto 320);
tmp_283_reg_5099 <= grp_fu_1355_p1(383 downto 352);
tmp_286_reg_5104 <= grp_fu_1365_p1(415 downto 384);
tmp_293_reg_5114 <= grp_fu_1375_p1(63 downto 32);
tmp_296_reg_5119 <= grp_fu_1385_p1(95 downto 64);
tmp_299_reg_5124 <= grp_fu_1395_p1(127 downto 96);
tmp_302_reg_5129 <= grp_fu_1405_p1(159 downto 128);
tmp_305_reg_5134 <= grp_fu_1415_p1(191 downto 160);
tmp_308_reg_5139 <= grp_fu_1425_p1(223 downto 192);
tmp_311_reg_5144 <= grp_fu_1435_p1(255 downto 224);
tmp_314_reg_5149 <= grp_fu_1445_p1(287 downto 256);
tmp_317_reg_5154 <= grp_fu_1455_p1(319 downto 288);
tmp_320_reg_5159 <= grp_fu_1465_p1(351 downto 320);
tmp_323_reg_5164 <= grp_fu_1475_p1(383 downto 352);
tmp_326_reg_5169 <= grp_fu_1485_p1(415 downto 384);
tmp_349_reg_4849 <= grp_fu_1099_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_0_0_2_reg_6474 <= grp_fu_1099_p2;
tmp_19_0_10_2_reg_6524 <= grp_fu_1139_p2;
tmp_19_0_11_2_reg_6529 <= grp_fu_1143_p2;
tmp_19_0_12_2_reg_6534 <= grp_fu_1147_p2;
tmp_19_0_1_2_reg_6479 <= grp_fu_1103_p2;
tmp_19_0_2_2_reg_6484 <= grp_fu_1107_p2;
tmp_19_0_3_2_reg_6489 <= grp_fu_1111_p2;
tmp_19_0_4_2_reg_6494 <= grp_fu_1115_p2;
tmp_19_0_5_2_reg_6499 <= grp_fu_1119_p2;
tmp_19_0_6_2_reg_6504 <= grp_fu_1123_p2;
tmp_19_0_7_2_reg_6509 <= grp_fu_1127_p2;
tmp_19_0_8_2_reg_6514 <= grp_fu_1131_p2;
tmp_19_0_9_2_reg_6519 <= grp_fu_1135_p2;
tmp_19_1_0_2_reg_6539 <= grp_fu_1151_p2;
tmp_19_1_10_2_reg_6589 <= grp_fu_1191_p2;
tmp_19_1_11_2_reg_6594 <= grp_fu_1195_p2;
tmp_19_1_12_2_reg_6599 <= grp_fu_1199_p2;
tmp_19_1_1_2_reg_6544 <= grp_fu_1155_p2;
tmp_19_1_2_2_reg_6549 <= grp_fu_1159_p2;
tmp_19_1_3_2_reg_6554 <= grp_fu_1163_p2;
tmp_19_1_4_2_reg_6559 <= grp_fu_1167_p2;
tmp_19_1_5_2_reg_6564 <= grp_fu_1171_p2;
tmp_19_1_6_2_reg_6569 <= grp_fu_1175_p2;
tmp_19_1_7_2_reg_6574 <= grp_fu_1179_p2;
tmp_19_1_8_2_reg_6579 <= grp_fu_1183_p2;
tmp_19_1_9_2_reg_6584 <= grp_fu_1187_p2;
tmp_19_7_0_1_reg_6604 <= grp_fu_1203_p2;
tmp_19_7_10_1_reg_6654 <= grp_fu_1243_p2;
tmp_19_7_11_1_reg_6659 <= grp_fu_1247_p2;
tmp_19_7_12_1_reg_6664 <= grp_fu_1251_p2;
tmp_19_7_1_1_reg_6609 <= grp_fu_1207_p2;
tmp_19_7_2_1_reg_6614 <= grp_fu_1211_p2;
tmp_19_7_3_1_reg_6619 <= grp_fu_1215_p2;
tmp_19_7_4_1_reg_6624 <= grp_fu_1219_p2;
tmp_19_7_5_1_reg_6629 <= grp_fu_1223_p2;
tmp_19_7_6_1_reg_6634 <= grp_fu_1227_p2;
tmp_19_7_7_1_reg_6639 <= grp_fu_1231_p2;
tmp_19_7_8_1_reg_6644 <= grp_fu_1235_p2;
tmp_19_7_9_1_reg_6649 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_1_0_1_reg_5244 <= grp_fu_1099_p2;
tmp_19_1_10_1_reg_5344 <= grp_fu_1139_p2;
tmp_19_1_11_1_reg_5354 <= grp_fu_1143_p2;
tmp_19_1_12_1_reg_5364 <= grp_fu_1147_p2;
tmp_19_1_1_1_reg_5254 <= grp_fu_1103_p2;
tmp_19_1_2_1_reg_5264 <= grp_fu_1107_p2;
tmp_19_1_3_1_reg_5274 <= grp_fu_1111_p2;
tmp_19_1_4_1_reg_5284 <= grp_fu_1115_p2;
tmp_19_1_5_1_reg_5294 <= grp_fu_1119_p2;
tmp_19_1_6_1_reg_5304 <= grp_fu_1123_p2;
tmp_19_1_7_1_reg_5314 <= grp_fu_1127_p2;
tmp_19_1_8_1_reg_5324 <= grp_fu_1131_p2;
tmp_19_1_9_1_reg_5334 <= grp_fu_1135_p2;
tmp_19_2_10_reg_5424 <= grp_fu_1195_p2;
tmp_19_2_11_reg_5429 <= grp_fu_1199_p2;
tmp_19_2_1_reg_5374 <= grp_fu_1155_p2;
tmp_19_2_2_reg_5379 <= grp_fu_1159_p2;
tmp_19_2_3_reg_5384 <= grp_fu_1163_p2;
tmp_19_2_4_reg_5389 <= grp_fu_1167_p2;
tmp_19_2_5_reg_5394 <= grp_fu_1171_p2;
tmp_19_2_6_reg_5399 <= grp_fu_1175_p2;
tmp_19_2_7_reg_5404 <= grp_fu_1179_p2;
tmp_19_2_8_reg_5409 <= grp_fu_1183_p2;
tmp_19_2_9_reg_5414 <= grp_fu_1187_p2;
tmp_19_2_reg_5369 <= grp_fu_1151_p2;
tmp_19_2_s_reg_5419 <= grp_fu_1191_p2;
tmp_19_3_10_reg_5489 <= grp_fu_1247_p2;
tmp_19_3_11_reg_5494 <= grp_fu_1251_p2;
tmp_19_3_1_reg_5439 <= grp_fu_1207_p2;
tmp_19_3_2_reg_5444 <= grp_fu_1211_p2;
tmp_19_3_3_reg_5449 <= grp_fu_1215_p2;
tmp_19_3_4_reg_5454 <= grp_fu_1219_p2;
tmp_19_3_5_reg_5459 <= grp_fu_1223_p2;
tmp_19_3_6_reg_5464 <= grp_fu_1227_p2;
tmp_19_3_7_reg_5469 <= grp_fu_1231_p2;
tmp_19_3_8_reg_5474 <= grp_fu_1235_p2;
tmp_19_3_9_reg_5479 <= grp_fu_1239_p2;
tmp_19_3_reg_5434 <= grp_fu_1203_p2;
tmp_19_3_s_reg_5484 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_1_reg_5504 <= grp_fu_1099_p2;
tmp_19_2_10_1_reg_5604 <= grp_fu_1139_p2;
tmp_19_2_11_1_reg_5614 <= grp_fu_1143_p2;
tmp_19_2_12_1_reg_5624 <= grp_fu_1147_p2;
tmp_19_2_1_1_reg_5514 <= grp_fu_1103_p2;
tmp_19_2_2_1_reg_5524 <= grp_fu_1107_p2;
tmp_19_2_3_1_reg_5534 <= grp_fu_1111_p2;
tmp_19_2_4_1_reg_5544 <= grp_fu_1115_p2;
tmp_19_2_5_1_reg_5554 <= grp_fu_1119_p2;
tmp_19_2_6_1_reg_5564 <= grp_fu_1123_p2;
tmp_19_2_7_1_reg_5574 <= grp_fu_1127_p2;
tmp_19_2_8_1_reg_5584 <= grp_fu_1131_p2;
tmp_19_2_9_1_reg_5594 <= grp_fu_1135_p2;
tmp_19_4_10_reg_5749 <= grp_fu_1195_p2;
tmp_19_4_11_reg_5754 <= grp_fu_1199_p2;
tmp_19_4_1_reg_5699 <= grp_fu_1155_p2;
tmp_19_4_2_reg_5704 <= grp_fu_1159_p2;
tmp_19_4_3_reg_5709 <= grp_fu_1163_p2;
tmp_19_4_4_reg_5714 <= grp_fu_1167_p2;
tmp_19_4_5_reg_5719 <= grp_fu_1171_p2;
tmp_19_4_6_reg_5724 <= grp_fu_1175_p2;
tmp_19_4_7_reg_5729 <= grp_fu_1179_p2;
tmp_19_4_8_reg_5734 <= grp_fu_1183_p2;
tmp_19_4_9_reg_5739 <= grp_fu_1187_p2;
tmp_19_4_reg_5694 <= grp_fu_1151_p2;
tmp_19_4_s_reg_5744 <= grp_fu_1191_p2;
tmp_19_5_10_reg_5814 <= grp_fu_1247_p2;
tmp_19_5_11_reg_5819 <= grp_fu_1251_p2;
tmp_19_5_1_reg_5764 <= grp_fu_1207_p2;
tmp_19_5_2_reg_5769 <= grp_fu_1211_p2;
tmp_19_5_3_reg_5774 <= grp_fu_1215_p2;
tmp_19_5_4_reg_5779 <= grp_fu_1219_p2;
tmp_19_5_5_reg_5784 <= grp_fu_1223_p2;
tmp_19_5_6_reg_5789 <= grp_fu_1227_p2;
tmp_19_5_7_reg_5794 <= grp_fu_1231_p2;
tmp_19_5_8_reg_5799 <= grp_fu_1235_p2;
tmp_19_5_9_reg_5804 <= grp_fu_1239_p2;
tmp_19_5_reg_5759 <= grp_fu_1203_p2;
tmp_19_5_s_reg_5809 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_2_reg_6669 <= grp_fu_1099_p2;
tmp_19_2_10_2_reg_6719 <= grp_fu_1139_p2;
tmp_19_2_11_2_reg_6724 <= grp_fu_1143_p2;
tmp_19_2_12_2_reg_6729 <= grp_fu_1147_p2;
tmp_19_2_1_2_reg_6674 <= grp_fu_1103_p2;
tmp_19_2_2_2_reg_6679 <= grp_fu_1107_p2;
tmp_19_2_3_2_reg_6684 <= grp_fu_1111_p2;
tmp_19_2_4_2_reg_6689 <= grp_fu_1115_p2;
tmp_19_2_5_2_reg_6694 <= grp_fu_1119_p2;
tmp_19_2_6_2_reg_6699 <= grp_fu_1123_p2;
tmp_19_2_7_2_reg_6704 <= grp_fu_1127_p2;
tmp_19_2_8_2_reg_6709 <= grp_fu_1131_p2;
tmp_19_2_9_2_reg_6714 <= grp_fu_1135_p2;
tmp_19_3_0_2_reg_6734 <= grp_fu_1151_p2;
tmp_19_3_10_2_reg_6784 <= grp_fu_1191_p2;
tmp_19_3_11_2_reg_6789 <= grp_fu_1195_p2;
tmp_19_3_12_2_reg_6794 <= grp_fu_1199_p2;
tmp_19_3_1_2_reg_6739 <= grp_fu_1155_p2;
tmp_19_3_2_2_reg_6744 <= grp_fu_1159_p2;
tmp_19_3_3_2_reg_6749 <= grp_fu_1163_p2;
tmp_19_3_4_2_reg_6754 <= grp_fu_1167_p2;
tmp_19_3_5_2_reg_6759 <= grp_fu_1171_p2;
tmp_19_3_6_2_reg_6764 <= grp_fu_1175_p2;
tmp_19_3_7_2_reg_6769 <= grp_fu_1179_p2;
tmp_19_3_8_2_reg_6774 <= grp_fu_1183_p2;
tmp_19_3_9_2_reg_6779 <= grp_fu_1187_p2;
tmp_19_4_0_2_reg_6799 <= grp_fu_1203_p2;
tmp_19_4_10_2_reg_6849 <= grp_fu_1243_p2;
tmp_19_4_11_2_reg_6854 <= grp_fu_1247_p2;
tmp_19_4_12_2_reg_6859 <= grp_fu_1251_p2;
tmp_19_4_1_2_reg_6804 <= grp_fu_1207_p2;
tmp_19_4_2_2_reg_6809 <= grp_fu_1211_p2;
tmp_19_4_3_2_reg_6814 <= grp_fu_1215_p2;
tmp_19_4_4_2_reg_6819 <= grp_fu_1219_p2;
tmp_19_4_5_2_reg_6824 <= grp_fu_1223_p2;
tmp_19_4_6_2_reg_6829 <= grp_fu_1227_p2;
tmp_19_4_7_2_reg_6834 <= grp_fu_1231_p2;
tmp_19_4_8_2_reg_6839 <= grp_fu_1235_p2;
tmp_19_4_9_2_reg_6844 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_3_0_1_reg_5824 <= grp_fu_1099_p2;
tmp_19_3_10_1_reg_5874 <= grp_fu_1139_p2;
tmp_19_3_11_1_reg_5879 <= grp_fu_1143_p2;
tmp_19_3_12_1_reg_5884 <= grp_fu_1147_p2;
tmp_19_3_1_1_reg_5829 <= grp_fu_1103_p2;
tmp_19_3_2_1_reg_5834 <= grp_fu_1107_p2;
tmp_19_3_3_1_reg_5839 <= grp_fu_1111_p2;
tmp_19_3_4_1_reg_5844 <= grp_fu_1115_p2;
tmp_19_3_5_1_reg_5849 <= grp_fu_1119_p2;
tmp_19_3_6_1_reg_5854 <= grp_fu_1123_p2;
tmp_19_3_7_1_reg_5859 <= grp_fu_1127_p2;
tmp_19_3_8_1_reg_5864 <= grp_fu_1131_p2;
tmp_19_3_9_1_reg_5869 <= grp_fu_1135_p2;
tmp_19_6_10_reg_6074 <= grp_fu_1195_p2;
tmp_19_6_11_reg_6079 <= grp_fu_1199_p2;
tmp_19_6_1_reg_6024 <= grp_fu_1155_p2;
tmp_19_6_2_reg_6029 <= grp_fu_1159_p2;
tmp_19_6_3_reg_6034 <= grp_fu_1163_p2;
tmp_19_6_4_reg_6039 <= grp_fu_1167_p2;
tmp_19_6_5_reg_6044 <= grp_fu_1171_p2;
tmp_19_6_6_reg_6049 <= grp_fu_1175_p2;
tmp_19_6_7_reg_6054 <= grp_fu_1179_p2;
tmp_19_6_8_reg_6059 <= grp_fu_1183_p2;
tmp_19_6_9_reg_6064 <= grp_fu_1187_p2;
tmp_19_6_reg_6019 <= grp_fu_1151_p2;
tmp_19_6_s_reg_6069 <= grp_fu_1191_p2;
tmp_19_7_10_reg_6139 <= grp_fu_1247_p2;
tmp_19_7_11_reg_6144 <= grp_fu_1251_p2;
tmp_19_7_1_reg_6089 <= grp_fu_1207_p2;
tmp_19_7_2_reg_6094 <= grp_fu_1211_p2;
tmp_19_7_3_reg_6099 <= grp_fu_1215_p2;
tmp_19_7_4_reg_6104 <= grp_fu_1219_p2;
tmp_19_7_5_reg_6109 <= grp_fu_1223_p2;
tmp_19_7_6_reg_6114 <= grp_fu_1227_p2;
tmp_19_7_7_reg_6119 <= grp_fu_1231_p2;
tmp_19_7_8_reg_6124 <= grp_fu_1235_p2;
tmp_19_7_9_reg_6129 <= grp_fu_1239_p2;
tmp_19_7_reg_6084 <= grp_fu_1203_p2;
tmp_19_7_s_reg_6134 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_4_0_1_reg_6149 <= grp_fu_1099_p2;
tmp_19_4_10_1_reg_6199 <= grp_fu_1139_p2;
tmp_19_4_11_1_reg_6204 <= grp_fu_1143_p2;
tmp_19_4_12_1_reg_6209 <= grp_fu_1147_p2;
tmp_19_4_1_1_reg_6154 <= grp_fu_1103_p2;
tmp_19_4_2_1_reg_6159 <= grp_fu_1107_p2;
tmp_19_4_3_1_reg_6164 <= grp_fu_1111_p2;
tmp_19_4_4_1_reg_6169 <= grp_fu_1115_p2;
tmp_19_4_5_1_reg_6174 <= grp_fu_1119_p2;
tmp_19_4_6_1_reg_6179 <= grp_fu_1123_p2;
tmp_19_4_7_1_reg_6184 <= grp_fu_1127_p2;
tmp_19_4_8_1_reg_6189 <= grp_fu_1131_p2;
tmp_19_4_9_1_reg_6194 <= grp_fu_1135_p2;
tmp_19_5_0_1_reg_6214 <= grp_fu_1151_p2;
tmp_19_5_10_1_reg_6264 <= grp_fu_1191_p2;
tmp_19_5_11_1_reg_6269 <= grp_fu_1195_p2;
tmp_19_5_12_1_reg_6274 <= grp_fu_1199_p2;
tmp_19_5_1_1_reg_6219 <= grp_fu_1155_p2;
tmp_19_5_2_1_reg_6224 <= grp_fu_1159_p2;
tmp_19_5_3_1_reg_6229 <= grp_fu_1163_p2;
tmp_19_5_4_1_reg_6234 <= grp_fu_1167_p2;
tmp_19_5_5_1_reg_6239 <= grp_fu_1171_p2;
tmp_19_5_6_1_reg_6244 <= grp_fu_1175_p2;
tmp_19_5_7_1_reg_6249 <= grp_fu_1179_p2;
tmp_19_5_8_1_reg_6254 <= grp_fu_1183_p2;
tmp_19_5_9_1_reg_6259 <= grp_fu_1187_p2;
tmp_19_6_0_1_reg_6284 <= grp_fu_1203_p2;
tmp_19_6_10_1_reg_6384 <= grp_fu_1243_p2;
tmp_19_6_11_1_reg_6394 <= grp_fu_1247_p2;
tmp_19_6_12_1_reg_6404 <= grp_fu_1251_p2;
tmp_19_6_1_1_reg_6294 <= grp_fu_1207_p2;
tmp_19_6_2_1_reg_6304 <= grp_fu_1211_p2;
tmp_19_6_3_1_reg_6314 <= grp_fu_1215_p2;
tmp_19_6_4_1_reg_6324 <= grp_fu_1219_p2;
tmp_19_6_5_1_reg_6334 <= grp_fu_1223_p2;
tmp_19_6_6_1_reg_6344 <= grp_fu_1227_p2;
tmp_19_6_7_1_reg_6354 <= grp_fu_1231_p2;
tmp_19_6_8_1_reg_6364 <= grp_fu_1235_p2;
tmp_19_6_9_1_reg_6374 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_5_0_2_reg_6864 <= grp_fu_1099_p2;
tmp_19_5_10_2_reg_6914 <= grp_fu_1139_p2;
tmp_19_5_11_2_reg_6919 <= grp_fu_1143_p2;
tmp_19_5_12_2_reg_6924 <= grp_fu_1147_p2;
tmp_19_5_1_2_reg_6869 <= grp_fu_1103_p2;
tmp_19_5_2_2_reg_6874 <= grp_fu_1107_p2;
tmp_19_5_3_2_reg_6879 <= grp_fu_1111_p2;
tmp_19_5_4_2_reg_6884 <= grp_fu_1115_p2;
tmp_19_5_5_2_reg_6889 <= grp_fu_1119_p2;
tmp_19_5_6_2_reg_6894 <= grp_fu_1123_p2;
tmp_19_5_7_2_reg_6899 <= grp_fu_1127_p2;
tmp_19_5_8_2_reg_6904 <= grp_fu_1131_p2;
tmp_19_5_9_2_reg_6909 <= grp_fu_1135_p2;
tmp_19_6_0_2_reg_6929 <= grp_fu_1151_p2;
tmp_19_6_10_2_reg_6979 <= grp_fu_1191_p2;
tmp_19_6_11_2_reg_6984 <= grp_fu_1195_p2;
tmp_19_6_12_2_reg_6989 <= grp_fu_1199_p2;
tmp_19_6_1_2_reg_6934 <= grp_fu_1155_p2;
tmp_19_6_2_2_reg_6939 <= grp_fu_1159_p2;
tmp_19_6_3_2_reg_6944 <= grp_fu_1163_p2;
tmp_19_6_4_2_reg_6949 <= grp_fu_1167_p2;
tmp_19_6_5_2_reg_6954 <= grp_fu_1171_p2;
tmp_19_6_6_2_reg_6959 <= grp_fu_1175_p2;
tmp_19_6_7_2_reg_6964 <= grp_fu_1179_p2;
tmp_19_6_8_2_reg_6969 <= grp_fu_1183_p2;
tmp_19_6_9_2_reg_6974 <= grp_fu_1187_p2;
tmp_19_7_0_2_reg_6994 <= grp_fu_1203_p2;
tmp_19_7_10_2_reg_7044 <= grp_fu_1243_p2;
tmp_19_7_11_2_reg_7049 <= grp_fu_1247_p2;
tmp_19_7_12_2_reg_7054 <= grp_fu_1251_p2;
tmp_19_7_1_2_reg_6999 <= grp_fu_1207_p2;
tmp_19_7_2_2_reg_7004 <= grp_fu_1211_p2;
tmp_19_7_3_2_reg_7009 <= grp_fu_1215_p2;
tmp_19_7_4_2_reg_7014 <= grp_fu_1219_p2;
tmp_19_7_5_2_reg_7019 <= grp_fu_1223_p2;
tmp_19_7_6_2_reg_7024 <= grp_fu_1227_p2;
tmp_19_7_7_2_reg_7029 <= grp_fu_1231_p2;
tmp_19_7_8_2_reg_7034 <= grp_fu_1235_p2;
tmp_19_7_9_2_reg_7039 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_0_0_1_reg_7579 <= grp_fu_943_p2;
tmp_20_0_10_1_reg_7629 <= grp_fu_983_p2;
tmp_20_0_11_1_reg_7634 <= grp_fu_987_p2;
tmp_20_0_12_1_reg_7639 <= grp_fu_991_p2;
tmp_20_0_1_1_reg_7584 <= grp_fu_947_p2;
tmp_20_0_2_1_reg_7589 <= grp_fu_951_p2;
tmp_20_0_3_1_reg_7594 <= grp_fu_955_p2;
tmp_20_0_4_1_reg_7599 <= grp_fu_959_p2;
tmp_20_0_5_1_reg_7604 <= grp_fu_963_p2;
tmp_20_0_6_1_reg_7609 <= grp_fu_967_p2;
tmp_20_0_7_1_reg_7614 <= grp_fu_971_p2;
tmp_20_0_8_1_reg_7619 <= grp_fu_975_p2;
tmp_20_0_9_1_reg_7624 <= grp_fu_979_p2;
tmp_20_1_0_1_reg_7644 <= grp_fu_995_p2;
tmp_20_1_10_1_reg_7694 <= grp_fu_1035_p2;
tmp_20_1_11_1_reg_7699 <= grp_fu_1039_p2;
tmp_20_1_12_1_reg_7704 <= grp_fu_1043_p2;
tmp_20_1_1_1_reg_7649 <= grp_fu_999_p2;
tmp_20_1_2_1_reg_7654 <= grp_fu_1003_p2;
tmp_20_1_3_1_reg_7659 <= grp_fu_1007_p2;
tmp_20_1_4_1_reg_7664 <= grp_fu_1011_p2;
tmp_20_1_5_1_reg_7669 <= grp_fu_1015_p2;
tmp_20_1_6_1_reg_7674 <= grp_fu_1019_p2;
tmp_20_1_7_1_reg_7679 <= grp_fu_1023_p2;
tmp_20_1_8_1_reg_7684 <= grp_fu_1027_p2;
tmp_20_1_9_1_reg_7689 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_0_0_2_reg_8099 <= grp_fu_943_p2;
tmp_20_0_10_2_reg_8149 <= grp_fu_983_p2;
tmp_20_0_11_2_reg_8154 <= grp_fu_987_p2;
tmp_20_0_12_2_reg_8159 <= grp_fu_991_p2;
tmp_20_0_1_2_reg_8104 <= grp_fu_947_p2;
tmp_20_0_2_2_reg_8109 <= grp_fu_951_p2;
tmp_20_0_3_2_reg_8114 <= grp_fu_955_p2;
tmp_20_0_4_2_reg_8119 <= grp_fu_959_p2;
tmp_20_0_5_2_reg_8124 <= grp_fu_963_p2;
tmp_20_0_6_2_reg_8129 <= grp_fu_967_p2;
tmp_20_0_7_2_reg_8134 <= grp_fu_971_p2;
tmp_20_0_8_2_reg_8139 <= grp_fu_975_p2;
tmp_20_0_9_2_reg_8144 <= grp_fu_979_p2;
tmp_20_1_0_2_reg_8164 <= grp_fu_995_p2;
tmp_20_1_10_2_reg_8214 <= grp_fu_1035_p2;
tmp_20_1_11_2_reg_8219 <= grp_fu_1039_p2;
tmp_20_1_12_2_reg_8224 <= grp_fu_1043_p2;
tmp_20_1_1_2_reg_8169 <= grp_fu_999_p2;
tmp_20_1_2_2_reg_8174 <= grp_fu_1003_p2;
tmp_20_1_3_2_reg_8179 <= grp_fu_1007_p2;
tmp_20_1_4_2_reg_8184 <= grp_fu_1011_p2;
tmp_20_1_5_2_reg_8189 <= grp_fu_1015_p2;
tmp_20_1_6_2_reg_8194 <= grp_fu_1019_p2;
tmp_20_1_7_2_reg_8199 <= grp_fu_1023_p2;
tmp_20_1_8_2_reg_8204 <= grp_fu_1027_p2;
tmp_20_1_9_2_reg_8209 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_0_10_reg_7114 <= grp_fu_987_p2;
tmp_20_0_11_reg_7119 <= grp_fu_991_p2;
tmp_20_0_1_reg_7064 <= grp_fu_947_p2;
tmp_20_0_2_reg_7069 <= grp_fu_951_p2;
tmp_20_0_3_reg_7074 <= grp_fu_955_p2;
tmp_20_0_4_reg_7079 <= grp_fu_959_p2;
tmp_20_0_5_reg_7084 <= grp_fu_963_p2;
tmp_20_0_6_reg_7089 <= grp_fu_967_p2;
tmp_20_0_7_reg_7094 <= grp_fu_971_p2;
tmp_20_0_8_reg_7099 <= grp_fu_975_p2;
tmp_20_0_9_reg_7104 <= grp_fu_979_p2;
tmp_20_0_s_reg_7109 <= grp_fu_983_p2;
tmp_20_1_10_reg_7179 <= grp_fu_1039_p2;
tmp_20_1_11_reg_7184 <= grp_fu_1043_p2;
tmp_20_1_1_reg_7129 <= grp_fu_999_p2;
tmp_20_1_2_reg_7134 <= grp_fu_1003_p2;
tmp_20_1_3_reg_7139 <= grp_fu_1007_p2;
tmp_20_1_4_reg_7144 <= grp_fu_1011_p2;
tmp_20_1_5_reg_7149 <= grp_fu_1015_p2;
tmp_20_1_6_reg_7154 <= grp_fu_1019_p2;
tmp_20_1_7_reg_7159 <= grp_fu_1023_p2;
tmp_20_1_8_reg_7164 <= grp_fu_1027_p2;
tmp_20_1_9_reg_7169 <= grp_fu_1031_p2;
tmp_20_1_reg_7124 <= grp_fu_995_p2;
tmp_20_1_s_reg_7174 <= grp_fu_1035_p2;
tmp_351_reg_7059 <= grp_fu_943_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_2_0_1_reg_7709 <= grp_fu_943_p2;
tmp_20_2_10_1_reg_7759 <= grp_fu_983_p2;
tmp_20_2_11_1_reg_7764 <= grp_fu_987_p2;
tmp_20_2_12_1_reg_7769 <= grp_fu_991_p2;
tmp_20_2_1_1_reg_7714 <= grp_fu_947_p2;
tmp_20_2_2_1_reg_7719 <= grp_fu_951_p2;
tmp_20_2_3_1_reg_7724 <= grp_fu_955_p2;
tmp_20_2_4_1_reg_7729 <= grp_fu_959_p2;
tmp_20_2_5_1_reg_7734 <= grp_fu_963_p2;
tmp_20_2_6_1_reg_7739 <= grp_fu_967_p2;
tmp_20_2_7_1_reg_7744 <= grp_fu_971_p2;
tmp_20_2_8_1_reg_7749 <= grp_fu_975_p2;
tmp_20_2_9_1_reg_7754 <= grp_fu_979_p2;
tmp_20_3_0_1_reg_7774 <= grp_fu_995_p2;
tmp_20_3_10_1_reg_7824 <= grp_fu_1035_p2;
tmp_20_3_11_1_reg_7829 <= grp_fu_1039_p2;
tmp_20_3_12_1_reg_7834 <= grp_fu_1043_p2;
tmp_20_3_1_1_reg_7779 <= grp_fu_999_p2;
tmp_20_3_2_1_reg_7784 <= grp_fu_1003_p2;
tmp_20_3_3_1_reg_7789 <= grp_fu_1007_p2;
tmp_20_3_4_1_reg_7794 <= grp_fu_1011_p2;
tmp_20_3_5_1_reg_7799 <= grp_fu_1015_p2;
tmp_20_3_6_1_reg_7804 <= grp_fu_1019_p2;
tmp_20_3_7_1_reg_7809 <= grp_fu_1023_p2;
tmp_20_3_8_1_reg_7814 <= grp_fu_1027_p2;
tmp_20_3_9_1_reg_7819 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_2_0_2_reg_8229 <= grp_fu_943_p2;
tmp_20_2_10_2_reg_8279 <= grp_fu_983_p2;
tmp_20_2_11_2_reg_8284 <= grp_fu_987_p2;
tmp_20_2_12_2_reg_8289 <= grp_fu_991_p2;
tmp_20_2_1_2_reg_8234 <= grp_fu_947_p2;
tmp_20_2_2_2_reg_8239 <= grp_fu_951_p2;
tmp_20_2_3_2_reg_8244 <= grp_fu_955_p2;
tmp_20_2_4_2_reg_8249 <= grp_fu_959_p2;
tmp_20_2_5_2_reg_8254 <= grp_fu_963_p2;
tmp_20_2_6_2_reg_8259 <= grp_fu_967_p2;
tmp_20_2_7_2_reg_8264 <= grp_fu_971_p2;
tmp_20_2_8_2_reg_8269 <= grp_fu_975_p2;
tmp_20_2_9_2_reg_8274 <= grp_fu_979_p2;
tmp_20_3_0_2_reg_8294 <= grp_fu_995_p2;
tmp_20_3_10_2_reg_8344 <= grp_fu_1035_p2;
tmp_20_3_11_2_reg_8349 <= grp_fu_1039_p2;
tmp_20_3_12_2_reg_8354 <= grp_fu_1043_p2;
tmp_20_3_1_2_reg_8299 <= grp_fu_999_p2;
tmp_20_3_2_2_reg_8304 <= grp_fu_1003_p2;
tmp_20_3_3_2_reg_8309 <= grp_fu_1007_p2;
tmp_20_3_4_2_reg_8314 <= grp_fu_1011_p2;
tmp_20_3_5_2_reg_8319 <= grp_fu_1015_p2;
tmp_20_3_6_2_reg_8324 <= grp_fu_1019_p2;
tmp_20_3_7_2_reg_8329 <= grp_fu_1023_p2;
tmp_20_3_8_2_reg_8334 <= grp_fu_1027_p2;
tmp_20_3_9_2_reg_8339 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_2_10_reg_7244 <= grp_fu_987_p2;
tmp_20_2_11_reg_7249 <= grp_fu_991_p2;
tmp_20_2_1_reg_7194 <= grp_fu_947_p2;
tmp_20_2_2_reg_7199 <= grp_fu_951_p2;
tmp_20_2_3_reg_7204 <= grp_fu_955_p2;
tmp_20_2_4_reg_7209 <= grp_fu_959_p2;
tmp_20_2_5_reg_7214 <= grp_fu_963_p2;
tmp_20_2_6_reg_7219 <= grp_fu_967_p2;
tmp_20_2_7_reg_7224 <= grp_fu_971_p2;
tmp_20_2_8_reg_7229 <= grp_fu_975_p2;
tmp_20_2_9_reg_7234 <= grp_fu_979_p2;
tmp_20_2_reg_7189 <= grp_fu_943_p2;
tmp_20_2_s_reg_7239 <= grp_fu_983_p2;
tmp_20_3_10_reg_7309 <= grp_fu_1039_p2;
tmp_20_3_11_reg_7314 <= grp_fu_1043_p2;
tmp_20_3_1_reg_7259 <= grp_fu_999_p2;
tmp_20_3_2_reg_7264 <= grp_fu_1003_p2;
tmp_20_3_3_reg_7269 <= grp_fu_1007_p2;
tmp_20_3_4_reg_7274 <= grp_fu_1011_p2;
tmp_20_3_5_reg_7279 <= grp_fu_1015_p2;
tmp_20_3_6_reg_7284 <= grp_fu_1019_p2;
tmp_20_3_7_reg_7289 <= grp_fu_1023_p2;
tmp_20_3_8_reg_7294 <= grp_fu_1027_p2;
tmp_20_3_9_reg_7299 <= grp_fu_1031_p2;
tmp_20_3_reg_7254 <= grp_fu_995_p2;
tmp_20_3_s_reg_7304 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_4_0_1_reg_7839 <= grp_fu_1047_p2;
tmp_20_4_10_1_reg_7889 <= grp_fu_1087_p2;
tmp_20_4_11_1_reg_7894 <= grp_fu_1091_p2;
tmp_20_4_12_1_reg_7899 <= grp_fu_1095_p2;
tmp_20_4_1_1_reg_7844 <= grp_fu_1051_p2;
tmp_20_4_2_1_reg_7849 <= grp_fu_1055_p2;
tmp_20_4_3_1_reg_7854 <= grp_fu_1059_p2;
tmp_20_4_4_1_reg_7859 <= grp_fu_1063_p2;
tmp_20_4_5_1_reg_7864 <= grp_fu_1067_p2;
tmp_20_4_6_1_reg_7869 <= grp_fu_1071_p2;
tmp_20_4_7_1_reg_7874 <= grp_fu_1075_p2;
tmp_20_4_8_1_reg_7879 <= grp_fu_1079_p2;
tmp_20_4_9_1_reg_7884 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_4_0_2_reg_8359 <= grp_fu_1047_p2;
tmp_20_4_10_2_reg_8409 <= grp_fu_1087_p2;
tmp_20_4_11_2_reg_8414 <= grp_fu_1091_p2;
tmp_20_4_12_2_reg_8419 <= grp_fu_1095_p2;
tmp_20_4_1_2_reg_8364 <= grp_fu_1051_p2;
tmp_20_4_2_2_reg_8369 <= grp_fu_1055_p2;
tmp_20_4_3_2_reg_8374 <= grp_fu_1059_p2;
tmp_20_4_4_2_reg_8379 <= grp_fu_1063_p2;
tmp_20_4_5_2_reg_8384 <= grp_fu_1067_p2;
tmp_20_4_6_2_reg_8389 <= grp_fu_1071_p2;
tmp_20_4_7_2_reg_8394 <= grp_fu_1075_p2;
tmp_20_4_8_2_reg_8399 <= grp_fu_1079_p2;
tmp_20_4_9_2_reg_8404 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_4_10_reg_7374 <= grp_fu_987_p2;
tmp_20_4_11_reg_7379 <= grp_fu_991_p2;
tmp_20_4_1_reg_7324 <= grp_fu_947_p2;
tmp_20_4_2_reg_7329 <= grp_fu_951_p2;
tmp_20_4_3_reg_7334 <= grp_fu_955_p2;
tmp_20_4_4_reg_7339 <= grp_fu_959_p2;
tmp_20_4_5_reg_7344 <= grp_fu_963_p2;
tmp_20_4_6_reg_7349 <= grp_fu_967_p2;
tmp_20_4_7_reg_7354 <= grp_fu_971_p2;
tmp_20_4_8_reg_7359 <= grp_fu_975_p2;
tmp_20_4_9_reg_7364 <= grp_fu_979_p2;
tmp_20_4_reg_7319 <= grp_fu_943_p2;
tmp_20_4_s_reg_7369 <= grp_fu_983_p2;
tmp_20_5_10_reg_7439 <= grp_fu_1039_p2;
tmp_20_5_11_reg_7444 <= grp_fu_1043_p2;
tmp_20_5_1_reg_7389 <= grp_fu_999_p2;
tmp_20_5_2_reg_7394 <= grp_fu_1003_p2;
tmp_20_5_3_reg_7399 <= grp_fu_1007_p2;
tmp_20_5_4_reg_7404 <= grp_fu_1011_p2;
tmp_20_5_5_reg_7409 <= grp_fu_1015_p2;
tmp_20_5_6_reg_7414 <= grp_fu_1019_p2;
tmp_20_5_7_reg_7419 <= grp_fu_1023_p2;
tmp_20_5_8_reg_7424 <= grp_fu_1027_p2;
tmp_20_5_9_reg_7429 <= grp_fu_1031_p2;
tmp_20_5_reg_7384 <= grp_fu_995_p2;
tmp_20_5_s_reg_7434 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_5_0_1_reg_7904 <= grp_fu_1047_p2;
tmp_20_5_10_1_reg_7954 <= grp_fu_1087_p2;
tmp_20_5_11_1_reg_7959 <= grp_fu_1091_p2;
tmp_20_5_12_1_reg_7964 <= grp_fu_1095_p2;
tmp_20_5_1_1_reg_7909 <= grp_fu_1051_p2;
tmp_20_5_2_1_reg_7914 <= grp_fu_1055_p2;
tmp_20_5_3_1_reg_7919 <= grp_fu_1059_p2;
tmp_20_5_4_1_reg_7924 <= grp_fu_1063_p2;
tmp_20_5_5_1_reg_7929 <= grp_fu_1067_p2;
tmp_20_5_6_1_reg_7934 <= grp_fu_1071_p2;
tmp_20_5_7_1_reg_7939 <= grp_fu_1075_p2;
tmp_20_5_8_1_reg_7944 <= grp_fu_1079_p2;
tmp_20_5_9_1_reg_7949 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_5_0_2_reg_8424 <= grp_fu_1047_p2;
tmp_20_5_10_2_reg_8474 <= grp_fu_1087_p2;
tmp_20_5_11_2_reg_8479 <= grp_fu_1091_p2;
tmp_20_5_12_2_reg_8484 <= grp_fu_1095_p2;
tmp_20_5_1_2_reg_8429 <= grp_fu_1051_p2;
tmp_20_5_2_2_reg_8434 <= grp_fu_1055_p2;
tmp_20_5_3_2_reg_8439 <= grp_fu_1059_p2;
tmp_20_5_4_2_reg_8444 <= grp_fu_1063_p2;
tmp_20_5_5_2_reg_8449 <= grp_fu_1067_p2;
tmp_20_5_6_2_reg_8454 <= grp_fu_1071_p2;
tmp_20_5_7_2_reg_8459 <= grp_fu_1075_p2;
tmp_20_5_8_2_reg_8464 <= grp_fu_1079_p2;
tmp_20_5_9_2_reg_8469 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_6_0_1_reg_7969 <= grp_fu_1047_p2;
tmp_20_6_10_1_reg_8019 <= grp_fu_1087_p2;
tmp_20_6_11_1_reg_8024 <= grp_fu_1091_p2;
tmp_20_6_12_1_reg_8029 <= grp_fu_1095_p2;
tmp_20_6_1_1_reg_7974 <= grp_fu_1051_p2;
tmp_20_6_2_1_reg_7979 <= grp_fu_1055_p2;
tmp_20_6_3_1_reg_7984 <= grp_fu_1059_p2;
tmp_20_6_4_1_reg_7989 <= grp_fu_1063_p2;
tmp_20_6_5_1_reg_7994 <= grp_fu_1067_p2;
tmp_20_6_6_1_reg_7999 <= grp_fu_1071_p2;
tmp_20_6_7_1_reg_8004 <= grp_fu_1075_p2;
tmp_20_6_8_1_reg_8009 <= grp_fu_1079_p2;
tmp_20_6_9_1_reg_8014 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_6_0_2_reg_8489 <= grp_fu_1047_p2;
tmp_20_6_10_2_reg_8539 <= grp_fu_1087_p2;
tmp_20_6_11_2_reg_8544 <= grp_fu_1091_p2;
tmp_20_6_12_2_reg_8549 <= grp_fu_1095_p2;
tmp_20_6_1_2_reg_8494 <= grp_fu_1051_p2;
tmp_20_6_2_2_reg_8499 <= grp_fu_1055_p2;
tmp_20_6_3_2_reg_8504 <= grp_fu_1059_p2;
tmp_20_6_4_2_reg_8509 <= grp_fu_1063_p2;
tmp_20_6_5_2_reg_8514 <= grp_fu_1067_p2;
tmp_20_6_6_2_reg_8519 <= grp_fu_1071_p2;
tmp_20_6_7_2_reg_8524 <= grp_fu_1075_p2;
tmp_20_6_8_2_reg_8529 <= grp_fu_1079_p2;
tmp_20_6_9_2_reg_8534 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
tmp_20_6_10_reg_7504 <= grp_fu_987_p2;
tmp_20_6_11_reg_7509 <= grp_fu_991_p2;
tmp_20_6_1_reg_7454 <= grp_fu_947_p2;
tmp_20_6_2_reg_7459 <= grp_fu_951_p2;
tmp_20_6_3_reg_7464 <= grp_fu_955_p2;
tmp_20_6_4_reg_7469 <= grp_fu_959_p2;
tmp_20_6_5_reg_7474 <= grp_fu_963_p2;
tmp_20_6_6_reg_7479 <= grp_fu_967_p2;
tmp_20_6_7_reg_7484 <= grp_fu_971_p2;
tmp_20_6_8_reg_7489 <= grp_fu_975_p2;
tmp_20_6_9_reg_7494 <= grp_fu_979_p2;
tmp_20_6_reg_7449 <= grp_fu_943_p2;
tmp_20_6_s_reg_7499 <= grp_fu_983_p2;
tmp_20_7_10_reg_7569 <= grp_fu_1039_p2;
tmp_20_7_11_reg_7574 <= grp_fu_1043_p2;
tmp_20_7_1_reg_7519 <= grp_fu_999_p2;
tmp_20_7_2_reg_7524 <= grp_fu_1003_p2;
tmp_20_7_3_reg_7529 <= grp_fu_1007_p2;
tmp_20_7_4_reg_7534 <= grp_fu_1011_p2;
tmp_20_7_5_reg_7539 <= grp_fu_1015_p2;
tmp_20_7_6_reg_7544 <= grp_fu_1019_p2;
tmp_20_7_7_reg_7549 <= grp_fu_1023_p2;
tmp_20_7_8_reg_7554 <= grp_fu_1027_p2;
tmp_20_7_9_reg_7559 <= grp_fu_1031_p2;
tmp_20_7_reg_7514 <= grp_fu_995_p2;
tmp_20_7_s_reg_7564 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_20_7_0_1_reg_8034 <= grp_fu_1047_p2;
tmp_20_7_10_1_reg_8084 <= grp_fu_1087_p2;
tmp_20_7_11_1_reg_8089 <= grp_fu_1091_p2;
tmp_20_7_12_1_reg_8094 <= grp_fu_1095_p2;
tmp_20_7_1_1_reg_8039 <= grp_fu_1051_p2;
tmp_20_7_2_1_reg_8044 <= grp_fu_1055_p2;
tmp_20_7_3_1_reg_8049 <= grp_fu_1059_p2;
tmp_20_7_4_1_reg_8054 <= grp_fu_1063_p2;
tmp_20_7_5_1_reg_8059 <= grp_fu_1067_p2;
tmp_20_7_6_1_reg_8064 <= grp_fu_1071_p2;
tmp_20_7_7_1_reg_8069 <= grp_fu_1075_p2;
tmp_20_7_8_1_reg_8074 <= grp_fu_1079_p2;
tmp_20_7_9_1_reg_8079 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_7_0_2_reg_8554 <= grp_fu_1047_p2;
tmp_20_7_10_2_reg_8604 <= grp_fu_1087_p2;
tmp_20_7_11_2_reg_8609 <= grp_fu_1091_p2;
tmp_20_7_12_2_reg_8614 <= grp_fu_1095_p2;
tmp_20_7_1_2_reg_8559 <= grp_fu_1051_p2;
tmp_20_7_2_2_reg_8564 <= grp_fu_1055_p2;
tmp_20_7_3_2_reg_8569 <= grp_fu_1059_p2;
tmp_20_7_4_2_reg_8574 <= grp_fu_1063_p2;
tmp_20_7_5_2_reg_8579 <= grp_fu_1067_p2;
tmp_20_7_6_2_reg_8584 <= grp_fu_1071_p2;
tmp_20_7_7_2_reg_8589 <= grp_fu_1075_p2;
tmp_20_7_8_2_reg_8594 <= grp_fu_1079_p2;
tmp_20_7_9_2_reg_8599 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_210_reg_3511 <= tmp_210_fu_1876_p2;
tmp_250_reg_3516 <= tmp_250_fu_1881_p2;
tmp_7_reg_3356 <= tmp_7_fu_1807_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_290_reg_3616 <= tmp_290_fu_1978_p2;
tmp_330_reg_3621 <= tmp_330_fu_1983_p2;
tmp_331_reg_3626 <= tmp_331_fu_1988_p2;
tmp_332_reg_3631 <= tmp_332_fu_1993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_2_reg_3281 <= tmp_2_fu_1657_p2;
tmp_90_reg_3299(9 downto 2) <= tmp_90_fu_1694_p2(9 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_355_reg_4719 <= tmp_355_fu_2149_p1;
tmp_356_reg_4784 <= tmp_356_fu_2153_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_357_reg_5044 <= tmp_357_fu_2157_p1;
tmp_358_reg_5109 <= tmp_358_fu_2161_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
tmp_5_mid2_reg_3286 <= tmp_5_mid2_fu_1662_p3;
end if;
end if;
end process;
tmp_90_reg_3299(1 downto 0) <= "00";
tmp_5_mid2_cast2_reg_3316(6 downto 3) <= "0000";
tmp_333_reg_4307(2 downto 0) <= "000";
bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter2_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter3_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter4_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter5_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter6_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter7_bufo_addr_reg_4317(2 downto 0) <= "000";
bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(2 downto 0) <= "001";
bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(2 downto 0) <= "010";
bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(2 downto 0) <= "011";
bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(2 downto 0) <= "100";
bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(2 downto 0) <= "101";
bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(2 downto 0) <= "110";
bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten1_fu_1541_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_subdone, ap_block_pp0_stage7_subdone, ap_block_pp0_stage1_subdone, ap_enable_reg_pp0_iter9, ap_block_pp0_stage2_subdone, ap_block_pp0_stage3_subdone, ap_block_pp0_stage4_subdone, ap_block_pp0_stage5_subdone, ap_block_pp0_stage6_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((not(((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) and (ap_block_pp0_stage1_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
elsif (((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_state76 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state76 <= ap_CS_fsm(9);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage3_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage4_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage5_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage6_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage7_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten1_fu_1541_p2)
begin
if ((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_i_phi_fu_900_p4_assign_proc : process(i_reg_896, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_1_mid2_v_reg_3225, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_i_phi_fu_900_p4 <= tmp_1_mid2_v_reg_3225;
else
ap_phi_mux_i_phi_fu_900_p4 <= i_reg_896;
end if;
end process;
ap_phi_mux_indvar_flatten1_phi_fu_889_p4_assign_proc : process(indvar_flatten1_reg_885, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next1_reg_3180, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten_next1_reg_3180;
else
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten1_reg_885;
end if;
end process;
ap_phi_mux_indvar_flatten_phi_fu_912_p4_assign_proc : process(indvar_flatten_reg_908, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next_reg_3252, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_next_reg_3252;
else
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_reg_908;
end if;
end process;
ap_phi_mux_j_phi_fu_923_p4_assign_proc : process(j_reg_919, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_5_mid2_reg_3286, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_j_phi_fu_923_p4 <= tmp_5_mid2_reg_3286;
else
ap_phi_mux_j_phi_fu_923_p4 <= j_reg_919;
end if;
end process;
ap_phi_mux_row_b_phi_fu_935_p4_assign_proc : process(row_b_reg_931, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, row_b_1_reg_3276, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_1_reg_3276;
else
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_reg_931;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_0_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Clk_A <= ap_clk;
bufi_0_Clk_B <= ap_clk;
bufi_0_Din_A <= ap_const_lv32_0;
bufi_0_Din_B <= ap_const_lv32_0;
bufi_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_A <= ap_const_logic_1;
else
bufi_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_0_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_B <= ap_const_logic_1;
else
bufi_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_0_Rst_A <= ap_rst_n_inv;
bufi_0_Rst_B <= ap_rst_n_inv;
bufi_0_WEN_A <= ap_const_lv4_0;
bufi_0_WEN_B <= ap_const_lv4_0;
bufi_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_1_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Clk_A <= ap_clk;
bufi_1_Clk_B <= ap_clk;
bufi_1_Din_A <= ap_const_lv32_0;
bufi_1_Din_B <= ap_const_lv32_0;
bufi_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_A <= ap_const_logic_1;
else
bufi_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_1_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_B <= ap_const_logic_1;
else
bufi_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_1_Rst_A <= ap_rst_n_inv;
bufi_1_Rst_B <= ap_rst_n_inv;
bufi_1_WEN_A <= ap_const_lv4_0;
bufi_1_WEN_B <= ap_const_lv4_0;
bufi_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_2_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Clk_A <= ap_clk;
bufi_2_Clk_B <= ap_clk;
bufi_2_Din_A <= ap_const_lv32_0;
bufi_2_Din_B <= ap_const_lv32_0;
bufi_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_A <= ap_const_logic_1;
else
bufi_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_2_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_B <= ap_const_logic_1;
else
bufi_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_2_Rst_A <= ap_rst_n_inv;
bufi_2_Rst_B <= ap_rst_n_inv;
bufi_2_WEN_A <= ap_const_lv4_0;
bufi_2_WEN_B <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_reg_4317, ap_reg_pp0_iter7_bufo_addr_2_reg_4429, ap_reg_pp0_iter7_bufo_addr_4_reg_4439, ap_reg_pp0_iter8_bufo_addr_6_reg_4579, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_334_fu_2029_p1, ap_block_pp0_stage2, tmp_338_fu_2054_p3, ap_block_pp0_stage3, tmp_342_fu_2082_p3, ap_block_pp0_stage4, tmp_346_fu_2118_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_6_reg_4579),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_4_reg_4439),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_2_reg_4429),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_reg_4317),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_A_orig <= tmp_346_fu_2118_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_A_orig <= tmp_342_fu_2082_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_A_orig <= tmp_338_fu_2054_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_A_orig <= tmp_334_fu_2029_p1(32 - 1 downto 0);
else
bufo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_1_reg_4322, ap_reg_pp0_iter7_bufo_addr_3_reg_4434, ap_reg_pp0_iter7_bufo_addr_5_reg_4444, ap_reg_pp0_iter8_bufo_addr_7_reg_4584, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, tmp_336_fu_2040_p3, ap_block_pp0_stage3, tmp_340_fu_2068_p3, ap_block_pp0_stage4, tmp_344_fu_2096_p3, tmp_348_fu_2132_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_7_reg_4584),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_5_reg_4444),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_3_reg_4434),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_1_reg_4322),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_B_orig <= tmp_348_fu_2132_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_B_orig <= tmp_344_fu_2096_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_B_orig <= tmp_340_fu_2068_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_B_orig <= tmp_336_fu_2040_p3(32 - 1 downto 0);
else
bufo_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Clk_A <= ap_clk;
bufo_Clk_B <= ap_clk;
bufo_Din_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_49_fu_2620_p14, tmp_129_fu_2760_p14, tmp_209_fu_2900_p14, tmp_289_fu_3040_p14, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_289_fu_3040_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_209_fu_2900_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_129_fu_2760_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_fu_2620_p14),512));
else
bufo_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Din_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_89_fu_2690_p14, tmp_169_fu_2830_p14, tmp_249_fu_2970_p14, ap_block_pp0_stage1, tmp_329_fu_3110_p14)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_329_fu_3110_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_249_fu_2970_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_169_fu_2830_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_89_fu_2690_p14),512));
else
bufo_Din_B <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_B <= ap_const_logic_1;
else
bufo_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_Rst_B <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_A <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_A <= ap_const_lv64_0;
end if;
end process;
bufo_WEN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_B <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_B <= ap_const_lv64_0;
end if;
end process;
bufw_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_0_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_0_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_0_Clk_A <= ap_clk;
bufw_0_Clk_B <= ap_clk;
bufw_0_Din_A <= ap_const_lv32_0;
bufw_0_Din_B <= ap_const_lv32_0;
bufw_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_0_EN_A <= ap_const_logic_1;
else
bufw_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_0_EN_B <= ap_const_logic_1;
else
bufw_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_0_Rst_A <= ap_rst_n_inv;
bufw_0_Rst_B <= ap_rst_n_inv;
bufw_0_WEN_A <= ap_const_lv4_0;
bufw_0_WEN_B <= ap_const_lv4_0;
bufw_10_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_10_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_10_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_10_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_10_Clk_A <= ap_clk;
bufw_10_Clk_B <= ap_clk;
bufw_10_Din_A <= ap_const_lv32_0;
bufw_10_Din_B <= ap_const_lv32_0;
bufw_10_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_10_EN_A <= ap_const_logic_1;
else
bufw_10_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_10_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_10_EN_B <= ap_const_logic_1;
else
bufw_10_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_10_Rst_A <= ap_rst_n_inv;
bufw_10_Rst_B <= ap_rst_n_inv;
bufw_10_WEN_A <= ap_const_lv4_0;
bufw_10_WEN_B <= ap_const_lv4_0;
bufw_11_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_11_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_11_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_11_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_11_Clk_A <= ap_clk;
bufw_11_Clk_B <= ap_clk;
bufw_11_Din_A <= ap_const_lv32_0;
bufw_11_Din_B <= ap_const_lv32_0;
bufw_11_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_11_EN_A <= ap_const_logic_1;
else
bufw_11_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_11_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_11_EN_B <= ap_const_logic_1;
else
bufw_11_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_11_Rst_A <= ap_rst_n_inv;
bufw_11_Rst_B <= ap_rst_n_inv;
bufw_11_WEN_A <= ap_const_lv4_0;
bufw_11_WEN_B <= ap_const_lv4_0;
bufw_12_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_12_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_12_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_12_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_12_Clk_A <= ap_clk;
bufw_12_Clk_B <= ap_clk;
bufw_12_Din_A <= ap_const_lv32_0;
bufw_12_Din_B <= ap_const_lv32_0;
bufw_12_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_12_EN_A <= ap_const_logic_1;
else
bufw_12_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_12_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_12_EN_B <= ap_const_logic_1;
else
bufw_12_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_12_Rst_A <= ap_rst_n_inv;
bufw_12_Rst_B <= ap_rst_n_inv;
bufw_12_WEN_A <= ap_const_lv4_0;
bufw_12_WEN_B <= ap_const_lv4_0;
bufw_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_1_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_1_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_1_Clk_A <= ap_clk;
bufw_1_Clk_B <= ap_clk;
bufw_1_Din_A <= ap_const_lv32_0;
bufw_1_Din_B <= ap_const_lv32_0;
bufw_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_1_EN_A <= ap_const_logic_1;
else
bufw_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_1_EN_B <= ap_const_logic_1;
else
bufw_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_1_Rst_A <= ap_rst_n_inv;
bufw_1_Rst_B <= ap_rst_n_inv;
bufw_1_WEN_A <= ap_const_lv4_0;
bufw_1_WEN_B <= ap_const_lv4_0;
bufw_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_2_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_2_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_2_Clk_A <= ap_clk;
bufw_2_Clk_B <= ap_clk;
bufw_2_Din_A <= ap_const_lv32_0;
bufw_2_Din_B <= ap_const_lv32_0;
bufw_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_2_EN_A <= ap_const_logic_1;
else
bufw_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_2_EN_B <= ap_const_logic_1;
else
bufw_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_2_Rst_A <= ap_rst_n_inv;
bufw_2_Rst_B <= ap_rst_n_inv;
bufw_2_WEN_A <= ap_const_lv4_0;
bufw_2_WEN_B <= ap_const_lv4_0;
bufw_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_3_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_3_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_3_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_3_Clk_A <= ap_clk;
bufw_3_Clk_B <= ap_clk;
bufw_3_Din_A <= ap_const_lv32_0;
bufw_3_Din_B <= ap_const_lv32_0;
bufw_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_3_EN_A <= ap_const_logic_1;
else
bufw_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_3_EN_B <= ap_const_logic_1;
else
bufw_3_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_3_Rst_A <= ap_rst_n_inv;
bufw_3_Rst_B <= ap_rst_n_inv;
bufw_3_WEN_A <= ap_const_lv4_0;
bufw_3_WEN_B <= ap_const_lv4_0;
bufw_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_4_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_4_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_4_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_4_Clk_A <= ap_clk;
bufw_4_Clk_B <= ap_clk;
bufw_4_Din_A <= ap_const_lv32_0;
bufw_4_Din_B <= ap_const_lv32_0;
bufw_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_4_EN_A <= ap_const_logic_1;
else
bufw_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_4_EN_B <= ap_const_logic_1;
else
bufw_4_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_4_Rst_A <= ap_rst_n_inv;
bufw_4_Rst_B <= ap_rst_n_inv;
bufw_4_WEN_A <= ap_const_lv4_0;
bufw_4_WEN_B <= ap_const_lv4_0;
bufw_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_5_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_5_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_5_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_5_Clk_A <= ap_clk;
bufw_5_Clk_B <= ap_clk;
bufw_5_Din_A <= ap_const_lv32_0;
bufw_5_Din_B <= ap_const_lv32_0;
bufw_5_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_5_EN_A <= ap_const_logic_1;
else
bufw_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_5_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_5_EN_B <= ap_const_logic_1;
else
bufw_5_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_5_Rst_A <= ap_rst_n_inv;
bufw_5_Rst_B <= ap_rst_n_inv;
bufw_5_WEN_A <= ap_const_lv4_0;
bufw_5_WEN_B <= ap_const_lv4_0;
bufw_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_6_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_6_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_6_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_6_Clk_A <= ap_clk;
bufw_6_Clk_B <= ap_clk;
bufw_6_Din_A <= ap_const_lv32_0;
bufw_6_Din_B <= ap_const_lv32_0;
bufw_6_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_6_EN_A <= ap_const_logic_1;
else
bufw_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_6_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_6_EN_B <= ap_const_logic_1;
else
bufw_6_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_6_Rst_A <= ap_rst_n_inv;
bufw_6_Rst_B <= ap_rst_n_inv;
bufw_6_WEN_A <= ap_const_lv4_0;
bufw_6_WEN_B <= ap_const_lv4_0;
bufw_7_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_7_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_7_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_7_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_7_Clk_A <= ap_clk;
bufw_7_Clk_B <= ap_clk;
bufw_7_Din_A <= ap_const_lv32_0;
bufw_7_Din_B <= ap_const_lv32_0;
bufw_7_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_7_EN_A <= ap_const_logic_1;
else
bufw_7_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_7_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_7_EN_B <= ap_const_logic_1;
else
bufw_7_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_7_Rst_A <= ap_rst_n_inv;
bufw_7_Rst_B <= ap_rst_n_inv;
bufw_7_WEN_A <= ap_const_lv4_0;
bufw_7_WEN_B <= ap_const_lv4_0;
bufw_8_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_8_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_8_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_8_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_8_Clk_A <= ap_clk;
bufw_8_Clk_B <= ap_clk;
bufw_8_Din_A <= ap_const_lv32_0;
bufw_8_Din_B <= ap_const_lv32_0;
bufw_8_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_8_EN_A <= ap_const_logic_1;
else
bufw_8_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_8_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_8_EN_B <= ap_const_logic_1;
else
bufw_8_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_8_Rst_A <= ap_rst_n_inv;
bufw_8_Rst_B <= ap_rst_n_inv;
bufw_8_WEN_A <= ap_const_lv4_0;
bufw_8_WEN_B <= ap_const_lv4_0;
bufw_9_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_9_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_9_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_9_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_9_Clk_A <= ap_clk;
bufw_9_Clk_B <= ap_clk;
bufw_9_Din_A <= ap_const_lv32_0;
bufw_9_Din_B <= ap_const_lv32_0;
bufw_9_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_9_EN_A <= ap_const_logic_1;
else
bufw_9_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_9_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_9_EN_B <= ap_const_logic_1;
else
bufw_9_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_9_Rst_A <= ap_rst_n_inv;
bufw_9_Rst_B <= ap_rst_n_inv;
bufw_9_WEN_A <= ap_const_lv4_0;
bufw_9_WEN_B <= ap_const_lv4_0;
exitcond_flatten1_fu_1541_p2 <= "1" when (ap_phi_mux_indvar_flatten1_phi_fu_889_p4 = ap_const_lv10_2A3) else "0";
exitcond_flatten_fu_1559_p2 <= "1" when (ap_phi_mux_indvar_flatten_phi_fu_912_p4 = ap_const_lv8_87) else "0";
grp_fu_1003_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_57_fu_2225_p1, tmp_137_fu_2329_p1, tmp_217_fu_2433_p1, tmp_297_fu_2537_p1, ap_enable_reg_pp0_iter3, tmp_20_1_2_reg_7134, tmp_20_3_2_reg_7264, ap_enable_reg_pp0_iter5, tmp_20_1_2_1_reg_7654, tmp_20_3_2_1_reg_7784, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_3_2_1_reg_7784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_1_2_1_reg_7654;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_3_2_reg_7264;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_1_2_reg_7134;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_297_fu_2537_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_217_fu_2433_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_137_fu_2329_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_57_fu_2225_p1;
else
grp_fu_1003_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1003_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_2_reg_4989, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264, tmp_19_3_2_reg_5444, tmp_19_5_2_reg_5769, ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834, tmp_19_7_2_reg_6094, ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549, ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_7_2_reg_6094;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_5_2_reg_5769;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_3_2_reg_5444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_1_2_reg_4989;
else
grp_fu_1003_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_60_fu_2229_p1, tmp_140_fu_2333_p1, tmp_220_fu_2437_p1, tmp_300_fu_2541_p1, ap_enable_reg_pp0_iter3, tmp_20_1_3_reg_7139, tmp_20_3_3_reg_7269, ap_enable_reg_pp0_iter5, tmp_20_1_3_1_reg_7659, tmp_20_3_3_1_reg_7789, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_3_3_1_reg_7789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_1_3_1_reg_7659;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_3_3_reg_7269;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_1_3_reg_7139;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_300_fu_2541_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_220_fu_2437_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_140_fu_2333_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_60_fu_2229_p1;
else
grp_fu_1007_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_3_reg_4994, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274, tmp_19_3_3_reg_5449, tmp_19_5_3_reg_5774, ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839, tmp_19_7_3_reg_6099, ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554, ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_7_3_reg_6099;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_5_3_reg_5774;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_3_3_reg_5449;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_1_3_reg_4994;
else
grp_fu_1007_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_63_fu_2233_p1, tmp_143_fu_2337_p1, tmp_223_fu_2441_p1, tmp_303_fu_2545_p1, ap_enable_reg_pp0_iter3, tmp_20_1_4_reg_7144, tmp_20_3_4_reg_7274, ap_enable_reg_pp0_iter5, tmp_20_1_4_1_reg_7664, tmp_20_3_4_1_reg_7794, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_3_4_1_reg_7794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_1_4_1_reg_7664;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_3_4_reg_7274;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_1_4_reg_7144;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_303_fu_2545_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_223_fu_2441_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_143_fu_2337_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_63_fu_2233_p1;
else
grp_fu_1011_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_4_reg_4999, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284, tmp_19_3_4_reg_5454, tmp_19_5_4_reg_5779, ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844, tmp_19_7_4_reg_6104, ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559, ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_7_4_reg_6104;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_5_4_reg_5779;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_3_4_reg_5454;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_1_4_reg_4999;
else
grp_fu_1011_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_66_fu_2237_p1, tmp_146_fu_2341_p1, tmp_226_fu_2445_p1, tmp_306_fu_2549_p1, ap_enable_reg_pp0_iter3, tmp_20_1_5_reg_7149, tmp_20_3_5_reg_7279, ap_enable_reg_pp0_iter5, tmp_20_1_5_1_reg_7669, tmp_20_3_5_1_reg_7799, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_3_5_1_reg_7799;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_1_5_1_reg_7669;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_3_5_reg_7279;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_1_5_reg_7149;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_306_fu_2549_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_226_fu_2445_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_146_fu_2341_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_66_fu_2237_p1;
else
grp_fu_1015_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_5_reg_5004, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294, tmp_19_3_5_reg_5459, tmp_19_5_5_reg_5784, ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849, tmp_19_7_5_reg_6109, ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564, ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_7_5_reg_6109;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_5_5_reg_5784;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_3_5_reg_5459;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_1_5_reg_5004;
else
grp_fu_1015_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_69_fu_2241_p1, tmp_149_fu_2345_p1, tmp_229_fu_2449_p1, tmp_309_fu_2553_p1, ap_enable_reg_pp0_iter3, tmp_20_1_6_reg_7154, tmp_20_3_6_reg_7284, ap_enable_reg_pp0_iter5, tmp_20_1_6_1_reg_7674, tmp_20_3_6_1_reg_7804, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_3_6_1_reg_7804;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_1_6_1_reg_7674;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_3_6_reg_7284;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_1_6_reg_7154;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_309_fu_2553_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_229_fu_2449_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_149_fu_2345_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_69_fu_2241_p1;
else
grp_fu_1019_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_6_reg_5009, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304, tmp_19_3_6_reg_5464, tmp_19_5_6_reg_5789, ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854, tmp_19_7_6_reg_6114, ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569, ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_7_6_reg_6114;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_5_6_reg_5789;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_3_6_reg_5464;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_1_6_reg_5009;
else
grp_fu_1019_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_72_fu_2245_p1, tmp_152_fu_2349_p1, tmp_232_fu_2453_p1, tmp_312_fu_2557_p1, ap_enable_reg_pp0_iter3, tmp_20_1_7_reg_7159, tmp_20_3_7_reg_7289, ap_enable_reg_pp0_iter5, tmp_20_1_7_1_reg_7679, tmp_20_3_7_1_reg_7809, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_3_7_1_reg_7809;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_1_7_1_reg_7679;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_3_7_reg_7289;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_1_7_reg_7159;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_312_fu_2557_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_232_fu_2453_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_152_fu_2349_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_72_fu_2245_p1;
else
grp_fu_1023_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_7_reg_5014, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314, tmp_19_3_7_reg_5469, tmp_19_5_7_reg_5794, ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859, tmp_19_7_7_reg_6119, ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574, ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_7_7_reg_6119;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_5_7_reg_5794;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_3_7_reg_5469;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_1_7_reg_5014;
else
grp_fu_1023_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_75_fu_2249_p1, tmp_155_fu_2353_p1, tmp_235_fu_2457_p1, tmp_315_fu_2561_p1, ap_enable_reg_pp0_iter3, tmp_20_1_8_reg_7164, tmp_20_3_8_reg_7294, ap_enable_reg_pp0_iter5, tmp_20_1_8_1_reg_7684, tmp_20_3_8_1_reg_7814, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_3_8_1_reg_7814;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_1_8_1_reg_7684;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_3_8_reg_7294;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_1_8_reg_7164;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_315_fu_2561_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_235_fu_2457_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_155_fu_2353_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_75_fu_2249_p1;
else
grp_fu_1027_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_8_reg_5019, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324, tmp_19_3_8_reg_5474, tmp_19_5_8_reg_5799, ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864, tmp_19_7_8_reg_6124, ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579, ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_7_8_reg_6124;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_5_8_reg_5799;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_3_8_reg_5474;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_1_8_reg_5019;
else
grp_fu_1027_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_78_fu_2253_p1, tmp_158_fu_2357_p1, tmp_238_fu_2461_p1, tmp_318_fu_2565_p1, ap_enable_reg_pp0_iter3, tmp_20_1_9_reg_7169, tmp_20_3_9_reg_7299, ap_enable_reg_pp0_iter5, tmp_20_1_9_1_reg_7689, tmp_20_3_9_1_reg_7819, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_3_9_1_reg_7819;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_1_9_1_reg_7689;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_3_9_reg_7299;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_1_9_reg_7169;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_318_fu_2565_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_238_fu_2461_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_158_fu_2357_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_78_fu_2253_p1;
else
grp_fu_1031_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_9_reg_5024, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334, tmp_19_3_9_reg_5479, tmp_19_5_9_reg_5804, ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869, tmp_19_7_9_reg_6129, ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584, ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_7_9_reg_6129;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_5_9_reg_5804;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_3_9_reg_5479;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_1_9_reg_5024;
else
grp_fu_1031_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_81_fu_2257_p1, tmp_161_fu_2361_p1, tmp_241_fu_2465_p1, tmp_321_fu_2569_p1, ap_enable_reg_pp0_iter3, tmp_20_1_s_reg_7174, tmp_20_3_s_reg_7304, ap_enable_reg_pp0_iter5, tmp_20_1_10_1_reg_7694, tmp_20_3_10_1_reg_7824, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_3_10_1_reg_7824;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_1_10_1_reg_7694;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_3_s_reg_7304;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_1_s_reg_7174;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_321_fu_2569_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_241_fu_2465_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_161_fu_2361_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_81_fu_2257_p1;
else
grp_fu_1035_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_s_reg_5029, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344, tmp_19_3_s_reg_5484, tmp_19_5_s_reg_5809, ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874, tmp_19_7_s_reg_6134, ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589, ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_7_s_reg_6134;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_5_s_reg_5809;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_3_s_reg_5484;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_1_s_reg_5029;
else
grp_fu_1035_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_84_fu_2261_p1, tmp_164_fu_2365_p1, tmp_244_fu_2469_p1, tmp_324_fu_2573_p1, ap_enable_reg_pp0_iter3, tmp_20_1_10_reg_7179, tmp_20_3_10_reg_7309, ap_enable_reg_pp0_iter5, tmp_20_1_11_1_reg_7699, tmp_20_3_11_1_reg_7829, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_3_11_1_reg_7829;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_1_11_1_reg_7699;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_3_10_reg_7309;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_1_10_reg_7179;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_324_fu_2573_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_244_fu_2469_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_164_fu_2365_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_84_fu_2261_p1;
else
grp_fu_1039_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_10_reg_5034, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354, tmp_19_3_10_reg_5489, tmp_19_5_10_reg_5814, ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879, tmp_19_7_10_reg_6139, ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594, ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_7_10_reg_6139;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_5_10_reg_5814;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_3_10_reg_5489;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_1_10_reg_5034;
else
grp_fu_1039_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_87_fu_2265_p1, tmp_167_fu_2369_p1, tmp_247_fu_2473_p1, tmp_327_fu_2577_p1, ap_enable_reg_pp0_iter3, tmp_20_1_11_reg_7184, tmp_20_3_11_reg_7314, ap_enable_reg_pp0_iter5, tmp_20_1_12_1_reg_7704, tmp_20_3_12_1_reg_7834, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_3_12_1_reg_7834;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_1_12_1_reg_7704;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_3_11_reg_7314;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_1_11_reg_7184;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_327_fu_2577_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_247_fu_2473_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_167_fu_2369_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_87_fu_2265_p1;
else
grp_fu_1043_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_11_reg_5039, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364, tmp_19_3_11_reg_5494, tmp_19_5_11_reg_5819, ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884, tmp_19_7_11_reg_6144, ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599, ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_7_11_reg_6144;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_5_11_reg_5819;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_3_11_reg_5494;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_1_11_reg_5039;
else
grp_fu_1043_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_reg_7319, tmp_20_5_reg_7384, tmp_20_6_reg_7449, ap_enable_reg_pp0_iter4, tmp_20_7_reg_7514, ap_enable_reg_pp0_iter5, tmp_20_4_0_1_reg_7839, tmp_20_5_0_1_reg_7904, tmp_20_6_0_1_reg_7969, tmp_20_7_0_1_reg_8034, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_7_0_1_reg_8034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_6_0_1_reg_7969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_5_0_1_reg_7904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_4_0_1_reg_7839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_7_reg_7514;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_6_reg_7449;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_5_reg_7384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_4_reg_7319;
else
grp_fu_1047_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149, ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214, ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284, ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604, ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799, ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864, ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929, ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149;
else
grp_fu_1047_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_1_reg_7324, tmp_20_5_1_reg_7389, ap_enable_reg_pp0_iter4, tmp_20_6_1_reg_7454, tmp_20_7_1_reg_7519, ap_enable_reg_pp0_iter5, tmp_20_4_1_1_reg_7844, tmp_20_5_1_1_reg_7909, tmp_20_6_1_1_reg_7974, ap_enable_reg_pp0_iter6, tmp_20_7_1_1_reg_8039, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_7_1_1_reg_8039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_6_1_1_reg_7974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_5_1_1_reg_7909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_4_1_1_reg_7844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_7_1_reg_7519;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_6_1_reg_7454;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_5_1_reg_7389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_4_1_reg_7324;
else
grp_fu_1051_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154, ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219, ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294, ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609, ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804, ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869, ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934, ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154;
else
grp_fu_1051_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_2_reg_7329, tmp_20_5_2_reg_7394, ap_enable_reg_pp0_iter4, tmp_20_6_2_reg_7459, tmp_20_7_2_reg_7524, ap_enable_reg_pp0_iter5, tmp_20_4_2_1_reg_7849, tmp_20_5_2_1_reg_7914, tmp_20_6_2_1_reg_7979, ap_enable_reg_pp0_iter6, tmp_20_7_2_1_reg_8044, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_7_2_1_reg_8044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_6_2_1_reg_7979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_5_2_1_reg_7914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_4_2_1_reg_7849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_7_2_reg_7524;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_6_2_reg_7459;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_5_2_reg_7394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_4_2_reg_7329;
else
grp_fu_1055_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159, ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224, ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304, ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614, ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809, ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874, ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939, ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159;
else
grp_fu_1055_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_3_reg_7334, tmp_20_5_3_reg_7399, ap_enable_reg_pp0_iter4, tmp_20_6_3_reg_7464, tmp_20_7_3_reg_7529, ap_enable_reg_pp0_iter5, tmp_20_4_3_1_reg_7854, tmp_20_5_3_1_reg_7919, tmp_20_6_3_1_reg_7984, ap_enable_reg_pp0_iter6, tmp_20_7_3_1_reg_8049, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_7_3_1_reg_8049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_6_3_1_reg_7984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_5_3_1_reg_7919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_4_3_1_reg_7854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_7_3_reg_7529;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_6_3_reg_7464;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_5_3_reg_7399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_4_3_reg_7334;
else
grp_fu_1059_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164, ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229, ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314, ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619, ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814, ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879, ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944, ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164;
else
grp_fu_1059_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_4_reg_7339, tmp_20_5_4_reg_7404, ap_enable_reg_pp0_iter4, tmp_20_6_4_reg_7469, tmp_20_7_4_reg_7534, ap_enable_reg_pp0_iter5, tmp_20_4_4_1_reg_7859, tmp_20_5_4_1_reg_7924, tmp_20_6_4_1_reg_7989, ap_enable_reg_pp0_iter6, tmp_20_7_4_1_reg_8054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_7_4_1_reg_8054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_6_4_1_reg_7989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_5_4_1_reg_7924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_4_4_1_reg_7859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_7_4_reg_7534;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_6_4_reg_7469;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_5_4_reg_7404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_4_4_reg_7339;
else
grp_fu_1063_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169, ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234, ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324, ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624, ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819, ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884, ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949, ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169;
else
grp_fu_1063_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_5_reg_7344, tmp_20_5_5_reg_7409, ap_enable_reg_pp0_iter4, tmp_20_6_5_reg_7474, tmp_20_7_5_reg_7539, ap_enable_reg_pp0_iter5, tmp_20_4_5_1_reg_7864, tmp_20_5_5_1_reg_7929, tmp_20_6_5_1_reg_7994, ap_enable_reg_pp0_iter6, tmp_20_7_5_1_reg_8059, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_7_5_1_reg_8059;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_6_5_1_reg_7994;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_5_5_1_reg_7929;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_4_5_1_reg_7864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_7_5_reg_7539;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_6_5_reg_7474;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_5_5_reg_7409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_4_5_reg_7344;
else
grp_fu_1067_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174, ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239, ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334, ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629, ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824, ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889, ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954, ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174;
else
grp_fu_1067_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_6_reg_7349, tmp_20_5_6_reg_7414, ap_enable_reg_pp0_iter4, tmp_20_6_6_reg_7479, tmp_20_7_6_reg_7544, ap_enable_reg_pp0_iter5, tmp_20_4_6_1_reg_7869, tmp_20_5_6_1_reg_7934, tmp_20_6_6_1_reg_7999, ap_enable_reg_pp0_iter6, tmp_20_7_6_1_reg_8064, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_7_6_1_reg_8064;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_6_6_1_reg_7999;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_5_6_1_reg_7934;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_4_6_1_reg_7869;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_7_6_reg_7544;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_6_6_reg_7479;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_5_6_reg_7414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_4_6_reg_7349;
else
grp_fu_1071_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179, ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244, ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344, ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634, ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829, ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894, ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959, ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179;
else
grp_fu_1071_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_7_reg_7354, tmp_20_5_7_reg_7419, ap_enable_reg_pp0_iter4, tmp_20_6_7_reg_7484, tmp_20_7_7_reg_7549, ap_enable_reg_pp0_iter5, tmp_20_4_7_1_reg_7874, tmp_20_5_7_1_reg_7939, tmp_20_6_7_1_reg_8004, ap_enable_reg_pp0_iter6, tmp_20_7_7_1_reg_8069, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_7_7_1_reg_8069;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_6_7_1_reg_8004;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_5_7_1_reg_7939;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_4_7_1_reg_7874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_7_7_reg_7549;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_6_7_reg_7484;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_5_7_reg_7419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_4_7_reg_7354;
else
grp_fu_1075_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184, ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249, ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354, ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639, ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834, ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899, ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964, ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184;
else
grp_fu_1075_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_8_reg_7359, tmp_20_5_8_reg_7424, ap_enable_reg_pp0_iter4, tmp_20_6_8_reg_7489, tmp_20_7_8_reg_7554, ap_enable_reg_pp0_iter5, tmp_20_4_8_1_reg_7879, tmp_20_5_8_1_reg_7944, tmp_20_6_8_1_reg_8009, ap_enable_reg_pp0_iter6, tmp_20_7_8_1_reg_8074, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_7_8_1_reg_8074;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_6_8_1_reg_8009;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_5_8_1_reg_7944;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_4_8_1_reg_7879;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_7_8_reg_7554;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_6_8_reg_7489;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_5_8_reg_7424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_4_8_reg_7359;
else
grp_fu_1079_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189, ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254, ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364, ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644, ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839, ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904, ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969, ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189;
else
grp_fu_1079_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_9_reg_7364, tmp_20_5_9_reg_7429, ap_enable_reg_pp0_iter4, tmp_20_6_9_reg_7494, tmp_20_7_9_reg_7559, ap_enable_reg_pp0_iter5, tmp_20_4_9_1_reg_7884, tmp_20_5_9_1_reg_7949, tmp_20_6_9_1_reg_8014, ap_enable_reg_pp0_iter6, tmp_20_7_9_1_reg_8079, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_7_9_1_reg_8079;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_6_9_1_reg_8014;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_5_9_1_reg_7949;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_4_9_1_reg_7884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_7_9_reg_7559;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_6_9_reg_7494;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_5_9_reg_7429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_4_9_reg_7364;
else
grp_fu_1083_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194, ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259, ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374, ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649, ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844, ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909, ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974, ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194;
else
grp_fu_1083_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_s_reg_7369, tmp_20_5_s_reg_7434, ap_enable_reg_pp0_iter4, tmp_20_6_s_reg_7499, tmp_20_7_s_reg_7564, ap_enable_reg_pp0_iter5, tmp_20_4_10_1_reg_7889, tmp_20_5_10_1_reg_7954, tmp_20_6_10_1_reg_8019, ap_enable_reg_pp0_iter6, tmp_20_7_10_1_reg_8084, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_7_10_1_reg_8084;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_6_10_1_reg_8019;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_5_10_1_reg_7954;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_4_10_1_reg_7889;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_7_s_reg_7564;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_6_s_reg_7499;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_5_s_reg_7434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_4_s_reg_7369;
else
grp_fu_1087_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199, ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264, ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384, ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654, ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849, ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914, ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979, ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199;
else
grp_fu_1087_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_10_reg_7374, tmp_20_5_10_reg_7439, ap_enable_reg_pp0_iter4, tmp_20_6_10_reg_7504, tmp_20_7_10_reg_7569, ap_enable_reg_pp0_iter5, tmp_20_4_11_1_reg_7894, tmp_20_5_11_1_reg_7959, tmp_20_6_11_1_reg_8024, ap_enable_reg_pp0_iter6, tmp_20_7_11_1_reg_8089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_7_11_1_reg_8089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_6_11_1_reg_8024;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_5_11_1_reg_7959;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_4_11_1_reg_7894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_7_10_reg_7569;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_6_10_reg_7504;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_5_10_reg_7439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_4_10_reg_7374;
else
grp_fu_1091_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204, ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269, ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394, ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659, ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854, ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919, ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984, ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204;
else
grp_fu_1091_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_11_reg_7379, tmp_20_5_11_reg_7444, ap_enable_reg_pp0_iter4, tmp_20_6_11_reg_7509, tmp_20_7_11_reg_7574, ap_enable_reg_pp0_iter5, tmp_20_4_12_1_reg_7899, tmp_20_5_12_1_reg_7964, tmp_20_6_12_1_reg_8029, ap_enable_reg_pp0_iter6, tmp_20_7_12_1_reg_8094, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_7_12_1_reg_8094;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_6_12_1_reg_8029;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_5_12_1_reg_7964;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_4_12_1_reg_7899;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_7_11_reg_7574;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_6_11_reg_7509;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_5_11_reg_7444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_4_11_reg_7379;
else
grp_fu_1095_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209, ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274, ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404, ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664, ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859, ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924, ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989, ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209;
else
grp_fu_1095_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1099_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1099_p0 <= bufw_0_load_1_reg_3710;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1099_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1099_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1099_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1099_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1099_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1099_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1099_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1099_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_1_reg_3710, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1103_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1103_p0 <= bufw_1_load_1_reg_3759;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p0 <= bufw_0_load_1_reg_3710;
else
grp_fu_1103_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1103_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1103_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1103_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1103_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1103_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1103_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1103_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1107_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1107_p0 <= bufw_2_load_1_reg_3774;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1107_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1107_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1107_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1107_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1107_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1107_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1107_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1107_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_1_reg_3759, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1111_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1111_p0 <= bufw_3_load_1_reg_3789;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p0 <= bufw_1_load_1_reg_3759;
else
grp_fu_1111_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1111_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1111_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1111_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1111_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1111_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1111_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1111_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1115_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1115_p0 <= bufw_4_load_1_reg_3804;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1115_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1115_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1115_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1115_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1115_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1115_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1115_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1115_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_1_reg_3774, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1119_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1119_p0 <= bufw_5_load_1_reg_3819;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p0 <= bufw_2_load_1_reg_3774;
else
grp_fu_1119_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1119_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1119_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1119_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1119_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1119_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1119_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1119_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1123_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1123_p0 <= bufw_6_load_1_reg_3834;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1123_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1123_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1123_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1123_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1123_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1123_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1123_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1123_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_1_reg_3789, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1127_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1127_p0 <= bufw_7_load_1_reg_3849;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p0 <= bufw_3_load_1_reg_3789;
else
grp_fu_1127_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1127_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1127_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1127_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1127_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1127_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1127_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1127_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1131_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1131_p0 <= bufw_8_load_1_reg_3864;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1131_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1131_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1131_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1131_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1131_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1131_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1131_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1131_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_1_reg_3804, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1135_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1135_p0 <= bufw_9_load_1_reg_3879;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p0 <= bufw_4_load_1_reg_3804;
else
grp_fu_1135_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1135_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1135_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1135_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1135_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1135_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1135_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1135_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1139_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1139_p0 <= bufw_10_load_1_reg_3894;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1139_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1139_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1139_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1139_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1139_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1139_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1139_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1139_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_1_reg_3819, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1143_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1143_p0 <= bufw_11_load_1_reg_3909;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p0 <= bufw_5_load_1_reg_3819;
else
grp_fu_1143_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1143_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1143_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1143_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1143_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1143_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1143_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1143_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1147_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1147_p0 <= bufw_12_load_1_reg_3924;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1147_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1147_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1147_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1147_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1147_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1147_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1147_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1147_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_6_load_1_reg_3834, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1151_p0 <= bufw_0_load_2_reg_4012;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1151_p0 <= bufw_0_load_reg_3686;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p0 <= bufw_6_load_1_reg_3834;
else
grp_fu_1151_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1151_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1151_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1151_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1151_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1151_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1151_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, bufw_7_load_reg_3842, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1155_p0 <= bufw_1_load_2_reg_4019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1155_p0 <= bufw_1_load_reg_3752;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1155_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1155_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1155_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1155_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1155_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1155_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1155_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1159_p0 <= bufw_2_load_2_reg_4026;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1159_p0 <= bufw_2_load_reg_3767;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p0 <= bufw_7_load_1_reg_3849;
else
grp_fu_1159_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1159_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1159_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1159_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1159_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1159_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1159_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, bufw_8_load_reg_3857, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1163_p0 <= bufw_3_load_2_reg_4033;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1163_p0 <= bufw_3_load_reg_3782;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1163_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1163_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1163_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1163_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1163_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1163_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1163_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1167_p0 <= bufw_4_load_2_reg_4040;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1167_p0 <= bufw_4_load_reg_3797;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p0 <= bufw_8_load_1_reg_3864;
else
grp_fu_1167_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1167_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1167_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1167_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1167_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1167_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1167_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, bufw_9_load_reg_3872, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1171_p0 <= bufw_5_load_2_reg_4047;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1171_p0 <= bufw_5_load_reg_3812;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1171_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1171_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1171_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1171_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1171_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1171_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1171_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1175_p0 <= bufw_6_load_2_reg_4054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1175_p0 <= bufw_6_load_reg_3827;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p0 <= bufw_9_load_1_reg_3879;
else
grp_fu_1175_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1175_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1175_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1175_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1175_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1175_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1175_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, bufw_10_load_reg_3887, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1179_p0 <= bufw_7_load_2_reg_4061;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1179_p0 <= bufw_7_load_reg_3842;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1179_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1179_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1179_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1179_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1179_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1179_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1179_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1183_p0 <= bufw_8_load_2_reg_4068;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1183_p0 <= bufw_8_load_reg_3857;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p0 <= bufw_10_load_1_reg_3894;
else
grp_fu_1183_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1183_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1183_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1183_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1183_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1183_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1183_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, bufw_11_load_reg_3902, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1187_p0 <= bufw_9_load_2_reg_4075;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1187_p0 <= bufw_9_load_reg_3872;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1187_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1187_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1187_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1187_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1187_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1187_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1187_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1191_p0 <= bufw_10_load_2_reg_4082;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1191_p0 <= bufw_10_load_reg_3887;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p0 <= bufw_11_load_1_reg_3909;
else
grp_fu_1191_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1191_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1191_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1191_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1191_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1191_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1191_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, bufw_12_load_reg_3917, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1195_p0 <= bufw_11_load_2_reg_4089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1195_p0 <= bufw_11_load_reg_3902;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1195_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1195_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1195_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1195_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1195_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1195_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1195_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1199_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1199_p0 <= bufw_12_load_reg_3917;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1199_p0 <= bufw_12_load_1_reg_3924;
else
grp_fu_1199_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1199_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1199_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1199_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1199_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1199_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1199_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1199_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1199_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1203_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1203_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1203_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1203_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1203_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1203_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1203_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1203_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1203_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1203_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1203_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1203_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1207_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1207_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1207_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1207_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1207_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1207_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1207_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1207_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1207_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1207_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1207_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1207_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1211_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1211_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1211_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1211_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1211_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1211_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1211_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1211_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1211_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1211_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1211_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1211_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1215_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1215_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1215_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1215_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1215_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1215_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1215_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1215_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1215_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1215_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1215_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1215_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1219_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1219_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1219_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1219_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1219_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1219_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1219_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1219_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1219_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1219_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1219_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1219_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1223_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1223_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1223_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1223_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1223_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1223_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1223_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1223_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1223_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1223_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1223_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1223_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1227_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1227_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1227_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1227_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1227_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1227_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1227_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1227_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1227_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1227_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1227_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1227_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1231_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1231_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1231_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1231_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1231_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1231_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1231_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1231_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1231_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1231_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1231_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1231_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1235_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1235_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1235_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1235_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1235_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1235_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1235_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1235_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1235_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1235_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1235_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1235_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1239_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1239_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1239_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1239_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1239_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1239_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1239_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1239_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1239_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1239_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1239_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1239_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1243_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1243_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1243_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1243_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1243_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1243_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1243_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1243_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1243_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1243_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1243_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1243_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1247_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1247_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1247_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1247_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1247_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1247_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1247_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1247_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1247_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1247_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1247_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1247_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1251_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1251_p0 <= bufw_12_load_1_reg_3924;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1251_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1251_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1251_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1251_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1251_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1251_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1251_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1251_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1251_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1251_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1255_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1265_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1275_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1285_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1295_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1305_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1315_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1325_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1335_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1345_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1355_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1365_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1375_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1385_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1395_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1405_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1415_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1425_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1435_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1445_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1455_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1465_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1475_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1485_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_943_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_11_fu_2165_p1, ap_enable_reg_pp0_iter2, tmp_91_fu_2269_p1, tmp_171_fu_2373_p1, tmp_251_fu_2477_p1, tmp_351_reg_7059, ap_enable_reg_pp0_iter3, tmp_20_2_reg_7189, tmp_20_0_0_1_reg_7579, ap_enable_reg_pp0_iter5, tmp_20_2_0_1_reg_7709, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_2_0_1_reg_7709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_0_0_1_reg_7579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_20_2_reg_7189;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_351_reg_7059;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_251_fu_2477_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_171_fu_2373_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_91_fu_2269_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_11_fu_2165_p1;
else
grp_fu_943_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_943_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_349_reg_4849, ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854, ap_enable_reg_pp0_iter2, tmp_19_2_reg_5369, ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504, tmp_19_4_reg_5694, tmp_19_6_reg_6019, ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474, ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_6_reg_6019;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_4_reg_5694;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_2_reg_5369;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_349_reg_4849;
else
grp_fu_943_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_14_fu_2169_p1, ap_enable_reg_pp0_iter2, tmp_94_fu_2273_p1, tmp_174_fu_2377_p1, tmp_254_fu_2481_p1, ap_enable_reg_pp0_iter3, tmp_20_0_1_reg_7064, tmp_20_2_1_reg_7194, ap_enable_reg_pp0_iter5, tmp_20_0_1_1_reg_7584, tmp_20_2_1_1_reg_7714, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_2_1_1_reg_7714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_0_1_1_reg_7584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_2_1_reg_7194;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_0_1_reg_7064;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_254_fu_2481_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_174_fu_2377_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_94_fu_2273_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_14_fu_2169_p1;
else
grp_fu_947_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_1_reg_4859, ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864, ap_enable_reg_pp0_iter2, tmp_19_2_1_reg_5374, ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514, tmp_19_4_1_reg_5699, tmp_19_6_1_reg_6024, ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479, ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_6_1_reg_6024;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_4_1_reg_5699;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_2_1_reg_5374;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_0_1_reg_4859;
else
grp_fu_947_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_17_fu_2173_p1, ap_enable_reg_pp0_iter2, tmp_97_fu_2277_p1, tmp_177_fu_2381_p1, tmp_257_fu_2485_p1, ap_enable_reg_pp0_iter3, tmp_20_0_2_reg_7069, tmp_20_2_2_reg_7199, ap_enable_reg_pp0_iter5, tmp_20_0_2_1_reg_7589, tmp_20_2_2_1_reg_7719, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_2_2_1_reg_7719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_0_2_1_reg_7589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_2_2_reg_7199;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_0_2_reg_7069;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_257_fu_2485_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_177_fu_2381_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_97_fu_2277_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_17_fu_2173_p1;
else
grp_fu_951_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_2_reg_4869, ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874, ap_enable_reg_pp0_iter2, tmp_19_2_2_reg_5379, ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524, tmp_19_4_2_reg_5704, tmp_19_6_2_reg_6029, ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484, ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_6_2_reg_6029;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_4_2_reg_5704;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_2_2_reg_5379;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_0_2_reg_4869;
else
grp_fu_951_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_fu_2177_p1, ap_enable_reg_pp0_iter2, tmp_100_fu_2281_p1, tmp_180_fu_2385_p1, tmp_260_fu_2489_p1, ap_enable_reg_pp0_iter3, tmp_20_0_3_reg_7074, tmp_20_2_3_reg_7204, ap_enable_reg_pp0_iter5, tmp_20_0_3_1_reg_7594, tmp_20_2_3_1_reg_7724, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_2_3_1_reg_7724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_0_3_1_reg_7594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_2_3_reg_7204;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_0_3_reg_7074;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_260_fu_2489_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_180_fu_2385_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_100_fu_2281_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_20_fu_2177_p1;
else
grp_fu_955_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_3_reg_4879, ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884, ap_enable_reg_pp0_iter2, tmp_19_2_3_reg_5384, ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534, tmp_19_4_3_reg_5709, tmp_19_6_3_reg_6034, ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489, ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_6_3_reg_6034;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_4_3_reg_5709;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_2_3_reg_5384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_0_3_reg_4879;
else
grp_fu_955_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_23_fu_2181_p1, ap_enable_reg_pp0_iter2, tmp_103_fu_2285_p1, tmp_183_fu_2389_p1, tmp_263_fu_2493_p1, ap_enable_reg_pp0_iter3, tmp_20_0_4_reg_7079, tmp_20_2_4_reg_7209, ap_enable_reg_pp0_iter5, tmp_20_0_4_1_reg_7599, tmp_20_2_4_1_reg_7729, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_2_4_1_reg_7729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_0_4_1_reg_7599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_2_4_reg_7209;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_0_4_reg_7079;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_263_fu_2493_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_183_fu_2389_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_103_fu_2285_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_23_fu_2181_p1;
else
grp_fu_959_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_4_reg_4889, ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894, ap_enable_reg_pp0_iter2, tmp_19_2_4_reg_5389, ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544, tmp_19_4_4_reg_5714, tmp_19_6_4_reg_6039, ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494, ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_6_4_reg_6039;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_4_4_reg_5714;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_2_4_reg_5389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_0_4_reg_4889;
else
grp_fu_959_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_26_fu_2185_p1, ap_enable_reg_pp0_iter2, tmp_106_fu_2289_p1, tmp_186_fu_2393_p1, tmp_266_fu_2497_p1, ap_enable_reg_pp0_iter3, tmp_20_0_5_reg_7084, tmp_20_2_5_reg_7214, ap_enable_reg_pp0_iter5, tmp_20_0_5_1_reg_7604, tmp_20_2_5_1_reg_7734, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_2_5_1_reg_7734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_0_5_1_reg_7604;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_2_5_reg_7214;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_0_5_reg_7084;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_266_fu_2497_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_186_fu_2393_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_106_fu_2289_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_26_fu_2185_p1;
else
grp_fu_963_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_5_reg_4899, ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904, ap_enable_reg_pp0_iter2, tmp_19_2_5_reg_5394, ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554, tmp_19_4_5_reg_5719, tmp_19_6_5_reg_6044, ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499, ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_6_5_reg_6044;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_4_5_reg_5719;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_2_5_reg_5394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_0_5_reg_4899;
else
grp_fu_963_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_29_fu_2189_p1, ap_enable_reg_pp0_iter2, tmp_109_fu_2293_p1, tmp_189_fu_2397_p1, tmp_269_fu_2501_p1, ap_enable_reg_pp0_iter3, tmp_20_0_6_reg_7089, tmp_20_2_6_reg_7219, ap_enable_reg_pp0_iter5, tmp_20_0_6_1_reg_7609, tmp_20_2_6_1_reg_7739, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_2_6_1_reg_7739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_0_6_1_reg_7609;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_2_6_reg_7219;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_0_6_reg_7089;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_269_fu_2501_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_189_fu_2397_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_109_fu_2293_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_29_fu_2189_p1;
else
grp_fu_967_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_6_reg_4909, ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914, ap_enable_reg_pp0_iter2, tmp_19_2_6_reg_5399, ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564, tmp_19_4_6_reg_5724, tmp_19_6_6_reg_6049, ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504, ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_6_6_reg_6049;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_4_6_reg_5724;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_2_6_reg_5399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_0_6_reg_4909;
else
grp_fu_967_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_32_fu_2193_p1, ap_enable_reg_pp0_iter2, tmp_112_fu_2297_p1, tmp_192_fu_2401_p1, tmp_272_fu_2505_p1, ap_enable_reg_pp0_iter3, tmp_20_0_7_reg_7094, tmp_20_2_7_reg_7224, ap_enable_reg_pp0_iter5, tmp_20_0_7_1_reg_7614, tmp_20_2_7_1_reg_7744, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_2_7_1_reg_7744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_0_7_1_reg_7614;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_2_7_reg_7224;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_0_7_reg_7094;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_272_fu_2505_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_192_fu_2401_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_112_fu_2297_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_32_fu_2193_p1;
else
grp_fu_971_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_7_reg_4919, ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924, ap_enable_reg_pp0_iter2, tmp_19_2_7_reg_5404, ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574, tmp_19_4_7_reg_5729, tmp_19_6_7_reg_6054, ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509, ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_6_7_reg_6054;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_4_7_reg_5729;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_2_7_reg_5404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_0_7_reg_4919;
else
grp_fu_971_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_35_fu_2197_p1, ap_enable_reg_pp0_iter2, tmp_115_fu_2301_p1, tmp_195_fu_2405_p1, tmp_275_fu_2509_p1, ap_enable_reg_pp0_iter3, tmp_20_0_8_reg_7099, tmp_20_2_8_reg_7229, ap_enable_reg_pp0_iter5, tmp_20_0_8_1_reg_7619, tmp_20_2_8_1_reg_7749, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_2_8_1_reg_7749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_0_8_1_reg_7619;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_2_8_reg_7229;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_0_8_reg_7099;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_275_fu_2509_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_195_fu_2405_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_115_fu_2301_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_35_fu_2197_p1;
else
grp_fu_975_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_8_reg_4929, ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934, ap_enable_reg_pp0_iter2, tmp_19_2_8_reg_5409, ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584, tmp_19_4_8_reg_5734, tmp_19_6_8_reg_6059, ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514, ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_6_8_reg_6059;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_4_8_reg_5734;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_2_8_reg_5409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_0_8_reg_4929;
else
grp_fu_975_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_38_fu_2201_p1, ap_enable_reg_pp0_iter2, tmp_118_fu_2305_p1, tmp_198_fu_2409_p1, tmp_278_fu_2513_p1, ap_enable_reg_pp0_iter3, tmp_20_0_9_reg_7104, tmp_20_2_9_reg_7234, ap_enable_reg_pp0_iter5, tmp_20_0_9_1_reg_7624, tmp_20_2_9_1_reg_7754, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_2_9_1_reg_7754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_0_9_1_reg_7624;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_2_9_reg_7234;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_0_9_reg_7104;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_278_fu_2513_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_198_fu_2409_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_118_fu_2305_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_38_fu_2201_p1;
else
grp_fu_979_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_9_reg_4939, ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944, ap_enable_reg_pp0_iter2, tmp_19_2_9_reg_5414, ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594, tmp_19_4_9_reg_5739, tmp_19_6_9_reg_6064, ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519, ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_6_9_reg_6064;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_4_9_reg_5739;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_2_9_reg_5414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_0_9_reg_4939;
else
grp_fu_979_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_41_fu_2205_p1, ap_enable_reg_pp0_iter2, tmp_121_fu_2309_p1, tmp_201_fu_2413_p1, tmp_281_fu_2517_p1, ap_enable_reg_pp0_iter3, tmp_20_0_s_reg_7109, tmp_20_2_s_reg_7239, ap_enable_reg_pp0_iter5, tmp_20_0_10_1_reg_7629, tmp_20_2_10_1_reg_7759, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_2_10_1_reg_7759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_0_10_1_reg_7629;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_2_s_reg_7239;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_0_s_reg_7109;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_281_fu_2517_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_201_fu_2413_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_121_fu_2309_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_41_fu_2205_p1;
else
grp_fu_983_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_s_reg_4949, ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954, ap_enable_reg_pp0_iter2, tmp_19_2_s_reg_5419, ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604, tmp_19_4_s_reg_5744, tmp_19_6_s_reg_6069, ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524, ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_6_s_reg_6069;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_4_s_reg_5744;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_2_s_reg_5419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_0_s_reg_4949;
else
grp_fu_983_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_44_fu_2209_p1, ap_enable_reg_pp0_iter2, tmp_124_fu_2313_p1, tmp_204_fu_2417_p1, tmp_284_fu_2521_p1, ap_enable_reg_pp0_iter3, tmp_20_0_10_reg_7114, tmp_20_2_10_reg_7244, ap_enable_reg_pp0_iter5, tmp_20_0_11_1_reg_7634, tmp_20_2_11_1_reg_7764, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_2_11_1_reg_7764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_0_11_1_reg_7634;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_2_10_reg_7244;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_0_10_reg_7114;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_284_fu_2521_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_204_fu_2417_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_124_fu_2313_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_44_fu_2209_p1;
else
grp_fu_987_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_10_reg_4959, ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964, ap_enable_reg_pp0_iter2, tmp_19_2_10_reg_5424, ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614, tmp_19_4_10_reg_5749, tmp_19_6_10_reg_6074, ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529, ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_6_10_reg_6074;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_4_10_reg_5749;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_2_10_reg_5424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_0_10_reg_4959;
else
grp_fu_987_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_47_fu_2213_p1, ap_enable_reg_pp0_iter2, tmp_127_fu_2317_p1, tmp_207_fu_2421_p1, tmp_287_fu_2525_p1, ap_enable_reg_pp0_iter3, tmp_20_0_11_reg_7119, tmp_20_2_11_reg_7249, ap_enable_reg_pp0_iter5, tmp_20_0_12_1_reg_7639, tmp_20_2_12_1_reg_7769, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_2_12_1_reg_7769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_0_12_1_reg_7639;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_2_11_reg_7249;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_0_11_reg_7119;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_287_fu_2525_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_207_fu_2421_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_127_fu_2317_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_47_fu_2213_p1;
else
grp_fu_991_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_11_reg_4969, ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974, ap_enable_reg_pp0_iter2, tmp_19_2_11_reg_5429, ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624, tmp_19_4_11_reg_5754, tmp_19_6_11_reg_6079, ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534, ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_6_11_reg_6079;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_4_11_reg_5754;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_2_11_reg_5429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_0_11_reg_4969;
else
grp_fu_991_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_51_fu_2217_p1, ap_enable_reg_pp0_iter2, tmp_131_fu_2321_p1, tmp_211_fu_2425_p1, tmp_291_fu_2529_p1, ap_enable_reg_pp0_iter3, tmp_20_1_reg_7124, tmp_20_3_reg_7254, ap_enable_reg_pp0_iter5, tmp_20_1_0_1_reg_7644, tmp_20_3_0_1_reg_7774, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_3_0_1_reg_7774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_1_0_1_reg_7644;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_3_reg_7254;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_1_reg_7124;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_291_fu_2529_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_211_fu_2425_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_131_fu_2321_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_51_fu_2217_p1;
else
grp_fu_995_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_reg_4979, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244, tmp_19_3_reg_5434, tmp_19_5_reg_5759, ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824, tmp_19_7_reg_6084, ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539, ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_7_reg_6084;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_5_reg_5759;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_3_reg_5434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_1_reg_4979;
else
grp_fu_995_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_54_fu_2221_p1, tmp_134_fu_2325_p1, tmp_214_fu_2429_p1, tmp_294_fu_2533_p1, ap_enable_reg_pp0_iter3, tmp_20_1_1_reg_7129, tmp_20_3_1_reg_7259, ap_enable_reg_pp0_iter5, tmp_20_1_1_1_reg_7649, tmp_20_3_1_1_reg_7779, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_3_1_1_reg_7779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_1_1_1_reg_7649;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_3_1_reg_7259;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_1_1_reg_7129;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_294_fu_2533_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_214_fu_2429_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_134_fu_2325_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_54_fu_2221_p1;
else
grp_fu_999_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_1_reg_4984, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254, tmp_19_3_1_reg_5439, tmp_19_5_1_reg_5764, ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829, tmp_19_7_1_reg_6089, ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544, ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_7_1_reg_6089;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_5_1_reg_5764;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_3_1_reg_5439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_1_1_reg_4984;
else
grp_fu_999_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_1_fu_1553_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(ap_phi_mux_i_phi_fu_900_p4));
indvar_flatten_next1_fu_1547_p2 <= std_logic_vector(unsigned(ap_phi_mux_indvar_flatten1_phi_fu_889_p4) + unsigned(ap_const_lv10_1));
indvar_flatten_next_fu_1613_p3 <=
ap_const_lv8_1 when (exitcond_flatten_reg_3190(0) = '1') else
indvar_flatten_op_reg_3211;
indvar_flatten_op_fu_1571_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(ap_phi_mux_indvar_flatten_phi_fu_912_p4));
j_1_fu_1642_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid_reg_3216));
j_mid_fu_1577_p3 <=
ap_const_lv3_0 when (exitcond_flatten_reg_3190(0) = '1') else
j_reg_919;
not_exitcond_flatten_fu_1590_p2 <= (exitcond_flatten_reg_3190 xor ap_const_lv1_1);
p_shl1_cast_fu_1690_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_50_fu_1683_p3),10));
p_shl2_cast_fu_1629_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1622_p3),6));
p_shl_cast_fu_1679_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_fu_1672_p3),10));
row_b_1_fu_1652_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(row_b_mid2_reg_3245));
row_b_mid2_fu_1605_p3 <=
ap_const_lv5_0 when (tmp_4_fu_1600_p2(0) = '1') else
row_b_reg_931;
tmp_100_fu_2281_p1 <= tmp_99_reg_4604;
tmp_101_fu_2730_p1 <= tmp_20_2_3_2_reg_8244;
tmp_103_fu_2285_p1 <= tmp_102_reg_4609;
tmp_104_fu_2733_p1 <= tmp_20_2_4_2_reg_8249;
tmp_106_fu_2289_p1 <= tmp_105_reg_4614;
tmp_107_fu_2736_p1 <= tmp_20_2_5_2_reg_8254;
tmp_109_fu_2293_p1 <= tmp_108_reg_4619;
tmp_10_fu_1672_p3 <= (tmp_s_reg_3270 & ap_const_lv4_0);
tmp_110_fu_2739_p1 <= tmp_20_2_6_2_reg_8259;
tmp_112_fu_2297_p1 <= tmp_111_reg_4624;
tmp_113_fu_2742_p1 <= tmp_20_2_7_2_reg_8264;
tmp_115_fu_2301_p1 <= tmp_114_reg_4629;
tmp_116_fu_2745_p1 <= tmp_20_2_8_2_reg_8269;
tmp_118_fu_2305_p1 <= tmp_117_reg_4634;
tmp_119_fu_2748_p1 <= tmp_20_2_9_2_reg_8274;
tmp_11_fu_2165_p1 <= tmp_350_reg_4449;
tmp_121_fu_2309_p1 <= tmp_120_reg_4639;
tmp_122_fu_2751_p1 <= tmp_20_2_10_2_reg_8279;
tmp_124_fu_2313_p1 <= tmp_123_reg_4644;
tmp_125_fu_2754_p1 <= tmp_20_2_11_2_reg_8284;
tmp_127_fu_2317_p1 <= tmp_126_reg_4649;
tmp_128_fu_2757_p1 <= tmp_20_2_12_2_reg_8289;
tmp_129_fu_2760_p14 <= ((((((((((((tmp_128_fu_2757_p1 & tmp_125_fu_2754_p1) & tmp_122_fu_2751_p1) & tmp_119_fu_2748_p1) & tmp_116_fu_2745_p1) & tmp_113_fu_2742_p1) & tmp_110_fu_2739_p1) & tmp_107_fu_2736_p1) & tmp_104_fu_2733_p1) & tmp_101_fu_2730_p1) & tmp_98_fu_2727_p1) & tmp_95_fu_2724_p1) & tmp_92_fu_2721_p1);
tmp_12_1_fu_1499_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_1));
tmp_12_1_mid1_fu_1667_p2 <= std_logic_vector(unsigned(ap_const_lv3_2) + unsigned(j_mid_reg_3216));
tmp_12_2_fu_1505_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_2));
tmp_12_2_mid1_fu_1748_p2 <= std_logic_vector(unsigned(ap_const_lv3_3) + unsigned(j_mid_reg_3216));
tmp_12_3_fu_1511_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_3));
tmp_12_3_mid1_fu_1824_p2 <= (j_mid_reg_3216 xor ap_const_lv3_4);
tmp_12_4_fu_1517_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_4));
tmp_12_4_mid1_fu_1840_p2 <= std_logic_vector(unsigned(ap_const_lv4_4) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_5_fu_1523_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_5));
tmp_12_5_mid1_fu_1846_p2 <= std_logic_vector(unsigned(ap_const_lv4_5) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_6_fu_1529_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_6));
tmp_12_6_mid1_fu_1852_p2 <= std_logic_vector(unsigned(ap_const_lv4_6) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_7_fu_1535_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_7));
tmp_12_7_mid1_fu_1858_p2 <= std_logic_vector(unsigned(ap_const_lv4_7) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_fu_2581_p1 <= tmp_20_0_0_2_reg_8099;
tmp_130_fu_1753_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_5_mid2_cast1_fu_1718_p1));
tmp_131_fu_2321_p1 <= tmp_354_reg_4654;
tmp_132_fu_2791_p1 <= tmp_20_3_0_2_reg_8294;
tmp_134_fu_2325_p1 <= tmp_133_reg_4659;
tmp_135_fu_2794_p1 <= tmp_20_3_1_2_reg_8299;
tmp_137_fu_2329_p1 <= tmp_136_reg_4664;
tmp_138_fu_2797_p1 <= tmp_20_3_2_2_reg_8304;
tmp_13_1_mid2_cast_fu_1744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_1_mid2_fu_1738_p3),10));
tmp_13_1_mid2_fu_1738_p3 <=
tmp_12_1_mid1_reg_3294 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_1_mid_fu_1712_p3;
tmp_13_1_mid_fu_1712_p3 <=
ap_const_lv3_1 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_1_reg_3141;
tmp_13_2_mid2_cast_fu_1820_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_2_mid2_fu_1814_p3),10));
tmp_13_2_mid2_fu_1814_p3 <=
tmp_12_2_mid1_reg_3331 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_2_mid_fu_1763_p3;
tmp_13_2_mid_fu_1763_p3 <=
ap_const_lv3_2 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_2_reg_3146;
tmp_13_3_mid2_cast_fu_1836_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_3_mid2_fu_1829_p3),10));
tmp_13_3_mid2_fu_1829_p3 <=
tmp_12_3_mid1_fu_1824_p2 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_3_mid_fu_1769_p3;
tmp_13_3_mid_fu_1769_p3 <=
ap_const_lv3_3 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_3_reg_3151;
tmp_13_4_mid2_cast_fu_1932_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_4_mid2_fu_1926_p3),10));
tmp_13_4_mid2_fu_1926_p3 <=
tmp_12_4_mid1_reg_3481 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_4_mid_fu_1886_p3;
tmp_13_4_mid_fu_1886_p3 <=
ap_const_lv4_4 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_4_reg_3156;
tmp_13_5_mid2_cast_fu_1942_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_5_mid2_fu_1936_p3),10));
tmp_13_5_mid2_fu_1936_p3 <=
tmp_12_5_mid1_reg_3486 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_5_mid_fu_1892_p3;
tmp_13_5_mid_fu_1892_p3 <=
ap_const_lv4_5 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_5_reg_3161;
tmp_13_6_mid2_cast_fu_1952_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_6_mid2_fu_1946_p3),10));
tmp_13_6_mid2_fu_1946_p3 <=
tmp_12_6_mid1_reg_3491 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_6_mid_fu_1898_p3;
tmp_13_6_mid_fu_1898_p3 <=
ap_const_lv4_6 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_6_reg_3166;
tmp_13_7_mid2_cast_fu_1962_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_7_mid2_fu_1956_p3),10));
tmp_13_7_mid2_fu_1956_p3 <=
tmp_12_7_mid1_reg_3496 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_7_mid_fu_1904_p3;
tmp_13_7_mid_fu_1904_p3 <=
ap_const_lv4_7 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_7_reg_3171;
tmp_140_fu_2333_p1 <= tmp_139_reg_4669;
tmp_141_fu_2800_p1 <= tmp_20_3_3_2_reg_8309;
tmp_143_fu_2337_p1 <= tmp_142_reg_4674;
tmp_144_fu_2803_p1 <= tmp_20_3_4_2_reg_8314;
tmp_146_fu_2341_p1 <= tmp_145_reg_4679;
tmp_147_fu_2806_p1 <= tmp_20_3_5_2_reg_8319;
tmp_149_fu_2345_p1 <= tmp_148_reg_4684;
tmp_14_fu_2169_p1 <= tmp_13_reg_4454;
tmp_150_fu_2809_p1 <= tmp_20_3_6_2_reg_8324;
tmp_152_fu_2349_p1 <= tmp_151_reg_4689;
tmp_153_fu_2812_p1 <= tmp_20_3_7_2_reg_8329;
tmp_155_fu_2353_p1 <= tmp_154_reg_4694;
tmp_156_fu_2815_p1 <= tmp_20_3_8_2_reg_8334;
tmp_158_fu_2357_p1 <= tmp_157_reg_4699;
tmp_159_fu_2818_p1 <= tmp_20_3_9_2_reg_8339;
tmp_15_fu_2584_p1 <= tmp_20_0_1_2_reg_8104;
tmp_161_fu_2361_p1 <= tmp_160_reg_4704;
tmp_162_fu_2821_p1 <= tmp_20_3_10_2_reg_8344;
tmp_164_fu_2365_p1 <= tmp_163_reg_4709;
tmp_165_fu_2824_p1 <= tmp_20_3_11_2_reg_8349;
tmp_167_fu_2369_p1 <= tmp_166_reg_4714;
tmp_168_fu_2827_p1 <= tmp_20_3_12_2_reg_8354;
tmp_169_fu_2830_p14 <= ((((((((((((tmp_168_fu_2827_p1 & tmp_165_fu_2824_p1) & tmp_162_fu_2821_p1) & tmp_159_fu_2818_p1) & tmp_156_fu_2815_p1) & tmp_153_fu_2812_p1) & tmp_150_fu_2809_p1) & tmp_147_fu_2806_p1) & tmp_144_fu_2803_p1) & tmp_141_fu_2800_p1) & tmp_138_fu_2797_p1) & tmp_135_fu_2794_p1) & tmp_132_fu_2791_p1);
tmp_170_fu_1758_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_1_mid2_cast_fu_1744_p1));
tmp_171_fu_2373_p1 <= tmp_355_reg_4719;
tmp_172_fu_2861_p1 <= tmp_20_4_0_2_reg_8359;
tmp_174_fu_2377_p1 <= tmp_173_reg_4724;
tmp_175_fu_2864_p1 <= tmp_20_4_1_2_reg_8364;
tmp_177_fu_2381_p1 <= tmp_176_reg_4729;
tmp_178_fu_2867_p1 <= tmp_20_4_2_2_reg_8369;
tmp_17_fu_2173_p1 <= tmp_16_reg_4459;
tmp_180_fu_2385_p1 <= tmp_179_reg_4734;
tmp_181_fu_2870_p1 <= tmp_20_4_3_2_reg_8374;
tmp_183_fu_2389_p1 <= tmp_182_reg_4739;
tmp_184_fu_2873_p1 <= tmp_20_4_4_2_reg_8379;
tmp_186_fu_2393_p1 <= tmp_185_reg_4744;
tmp_187_fu_2876_p1 <= tmp_20_4_5_2_reg_8384;
tmp_189_fu_2397_p1 <= tmp_188_reg_4749;
tmp_18_fu_2587_p1 <= tmp_20_0_2_2_reg_8109;
tmp_190_fu_2879_p1 <= tmp_20_4_6_2_reg_8389;
tmp_192_fu_2401_p1 <= tmp_191_reg_4754;
tmp_193_fu_2882_p1 <= tmp_20_4_7_2_reg_8394;
tmp_195_fu_2405_p1 <= tmp_194_reg_4759;
tmp_196_fu_2885_p1 <= tmp_20_4_8_2_reg_8399;
tmp_198_fu_2409_p1 <= tmp_197_reg_4764;
tmp_199_fu_2888_p1 <= tmp_20_4_9_2_reg_8404;
tmp_1_cast_fu_1700_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_reg_3257),7));
tmp_1_fu_1633_p2 <= std_logic_vector(unsigned(tmp_1_mid2_cast_fu_1619_p1) + unsigned(p_shl2_cast_fu_1629_p1));
tmp_1_mid2_cast_fu_1619_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),6));
tmp_1_mid2_v_fu_1584_p3 <=
i_1_reg_3185 when (exitcond_flatten_reg_3190(0) = '1') else
i_reg_896;
tmp_201_fu_2413_p1 <= tmp_200_reg_4769;
tmp_202_fu_2891_p1 <= tmp_20_4_10_2_reg_8409;
tmp_204_fu_2417_p1 <= tmp_203_reg_4774;
tmp_205_fu_2894_p1 <= tmp_20_4_11_2_reg_8414;
tmp_207_fu_2421_p1 <= tmp_206_reg_4779;
tmp_208_fu_2897_p1 <= tmp_20_4_12_2_reg_8419;
tmp_209_fu_2900_p14 <= ((((((((((((tmp_208_fu_2897_p1 & tmp_205_fu_2894_p1) & tmp_202_fu_2891_p1) & tmp_199_fu_2888_p1) & tmp_196_fu_2885_p1) & tmp_193_fu_2882_p1) & tmp_190_fu_2879_p1) & tmp_187_fu_2876_p1) & tmp_184_fu_2873_p1) & tmp_181_fu_2870_p1) & tmp_178_fu_2867_p1) & tmp_175_fu_2864_p1) & tmp_172_fu_2861_p1);
tmp_20_fu_2177_p1 <= tmp_19_reg_4464;
tmp_210_fu_1876_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_2_mid2_cast_fu_1820_p1));
tmp_211_fu_2425_p1 <= tmp_356_reg_4784;
tmp_212_fu_2931_p1 <= tmp_20_5_0_2_reg_8424;
tmp_214_fu_2429_p1 <= tmp_213_reg_4789;
tmp_215_fu_2934_p1 <= tmp_20_5_1_2_reg_8429;
tmp_217_fu_2433_p1 <= tmp_216_reg_4794;
tmp_218_fu_2937_p1 <= tmp_20_5_2_2_reg_8434;
tmp_21_fu_2590_p1 <= tmp_20_0_3_2_reg_8114;
tmp_220_fu_2437_p1 <= tmp_219_reg_4799;
tmp_221_fu_2940_p1 <= tmp_20_5_3_2_reg_8439;
tmp_223_fu_2441_p1 <= tmp_222_reg_4804;
tmp_224_fu_2943_p1 <= tmp_20_5_4_2_reg_8444;
tmp_226_fu_2445_p1 <= tmp_225_reg_4809;
tmp_227_fu_2946_p1 <= tmp_20_5_5_2_reg_8449;
tmp_229_fu_2449_p1 <= tmp_228_reg_4814;
tmp_230_fu_2949_p1 <= tmp_20_5_6_2_reg_8454;
tmp_232_fu_2453_p1 <= tmp_231_reg_4819;
tmp_233_fu_2952_p1 <= tmp_20_5_7_2_reg_8459;
tmp_235_fu_2457_p1 <= tmp_234_reg_4824;
tmp_236_fu_2955_p1 <= tmp_20_5_8_2_reg_8464;
tmp_238_fu_2461_p1 <= tmp_237_reg_4829;
tmp_239_fu_2958_p1 <= tmp_20_5_9_2_reg_8469;
tmp_23_fu_2181_p1 <= tmp_22_reg_4469;
tmp_241_fu_2465_p1 <= tmp_240_reg_4834;
tmp_242_fu_2961_p1 <= tmp_20_5_10_2_reg_8474;
tmp_244_fu_2469_p1 <= tmp_243_reg_4839;
tmp_245_fu_2964_p1 <= tmp_20_5_11_2_reg_8479;
tmp_247_fu_2473_p1 <= tmp_246_reg_4844;
tmp_248_fu_2967_p1 <= tmp_20_5_12_2_reg_8484;
tmp_249_fu_2970_p14 <= ((((((((((((tmp_248_fu_2967_p1 & tmp_245_fu_2964_p1) & tmp_242_fu_2961_p1) & tmp_239_fu_2958_p1) & tmp_236_fu_2955_p1) & tmp_233_fu_2952_p1) & tmp_230_fu_2949_p1) & tmp_227_fu_2946_p1) & tmp_224_fu_2943_p1) & tmp_221_fu_2940_p1) & tmp_218_fu_2937_p1) & tmp_215_fu_2934_p1) & tmp_212_fu_2931_p1);
tmp_24_fu_2593_p1 <= tmp_20_0_4_2_reg_8119;
tmp_250_fu_1881_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_3_mid2_cast_fu_1836_p1));
tmp_251_fu_2477_p1 <= tmp_357_reg_5044;
tmp_252_fu_3001_p1 <= tmp_20_6_0_2_reg_8489;
tmp_254_fu_2481_p1 <= tmp_253_reg_5049;
tmp_255_fu_3004_p1 <= tmp_20_6_1_2_reg_8494;
tmp_257_fu_2485_p1 <= tmp_256_reg_5054;
tmp_258_fu_3007_p1 <= tmp_20_6_2_2_reg_8499;
tmp_260_fu_2489_p1 <= tmp_259_reg_5059;
tmp_261_fu_3010_p1 <= tmp_20_6_3_2_reg_8504;
tmp_263_fu_2493_p1 <= tmp_262_reg_5064;
tmp_264_fu_3013_p1 <= tmp_20_6_4_2_reg_8509;
tmp_266_fu_2497_p1 <= tmp_265_reg_5069;
tmp_267_fu_3016_p1 <= tmp_20_6_5_2_reg_8514;
tmp_269_fu_2501_p1 <= tmp_268_reg_5074;
tmp_26_fu_2185_p1 <= tmp_25_reg_4474;
tmp_270_fu_3019_p1 <= tmp_20_6_6_2_reg_8519;
tmp_272_fu_2505_p1 <= tmp_271_reg_5079;
tmp_273_fu_3022_p1 <= tmp_20_6_7_2_reg_8524;
tmp_275_fu_2509_p1 <= tmp_274_reg_5084;
tmp_276_fu_3025_p1 <= tmp_20_6_8_2_reg_8529;
tmp_278_fu_2513_p1 <= tmp_277_reg_5089;
tmp_279_fu_3028_p1 <= tmp_20_6_9_2_reg_8534;
tmp_27_fu_2596_p1 <= tmp_20_0_5_2_reg_8124;
tmp_281_fu_2517_p1 <= tmp_280_reg_5094;
tmp_282_fu_3031_p1 <= tmp_20_6_10_2_reg_8539;
tmp_284_fu_2521_p1 <= tmp_283_reg_5099;
tmp_285_fu_3034_p1 <= tmp_20_6_11_2_reg_8544;
tmp_287_fu_2525_p1 <= tmp_286_reg_5104;
tmp_288_fu_3037_p1 <= tmp_20_6_12_2_reg_8549;
tmp_289_fu_3040_p14 <= ((((((((((((tmp_288_fu_3037_p1 & tmp_285_fu_3034_p1) & tmp_282_fu_3031_p1) & tmp_279_fu_3028_p1) & tmp_276_fu_3025_p1) & tmp_273_fu_3022_p1) & tmp_270_fu_3019_p1) & tmp_267_fu_3016_p1) & tmp_264_fu_3013_p1) & tmp_261_fu_3010_p1) & tmp_258_fu_3007_p1) & tmp_255_fu_3004_p1) & tmp_252_fu_3001_p1);
tmp_290_fu_1978_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_4_mid2_cast_fu_1932_p1));
tmp_291_fu_2529_p1 <= tmp_358_reg_5109;
tmp_292_fu_3071_p1 <= tmp_20_7_0_2_reg_8554;
tmp_294_fu_2533_p1 <= tmp_293_reg_5114;
tmp_295_fu_3074_p1 <= tmp_20_7_1_2_reg_8559;
tmp_297_fu_2537_p1 <= tmp_296_reg_5119;
tmp_298_fu_3077_p1 <= tmp_20_7_2_2_reg_8564;
tmp_29_fu_2189_p1 <= tmp_28_reg_4479;
tmp_2_cast_fu_1703_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3281),7));
tmp_2_cast_mid2_fu_1639_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),5));
tmp_2_fu_1657_p2 <= std_logic_vector(unsigned(ap_const_lv6_19) + unsigned(tmp_1_reg_3257));
tmp_300_fu_2541_p1 <= tmp_299_reg_5124;
tmp_301_fu_3080_p1 <= tmp_20_7_3_2_reg_8569;
tmp_303_fu_2545_p1 <= tmp_302_reg_5129;
tmp_304_fu_3083_p1 <= tmp_20_7_4_2_reg_8574;
tmp_306_fu_2549_p1 <= tmp_305_reg_5134;
tmp_307_fu_3086_p1 <= tmp_20_7_5_2_reg_8579;
tmp_309_fu_2553_p1 <= tmp_308_reg_5139;
tmp_30_fu_2599_p1 <= tmp_20_0_6_2_reg_8129;
tmp_310_fu_3089_p1 <= tmp_20_7_6_2_reg_8584;
tmp_312_fu_2557_p1 <= tmp_311_reg_5144;
tmp_313_fu_3092_p1 <= tmp_20_7_7_2_reg_8589;
tmp_315_fu_2561_p1 <= tmp_314_reg_5149;
tmp_316_fu_3095_p1 <= tmp_20_7_8_2_reg_8594;
tmp_318_fu_2565_p1 <= tmp_317_reg_5154;
tmp_319_fu_3098_p1 <= tmp_20_7_9_2_reg_8599;
tmp_321_fu_2569_p1 <= tmp_320_reg_5159;
tmp_322_fu_3101_p1 <= tmp_20_7_10_2_reg_8604;
tmp_324_fu_2573_p1 <= tmp_323_reg_5164;
tmp_325_fu_3104_p1 <= tmp_20_7_11_2_reg_8609;
tmp_327_fu_2577_p1 <= tmp_326_reg_5169;
tmp_328_fu_3107_p1 <= tmp_20_7_12_2_reg_8614;
tmp_329_fu_3110_p14 <= ((((((((((((tmp_328_fu_3107_p1 & tmp_325_fu_3104_p1) & tmp_322_fu_3101_p1) & tmp_319_fu_3098_p1) & tmp_316_fu_3095_p1) & tmp_313_fu_3092_p1) & tmp_310_fu_3089_p1) & tmp_307_fu_3086_p1) & tmp_304_fu_3083_p1) & tmp_301_fu_3080_p1) & tmp_298_fu_3077_p1) & tmp_295_fu_3074_p1) & tmp_292_fu_3071_p1);
tmp_32_fu_2193_p1 <= tmp_31_reg_4484;
tmp_330_cast_fu_1910_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_reg_3356),64));
tmp_330_fu_1983_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_5_mid2_cast_fu_1942_p1));
tmp_331_fu_1988_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_6_mid2_cast_fu_1952_p1));
tmp_332_fu_1993_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_7_mid2_cast_fu_1962_p1));
tmp_333_fu_2022_p3 <= (ap_reg_pp0_iter1_row_b_mid2_reg_3245 & ap_const_lv3_0);
tmp_334_cast_fu_1864_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_130_reg_3336),64));
tmp_334_fu_2029_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_333_fu_2022_p3),64));
tmp_335_cast_fu_1870_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_170_reg_3341),64));
tmp_335_fu_2034_p2 <= (tmp_333_fu_2022_p3 or ap_const_lv8_1);
tmp_336_cast_fu_1966_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_210_reg_3511),64));
tmp_336_fu_2040_p3 <= (ap_const_lv56_0 & tmp_335_fu_2034_p2);
tmp_337_cast_fu_1972_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_250_reg_3516),64));
tmp_337_fu_2049_p2 <= (tmp_333_reg_4307 or ap_const_lv8_2);
tmp_338_cast_fu_1998_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_290_reg_3616),64));
tmp_338_fu_2054_p3 <= (ap_const_lv56_0 & tmp_337_fu_2049_p2);
tmp_339_cast_fu_2004_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_330_reg_3621),64));
tmp_339_fu_2063_p2 <= (tmp_333_reg_4307 or ap_const_lv8_3);
tmp_33_fu_2602_p1 <= tmp_20_0_7_2_reg_8134;
tmp_340_cast_fu_2010_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_331_reg_3626),64));
tmp_340_fu_2068_p3 <= (ap_const_lv56_0 & tmp_339_fu_2063_p2);
tmp_341_cast_fu_2016_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_332_reg_3631),64));
tmp_341_fu_2077_p2 <= (tmp_333_reg_4307 or ap_const_lv8_4);
tmp_342_fu_2082_p3 <= (ap_const_lv56_0 & tmp_341_fu_2077_p2);
tmp_343_fu_2091_p2 <= (tmp_333_reg_4307 or ap_const_lv8_5);
tmp_344_fu_2096_p3 <= (ap_const_lv56_0 & tmp_343_fu_2091_p2);
tmp_345_fu_2113_p2 <= (tmp_333_reg_4307 or ap_const_lv8_6);
tmp_346_fu_2118_p3 <= (ap_const_lv56_0 & tmp_345_fu_2113_p2);
tmp_347_fu_2127_p2 <= (tmp_333_reg_4307 or ap_const_lv8_7);
tmp_348_fu_2132_p3 <= (ap_const_lv56_0 & tmp_347_fu_2127_p2);
tmp_350_fu_2105_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_350_fu_2105_p1 <= tmp_350_fu_2105_p0(32 - 1 downto 0);
tmp_352_fu_2109_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_352_fu_2109_p1 <= tmp_352_fu_2109_p0(32 - 1 downto 0);
tmp_353_fu_2141_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_353_fu_2141_p1 <= tmp_353_fu_2141_p0(32 - 1 downto 0);
tmp_354_fu_2145_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_354_fu_2145_p1 <= tmp_354_fu_2145_p0(32 - 1 downto 0);
tmp_355_fu_2149_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_355_fu_2149_p1 <= tmp_355_fu_2149_p0(32 - 1 downto 0);
tmp_356_fu_2153_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_356_fu_2153_p1 <= tmp_356_fu_2153_p0(32 - 1 downto 0);
tmp_357_fu_2157_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_357_fu_2157_p1 <= tmp_357_fu_2157_p0(32 - 1 downto 0);
tmp_358_fu_2161_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_358_fu_2161_p1 <= tmp_358_fu_2161_p0(32 - 1 downto 0);
tmp_35_fu_2197_p1 <= tmp_34_reg_4489;
tmp_36_fu_2605_p1 <= tmp_20_0_8_2_reg_8139;
tmp_38_fu_2201_p1 <= tmp_37_reg_4494;
tmp_39_fu_2608_p1 <= tmp_20_0_9_2_reg_8144;
tmp_3_fu_1706_p2 <= std_logic_vector(unsigned(ap_const_lv7_32) + unsigned(tmp_1_cast_fu_1700_p1));
tmp_41_fu_2205_p1 <= tmp_40_reg_4499;
tmp_42_fu_2611_p1 <= tmp_20_0_10_2_reg_8149;
tmp_44_fu_2209_p1 <= tmp_43_reg_4504;
tmp_45_fu_2614_p1 <= tmp_20_0_11_2_reg_8154;
tmp_47_fu_2213_p1 <= tmp_46_reg_4509;
tmp_48_fu_2617_p1 <= tmp_20_0_12_2_reg_8159;
tmp_49_fu_2620_p14 <= ((((((((((((tmp_48_fu_2617_p1 & tmp_45_fu_2614_p1) & tmp_42_fu_2611_p1) & tmp_39_fu_2608_p1) & tmp_36_fu_2605_p1) & tmp_33_fu_2602_p1) & tmp_30_fu_2599_p1) & tmp_27_fu_2596_p1) & tmp_24_fu_2593_p1) & tmp_21_fu_2590_p1) & tmp_18_fu_2587_p1) & tmp_15_fu_2584_p1) & tmp_12_fu_2581_p1);
tmp_4_fu_1600_p2 <= (tmp_7_mid_fu_1595_p2 or exitcond_flatten_reg_3190);
tmp_50_fu_1683_p3 <= (tmp_s_reg_3270 & ap_const_lv2_0);
tmp_51_fu_2217_p1 <= tmp_352_reg_4514;
tmp_52_fu_2651_p1 <= tmp_20_1_0_2_reg_8164;
tmp_54_fu_2221_p1 <= tmp_53_reg_4519;
tmp_55_fu_2654_p1 <= tmp_20_1_1_2_reg_8169;
tmp_57_fu_2225_p1 <= tmp_56_reg_4524;
tmp_58_fu_2657_p1 <= tmp_20_1_2_2_reg_8174;
tmp_5_fu_1565_p2 <= "1" when (ap_phi_mux_row_b_phi_fu_935_p4 = ap_const_lv5_1B) else "0";
tmp_5_mid2_cast1_fu_1718_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),10));
tmp_5_mid2_cast2_fu_1721_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),7));
tmp_5_mid2_cast_fu_1724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),6));
tmp_5_mid2_fu_1662_p3 <=
j_1_reg_3264 when (tmp_7_mid_reg_3233(0) = '1') else
j_mid_reg_3216;
tmp_60_fu_2229_p1 <= tmp_59_reg_4529;
tmp_61_fu_2660_p1 <= tmp_20_1_3_2_reg_8179;
tmp_63_fu_2233_p1 <= tmp_62_reg_4534;
tmp_64_fu_2663_p1 <= tmp_20_1_4_2_reg_8184;
tmp_66_fu_2237_p1 <= tmp_65_reg_4539;
tmp_67_fu_2666_p1 <= tmp_20_1_5_2_reg_8189;
tmp_69_fu_2241_p1 <= tmp_68_reg_4544;
tmp_6_cast2_fu_1495_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_phi_mux_j_phi_fu_923_p4),4));
tmp_6_cast2_mid1_fu_1811_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_1_reg_3264),4));
tmp_6_cast_fu_1775_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_reg_3321),64));
tmp_6_fu_1727_p2 <= std_logic_vector(unsigned(tmp_1_reg_3257) + unsigned(tmp_5_mid2_cast_fu_1724_p1));
tmp_70_fu_2669_p1 <= tmp_20_1_6_2_reg_8194;
tmp_72_fu_2245_p1 <= tmp_71_reg_4549;
tmp_73_fu_2672_p1 <= tmp_20_1_7_2_reg_8199;
tmp_75_fu_2249_p1 <= tmp_74_reg_4554;
tmp_76_fu_2675_p1 <= tmp_20_1_8_2_reg_8204;
tmp_78_fu_2253_p1 <= tmp_77_reg_4559;
tmp_79_fu_2678_p1 <= tmp_20_1_9_2_reg_8209;
tmp_7_fu_1807_p2 <= std_logic_vector(unsigned(tmp_3_reg_3311) + unsigned(tmp_5_mid2_cast2_reg_3316));
tmp_7_mid_fu_1595_p2 <= (tmp_5_reg_3206 and not_exitcond_flatten_fu_1590_p2);
tmp_81_fu_2257_p1 <= tmp_80_reg_4564;
tmp_82_fu_2681_p1 <= tmp_20_1_10_2_reg_8214;
tmp_84_fu_2261_p1 <= tmp_83_reg_4569;
tmp_85_fu_2684_p1 <= tmp_20_1_11_2_reg_8219;
tmp_87_fu_2265_p1 <= tmp_86_reg_4574;
tmp_88_fu_2687_p1 <= tmp_20_1_12_2_reg_8224;
tmp_89_fu_2690_p14 <= ((((((((((((tmp_88_fu_2687_p1 & tmp_85_fu_2684_p1) & tmp_82_fu_2681_p1) & tmp_79_fu_2678_p1) & tmp_76_fu_2675_p1) & tmp_73_fu_2672_p1) & tmp_70_fu_2669_p1) & tmp_67_fu_2666_p1) & tmp_64_fu_2663_p1) & tmp_61_fu_2660_p1) & tmp_58_fu_2657_p1) & tmp_55_fu_2654_p1) & tmp_52_fu_2651_p1);
tmp_8_cast_fu_1791_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_3326),64));
tmp_8_fu_1732_p2 <= std_logic_vector(unsigned(tmp_2_cast_fu_1703_p1) + unsigned(tmp_5_mid2_cast2_fu_1721_p1));
tmp_90_fu_1694_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1679_p1) - unsigned(p_shl1_cast_fu_1690_p1));
tmp_91_fu_2269_p1 <= tmp_353_reg_4589;
tmp_92_fu_2721_p1 <= tmp_20_2_0_2_reg_8229;
tmp_94_fu_2273_p1 <= tmp_93_reg_4594;
tmp_95_fu_2724_p1 <= tmp_20_2_1_2_reg_8234;
tmp_97_fu_2277_p1 <= tmp_96_reg_4599;
tmp_98_fu_2727_p1 <= tmp_20_2_2_2_reg_8239;
tmp_fu_1622_p3 <= (tmp_1_mid2_v_reg_3225 & ap_const_lv2_0);
tmp_s_fu_1647_p2 <= std_logic_vector(unsigned(tmp_2_cast_mid2_fu_1639_p1) + unsigned(row_b_mid2_reg_3245));
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/ac94cfa13c34e2aa/zqynq_lab_1_design_axi_gpio_1_0_stub.vhdl
|
1
|
2550
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:58 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_1_0_stub.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[4:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.2";
begin
end;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/ip_repo/xilinx_com_hls_nco_1_0/hdl/vhdl/nco.vhd
|
2
|
10427
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nco is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC );
end;
architecture behav of nco is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nco,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.350000,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=98,HLS_SYN_LUT=121}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
signal ap_rst_n_inv : STD_LOGIC;
signal sine_sample_V : STD_LOGIC_VECTOR (15 downto 0);
signal sine_sample_V_ap_vld : STD_LOGIC;
signal step_size_V : STD_LOGIC_VECTOR (15 downto 0);
signal temp_V : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal sine_lut_V_address0 : STD_LOGIC_VECTOR (11 downto 0);
signal sine_lut_V_ce0 : STD_LOGIC;
signal sine_lut_V_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal nco_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_66 : BOOLEAN;
signal tmp_6_fu_89_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Val2_1_fu_67_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_79 : BOOLEAN;
signal address_V_fu_79_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component nco_sine_lut_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (11 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nco_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
sine_sample_V : IN STD_LOGIC_VECTOR (15 downto 0);
sine_sample_V_ap_vld : IN STD_LOGIC;
step_size_V : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
sine_lut_V_U : component nco_sine_lut_V
generic map (
DataWidth => 16,
AddressRange => 4096,
AddressWidth => 12)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => sine_lut_V_address0,
ce0 => sine_lut_V_ce0,
q0 => sine_lut_V_q0);
nco_AXILiteS_s_axi_U : component nco_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => nco_AXILiteS_s_axi_U_ap_dummy_ce,
sine_sample_V => sine_sample_V,
sine_sample_V_ap_vld => sine_sample_V_ap_vld,
step_size_V => step_size_V);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
temp_V <= p_Val2_1_fu_67_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
address_V_fu_79_p4 <= p_Val2_1_fu_67_p2(15 downto 4);
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_66 assign process. --
ap_sig_bdd_66_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_66 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_79 assign process. --
ap_sig_bdd_79_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_79 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_66)
begin
if (ap_sig_bdd_66) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_79)
begin
if (ap_sig_bdd_79) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
nco_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
p_Val2_1_fu_67_p2 <= std_logic_vector(unsigned(temp_V) + unsigned(step_size_V));
sine_lut_V_address0 <= tmp_6_fu_89_p1(12 - 1 downto 0);
-- sine_lut_V_ce0 assign process. --
sine_lut_V_ce0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
sine_lut_V_ce0 <= ap_const_logic_1;
else
sine_lut_V_ce0 <= ap_const_logic_0;
end if;
end process;
sine_sample_V <= sine_lut_V_q0;
-- sine_sample_V_ap_vld assign process. --
sine_sample_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
sine_sample_V_ap_vld <= ap_const_logic_1;
else
sine_sample_V_ap_vld <= ap_const_logic_0;
end if;
end process;
tmp_6_fu_89_p1 <= std_logic_vector(resize(unsigned(address_V_fu_79_p4),64));
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_adEe.vhd
|
1
|
2143
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_DSP48_0 is
port (
in0: in std_logic_vector(5 - 1 downto 0);
in1: in std_logic_vector(2 - 1 downto 0);
in2: in std_logic_vector(6 - 1 downto 0);
dout: out std_logic_vector(9 - 1 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_DSP48_0 is
signal b : signed(18-1 downto 0);
signal a : signed(25-1 downto 0);
signal d : signed(25-1 downto 0);
signal m : signed(43-1 downto 0);
signal ad : signed(25-1 downto 0);
begin
a <= signed(resize(signed(in0), 25));
d <= signed(resize(unsigned(in1), 25));
b <= signed(resize(unsigned(in2), 18));
ad <= a + d;
m <= ad * b;
dout <= std_logic_vector(resize(unsigned(m), 9));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_DSP48_0 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_DSP48_0_U : component convolve_kernel_adEe_DSP48_0
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/b9c82e235214f825/zynq_design_1_auto_pc_0_sim_netlist.vhdl
|
1
|
533310
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/ip/hdl/vhdl/convolve_kernel_fcud.vhd
|
3
|
3077
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 8;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_6_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_6_max_dsp_32_u : component convolve_kernel_ap_fmul_6_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
16
|
103154
|
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_3_full_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
16
|
103154
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/synth/convolve_kernel_ap_fmul_2_max_dsp_32.vhd
|
3
|
12828
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_2_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_2_max_dsp_32_arch OF convolve_kernel_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_2_max_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_2_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_2_max_dsp_32_arch;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd
|
16
|
292080
|
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rkVEK9Ta5cXu0NoFk3YELqQAZjmrRfYuzOe4KXU1O1IPigHxffLH2jmT0K+5BnULQWmCLRsKurJT
XXgN7dUSlGAw7+bX0CUxyoXix4AyCsjenB7C+3FmVp9AQT+A6MQPJ6TmUHK+lwFOfcrQvQcgncLo
AKoifYOHlQ5PPHcTGRkCtBKMJiO6YNUxizP1+przyclAjIlk0IJ5PpZiYnq2GCSV2g1WCXFEFKPd
2FbYZLbzTsNQZhYQ48ibqcagbojfL+dcNBDK26x5LGBHipaxKnxMEk1TPQZA
`protect end_protected
|
mit
|
khaledhassan/vhdl-examples
|
adders_1bit/full_adder_tb.vhd
|
1
|
2406
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the full adder.
library ieee;
use ieee.std_logic_1164.all;
entity full_adder_tb is
end full_adder_tb;
architecture TB of full_adder_tb is
signal a, b, sum, c_in, c_out : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.full_adder
port map (
a => a,
b => b,
c_in => c_in,
sum => sum,
c_out => c_out
);
-- Stimulus process
process
begin
a <= '0';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '1';
wait;
end process;
end TB;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution1/syn/vhdl/matrix_mult.vhd
|
2
|
17072
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.492500,HLS_SYN_LAT=686,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=1,HLS_SYN_FF=177,HLS_SYN_LUT=165}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal tmp_7_fu_137_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_reg_251 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_1_fu_149_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_260 : STD_LOGIC_VECTOR (2 downto 0);
signal j_cast2_cast_fu_155_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast2_cast_reg_265 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal prod_addr_reg_270 : STD_LOGIC_VECTOR (4 downto 0);
signal j_1_fu_175_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_278 : STD_LOGIC_VECTOR (2 downto 0);
signal a_addr_reg_283 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal b_addr_reg_288 : STD_LOGIC_VECTOR (4 downto 0);
signal k_1_fu_229_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal k_1_reg_296 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal grp_fu_243_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal i_reg_75 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond1_fu_169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal j_reg_86 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond2_fu_143_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal prod_load_reg_97 : STD_LOGIC_VECTOR (15 downto 0);
signal k_reg_110 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_8_cast_fu_164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_cast_fu_190_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_cast_fu_218_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_6_fu_125_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal i_cast3_cast_fu_121_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl_cast_fu_133_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_159_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal k_cast1_cast_fu_181_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_fu_185_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_fu_195_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl1_cast_fu_203_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_fu_207_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_fu_213_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
component matrix_mult_mac_mbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mac_mbkb_U0 : component matrix_mult_mac_mbkb
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => a_q0,
din2 => prod_load_reg_97,
ce => ap_const_logic_1,
dout => grp_fu_243_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
i_reg_75_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_1))) then
i_reg_75 <= i_1_reg_260;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_75 <= ap_const_lv3_0;
end if;
end if;
end process;
j_reg_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_223_p2))) then
j_reg_86 <= j_1_reg_278;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_143_p2 = ap_const_lv1_0))) then
j_reg_86 <= ap_const_lv3_0;
end if;
end if;
end process;
k_reg_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
k_reg_110 <= k_1_reg_296;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_0))) then
k_reg_110 <= ap_const_lv3_0;
end if;
end if;
end process;
prod_load_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
prod_load_reg_97 <= grp_fu_243_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_0))) then
prod_load_reg_97 <= ap_const_lv16_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
a_addr_reg_283 <= tmp_9_cast_fu_190_p1(5 - 1 downto 0);
b_addr_reg_288 <= tmp_12_cast_fu_218_p1(5 - 1 downto 0);
k_1_reg_296 <= k_1_fu_229_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_1_reg_260 <= i_1_fu_149_p2;
tmp_7_reg_251 <= tmp_7_fu_137_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
j_1_reg_278 <= j_1_fu_175_p2;
j_cast2_cast_reg_265(2 downto 0) <= j_cast2_cast_fu_155_p1(2 downto 0);
prod_addr_reg_270 <= tmp_8_cast_fu_164_p1(5 - 1 downto 0);
end if;
end if;
end process;
j_cast2_cast_reg_265(5 downto 3) <= "000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, exitcond1_fu_169_p2, exitcond2_fu_143_p2, exitcond_fu_223_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_223_p2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
a_address0 <= a_addr_reg_283;
a_ce0_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_done_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_143_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_143_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
b_address0 <= b_addr_reg_288;
b_ce0_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
exitcond1_fu_169_p2 <= "1" when (j_reg_86 = ap_const_lv3_5) else "0";
exitcond2_fu_143_p2 <= "1" when (i_reg_75 = ap_const_lv3_5) else "0";
exitcond_fu_223_p2 <= "1" when (k_reg_110 = ap_const_lv3_5) else "0";
i_1_fu_149_p2 <= std_logic_vector(unsigned(i_reg_75) + unsigned(ap_const_lv3_1));
i_cast3_cast_fu_121_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_75),6));
j_1_fu_175_p2 <= std_logic_vector(unsigned(j_reg_86) + unsigned(ap_const_lv3_1));
j_cast2_cast_fu_155_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_86),6));
k_1_fu_229_p2 <= std_logic_vector(unsigned(k_reg_110) + unsigned(ap_const_lv3_1));
k_cast1_cast_fu_181_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(k_reg_110),6));
p_shl1_cast_fu_203_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_195_p3),6));
p_shl_cast_fu_133_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_fu_125_p3),6));
prod_address0 <= prod_addr_reg_270;
prod_ce0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_d0 <= prod_load_reg_97;
prod_we0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_207_p2 <= std_logic_vector(unsigned(k_cast1_cast_fu_181_p1) + unsigned(p_shl1_cast_fu_203_p1));
tmp_11_fu_213_p2 <= std_logic_vector(unsigned(tmp_10_fu_207_p2) + unsigned(j_cast2_cast_reg_265));
tmp_12_cast_fu_218_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_213_p2),32));
tmp_6_fu_125_p3 <= (i_reg_75 & ap_const_lv2_0);
tmp_7_fu_137_p2 <= std_logic_vector(unsigned(i_cast3_cast_fu_121_p1) + unsigned(p_shl_cast_fu_133_p1));
tmp_8_cast_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_fu_159_p2),32));
tmp_8_fu_159_p2 <= std_logic_vector(unsigned(tmp_7_reg_251) + unsigned(j_cast2_cast_fu_155_p1));
tmp_9_cast_fu_190_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_fu_185_p2),32));
tmp_9_fu_185_p2 <= std_logic_vector(unsigned(tmp_7_reg_251) + unsigned(k_cast1_cast_fu_181_p1));
tmp_s_fu_195_p3 <= (k_reg_110 & ap_const_lv2_0);
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_3_full_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
16
|
142619
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
16
|
142619
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
16
|
80739
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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2eHYW6nFzA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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zAKt6BTAoXaltKesRuE=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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DXQn5yxt3fuWLEGSbs8=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
16
|
80739
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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cfXV/ALTk7u747xoM5GCA9HtVWObRYEbX8C6uFUG/aMBuZxtZJqzr15grKZROnDDT8qKEsE969dq
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V/1cDsI=
`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/synth/zynq_design_1_axi_bram_ctrl_0_bram_0.vhd
|
2
|
15710
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_6;
USE blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6;
ENTITY zynq_design_1_axi_bram_ctrl_0_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_bram_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_bram_0_arch OF zynq_design_1_axi_bram_ctrl_0_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_6 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_6,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_axi_bram_ctrl_0_bram_0_arch : ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_I" &
"NIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ" &
"_WIDTH_B=32,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_E" &
"N_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_6
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "16",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END zynq_design_1_axi_bram_ctrl_0_bram_0_arch;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/syn/vhdl/convolve_kernel_fbkb.vhd
|
4
|
3597
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd
|
7
|
292628
|
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`protect end_protected
|
mit
|
noelnamai/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution2/syn/vhdl/fir.vhd
|
1
|
18991
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0);
x_ap_vld : IN STD_LOGIC );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.912000,HLS_SYN_LAT=67,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=561,HLS_SYN_LUT=266}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal x_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal x_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal x_ap_vld_preg : STD_LOGIC := '0';
signal x_ap_vld_in_sig : STD_LOGIC;
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal x_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal i_cast_fu_143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_199 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_147_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_136_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_218 : STD_LOGIC_VECTOR (4 downto 0);
signal c_load_reg_223 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_174_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_228 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal acc_1_fu_179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal acc_reg_101 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_118_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_114 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_126 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_161_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_166_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_170_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_136_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
component fir_mul_32s_32s_3bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
fir_mul_32s_32s_3bkb_U1 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => c_load_reg_223,
din1 => data1_reg_126,
ce => ap_const_logic_1,
dout => grp_fu_174_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
x_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
x_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_ap_vld_preg <= x_ap_vld;
end if;
end if;
end if;
end process;
x_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_preg <= x;
end if;
end if;
end if;
end process;
acc_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
acc_reg_101 <= acc_1_fu_179_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
acc_reg_101 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_126_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0))) then
data1_reg_126 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
data1_reg_126 <= x_in_sig;
end if;
end if;
end process;
i_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_reg_114 <= i_1_reg_218;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
i_reg_114 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
c_load_reg_223 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_218 <= grp_fu_136_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_190 <= i_cast_fu_143_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0))) then
tmp_1_reg_199 <= tmp_1_fu_155_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp_6_reg_228 <= grp_fu_174_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, x_ap_vld_in_sig, ap_CS_fsm_state2, tmp_fu_147_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
acc_1_fu_179_p2 <= std_logic_vector(unsigned(tmp_6_reg_228) + unsigned(acc_reg_101));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_block_state1_assign_proc : process(ap_start, x_ap_vld_in_sig)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig));
end process;
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_170_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_136_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_118_p4, i_reg_114)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_136_p0 <= i_reg_114;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_136_p0 <= i_phi_fu_118_p4;
else
grp_fu_136_p0 <= "XXXXX";
end if;
end process;
grp_fu_136_p2 <= std_logic_vector(unsigned(grp_fu_136_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_143_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_114),32));
i_phi_fu_118_p4 <= i_reg_114;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3, tmp_3_fu_161_p1, tmp_4_fu_166_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_166_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_161_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x_in_sig, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x_in_sig;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_1_reg_199, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_155_p2 <= "1" when (i_reg_114 = ap_const_lv5_0) else "0";
tmp_3_fu_161_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_136_p2),64));
tmp_4_fu_166_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_5_fu_170_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_fu_147_p3 <= i_reg_114(4 downto 4);
x_ap_vld_in_sig_assign_proc : process(x_ap_vld, x_ap_vld_preg)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_ap_vld_in_sig <= x_ap_vld;
else
x_ap_vld_in_sig <= x_ap_vld_preg;
end if;
end process;
x_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, x_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
x_blk_n <= x_ap_vld;
else
x_blk_n <= ap_const_logic_1;
end if;
end process;
x_in_sig_assign_proc : process(x, x_preg, x_ap_vld)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_in_sig <= x;
else
x_in_sig <= x_preg;
end if;
end process;
y <= acc_reg_101;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/1134498f5baab19e/ip_design_processing_system7_0_0_stub.vhdl
|
1
|
5936
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Wed Oct 18 15:15:21 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_stub.vhdl
-- Design : ip_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
begin
end;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/c7ba741286d72229/led_controller_design_auto_pc_0_stub.vhdl
|
1
|
4998
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_auto_pc_0_stub.vhdl
-- Design : led_controller_design_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
begin
end;
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Labs/POCP/POCP-5/src/Task2_TB/Task2_tb2.vhd
|
1
|
4337
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task2_ent_tb2 is
end entity Task2_ent_tb2;
architecture Task2_arch_tb2 of Task2_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task2 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task2;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task2
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 10
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task2_arch_tb2;
configuration Task2_cfg_tb2 of Task2_ent_tb2 is
for Task2_arch_tb2
for UUT : Task2 use entity work.Task2(Beh);
end for;
end for;
end Task2_cfg_tb2;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel_control_s_axi.vhd
|
1
|
12110
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_control_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity convolve_kernel_control_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of convolve_kernel_control_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/sim/zynq_design_1_axi_gpio_0_0.vhd
|
2
|
8848
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zynq_design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zynq_design_1_axi_gpio_0_0;
ARCHITECTURE zynq_design_1_axi_gpio_0_0_arch OF zynq_design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_design_1_axi_gpio_0_0_arch;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_blk_mem_gen_0_0/synth/design_1_blk_mem_gen_0_0.vhd
|
1
|
15972
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_4_0;
USE blk_mem_gen_v8_4_0.blk_mem_gen_v8_4_0;
ENTITY design_1_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_0;
ARCHITECTURE design_1_blk_mem_gen_0_0_arch OF design_1_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_4_0 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_4_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_0_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_4_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_4_0,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM" &
"E=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_" &
"WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C" &
"_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clkb: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 1200, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
BEGIN
U0 : blk_mem_gen_v8_4_0
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_0_arch;
|
mit
|
frankvanbever/MIPS_processor
|
testbenches/Imem_tb.vhd
|
1
|
2366
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:48 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/Imem_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: imem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Imem_tb IS
END Imem_tb;
ARCHITECTURE behavior OF Imem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT imem
PORT(
pc : IN std_logic_vector(31 downto 0);
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal pc : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
signal clk : std_logic;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: imem PORT MAP (
pc => pc,
Instruction => Instruction
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
pc <= X"00000000";
wait for clk_period;
pc <= X"00000004";
wait for clk_period;
pc <= X"00000008";
wait for clk_period;
pc <= X"0000000C";
wait for clk_period;
pc <= X"00000010";
wait for clk_period;
wait;
end process;
END;
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/direct_path_cntr.vhd
|
15
|
12275
|
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr.vhd
--
-- Description: This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n is false,
-- Dout increments by one each time Cnt_en is true at
-- the positive edge of Clk.
--
-- The implementation has a one-LUT delay (via the XORCY)
-- in direct pass-through mode and the same delay plus
-- carry-chain propogation in count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/30/2003 -- First version
--
-- <initials> <date>
-- ^^^^^^
-- Description of changes. If multiple lines are needed to fully describe
-- the changes made to the design, these lines should align with each other.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end direct_path_cntr;
library unisim;
use unisim.all;
architecture imp of direct_path_cntr is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
component FDE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component FDE;
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
begin
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
signal gen_cry: std_logic;
begin
gen_cry <= '1' when j = C_WIDTH-1 else '0'; -- cntrl increments
-- at LSB
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
LSB_LUT_GEN: if j = C_WIDTH-1 generate
begin
lut_out(j) <= not q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
--
NON_LSB_LUT_GEN: if j /= C_WIDTH-1 generate
begin
lut_out(j) <= q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
------------------------------------------------------------------------
-- Propagate the carry out.
------------------------------------------------------------------------
LSB_MUXCY_GEN: if j = C_WIDTH-1 generate
signal sel_cntr_and_Load_n : std_logic;
begin
I_MULT_AND : MULT_AND
port map (
LO => sel_cntr_and_Load_n,
I1 => sel_cntr,
I0 => Load_n
);
MUXCY_i1: MUXCY
port map (
DI => sel_cntr_and_Load_n,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
NON_LSB_MUXCY_GEN: if j /= C_WIDTH-1 generate
begin
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDRE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd
|
19
|
32006
|
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
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1k/c81PcAQ==
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd
|
19
|
32006
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
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1k/c81PcAQ==
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/common/wr_pf_ss.vhd
|
19
|
30385
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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q1PX6Q==
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd
|
19
|
13156
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd
|
19
|
13156
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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ZkaGINks7Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd
|
27
|
61464
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd
|
27
|
61464
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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bBdLdBNTBw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd
|
27
|
61464
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
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`protect end_protected
|
mit
|
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