repo_name
stringlengths 6
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stringlengths 5
236
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stringclasses 54
values | size
stringlengths 1
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stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
carlosrd/DAS
|
P4/Parte A/debouncer.vhd
|
4
|
3528
|
-------------------------------------------------------------------
--
-- Fichero:
-- debouncer.vhd 12/7/2013
--
-- (c) J.M. Mendias
-- Diseño Automático de Sistemas
-- Facultad de Informática. Universidad Complutense de Madrid
--
-- Propósito:
-- Elimina los rebotes de una línea binaria mediante la espera
-- de 50 ms tras cada flanco detectado
--
-- Notas de diseño:
-- El timer usado para medir 50 ms esta dimensionado para
-- funcionar con un reloj de 50 MHz
--
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY debouncer IS
PORT (
rst: IN std_logic; -- Reset asíncrono del sistema
clk: IN std_logic; -- Reloj del sistema
x: IN std_logic; -- Entrada binaria a la que deben eliminars los rebotes
xDeb: OUT std_logic; -- Salida que sique a la entrada pero sin rebotes
xDebFallingEdge: OUT std_logic; -- Se activa durante 1 ciclo cada vez que detecta un flanco de subida en x
xDebRisingEdge: OUT std_logic -- Se activa durante 1 ciclo cada vez que detecta un flanco de bajada en x
);
END debouncer;
ARCHITECTURE debouncerArch of debouncer is
SIGNAL xSync: std_logic;
SIGNAL startTimer, timerEnd: std_logic;
BEGIN
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
xSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
xSync <= aux1;
aux1 := x;
END IF;
END PROCESS synchronizer;
timer:
PROCESS (rst, clk)
CONSTANT timeOut: std_logic_vector (21 DOWNTO 0) := "1001100010010110100000"; -- 2500000/(50MHz) = 50 ms
VARIABLE count: std_logic_vector (21 DOWNTO 0);
BEGIN
IF (count=timeOut) THEN
timerEnd <= '1';
ELSE
timerEnd <= '0';
END IF;
IF (rst='0') THEN
count := timeOut;
ELSIF (clk'EVENT AND clk='1') THEN
IF (startTimer='1') THEN
count := (OTHERS=>'0');
ELSIF (timerEnd='0') THEN
count := count + 1;
END IF;
END IF;
END PROCESS timer;
controller:
PROCESS (xSync, rst, clk)
TYPE states IS (waitingKeyDown, keyDownDebouncing, waitingKeyUp, KeyUpDebouncing);
VARIABLE state: states;
BEGIN
xDeb <= '1';
xDebFallingEdge <= '0';
xDebRisingEdge <= '0';
startTimer <= '0';
CASE state IS
WHEN waitingKeyDown =>
IF (xSync='0') THEN
xDebFallingEdge <= '1';
startTimer <= '1';
END IF;
WHEN keyDownDebouncing =>
xDeb <= '0';
WHEN waitingKeyUp =>
xDeb <= '0';
IF (xSync='1') THEN
xDebRisingEdge <= '1';
startTimer <= '1';
END IF;
WHEN KeyUpDebouncing =>
NULL;
END CASE;
IF (rst='0') THEN
state := waitingKeyDown;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingKeyDown =>
IF (xSync='0') THEN
state := keyDownDebouncing;
END IF;
WHEN keyDownDebouncing =>
IF (timerEnd='1') THEN
state := waitingKeyUp;
END IF;
WHEN waitingKeyUp =>
IF (xSync='1') THEN
state := KeyUpDebouncing;
END IF;
WHEN KeyUpDebouncing =>
IF (timerEnd='1') THEN
state := waitingKeyDown;
END IF;
END CASE;
END IF;
END PROCESS controller;
END debouncerArch;
|
mit
|
hanyazou/vivado-ws
|
playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/SyncBase.vhd
|
15
|
3854
|
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aReset, InClk)
begin
if (aReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
mit
|
es17m014/vhdl-counter
|
src/old/tb/tb_io_ctrl.vhd
|
1
|
918
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_io_ctrl.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: IO Controller testbenc
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 02.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_io_ctrl is
end tb_io_ctrl;
architecture sim of tb_io_ctrl is
begin
end sim;
|
mit
|
TheMassController/VHDL_experimenting
|
project/SPI/spi_tb.vhd
|
1
|
12925
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
use IEEE.numeric_std.ALL;
use IEEE.math_real.ALL;
entity spi_tb is
generic (
clock_period : time;
randVal : natural
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end spi_tb;
architecture Behavioral of spi_tb is
constant sclk_period : time := clock_period * 2; -- Run eight times slower than the system clock
constant FRAME_SIZE_L2 : natural := 5;
constant FRAME_SIZE : natural := 2**FRAME_SIZE_L2;
-- inout signals slave 1
signal slave_1_rst : STD_LOGIC;
signal slave_1_sclk : STD_LOGIC;
signal slave_1_mosi : STD_LOGIC;
signal slave_1_miso : STD_LOGIC;
signal slave_1_ss : STD_LOGIC;
signal slave_1_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_1_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_1_done : boolean;
-- meta signals slave 1
signal spi_slave_1_done : boolean;
signal spi_slave_1_suc : boolean := true;
-- inout signals slave 2
signal slave_2_rst : STD_LOGIC;
signal slave_2_sclk : STD_LOGIC;
signal slave_2_mosi : STD_LOGIC;
signal slave_2_miso : STD_LOGIC;
signal slave_2_ss : STD_LOGIC;
signal slave_2_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_2_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_2_done : boolean;
-- meta signals slave 2
signal spi_slave_2_done : boolean;
signal spi_slave_2_suc : boolean := true;
-- inout signals slave 3
signal slave_3_rst : STD_LOGIC;
signal slave_3_sclk : STD_LOGIC;
signal slave_3_mosi : STD_LOGIC;
signal slave_3_miso : STD_LOGIC;
signal slave_3_ss : STD_LOGIC;
signal slave_3_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_3_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_3_done : boolean;
-- meta signals slave 3
signal spi_slave_3_done : boolean;
signal spi_slave_3_suc : boolean := true;
-- inout signals slave 4
signal slave_4_rst : STD_LOGIC;
signal slave_4_sclk : STD_LOGIC;
signal slave_4_mosi : STD_LOGIC;
signal slave_4_miso : STD_LOGIC;
signal slave_4_ss : STD_LOGIC;
signal slave_4_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_4_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_4_done : boolean;
-- meta signals slave 4
signal spi_slave_4_done : boolean;
signal spi_slave_4_suc : boolean := true;
begin
success <= spi_slave_1_suc and spi_slave_2_suc and spi_slave_3_suc and spi_slave_4_suc;
done <= spi_slave_1_done and spi_slave_2_done and spi_slave_3_done and spi_slave_4_done;
-- Frame size 16 bit
-- SPO = SPH = 0
spi_slave_1 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2
)
port map (
rst => slave_1_rst,
clk => clk,
sclk => slave_1_sclk,
mosi => slave_1_mosi,
miso => slave_1_miso,
ss => slave_1_ss,
trans_data => slave_1_data_in,
receiv_data => slave_1_data_out,
done => slave_1_done
);
-- Frame size 16 bit
spi_slave_2 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '1',
PHASE => '0'
)
port map (
rst => slave_2_rst,
clk => clk,
sclk => slave_2_sclk,
mosi => slave_2_mosi,
miso => slave_2_miso,
ss => slave_2_ss,
trans_data => slave_2_data_in,
receiv_data => slave_2_data_out,
done => slave_2_done
);
-- Frame size 16 bit
spi_slave_3 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '0',
PHASE => '1'
)
port map (
rst => slave_3_rst,
clk => clk,
sclk => slave_3_sclk,
mosi => slave_3_mosi,
miso => slave_3_miso,
ss => slave_3_ss,
trans_data => slave_3_data_in,
receiv_data => slave_3_data_out,
done => slave_3_done
);
-- Frame size 16 bit
spi_slave_4 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '1',
PHASE => '1'
)
port map (
rst => slave_4_rst,
clk => clk,
sclk => slave_4_sclk,
mosi => slave_4_mosi,
miso => slave_4_miso,
ss => slave_4_ss,
trans_data => slave_4_data_in,
receiv_data => slave_4_data_out,
done => slave_4_done
);
slave_1_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_1_rst <= '1';
slave_1_ss <= '0';
slave_1_sclk <= '0';
slave_1_data_in <= (others => '0');
slave_1_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_1_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_1_data_in <= cur_data_out;
-- Pre set
slave_1_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 2 downto 0 loop
-- Get/read
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
assert(slave_1_miso = cur_data_out(B + 1));
-- Set/write
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
slave_1_mosi <= cur_data_out(B);
end loop;
-- End the loop prematurely, since the last set is not actually a set, since we are already out of data
-- Get/read
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
assert(slave_1_miso = cur_data_out(0));
-- Finishing edge
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
slave_1_mosi <= '0';
wait for (1.5)*clock_period;
assert slave_1_done = true;
assert(slave_1_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_1_sclk <= '0';
spi_slave_1_done <= true;
report "SPI slave 1 tests done" severity note;
wait;
end process;
slave_2_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_2_rst <= '1';
slave_2_ss <= '0';
slave_2_sclk <= '1';
slave_2_data_in <= (others => '0');
slave_2_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_2_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_2_data_in <= cur_data_out;
-- Pre set
slave_2_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 1 downto 0 loop
-- Set/write
wait for sclk_period/2;
slave_2_sclk <= not slave_2_sclk;
slave_2_mosi <= cur_data_out(B);
-- Get/read
wait for sclk_period/2;
slave_2_sclk <= not slave_2_sclk;
assert(slave_2_miso = cur_data_out(B));
end loop;
wait for (1.5)*clock_period;
assert slave_2_done = true;
assert(slave_2_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_2_sclk <= '0';
spi_slave_2_done <= true;
report "SPI slave 2 tests done" severity note;
wait;
end process;
slave_3_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_3_rst <= '1';
slave_3_ss <= '0';
slave_3_sclk <= '0';
slave_3_data_in <= (others => '0');
slave_3_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_3_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_3_data_in <= cur_data_out;
-- Pre set
slave_3_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 1 downto 0 loop
-- Set/write
wait for sclk_period/2;
slave_3_sclk <= not slave_3_sclk;
slave_3_mosi <= cur_data_out(B);
-- Get/read
wait for sclk_period/2;
slave_3_sclk <= not slave_3_sclk;
assert(slave_3_miso = cur_data_out(B));
end loop;
slave_3_sclk <= not slave_3_sclk;
wait for (1.5)*clock_period;
assert slave_3_done = true;
assert(slave_3_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_3_sclk <= '0';
spi_slave_3_done <= true;
report "SPI slave 3 tests done" severity note;
wait;
end process;
slave_4_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_4_rst <= '1';
slave_4_ss <= '0';
slave_4_sclk <= '1';
slave_4_data_in <= (others => '0');
slave_4_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_4_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_4_data_in <= cur_data_out;
-- Pre set
slave_4_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 2 downto 0 loop
-- Get/read
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
assert(slave_4_miso = cur_data_out(B + 1));
-- Set/write
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
slave_4_mosi <= cur_data_out(B);
end loop;
-- End the loop prematurely, since the last set is not actually a set, since we are already out of data
-- Get/read
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
assert(slave_4_miso = cur_data_out(0));
-- Finishing edge
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
slave_4_mosi <= '0';
wait for (1.5)*clock_period;
assert slave_4_done = true;
assert(slave_4_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_4_sclk <= '0';
spi_slave_4_done <= true;
report "SPI slave 4 tests done" severity note;
wait;
end process;
end Behavioral;
|
mit
|
LucasMahieu/TP_secu
|
code/AES/vhd/vhd/Aff_Trans.vhd
|
2
|
803
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= not (a(0)) xor a(4) xor a(5) xor a(6) xor a(7);
b_out(1) <= not (a(5)) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(2) <= a(2) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(3) <= a(7) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(4) <= a(4) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(5) <= not (a(1)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(6) <= not (a(6)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(7) <= a(3) xor a(4) xor a(5) xor a(6) xor a(7);
end a_aff_trans;
|
mit
|
digital-sound-antiques/vm2413
|
Operator.vhd
|
2
|
3716
|
--
-- Operator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity Operator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
WF : in WF_TYPE;
FB : in FB_TYPE;
noise : in std_logic;
pgout : in PGOUT_TYPE;
egout : in DB_TYPE;
faddr : out CH_TYPE;
fdata : in SIGNED_LI_TYPE;
opout : out SIGNED_DB_TYPE
);
end Operator;
architecture RTL of Operator is
component AttackTable port (
clk : in std_logic;
addr : in DB_TYPE;
data : out DB_TYPE
);
end component;
component SineTable port (
clk : in std_logic;
wf : in std_logic;
addr : in integer range 0 to (2 ** (PGOUT_TYPE'high+1) - 1);
data : out SIGNED_DB_TYPE
);
end component;
signal addr : integer range 0 to (2 ** (PGOUT_TYPE'high+1) - 1);
signal data : SIGNED_DB_TYPE;
begin
SINTBL : SineTable port map ( clk, WF, addr, data );
process(clk, reset)
variable modula : std_logic_vector(LI_TYPE'high + 2 downto 0);
variable opout_buf : SIGNED_DB_TYPE;
begin
if reset='1' then
opout <= ( sign=>'0', value=>(others=>'0') );
elsif clk'event and clk='1' then if clkena = '1' then
if stage = 0 then
-- periodic noise
if rhythm = '1' and ( slot = 14 or slot = 17 ) then -- HH or CYM
if noise = '1' then
addr <= 127; -- phase of max value
else
addr <= 383; -- phase of min value
end if;
elsif rhythm = '1' and slot = 15 then -- SD
if pgout(pgout'high) = '1' then
addr <= 127; -- phase of max value
else
addr <= 383; -- phase of min value
end if;
elsif rhythm = '1' and slot = 16 then -- TOM
addr <= CONV_INTEGER(pgout);
else
if slot mod 2 = 0 then
if FB = "000" then
modula := (others => '0') ;
else
modula := "0" & fdata.value & "0";
modula := SHR( modula, "111" - FB );
end if;
else
modula := fdata.value & "00";
end if;
if fdata.sign = '0' then
addr <= CONV_INTEGER(pgout + modula(pgout'range));
else
addr <= CONV_INTEGER(pgout - modula(pgout'range));
end if;
end if;
elsif stage = 1 then
-- Wait for sine and attack table.
elsif stage = 2 then
-- output
if ( ( '0'&egout ) + ('0'&data.value) ) < "10000000" then
opout_buf := ( sign=>data.sign, value=> egout + data.value );
else
opout_buf := ( sign=>data.sign, value=> (others=>'1') );
end if;
-- read feedback data for the next slot
if slot mod 2 = 1 then
if slot/2 = 8 then
faddr <= 0;
else
faddr <= slot/2 + 1;
end if;
else
faddr <= slot/2;
end if;
opout <= opout_buf;
elsif stage = 3 then
-- wait for feedback data.
end if;
end if; end if;
end process;
end RTL;
|
mit
|
es17m014/vhdl-counter
|
src/old/tb/tb_bcd_driver.vhd
|
1
|
3182
|
-- --------------------------------------------------------------
-- Title : Testbench for design "BCD driver"
-- Project :
-- --------------------------------------------------------------
-- File : tb_bcd_driver.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 2017-10-28
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description :
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2017 1.0 Martin Angerair init
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity tb_bcd_driver is
end tb_bcd_driver;
-------------------------------------------------------------------------------
architecture sim of tb_bcd_driver is
component seven_segment_driver
generic (g_refresh_rate : positive);
port ( clk_i : in std_logic; -- 100Mhz clock on Basys 3 FPGA board
reset_i : in std_logic; -- reset_i
dig0_i : in std_logic_vector(7 downto 0); -- first digit value
dig1_i : in std_logic_vector(7 downto 0); -- second digit value
dig2_i : in std_logic_vector(7 downto 0); -- third digit value
dig3_i : in std_logic_vector(7 downto 0); -- fourth digit value
ss_sel_o : out std_logic_vector(3 downto 0); -- 4 anode signals
ss_o : out std_logic_vector(7 downto 0));
end component;
-- component ports
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal dig0_i : std_logic_vector(7 downto 0) := "00001111";
signal dig1_i : std_logic_vector(7 downto 0) := "00110011";
signal dig2_i : std_logic_vector(7 downto 0) := "11001100";
signal dig3_i : std_logic_vector(7 downto 0) := "11110000";
signal ss_sel_o : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
begin -- sim
-- component instantiation
DUT: seven_segment_driver generic map (
g_refresh_rate => 3)
port map (
clk_i => clk_i,
reset_i => reset_i,
dig0_i => dig0_i,
dig1_i => dig1_i,
dig2_i => dig2_i,
dig3_i => dig3_i,
ss_sel_o => ss_sel_o,
ss_o => ss_o);
-- clock generation
clk_i <= not clk_i after 5 ns;
reset_i <= '1' after 10 ns;
-- compare enable signals
-- a_en1_check: assert s_en_1_check = s_en_1_o report "Wrong enable generation by DUT_8" severity error;
-- a_en2_check: assert s_en_2_check = s_en_2_o report "Wrong enable generation by DUT_32" severity error;
end sim;
-------------------------------------------------------------------------------
configuration tb_bcd_driver_sim_cfg of tb_bcd_driver is
for sim
end for;
end tb_bcd_driver_sim_cfg;
-------------------------------------------------------------------------------
|
mit
|
es17m014/vhdl-counter
|
src/vhdl/gen_debouncer.vhd
|
1
|
1546
|
-- --------------------------------------------------------------
-- Title : Debounce Logic
-- Project : Counter
-- -------- ------------------------------------------------------
-- File : gen_debouncer.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 31.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : Debounce input signals from switches and buttons
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 31.10.2017 1.0 Martin Angermair
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture rtl of gen_debouncer is
signal s_delay1 : std_logic_vector(N-1 downto 0); -- delay signal between ff1 and ff2
signal s_delay2 : std_logic_vector(N-1 downto 0); -- delay signal between ff2 and ff2
signal s_delay3 : std_logic_vector(N-1 downto 0); -- delay signal between ff3 and and gatter
begin
process(clk_i, reset_i)
begin
if reset_i = '1' then
s_delay1 <= (others => '0');
s_delay2 <= (others => '0');
s_delay3 <= (others => '0');
elsif rising_edge(clk_i) then
s_delay1 <= data_i;
s_delay2 <= s_delay1;
s_delay3 <= s_delay2;
end if;
end process;
q_o <= s_delay1 and s_delay2 and s_delay3;
end rtl;
|
mit
|
es17m014/vhdl-counter
|
src/old/vhdl/bcd_driver.vhd
|
1
|
3181
|
-- --------------------------------------------------------------
-- Title : BCD driver
-- Project : Counter
-- --------------------------------------------------------------
-- File : bcd_dekoder.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 29.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : This unit is the driver for the BCD 7-seg module
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 29.10.2017 1.0 Martin Angermair init
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seven_segment_driver is
generic (g_refresh_rate : positive := 100000);
port ( clk_i : in std_logic; -- 100Mhz clock on Basys 3 FPGA board
reset_i : in std_logic; -- reset_i
dig0_i : in std_logic_vector(7 downto 0); -- first digit value
dig1_i : in std_logic_vector(7 downto 0); -- second digit value
dig2_i : in std_logic_vector(7 downto 0); -- third digit value
dig3_i : in std_logic_vector(7 downto 0); -- fourth digit value
ss_sel_o : out std_logic_vector(3 downto 0); -- 4 anode signals
ss_o : out std_logic_vector(7 downto 0)); -- cathode patterns of 7-segment display
end seven_segment_driver;
architecture rtl of seven_segment_driver is
TYPE led_refresh_state IS (SEG1, SEG2, SEG3, SEG4);
signal s_bcd_state : led_refresh_state;
signal s_1kHz : std_logic;
begin
-- refresh rate at which the 4 7-seg digits will be updated
e_1kHz_prescaler: entity work.prescaler generic map (G_N => g_refresh_rate) port map (clk_i, reset_i, s_1kHz, '0');
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs
p_bcd_mux_state: process(clk_i)
begin
if reset_i = '0' then -- asynchronous reset (active low)
ss_sel_o <= "1111"; -- disable all LED
ss_o <= "11111111";
s_bcd_state <= SEG1;
elsif rising_edge(clk_i) and s_1kHz = '1' then
case s_bcd_state is
when SEG1 =>
ss_sel_o <= "0111"; -- activate only LED1
ss_o <= dig0_i;
s_bcd_state <= SEG2;
when SEG2 =>
ss_sel_o <= "1011"; -- activate only LED2
ss_o <= dig1_i;
s_bcd_state <= SEG3;
when SEG3 =>
ss_sel_o <= "1101"; -- activate only LED3
ss_o <= dig2_i;
s_bcd_state <= SEG4;
when SEG4 =>
ss_sel_o <= "1110"; -- activate only LED4
ss_o <= dig3_i;
s_bcd_state <= SEG1;
end case;
end if;
end process p_bcd_mux_state;
end rtl;
|
mit
|
LucasMahieu/TP_secu
|
code/AES/vhd/vhd/dataunit_ddr.vhd
|
2
|
6942
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- DataUnit: this entity contains the actual encryption datapath (the control
-- and the key-related logic are in separate entities). It instantiate:
-- + the four columns making the AES states,
-- + the barrel shifter implementing the ShiftRows operation,
-- + a DDR register layer after the barrel shifter to balance the critical path
-----------------------------------------------------------------------
-- Component Declaration
entity dataunit_ddr is port (
inH : in std_logic_vector( 127 downto 0 );
key : in std_logic_vector( 127 downto 0 );
aux_sbox_in : in std_logic_vector(31 downto 0);
ctrl_dec : in T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
enable_SBox_sharing : T_ENABLE;
ctrl_barrel : in std_logic_vector( 1 downto 0 );
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken: out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
outH : out std_logic_vector( 127 downto 0 );
outKey : out std_logic_vector(31 downto 0);
fault_data_unit_port : in std_logic_vector( 7 downto 0 )
);
end dataunit_ddr;
-- Architecture of the Component
architecture a_dataunit of dataunit_ddr is
component column is port (
in_hi, in_lo : in std_logic_vector (7 downto 0);
side_in : in std_logic_vector( 31 downto 0 ); -- horizontal input for I/O
roundkey : in std_logic_vector( 31 downto 0 );
aux_sbox_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
enable_SBox_sharing : T_ENABLE;
--ctrl_sub : in T_CTRL_SUB;
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken: out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
side_out : out std_logic_vector( 31 downto 0 );
aux_sbox_out : out std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0);
fault_injection : in std_logic_vector( 7 downto 0)
);
end component;
component DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component L_barrel is
generic ( SIZE : integer := 32 );
port (
d_in : in std_logic_vector (SIZE-1 downto 0);
amount : in std_logic_vector (1 downto 0); -- 0 to 3
d_out : out std_logic_vector (SIZE-1 downto 0) ) ;
end component;
component pos_trigger is port (
switch : in std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
clock, reset : in std_logic;
value : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 ) );
end component;
signal column_out, barrel_out, sbox_regs_hi, sbox_regs_lo : std_logic_vector(31 downto 0);
signal side_data_in, side_data_out : std_logic_vector( 127 downto 0 );
signal broken_col : std_logic_vector( 4*C_ERR_SIGNAL_SIZE-1 downto 0 );
signal broken_du : std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
-- Fort fault injection
signal fault_sig : std_logic_vector( 7 downto 0 );
signal no_fault_sig : std_logic_vector( 7 downto 0 ) := "00000000";
begin
side_data_in <= inH; --*
fault_sig <= fault_data_unit_port;
-- for_col : for I in 0 to 3 generate
col0 : column port map(
sbox_regs_hi( 7 downto 0 ), sbox_regs_lo( 7 downto 0 ),
side_data_in( 31 downto 0 ), --*
key( 31 downto 0 ),
aux_sbox_in( 7 downto 0 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE-1 downto 0 ),
side_data_out( 31 downto 0 ), --*
outKey( 7 downto 0 ),
column_out( 7 downto 0 ),
fault_sig(7 downto 0)
);
col1 : column port map(
sbox_regs_hi( 15 downto 8 ), sbox_regs_lo( 15 downto 8 ),
side_data_in( 63 downto 32 ), --*
key( 63 downto 32 ),
aux_sbox_in( 15 downto 8 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*1+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE ),
side_data_out( 63 downto 32 ), --*
outKey( 15 downto 8 ),
column_out( 15 downto 8 ),
no_fault_sig(7 downto 0) );
col2 : column port map(
sbox_regs_hi( 23 downto 16 ), sbox_regs_lo( 23 downto 16 ),
side_data_in( 95 downto 64 ), --*
key( 95 downto 64 ),
aux_sbox_in( 23 downto 16 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*2+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE*2 ),
side_data_out( 95 downto 64 ), --*
outKey( 23 downto 16 ),
column_out( 23 downto 16 ),
no_fault_sig(7 downto 0) );
col3 : column port map(
sbox_regs_hi( 31 downto 24 ), sbox_regs_lo( 31 downto 24 ),
side_data_in( 127 downto 96 ), --*
key( 127 downto 96 ),
aux_sbox_in( 31 downto 24 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*3+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE*3 ),
side_data_out( 127 downto 96 ), --*
outKey( 31 downto 24 ),
column_out( 31 downto 24 ),
no_fault_sig(7 downto 0) );
-- end generate;
barrel_shifter : L_barrel port map( column_out, ctrl_barrel, barrel_out );
sbox_regs_layer : for I in 0 to 3 generate
sbox_DDR : DDR_register port map( din_hi=>barrel_out(8*I+7 downto 8*I),
din_lo=>barrel_out(8*I+7 downto 8*I),
dout_hi=>sbox_regs_hi(8*I+7 downto 8*I),
dout_lo=>sbox_regs_lo(8*I+7 downto 8*I),
rst=>reset, clk=>clock );
end generate; -- for I sbox_regs_layer
outH <= side_data_out; --*
broken_du <= not C_BROKEN
when ( broken_col = not( C_BROKEN & C_BROKEN & C_BROKEN & C_BROKEN ) )
else C_BROKEN;
broken <= broken_du;
end a_dataunit;
|
mit
|
es17m014/vhdl-counter
|
src/tb/io_ctrl_tb.vhd
|
1
|
2922
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Testbench for the io_ctrl module
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity io_ctrl_tb is
end io_ctrl_tb;
architecture sim of io_ctrl_tb is
component io_ctrl is
port (clk_i : in std_logic;
reset_i : in std_logic;
digits_i : in std_logic_vector(13 downto 0);
sw_i : in std_logic_vector(15 downto 0);
pb_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(7 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
swclean_o : out std_logic_vector(15 downto 0);
pbclean_o : out std_logic_vector(3 downto 0));
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal digits_i : std_logic_vector(13 downto 0);
signal sw_i : std_logic_vector(15 downto 0);
signal pb_i : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
signal ss_sel_o : std_logic_vector(3 downto 0);
signal swclean_o : std_logic_vector(15 downto 0);
signal pbclean_o : std_logic_vector(3 downto 0);
begin
-- Generate system clock 100 MHz
p_clk : process
begin
clk_i <= '0';
wait for 5 ns;
clk_i <= '1';
wait for 5 ns;
end process;
-- Component under test
p_io_ctrl : io_ctrl
port map (
clk_i => clk_i,
reset_i => reset_i,
digits_i => digits_i,
sw_i => sw_i,
pb_i => pb_i,
ss_o => ss_o,
ss_sel_o => ss_sel_o,
swclean_o => swclean_o,
pbclean_o => pbclean_o);
p_sim : process
begin
reset_i <= '1';
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
reset_i <= '0';
-- test debouncing
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 5 ns;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 5 ns;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 10 ms;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 10 ms;
end process;
end sim;
|
mit
|
es17m014/vhdl-counter
|
src/old/vhdl/mux7seg.vhd
|
1
|
2059
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : mux7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Multiplexer 4 inputs, 4 selector and one output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux7seg is
port (
sw_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end mux7seg;
architecture rtl of mux7seg is
component mux44to1 is
port (
digits_i : in std_logic_vector(15 downto 0);
sel_i : in std_logic_vector(1 downto 0);
digit_o : out std_logic_vector(3 downto 0)
);
end component;
component hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0)
);
end component;
signal digits_i : std_logic_vector(15 downto 0);
signal sel_i : std_logic_vector(1 downto 0);
signal digit_i : std_logic_vector(3 downto 0);
begin
digits_i <= X"1234";
ss_sel_o <= not sw_i;
sel_i(1) <= sw_i(2) or sw_i(3);
sel_i(0) <= sw_i(1) or sw_i(3);
dp_o <= '1';
comp1: mux44to1
port map(
digits_i => digits_i,
sel_i => sel_i,
digit_o => digit_i
);
comp2: hex7seg
port map(
digit_i => digit_i,
ss_o => ss_o
);
end rtl;
|
mit
|
digital-sound-antiques/vm2413
|
EnvelopeGenerator.vhd
|
2
|
6777
|
--
-- EnvelopeGenerator.vhd
-- The envelope generator module of VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity EnvelopeGenerator is
port (clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE);
end EnvelopeGenerator;
architecture RTL of EnvelopeGenerator is
component EnvelopeMemory port (
clk : in std_logic;
reset : in std_logic;
waddr : in SLOT_TYPE;
wr : in std_logic;
wdata : in EGDATA_TYPE;
raddr : in SLOT_TYPE;
rdata : out EGDATA_TYPE
);
end component;
component AttackTable port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end component;
signal rslot : SLOT_TYPE;
signal memin, memout : EGDATA_TYPE;
signal memwr : std_logic;
signal aridx : integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
signal ardata : DB_TYPE;
begin
ARTBL : AttackTable port map ( clk, aridx, ardata );
EGMEM : EnvelopeMemory port map ( clk, reset, slot, memwr, memin, rslot, memout );
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable rm : std_logic_vector(4 downto 0);
variable egtmp : std_logic_vector(DB_TYPE'high + 2 downto 0);
variable ntable : std_logic_vector(17 downto 0);
variable amphase : std_logic_vector(19 downto 0);
variable rslot_buf : SLOT_TYPE;
variable egphase : EGPHASE_TYPE;
variable egstate : EGSTATE_TYPE;
variable dphase : EGPHASE_TYPE;
begin
if(reset = '1') then
rm := (others=>'0');
lastkey := (others=>'0');
ntable := (others=>'1');
amphase(amphase'high downto amphase'high-4) := "00001";
amphase(amphase'high-5 downto 0) := (others=>'0');
memwr <= '0';
egstate := Finish;
egphase := (others=>'0');
rslot_buf := 0;
elsif(clk'event and clk='1') then if clkena ='1' then
-- White noise generator
for I in 17 downto 1 loop
ntable(I) := ntable(I-1);
end loop;
ntable(0) := ntable(17) xor ntable(14);
-- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz )
amphase := amphase + '1';
if amphase(amphase'high downto amphase'high-4) = "11111" then
amphase(amphase'high downto amphase'high-4) := "00001";
end if;
if stage = 0 then
egstate := memout.state;
egphase := memout.phase;
aridx <= CONV_INTEGER( egphase( egphase'high-1 downto egphase'high-7 ) );
elsif stage = 1 then
-- Wait for AttackTable
elsif stage = 2 then
case egstate is
when Attack =>
rm := '0'&ar;
egtmp := ("00"&tl) + ("00"&ardata);
when Decay =>
rm := '0'&dr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Release=>
rm := '0'&rr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Finish =>
egtmp(egtmp'high downto egtmp'high -1) := "00";
egtmp(egtmp'high-2 downto 0) := (others=>'1');
end case;
-- SD and HH
if ntable(0)='1' and slot/2 = 7 and rhythm = '1' then
egtmp := egtmp + "010000000";
end if;
-- Amplitude LFO
if am ='1' then
if (amphase(amphase'high) = '0') then
egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4)-'1'));
else
egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4)));
end if;
end if;
-- Generate output
if egtmp(egtmp'high downto egtmp'high-1) = "00" then
egout <= egtmp(egout'range);
else
egout <= (others=>'1');
end if;
if rm /= "00000" then
rm := rm + rks(3 downto 2);
if rm(rm'high)='1' then
rm(3 downto 0):="1111";
end if;
case egstate is
when Attack =>
dphase(dphase'high downto 5) := (others=>'0');
dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0));
dphase := SHL( dphase, rm(3 downto 0) );
egphase := egphase - dphase(egphase'range);
when Decay | Release =>
dphase(dphase'high downto 3) := (others=>'0');
dphase(2 downto 0) := '1'&rks(1 downto 0);
dphase := SHL(dphase, rm(3 downto 0) - '1');
egphase := egphase + dphase(egphase'range);
when Finish =>
null;
end case;
end if;
case egstate is
when Attack =>
if egphase(egphase'high) = '1' then
egphase := (others=>'0');
egstate := Decay;
end if;
when Decay =>
if egphase(egphase'high downto egphase'high-4) >= '0'&sl then
egstate := Release;
end if;
when Release =>
if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then
egstate:= Finish;
end if;
when Finish =>
egphase := (others => '1');
end case;
if lastkey(slot) = '0' and key = '1' then
egphase(egphase'high):= '0';
egphase(egphase'high-1 downto 0) := (others =>'1');
egstate:= Attack;
elsif lastkey(slot) = '1' and key = '0' and egstate /= Finish then
egstate:= Release;
end if;
lastkey(slot) := key;
-- update phase and state memory
memin <= ( state => egstate, phase => egphase );
memwr <='1';
-- read phase of next slot (prefetch)
if slot = 17 then
rslot_buf := 0;
else
rslot_buf := slot + 1;
end if;
rslot <= rslot_buf;
elsif stage = 3 then
-- wait for phase memory
memwr <='0';
end if;
end if; end if;
end process;
end RTL;
|
mit
|
caiopo/battleship-vhdl
|
src/comparador.vhd
|
1
|
1183
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparador is
port (compara, player, clock: in std_logic;
tiro: in std_logic_vector(13 downto 0);
address: in std_logic_vector(1 downto 0);
match: out std_logic
);
end comparador;
architecture comparador of comparador is
signal linha: std_logic_vector(13 downto 0);
component ROM is
port(player : in std_logic;
address : in std_logic_vector(1 downto 0);
data : out std_logic_vector(13 downto 0)
);
end component;
begin
-- cria a memoria designando os parametros de entrada: jogador atual e endereco de memoria; saida: linha correspondente ao endereco
memoria: ROM port map(player, address, linha);
process(compara, clock)
begin
if rising_edge(clock) then
if compara = '1' then
-- se o enable do comparador estiver ativo, testa se algum um bit do vetor da memoria e do tiro do jogador sao iguais a 1 na mesma posicao
if ((linha(13 downto 0) and tiro(13 downto 0)) /= "00000000000000") then
match <= '1';
end if;
else
match <= '0';
end if;
end if;
end process;
end comparador;
|
mit
|
es17m014/vhdl-counter
|
src/old/tb/tb_debounce_.vhd
|
1
|
2077
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_debounce.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_debounce is
end tb_debounce;
architecture sim of tb_debounce is
-- Declaration of the component under test
component debounce
port (
clk_i : in std_logic; --input clock
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic); --debounced signal
end component;
signal clk_i : std_logic;
signal btn_i : std_logic;
signal deb_o : std_logic;
begin
-- Instantiate the design under test
i_debounce : debounce
port map (
clk_i => clk_i,
btn_i => btn_i,
deb_o => deb_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for 50 ns;
clk_i <= '1';
wait for 50 ns;
end process p_clk;
-- Generate reset
p_reset : process
begin
reset_i <= '1';
wait for 120 ns;
reset_i <= '0';
wait;
end process p_reset;
p_stim : process
begin
data_i <= '0';
wait for 320 ns;
data_i <= '1';
wait for 400 ns;
data_i <= '0';
wait for 400 ns;
data_i <= '1';
wait for 400 ns;
-- stop simulation
assert false report "END OF SIMULATION" severity error;
end process p_stim;
end sim;
|
mit
|
TheMassController/VHDL_experimenting
|
project/UART/uart_transmit.vhd
|
1
|
11282
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
-- Handles the outgoing data.
-- A note about parity:
-- 0: odd parity
-- 1: even parity
-- 2: always 0 parity
-- 3: always 1 parity
-- if parity_bit is false, this parameter is ignored
-- On the next clockcycle from data_send_start the component will lock the data and send all the data, unless reset is asserted in the process.
-- If ready is low the uart transmitter is busy.
-- It is a violation of the UART standard to send 9 bits and a parity bit. This component will not care, however.
entity uart_transmit is
generic (
baudrate : Natural;
clk_freq : Natural;
parity_bit_en : boolean;
parity_bit_type : Natural range 0 to 3;
bit_count : Natural range 5 to 9;
stop_bits : Natural range 1 to 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
uart_tx : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(8 DOWNTO 0);
data_send_start : in STD_LOGIC; -- Signals that the data can now be send
ready : out STD_LOGIC
);
end uart_transmit;
architecture Behavioral of uart_transmit is
function BOOL_TO_INT(X : boolean) return integer is
begin
if X then
return 1;
else
return 0;
end if;
end BOOL_TO_INT;
-- Type definition
type state_type is (reset, wait_send, start_one, start_two, bit_one, bit_two, bit_end, parity_one, parity_two, stop_one, stop_two, restore_timing);
type output_type is (start, bits, parity, stop);
-- Constant definition
constant totalBitsSend : integer := 1 + bit_count + stop_bits + BOOL_TO_INT(parity_bit_en);
constant ticksPerHalfSend : integer := integer(clk_freq/(baudrate*2));
constant restorationTicks : natural := (clk_freq * totalBitsSend)/baudrate - (ticksPerHalfSend * totalBitsSend * 2);
-- Signals
-- Related to the timer
signal ticker_rst : STD_LOGIC := '1';
signal ticker_done : STD_LOGIC;
signal restore_rst : STD_LOGIC := '1';
signal restore_done : STD_LOGIC;
-- Related to the mux
signal cur_output : output_type := stop;
-- Related to the bit output selector and the parity generator.
-- On the falling edge of next_bit the next bit is send to the output_bit line and the parity_output is updated
signal lock_data : boolean := false;
signal next_bit : boolean := false;
signal output_bit : STD_LOGIC;
signal parity_output : STD_LOGIC;
-- The state variable of the FSM
signal state : state_type := reset;
-- Helper function for state transitions
function simple_state_transition(if0: state_type; if1 : state_type; var: STD_LOGIC) return state_type is
begin
if var = '1' then
return if1;
else
return if0;
end if;
end simple_state_transition;
begin
-- The ticker
ticker : entity work.simple_multishot_timer
generic map (
match_val => ticksPerHalfSend
)
port map (
clk => clk,
rst => ticker_rst,
done => ticker_done
);
-- Restoration ticker
rest_ticker : entity work.simple_multishot_timer
generic map (
match_val => restorationTicks
)
port map (
clk => clk,
rst => restore_rst,
done => restore_done
);
-- The mux
output_mux : process (cur_output, output_bit, parity_output)
begin
case cur_output is
when start =>
uart_tx <= '0';
when bits =>
uart_tx <= output_bit;
when parity =>
uart_tx <= parity_output;
when stop =>
uart_tx <= '1';
end case;
end process;
-- The parity generator
parity_gen : process(clk)
variable even : STD_LOGIC := '1';
variable last_next_bit : boolean := false;
begin
if rising_edge(clk) then
if not lock_data then
even := '1';
elsif next_bit then
last_next_bit := true;
elsif last_next_bit then
last_next_bit := false;
if output_bit = '1' then
even := not even;
end if;
end if;
end if;
case parity_bit_type is
when 0 =>
parity_output <= not even;
when 1 =>
parity_output <= even;
when 2 =>
parity_output <= '0';
when 3 =>
parity_output <= '1';
end case;
end process;
-- The data storage facility
bit_selector : process(clk)
variable cur_data : STD_LOGIC_VECTOR(bit_count - 1 DOWNTO 0) := (others => '0');
variable last_next_bit : boolean := false;
begin
if rising_edge(clk) then
if not lock_data then
cur_data := data_in(bit_count-1 DOWNTO 0);
elsif next_bit then
last_next_bit := true;
elsif last_next_bit then
last_next_bit := false;
cur_data := '0' & cur_data(bit_count - 1 DOWNTO 1);
end if;
end if;
output_bit <= cur_data(0);
end process;
state_selector : process(clk, rst)
variable bits_send : natural := 0;
variable stop_bits_send : natural := 0;
begin
if rst = '1' then
bits_send := 0;
stop_bits_send := 0;
state <= reset;
elsif rising_edge(clk) then
case state is
when reset =>
state <= wait_send;
when wait_send =>
bits_send := 0;
stop_bits_send := 0;
state <= simple_state_transition(wait_send, start_one, data_send_start);
when start_one =>
state <= simple_state_transition(start_one, start_two, ticker_done);
when start_two =>
state <= simple_state_transition(start_two, bit_one, ticker_done);
when bit_one =>
if ticker_done = '1' then
if bits_send = bit_count - 1 then
state <= bit_end;
else
state <= bit_two;
end if;
else
state <= bit_one;
end if;
when bit_two =>
if ticker_done = '1' then
bits_send := bits_send + 1;
state <= bit_one;
else
state <= bit_two;
end if;
when bit_end =>
if ticker_done = '1' then
if parity_bit_en then
state <= parity_one;
else
state <= stop_one;
end if;
else
state <= bit_end;
end if;
when parity_one =>
state <= simple_state_transition(parity_one, parity_two, ticker_done);
when parity_two =>
state <= simple_state_transition(parity_two, stop_one, ticker_done);
when stop_one =>
state <= simple_state_transition(stop_one, stop_two, ticker_done);
when stop_two =>
if ticker_done = '1' then
if stop_bits = 2 then
stop_bits_send := stop_bits_send + 1;
if stop_bits_send = stop_bits then
state <= restore_timing;
else
state <= stop_one;
end if;
else
state <= restore_timing;
end if;
else
state <= stop_two;
end if;
when restore_timing =>
if restore_done = '1' or restorationTicks = 0 then
state <= wait_send;
else
state <= restore_timing;
end if;
end case;
end if;
end process;
-- The state behaviour
state_output : process (state)
begin
case state is
when reset =>
ready <= '0';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '1';
when wait_send =>
ready <= '1';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '1';
when start_one =>
ready <= '0';
ticker_rst <= '0';
cur_output <= start;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when start_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= start;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when bit_one =>
ready <= '0';
ticker_rst <= '0';
cur_output <= bits;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when bit_two|bit_end =>
ready <= '0';
ticker_rst <= '0';
cur_output <= bits;
lock_data <= true;
next_bit <= true;
restore_rst <= '1';
when parity_one|parity_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= parity;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when stop_one|stop_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= stop;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when restore_timing =>
ready <= '0';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '0';
end case;
end process;
end Behavioral;
|
mit
|
LucasMahieu/TP_secu
|
code/AES/vhd/X2Time.vhd
|
2
|
589
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x2time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x2time;
-- Architecture of the Component
architecture a_x2time of x2time is
begin
b_out(7) <= b_in(5);
b_out(6) <= b_in(4);
b_out(5) <= b_in(3) xor b_in(7);
b_out(4) <= b_in(2) xor b_in(6) xor b_in(7);
b_out(3) <= b_in(1) xor b_in(6);
b_out(2) <= b_in(0) xor b_in(7);
b_out(1) <= b_in(6) xor b_in(7);
b_out(0) <= b_in(6);
end a_x2time;
|
mit
|
LucasMahieu/TP_secu
|
code/AES/vhd/vhd/X_e.vhd
|
2
|
461
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x_e is port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0) );
end x_e;
-- Architecture of the Component
architecture a_x_e of x_e is
begin
-- Moltiplication Process
d(3) <= a(3) xor a(2) xor a(1) xor a(0);
d(2) <= a(2) xor a(1) xor a(0);
d(1) <= a(1) xor a(0);
d(0) <= a(3) xor a(2) xor a(1);
end a_x_e;
|
mit
|
LucasMahieu/TP_secu
|
code/AES/vhd/MixColumn.vhd
|
2
|
1145
|
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity mixcolumn is
generic( G_ROW : integer range 0 to 3 );
port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end mixcolumn;
architecture a_mixcolumn of mixcolumn is
component mixcolumn0 is port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
component PreMcRot is
generic( G_ROW : integer range 0 to 3 );
port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
out_0, out_1, out_2, out_3 : out std_logic_vector (7 downto 0) ) ;
end component;
signal t0, t1, t2, t3 : std_logic_vector (7 downto 0);
begin
-- Rotate inputs accordingly with respect to the actual row index:
Rot : PreMcRot generic map( G_ROW=>G_ROW )
port map( in_0, in_1, in_2, in_3, t0, t1, t2, t3 );
-- Compute actual operation:
MC : mixcolumn0 port map( t0, t1, t2, t3, ctrl_dec, b_out );
end a_mixcolumn;
|
mit
|
TheMassController/VHDL_experimenting
|
project/main_file.vhd
|
1
|
3128
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity main_file is
Port (
--JA_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JB_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JC_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JD_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
slide_switch : in STD_LOGIC_VECTOR (7 downto 0);
--push_button : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_kath : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_an : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
usb_db : inout std_logic_vector(7 downto 0);
usb_write : in std_logic;
usb_astb : in std_logic;
usb_dstb : in std_logic;
usb_wait : out std_logic
);
end main_file;
architecture Behavioral of main_file is
constant address_map : addr_range_and_mapping_array := (
address_range_and_map(
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(3, bus_address_type'length))
),
address_range_and_map(
low => std_logic_vector(to_unsigned(4, bus_address_type'length))
));
signal rst : STD_LOGIC;
signal depp2demux : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal demux2depp : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2ss : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2mem : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal mem2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
rst <= '0';
concurrent : process(slide_switch)
begin
led <= slide_switch;
end process;
depp_slave_controller : entity work.depp_slave_controller
port map (
rst => rst,
clk => clk,
mst2slv => depp2demux,
slv2mst => demux2depp,
USB_DB => usb_db,
USB_WRITE => usb_write,
USB_ASTB => usb_astb,
USB_DSTB => usb_dstb,
USB_WAIT => usb_wait
);
demux : entity work.bus_demux
generic map (
ADDRESS_MAP => address_map
)
port map (
rst => rst,
mst2demux => depp2demux,
demux2mst => demux2depp,
demux2slv(0) => demux2ss,
demux2slv(1) => demux2mem,
slv2demux(0) => ss2demux,
slv2demux(1) => mem2demux
);
ss : entity work.seven_seg_controller
generic map (
hold_count => 200000,
digit_count => 4
)
port map (
clk => clk,
rst => rst,
mst2slv => demux2ss,
slv2mst => ss2demux,
digit_anodes => seven_seg_an,
kathode => seven_seg_kath
);
mem : entity work.bus_singleport_ram
generic map (
DEPTH_LOG2B => 11
)
port map (
rst => rst,
clk => clk,
mst2mem => demux2mem,
mem2mst => mem2demux
);
end Behavioral;
|
mit
|
es17m014/vhdl-counter
|
src/vhdl/mux44to1.vhd
|
1
|
1304
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : mux44to1.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Multiplexer 4 inputs, 4 selector and one output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of mux44to1 is
begin
process(sel_i, digits_i)
begin
case sel_i is
when "00" => digit_o <= digits_i(3 downto 0); -- Digit 1
when "01" => digit_o <= digits_i(7 downto 4); -- Digit 2
when "10" => digit_o <= digits_i(11 downto 8); -- Digit 3
when others => digit_o <= digits_i(15 downto 12); -- Digit 3
end case;
end process;
end rtl;
|
mit
|
caiopo/battleship-vhdl
|
src/vector_to_bcd.vhd
|
1
|
2933
|
library ieee;
use ieee.std_logic_1164.all;
entity vector_to_bcd is port(
input: in std_logic_vector(7 downto 0);
to_decod1, to_decod0: out std_logic_vector(3 downto 0)
);
end vector_to_bcd;
architecture behv of vector_to_bcd is
signal total: std_logic_vector(7 downto 0);
signal dec1, dec0: std_logic_vector(3 downto 0);
begin
-- converte um vetor de 8 bits em dois vetores de 4 bits em bcd
process(input)
begin
case input is
when "00000000" =>
dec1 <= "0000";
dec0 <= "0000";
when "00000001" =>
dec1 <= "0000";
dec0 <= "0001";
when "00000010" =>
dec1 <= "0000";
dec0 <= "0010";
when "00000011" =>
dec1 <= "0000";
dec0 <= "0011";
when "00000100" =>
dec1 <= "0000";
dec0 <= "0100";
when "00000101" =>
dec1 <= "0000";
dec0 <= "0101";
when "00000110" =>
dec1 <= "0000";
dec0 <= "0110";
when "00000111" =>
dec1 <= "0000";
dec0 <= "0111";
when "00001000" =>
dec1 <= "0000";
dec0 <= "1000";
when "00001001" =>
dec1 <= "0000";
dec0 <= "1001";
when "00001010" =>
dec1 <= "0001";
dec0 <= "0000";
when "00001011" =>
dec1 <= "0001";
dec0 <= "0001";
when "00001100" =>
dec1 <= "0001";
dec0 <= "0010";
when "00001101" =>
dec1 <= "0001";
dec0 <= "0011";
when "00001110" =>
dec1 <= "0001";
dec0 <= "0100";
when "00001111" =>
dec1 <= "0001";
dec0 <= "0101";
when "00010000" =>
dec1 <= "0001";
dec0 <= "0110";
when "00010001" =>
dec1 <= "0001";
dec0 <= "0111";
when "00010010" =>
dec1 <= "0001";
dec0 <= "1000";
when "00010011" =>
dec1 <= "0001";
dec0 <= "1001";
when "00010100" =>
dec1 <= "0010";
dec0 <= "0000";
when "00010101" =>
dec1 <= "0010";
dec0 <= "0001";
when "00010110" =>
dec1 <= "0010";
dec0 <= "0010";
when "00010111" =>
dec1 <= "0010";
dec0 <= "0011";
when "00011000" =>
dec1 <= "0010";
dec0 <= "0100";
when "00011001" =>
dec1 <= "0010";
dec0 <= "0101";
when "00011010" =>
dec1 <= "0010";
dec0 <= "0110";
when "00011011" =>
dec1 <= "0010";
dec0 <= "0111";
when "00011100" =>
dec1 <= "0010";
dec0 <= "1000";
when "00011101" =>
dec1 <= "0010";
dec0 <= "1001";
when "00011110" =>
dec1 <= "0011";
dec0 <= "0000";
when "00011111" =>
dec1 <= "0011";
dec0 <= "0001";
when "00100000" =>
dec1 <= "0011";
dec0 <= "0010";
when others =>
dec1 <= "1110";
dec0 <= "1110";
end case;
to_decod0 <= dec0;
to_decod1 <= dec1;
end process;
end behv;
|
mit
|
digital-sound-antiques/vm2413
|
AttackTable.vhd
|
2
|
2045
|
--
-- AttackTable.vhd
-- Envelope attack shaping table for VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity AttackTable is
port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end AttackTable;
architecture RTL of AttackTable is
type AR_ADJUST_ARRAY is array (addr'range) of DB_TYPE;
constant ar_adjust : AR_ADJUST_ARRAY :=(
"1111111","1111111","1101100","1100010","1011010","1010100","1010000","1001011",
"1001000","1000101","1000010","1000000","0111101","0111011","0111001","0111000",
"0110110","0110100","0110011","0110001","0110000","0101111","0101101","0101100",
"0101011","0101010","0101001","0101000","0100111","0100110","0100101","0100100",
"0100100","0100011","0100010","0100001","0100001","0100000","0011111","0011110",
"0011110","0011101","0011101","0011100","0011011","0011011","0011010","0011010",
"0011001","0011000","0011000","0010111","0010111","0010110","0010110","0010101",
"0010101","0010101","0010100","0010100","0010011","0010011","0010010","0010010",
"0010001","0010001","0010001","0010000","0010000","0001111","0001111","0001111",
"0001110","0001110","0001110","0001101","0001101","0001101","0001100","0001100",
"0001100","0001011","0001011","0001011","0001010","0001010","0001010","0001001",
"0001001","0001001","0001001","0001000","0001000","0001000","0000111","0000111",
"0000111","0000111","0000110","0000110","0000110","0000110","0000101","0000101",
"0000101","0000100","0000100","0000100","0000100","0000100","0000011","0000011",
"0000011","0000011","0000010","0000010","0000010","0000010","0000001","0000001",
"0000001","0000001","0000001","0000000","0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= ar_adjust(addr'high - addr);
end if;
end process;
end RTL;
|
mit
|
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg0.vhd
|
1
|
1711
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where slices of next signal are set conditionally
--
ENTITY AssignToASliceOfReg0 IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg0 IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "1" THEN
r_next_15downto8 <= data_in_data;
ELSE
r_next_15downto8 <= r(15 DOWNTO 8);
END IF;
END PROCESS;
assig_process_r_next_7downto0: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
r_next_7downto0 <= data_in_data;
ELSE
r_next_7downto0 <= r(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/@a@l@t@e@r@a_@l@n@s@i@m_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
|
5
|
128
|
library verilog;
use verilog.vl_types.all;
entity ALTERA_LNSIM_MEMORY_INITIALIZATION is
end ALTERA_LNSIM_MEMORY_INITIALIZATION;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/alt_dspbuilder_cast_GN46N4UJ5S.vhd
|
20
|
844
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_testbench_salt_GN6DKNTQ5M.vhd
|
13
|
1747
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 2) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/alt_dspbuilder_SInitDelay.vhd
|
20
|
3601
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2007 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SInitDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1";
ResetValue : std_logic_vector :="00000001"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SInitDelay;
architecture SInitDelay_SYNTH of alt_dspbuilder_SInitDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <= ResetValue;
elsif clock'event and clock='1' then
if (sclr ='1') then
result <= ResetValue;
elsif enadff ='1' then
result <= dataa_int;
end if;
end if;
end process;
end generate;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => ResetValue);
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => ResetValue);
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if;
end if;
end process;
result <= DelayLine(lpm_delay-1);
end generate;
end SInitDelay_SYNTH;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_constant_GNNKZSYI73.vhd
|
20
|
592
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/ama_register_with_ext_function/_primary.vhd
|
5
|
1580
|
library verilog;
use verilog.vl_types.all;
entity ama_register_with_ext_function is
generic(
width_data_in : integer := 1;
width_data_out : vl_notype;
register_clock : string := "UNREGISTERED";
register_aclr : string := "NONE";
port_sign : string := "PORT_UNUSED";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_sign_ext_output: vl_notype;
width_sign_ext_output_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of register_clock : constant is 1;
attribute mti_svvh_generic_type of register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_sign_ext_output : constant is 3;
attribute mti_svvh_generic_type of width_sign_ext_output_msb : constant is 3;
end ama_register_with_ext_function;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/alt_dspbuilder_sAltrPropagate.vhd
|
20
|
1635
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrPropagate is
generic (
WIDTH : positive ;
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic_vector(WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0)
);
end alt_dspbuilder_sAltrPropagate ;
architecture sAltrPropagate_Synth of alt_dspbuilder_sAltrPropagate is
begin
r<=d;
end sAltrPropagate_Synth;
|
mit
|
VladisM/MARK_II
|
VHDL/src/sdram/sdram_driver.vhd
|
1
|
41949
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdram_driver is
port(
clk_100: in std_logic;
res: in std_logic;
address: in std_logic_vector(22 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
busy: out std_logic;
wr_req: in std_logic;
rd_req: in std_logic;
data_out_ready: out std_logic;
ack: out std_logic;
sdram_ras_n: out std_logic;
sdram_cas_n: out std_logic;
sdram_we_n: out std_logic;
sdram_addr: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_data: inout std_logic_vector(7 downto 0)
);
end entity sdram_driver;
architecture sdram_driver_arch of sdram_driver is
component data_io_buff is
port(
datain: in std_logic_vector (15 downto 0);
oe: in std_logic_vector (15 downto 0);
dataio: inout std_logic_vector (15 downto 0);
dataout: out std_logic_vector (15 downto 0)
);
end component;
--data from sdram (registered)
signal captured_data: std_logic_vector(7 downto 0);
--oe control signal for bidir buff
signal bidir_buff_oe, bidir_buff_oe_buff: std_logic;
--datainput to bidir buff
signal bidir_buff_datain, bidir_buff_datain_buff: std_logic_vector(7 downto 0);
--unregistered output from bidirbuff
signal sdram_dataout: std_logic_vector(7 downto 0);
--these signals are controling control outputs for sdram
signal sdram_addr_unbuff: std_logic_vector(12 downto 0);
signal sdram_ba_unbuff: std_logic_vector(1 downto 0);
signal sdram_control: std_logic_vector(2 downto 0);
--comands for sdram maped into vectors
constant com_device_deselect: std_logic_vector(2 downto 0):= "000";
constant com_no_operation: std_logic_vector(2 downto 0):= "111";
constant com_burst_stop: std_logic_vector(2 downto 0):= "110";
constant com_read: std_logic_vector(2 downto 0):= "101"; --bank and A0..A9 must be valid; A10 must be low
constant com_read_precharge: std_logic_vector(2 downto 0):= "101"; --A10 must be high
constant com_write: std_logic_vector(2 downto 0):= "100"; --A10 must be low
constant com_write_precharge: std_logic_vector(2 downto 0):= "100";--A10 must be high
constant com_bank_active: std_logic_vector(2 downto 0):= "011"; --bank and addr must be valid
constant com_precharge_select_bank: std_logic_vector(2 downto 0):= "010";--bank valid and A10 low; rest of addr dont care
constant com_precharge_all_banks: std_logic_vector(2 downto 0):= "010"; --A10 high; others dont care
constant com_cbr_auto_refresh: std_logic_vector(2 downto 0):= "001"; --everything dont care
constant com_mode_reg_set: std_logic_vector(2 downto 0):= "000"; --bank low; A10 low; A0..A9 valid
--put this constant on address bus it is configuration register
-- CAS = 2; burst = 4 words;
constant mode_register: std_logic_vector(12 downto 0) := "0000000100010";
--this signal is we into output register
signal write_input_data_reg: std_logic;
--clean refresh counter
signal refresh_counter_clean: std_logic;
--signalize refresh need
signal force_refresh: std_logic;
--for init seq
signal init_counter_val: unsigned(17 downto 0);
signal init_counter_clean: std_logic; -- clean startup counter
--main sdram FSM
type sdram_fsm_state_type is (
init_delay, init_precharge, init_precharge_wait,
init_refresh_0, init_refresh_1,
init_refresh_2, init_refresh_3,
init_refresh_4, init_refresh_5,
init_refresh_6, init_refresh_7,
init_refresh_0_wait, init_refresh_1_wait,
init_refresh_2_wait, init_refresh_3_wait,
init_refresh_4_wait, init_refresh_5_wait,
init_refresh_6_wait, init_refresh_7_wait,
init_mode_reg, init_mode_reg_wait, idle,
autorefresh, autorefresh_wait,
bank_active, bank_active_nop0, bank_active_nop1,
write_data, write_nop_0, write_nop_1, write_nop_2, write_nop_3, write_nop_4, write_nop_5, write_nop_6,
read_command, read_nop_0, read_nop_1, read_nop_2, read_nop_3, read_nop_4, read_nop_5, read_nop_6, read_completed
);
signal fsm_state: sdram_fsm_state_type := init_delay;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of fsm_state : signal is "ONE-HOT";
--address parts
signal address_ba: std_logic_vector(1 downto 0);
signal address_row: std_logic_vector(12 downto 0);
signal address_col: std_logic_vector(9 downto 0);
--signals from command register
signal cmd_wr_req: std_logic;
--~ signal cmd_rd_req: std_logic;
signal cmd_address: std_logic_vector(22 downto 0);
signal cmd_data_in: std_logic_vector(31 downto 0);
signal write_cmd_reg: std_logic;
begin
--split address into multiple parts
address_ba <= cmd_address(22 downto 21);
address_row <= cmd_address(20 downto 8);
address_col <= cmd_address(7 downto 0) & "00";
--bidirectional buffer for DQ pins
sdram_dataout <= sdram_data;
sdram_data <= bidir_buff_datain_buff when bidir_buff_oe_buff = '1' else (others => 'Z');
process(clk_100) is
variable bidir_buff_oe_var: std_logic := '0';
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_oe_var := '0';
else
bidir_buff_oe_var := bidir_buff_oe;
end if;
end if;
bidir_buff_oe_buff <= bidir_buff_oe_var;
end process;
process(clk_100) is
variable bidir_buff_datain_var: std_logic_vector(7 downto 0) := x"00";
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_datain_var := (others => '0');
else
bidir_buff_datain_var := bidir_buff_datain;
end if;
end if;
bidir_buff_datain_buff <= bidir_buff_datain_var;
end process;
--register input data from sdram
process(clk_100) is
variable captured_data_var: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
captured_data_var := (others => '0');
else
captured_data_var := sdram_dataout;
end if;
end if;
captured_data <= captured_data_var;
end process;
--this is register for dataout
process(clk_100) is
variable input_data_register_var_low: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mlow: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mhigh: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_high: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
input_data_register_var_low := (others => '0');
input_data_register_var_mlow := (others => '0');
input_data_register_var_mhigh := (others => '0');
input_data_register_var_high := (others => '0');
elsif write_input_data_reg = '1' then
input_data_register_var_high := input_data_register_var_mhigh;
input_data_register_var_mhigh := input_data_register_var_mlow;
input_data_register_var_mlow := input_data_register_var_low;
input_data_register_var_low := captured_data;
end if;
end if;
data_out <= input_data_register_var_high & input_data_register_var_mhigh & input_data_register_var_mlow & input_data_register_var_low;
end process;
--register all outputs
process(clk_100) is
variable sdram_ras_n_var: std_logic := '1';
variable sdram_cas_n_var: std_logic := '1';
variable sdram_we_n_var: std_logic := '1';
variable sdram_addr_var: std_logic_vector(12 downto 0) := (others => '0');
variable sdram_ba_var: std_logic_vector(1 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
sdram_ras_n_var := '1';
sdram_cas_n_var := '1';
sdram_we_n_var := '1';
sdram_addr_var := (others => '0');
sdram_ba_var := (others => '0');
else
sdram_addr_var := sdram_addr_unbuff;
sdram_ba_var := sdram_ba_unbuff;
sdram_ras_n_var := sdram_control(2);
sdram_cas_n_var := sdram_control(1);
sdram_we_n_var := sdram_control(0);
end if;
end if;
sdram_ras_n <= sdram_ras_n_var;
sdram_cas_n <= sdram_cas_n_var;
sdram_we_n <= sdram_we_n_var;
sdram_addr <= sdram_addr_var;
sdram_ba <= sdram_ba_var;
end process;
--refresh counter
process(clk_100) is
variable counter_var: unsigned(12 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or refresh_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
--refresh is needed each 7.8125 us
--this call it each 4.096 us
force_refresh <= counter_var(12);
end process;
--startup counter
process(clk_100) is
variable counter_var: unsigned(17 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or init_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
init_counter_val <= counter_var;
end process;
--register for command
process(clk_100) is
variable wr_req_var: std_logic := '0';
--~ variable rd_req_var: std_logic := '0';
variable address_var: std_logic_vector(22 downto 0) := (others => '0');
variable data_in_var: std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
wr_req_var := '0';
--~ rd_req_var := '0';
address_var := (others => '0');
data_in_var := (others => '0');
elsif write_cmd_reg = '1' then
wr_req_var := wr_req;
--~ rd_req_var := rd_req;
address_var := address;
data_in_var := data_in;
end if;
end if;
cmd_wr_req <= wr_req_var;
--~ cmd_rd_req <= rd_req_var;
cmd_address <= address_var;
cmd_data_in <= data_in_var;
end process;
--main fsm
process(clk_100) is
begin
if rising_edge(clk_100) then
if res = '1' then
fsm_state <= init_delay;
else
case fsm_state is
when init_delay =>
if init_counter_val = 200000 then
fsm_state <= init_precharge;
else
fsm_state <= init_delay;
end if;
when init_precharge =>
fsm_state <= init_precharge_wait;
when init_precharge_wait =>
if init_counter_val = 2 then
fsm_state <= init_refresh_0;
else
fsm_state <= init_precharge_wait;
end if;
when init_refresh_0 =>
fsm_state <= init_refresh_0_wait;
when init_refresh_0_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_1;
else
fsm_state <= init_refresh_0_wait;
end if;
when init_refresh_1 =>
fsm_state <= init_refresh_1_wait;
when init_refresh_1_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_2;
else
fsm_state <= init_refresh_1_wait;
end if;
when init_refresh_2 =>
fsm_state <= init_refresh_2_wait;
when init_refresh_2_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_3;
else
fsm_state <= init_refresh_2_wait;
end if;
when init_refresh_3 =>
fsm_state <= init_refresh_3_wait;
when init_refresh_3_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_4;
else
fsm_state <= init_refresh_3_wait;
end if;
when init_refresh_4 =>
fsm_state <= init_refresh_4_wait;
when init_refresh_4_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_5;
else
fsm_state <= init_refresh_4_wait;
end if;
when init_refresh_5 =>
fsm_state <= init_refresh_5_wait;
when init_refresh_5_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_6;
else
fsm_state <= init_refresh_5_wait;
end if;
when init_refresh_6 =>
fsm_state <= init_refresh_6_wait;
when init_refresh_6_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_7;
else
fsm_state <= init_refresh_6_wait;
end if;
when init_refresh_7 =>
fsm_state <= init_refresh_7_wait;
when init_refresh_7_wait =>
if init_counter_val = 7 then
fsm_state <= init_mode_reg;
else
fsm_state <= init_refresh_7_wait;
end if;
when init_mode_reg =>
fsm_state <= init_mode_reg_wait;
when init_mode_reg_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= init_mode_reg_wait;
end if;
--there is idle process
when idle =>
if force_refresh = '1' then
fsm_state <= autorefresh;
elsif wr_req = '1' or rd_req = '1' then
fsm_state <= bank_active;
else
fsm_state <= idle;
end if;
--autorefresh stage
when autorefresh =>
fsm_state <= autorefresh_wait;
when autorefresh_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= autorefresh_wait;
end if;
--active bank and row
when bank_active =>
fsm_state <= bank_active_nop0;
when bank_active_nop0 =>
fsm_state <= bank_active_nop1;
when bank_active_nop1 =>
if cmd_wr_req = '1' then
fsm_state <= write_data;
else
fsm_state <= read_command;
end if;
-- write data into sdram
when write_data =>
fsm_state <= write_nop_0;
when write_nop_0 =>
fsm_state <= write_nop_1;
when write_nop_1 =>
fsm_state <= write_nop_2;
when write_nop_2 =>
fsm_state <= write_nop_3;
when write_nop_3 =>
fsm_state <= write_nop_4;
when write_nop_4 =>
fsm_state <= write_nop_5;
when write_nop_5 =>
fsm_state <= write_nop_6;
when write_nop_6 =>
fsm_state <= idle;
--read data block
when read_command =>
fsm_state <= read_nop_0;
when read_nop_0 =>
fsm_state <= read_nop_1;
when read_nop_1 =>
fsm_state <= read_nop_2;
when read_nop_2 =>
fsm_state <= read_nop_3;
when read_nop_3 =>
fsm_state <= read_nop_4;
when read_nop_4 =>
fsm_state <= read_nop_5;
when read_nop_5 =>
fsm_state <= read_nop_6;
when read_nop_6 =>
fsm_state <= read_completed;
when read_completed =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state, address_row, address_ba, address_col, cmd_data_in) is
begin
case fsm_state is
when init_delay =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_precharge_all_banks;
sdram_addr_unbuff <= "0010000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_mode_reg_set;
sdram_addr_unbuff <= mode_register;
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when idle =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '0';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '1';
ack <= '0';
when autorefresh =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when autorefresh_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_bank_active;
sdram_addr_unbuff <= address_row;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '1';
when bank_active_nop0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active_nop1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_data =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_write_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= cmd_data_in(31 downto 24);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(23 downto 16);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(15 downto 8);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(7 downto 0);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_command =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_read_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_completed =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '1';
write_cmd_reg <= '0';
ack <= '0';
end case;
end process;
end architecture sdram_driver_arch;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_vcc.vhd
|
20
|
747
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
mit
|
VladisM/MARK_II
|
VHDL/src/interruptControl/intController.vhd
|
1
|
22667
|
-- Interrupt controller peripheral
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intController is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"00000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
int_req: in std_logic_vector(15 downto 0); --peripherals may request interrupt with this signal
int_accept: in std_logic; --from the CPU
int_completed: in std_logic; --from the CPU
int_cpu_address: out std_logic_vector(23 downto 0); --connect this to the CPU, this is address of ISR
int_cpu_rq: out std_logic
);
end entity intController;
architecture intControllerArch of intController is
--this is one rs flip flop
component intRSFF is
port(
clk: in std_logic;
res: in std_logic;
intSet: in std_logic;
intTaken: in std_logic;
intOut: out std_logic
);
end component intRSFF;
--FSM for interrupt control
component intFSM is
port(
res: in std_logic;
clk: in std_logic;
intFiltred: in std_logic_vector(15 downto 0);
int_cpu_addr_sel: out std_logic_vector(3 downto 0);
int_cpu_rq: out std_logic;
int_taken: out std_logic_vector(15 downto 0);
int_accept: in std_logic;
int_completed: in std_logic
);
end component intFSM;
component vector_reg is
port(
clk: in std_logic;
res: in std_logic;
we_a: in std_logic;
we_b: in std_logic;
data_mosi: in std_logic_vector(31 downto 0);
q: out std_logic_vector(23 downto 0)
);
end component vector_reg;
--chip select signal for mask register
signal reg_sel_int_msk: std_logic;
signal interrupt_mask_reg: std_logic_vector(15 downto 0); --interrupt mask
signal intTaken: std_logic_vector(15 downto 0); --signal from FSM to RSFF, this reset FF after interrupt is taken
signal intRaw: std_logic_vector(15 downto 0); --unmasked signals
signal intFiltred: std_logic_vector(15 downto 0); --masked int signals
signal int_cpu_addr_sel: std_logic_vector(3 downto 0);
signal reg_sel_vector: std_logic_vector(15 downto 0);
signal selected_miso_vector: std_logic_vector(23 downto 0);
signal vector_0, vector_1, vector_2, vector_3, vector_4, vector_5,
vector_6, vector_7, vector_8, vector_9, vector_10, vector_11, vector_12,
vector_13, vector_14, vector_15: std_logic_vector(23 downto 0);
signal int_cpu_address_signal: std_logic_vector(23 downto 0);
signal int_cpu_rq_signal: std_logic;
begin
--chip select
process(address) is begin
if(unsigned(address) = BASE_ADDRESS)then
reg_sel_int_msk <= '1';
else
reg_sel_int_msk <= '0';
end if;
end process;
--register for interrupt mask
process(clk, res, WR, data_mosi, reg_sel_int_msk) is begin
if rising_edge(clk) then
if(res = '1') then
interrupt_mask_reg <= (others => '0');
elsif (WR = '1' and reg_sel_int_msk = '1') then
interrupt_mask_reg <= data_mosi(15 downto 0);
end if;
end if;
end process;
--output from register
data_miso <= x"0000" & interrupt_mask_reg when (RD = '1' and reg_sel_int_msk = '1') else (others => 'Z');
ack <= '1' when
(WR = '1' and reg_sel_int_msk = '1') or
(RD = '1' and reg_sel_int_msk = '1') or
(RD = '1' and reg_sel_vector /= x"0000") or
(WR = '1' and reg_sel_vector /= x"0000")
else '0';
--this is 32 RS flip flops, for asynchronous inputs
gen_intrsff:
for I in 15 downto 0 generate
intRSFF_gen: intRSFF port map(clk, res, int_req(I), intTaken(I), intRaw(I));
end generate gen_intrsff;
--interrupt mask
intFiltred <= intRaw and interrupt_mask_reg;
--FSM which control interrupts
fsm: intFSM
port map(res, clk, intFiltred, int_cpu_addr_sel, int_cpu_rq_signal, intTaken, int_accept, int_completed);
reg_sel_vector(0) <= '1' when (unsigned(address) = (BASE_ADDRESS + 1)) else '0';
reg_sel_vector(1) <= '1' when (unsigned(address) = (BASE_ADDRESS + 2)) else '0';
reg_sel_vector(2) <= '1' when (unsigned(address) = (BASE_ADDRESS + 3)) else '0';
reg_sel_vector(3) <= '1' when (unsigned(address) = (BASE_ADDRESS + 4)) else '0';
reg_sel_vector(4) <= '1' when (unsigned(address) = (BASE_ADDRESS + 5)) else '0';
reg_sel_vector(5) <= '1' when (unsigned(address) = (BASE_ADDRESS + 6)) else '0';
reg_sel_vector(6) <= '1' when (unsigned(address) = (BASE_ADDRESS + 7)) else '0';
reg_sel_vector(7) <= '1' when (unsigned(address) = (BASE_ADDRESS + 8)) else '0';
reg_sel_vector(8) <= '1' when (unsigned(address) = (BASE_ADDRESS + 9)) else '0';
reg_sel_vector(9) <= '1' when (unsigned(address) = (BASE_ADDRESS + 10)) else '0';
reg_sel_vector(10) <= '1' when (unsigned(address) = (BASE_ADDRESS + 11)) else '0';
reg_sel_vector(11) <= '1' when (unsigned(address) = (BASE_ADDRESS + 12)) else '0';
reg_sel_vector(12) <= '1' when (unsigned(address) = (BASE_ADDRESS + 13)) else '0';
reg_sel_vector(13) <= '1' when (unsigned(address) = (BASE_ADDRESS + 14)) else '0';
reg_sel_vector(14) <= '1' when (unsigned(address) = (BASE_ADDRESS + 15)) else '0';
reg_sel_vector(15) <= '1' when (unsigned(address) = (BASE_ADDRESS + 16)) else '0';
vectorreg0: vector_reg port map(clk, res, reg_sel_vector(0), WR, data_mosi, vector_0);
vectorreg1: vector_reg port map(clk, res, reg_sel_vector(1), WR, data_mosi, vector_1);
vectorreg2: vector_reg port map(clk, res, reg_sel_vector(2), WR, data_mosi, vector_2);
vectorreg3: vector_reg port map(clk, res, reg_sel_vector(3), WR, data_mosi, vector_3);
vectorreg4: vector_reg port map(clk, res, reg_sel_vector(4), WR, data_mosi, vector_4);
vectorreg5: vector_reg port map(clk, res, reg_sel_vector(5), WR, data_mosi, vector_5);
vectorreg6: vector_reg port map(clk, res, reg_sel_vector(6), WR, data_mosi, vector_6);
vectorreg7: vector_reg port map(clk, res, reg_sel_vector(7), WR, data_mosi, vector_7);
vectorreg8: vector_reg port map(clk, res, reg_sel_vector(8), WR, data_mosi, vector_8);
vectorreg9: vector_reg port map(clk, res, reg_sel_vector(9), WR, data_mosi, vector_9);
vectorreg10: vector_reg port map(clk, res, reg_sel_vector(10), WR, data_mosi, vector_10);
vectorreg11: vector_reg port map(clk, res, reg_sel_vector(11), WR, data_mosi, vector_11);
vectorreg12: vector_reg port map(clk, res, reg_sel_vector(12), WR, data_mosi, vector_12);
vectorreg13: vector_reg port map(clk, res, reg_sel_vector(13), WR, data_mosi, vector_13);
vectorreg14: vector_reg port map(clk, res, reg_sel_vector(14), WR, data_mosi, vector_14);
vectorreg15: vector_reg port map(clk, res, reg_sel_vector(15), WR, data_mosi, vector_15);
process(reg_sel_vector, vector_0, vector_1, vector_2, vector_3, vector_4,
vector_5, vector_6, vector_7, vector_8, vector_9, vector_10, vector_11,
vector_12, vector_13, vector_14, vector_15) is begin
case reg_sel_vector is
when x"0001" => selected_miso_vector <= vector_0;
when x"0002" => selected_miso_vector <= vector_1;
when x"0004" => selected_miso_vector <= vector_2;
when x"0008" => selected_miso_vector <= vector_3;
when x"0010" => selected_miso_vector <= vector_4;
when x"0020" => selected_miso_vector <= vector_5;
when x"0040" => selected_miso_vector <= vector_6;
when x"0080" => selected_miso_vector <= vector_7;
when x"0100" => selected_miso_vector <= vector_8;
when x"0200" => selected_miso_vector <= vector_9;
when x"0400" => selected_miso_vector <= vector_10;
when x"0800" => selected_miso_vector <= vector_11;
when x"1000" => selected_miso_vector <= vector_12;
when x"2000" => selected_miso_vector <= vector_13;
when x"4000" => selected_miso_vector <= vector_14;
when others => selected_miso_vector <= vector_15;
end case;
end process;
process(RD, reg_sel_vector, selected_miso_vector) is begin
if ((RD = '1') and (reg_sel_vector /= x"0000")) then
data_miso <= x"00" & selected_miso_vector;
else
data_miso <= (others => 'Z');
end if;
end process;
process(int_cpu_addr_sel, vector_0, vector_1, vector_2, vector_3, vector_4,
vector_5, vector_6, vector_7, vector_8, vector_9, vector_10, vector_11,
vector_12, vector_13, vector_14, vector_15) is begin
case int_cpu_addr_sel is
when "0000" => int_cpu_address_signal <= vector_0;
when "0001" => int_cpu_address_signal <= vector_1;
when "0010" => int_cpu_address_signal <= vector_2;
when "0011" => int_cpu_address_signal <= vector_3;
when "0100" => int_cpu_address_signal <= vector_4;
when "0101" => int_cpu_address_signal <= vector_5;
when "0110" => int_cpu_address_signal <= vector_6;
when "0111" => int_cpu_address_signal <= vector_7;
when "1000" => int_cpu_address_signal <= vector_8;
when "1001" => int_cpu_address_signal <= vector_9;
when "1010" => int_cpu_address_signal <= vector_10;
when "1011" => int_cpu_address_signal <= vector_11;
when "1100" => int_cpu_address_signal <= vector_12;
when "1101" => int_cpu_address_signal <= vector_13;
when "1110" => int_cpu_address_signal <= vector_14;
when others => int_cpu_address_signal <= vector_15;
end case;
end process;
process(clk) is
variable vector_reg: std_logic_vector(23 downto 0);
variable rq_reg: std_logic;
begin
if rising_edge(clk) then
if res = '1' then
vector_reg := (others => '0');
rq_reg := '0';
else
vector_reg := int_cpu_address_signal;
rq_reg := int_cpu_rq_signal;
end if;
end if;
int_cpu_rq <= rq_reg;
int_cpu_address <= vector_reg;
end process;
end architecture intControllerArch;
library ieee;
use ieee.std_logic_1164.all;
entity vector_reg is
port(
clk: in std_logic;
res: in std_logic;
we_a: in std_logic;
we_b: in std_logic;
data_mosi: in std_logic_vector(31 downto 0);
q: out std_logic_vector(23 downto 0)
);
end entity vector_reg;
architecture vector_reg_arch of vector_reg is
begin
process(clk) is
variable vector: std_logic_vector(23 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
vector := (others => '0');
elsif we_a = '1' and we_b = '1' then
vector := data_mosi(23 downto 0);
end if;
end if;
q <= vector;
end process;
end architecture vector_reg_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intRSFF is
port(
clk: in std_logic;
res: in std_logic;
intSet: in std_logic;
intTaken: in std_logic;
intOut: out std_logic
);
end entity intRSFF;
architecture intRSFFArch of intRSFF is
begin
process(clk, res, intSet, intTaken) is
variable var: std_logic;
begin
if(rising_edge(clk))then
if(intTaken = '1' or res = '1') then
var := '0';
elsif(intSet = '1') then
var := '1';
end if;
end if;
intOut <= var;
end process;
end architecture intRSFFArch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intFSM is
port(
res: in std_logic;
clk: in std_logic;
intFiltred: in std_logic_vector(15 downto 0);
int_cpu_addr_sel: out std_logic_vector(3 downto 0);
int_cpu_rq: out std_logic;
int_taken: out std_logic_vector(15 downto 0);
int_accept: in std_logic;
int_completed: in std_logic
);
end entity intFSM;
architecture intFSMArch of intFSM is
--states for FSM
type states is (
start, wait_for_int_come, wait_for_int_complete,
setint0, clearint0, setint1, clearint1, setint2, clearint2,
setint3, clearint3, setint4, clearint4, setint5, clearint5,
setint6, clearint6, setint7, clearint7, setint8, clearint8,
setint9, clearint9, setint10, clearint10, setint11, clearint11,
setint12, clearint12, setint13, clearint13, setint14, clearint14,
setint15, clearint15
);
--this is reg holding state
signal state: states;
begin
--logic to set up next state
process (clk, res, intFiltred, int_accept, int_completed) begin
if (rising_edge(clk)) then
if res = '1' then
state <= start;
else
case state is
when start => state <= wait_for_int_come;
when wait_for_int_come => --this is also priority decoder :)
if intFiltred(0) = '1' then state <= setint0;
elsif intFiltred(1) = '1' then state <= setint1;
elsif intFiltred(2) = '1' then state <= setint2;
elsif intFiltred(3) = '1' then state <= setint3;
elsif intFiltred(4) = '1' then state <= setint4;
elsif intFiltred(5) = '1' then state <= setint5;
elsif intFiltred(6) = '1' then state <= setint6;
elsif intFiltred(7) = '1' then state <= setint7;
elsif intFiltred(8) = '1' then state <= setint8;
elsif intFiltred(9) = '1' then state <= setint9;
elsif intFiltred(10) = '1' then state <= setint10;
elsif intFiltred(11) = '1' then state <= setint11;
elsif intFiltred(12) = '1' then state <= setint12;
elsif intFiltred(13) = '1' then state <= setint13;
elsif intFiltred(14) = '1' then state <= setint14;
elsif intFiltred(15) = '1' then state <= setint15;
else state <= start;
end if;
--ugly things, waiting for CPU take interrupt routine
when setint0 => if(int_accept = '1') then state <= clearint0; else state <= setint0; end if;
when setint1 => if(int_accept = '1') then state <= clearint1; else state <= setint1; end if;
when setint2 => if(int_accept = '1') then state <= clearint2; else state <= setint2; end if;
when setint3 => if(int_accept = '1') then state <= clearint3; else state <= setint3; end if;
when setint4 => if(int_accept = '1') then state <= clearint4; else state <= setint4; end if;
when setint5 => if(int_accept = '1') then state <= clearint5; else state <= setint5; end if;
when setint6 => if(int_accept = '1') then state <= clearint6; else state <= setint6; end if;
when setint7 => if(int_accept = '1') then state <= clearint7; else state <= setint7; end if;
when setint8 => if(int_accept = '1') then state <= clearint8; else state <= setint8; end if;
when setint9 => if(int_accept = '1') then state <= clearint9; else state <= setint9; end if;
when setint10 => if(int_accept = '1') then state <= clearint10; else state <= setint10; end if;
when setint11 => if(int_accept = '1') then state <= clearint11; else state <= setint11; end if;
when setint12 => if(int_accept = '1') then state <= clearint12; else state <= setint12; end if;
when setint13 => if(int_accept = '1') then state <= clearint13; else state <= setint13; end if;
when setint14 => if(int_accept = '1') then state <= clearint14; else state <= setint14; end if;
when setint15 => if(int_accept = '1') then state <= clearint15; else state <= setint15; end if;
--clearint will reset RS flip flop so, next interrupt can be catch
when clearint0 => state <= wait_for_int_complete;
when clearint1 => state <= wait_for_int_complete;
when clearint2 => state <= wait_for_int_complete;
when clearint3 => state <= wait_for_int_complete;
when clearint4 => state <= wait_for_int_complete;
when clearint5 => state <= wait_for_int_complete;
when clearint6 => state <= wait_for_int_complete;
when clearint7 => state <= wait_for_int_complete;
when clearint8 => state <= wait_for_int_complete;
when clearint9 => state <= wait_for_int_complete;
when clearint10 => state <= wait_for_int_complete;
when clearint11 => state <= wait_for_int_complete;
when clearint12 => state <= wait_for_int_complete;
when clearint13 => state <= wait_for_int_complete;
when clearint14 => state <= wait_for_int_complete;
when clearint15 => state <= wait_for_int_complete;
--but we also waiting for interrupt routine is completed, there isn't nested interrupts
when wait_for_int_complete =>
if(int_completed = '1') then state <= wait_for_int_come;
else state <= wait_for_int_complete;
end if;
end case;
end if;
end if;
end process;
process (state) begin
case state is
when start => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when wait_for_int_come => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when wait_for_int_complete => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when setint0 => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '1';
when setint1 => int_taken <= x"0000"; int_cpu_addr_sel <= "0001"; int_cpu_rq <= '1';
when setint2 => int_taken <= x"0000"; int_cpu_addr_sel <= "0010"; int_cpu_rq <= '1';
when setint3 => int_taken <= x"0000"; int_cpu_addr_sel <= "0011"; int_cpu_rq <= '1';
when setint4 => int_taken <= x"0000"; int_cpu_addr_sel <= "0100"; int_cpu_rq <= '1';
when setint5 => int_taken <= x"0000"; int_cpu_addr_sel <= "0101"; int_cpu_rq <= '1';
when setint6 => int_taken <= x"0000"; int_cpu_addr_sel <= "0110"; int_cpu_rq <= '1';
when setint7 => int_taken <= x"0000"; int_cpu_addr_sel <= "0111"; int_cpu_rq <= '1';
when setint8 => int_taken <= x"0000"; int_cpu_addr_sel <= "1000"; int_cpu_rq <= '1';
when setint9 => int_taken <= x"0000"; int_cpu_addr_sel <= "1001"; int_cpu_rq <= '1';
when setint10 => int_taken <= x"0000"; int_cpu_addr_sel <= "1010"; int_cpu_rq <= '1';
when setint11 => int_taken <= x"0000"; int_cpu_addr_sel <= "1011"; int_cpu_rq <= '1';
when setint12 => int_taken <= x"0000"; int_cpu_addr_sel <= "1100"; int_cpu_rq <= '1';
when setint13 => int_taken <= x"0000"; int_cpu_addr_sel <= "1101"; int_cpu_rq <= '1';
when setint14 => int_taken <= x"0000"; int_cpu_addr_sel <= "1110"; int_cpu_rq <= '1';
when setint15 => int_taken <= x"0000"; int_cpu_addr_sel <= "1111"; int_cpu_rq <= '1';
when clearint0 => int_taken <= x"0001"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint1 => int_taken <= x"0002"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint2 => int_taken <= x"0004"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint3 => int_taken <= x"0008"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint4 => int_taken <= x"0010"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint5 => int_taken <= x"0020"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint6 => int_taken <= x"0040"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint7 => int_taken <= x"0080"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint8 => int_taken <= x"0100"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint9 => int_taken <= x"0200"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint10 => int_taken <= x"0400"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint11 => int_taken <= x"0800"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint12 => int_taken <= x"1000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint13 => int_taken <= x"2000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint14 => int_taken <= x"4000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint15 => int_taken <= x"8000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
end case;
end process;
end architecture intFSMArch;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_SBF.vhd
|
20
|
8869
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_SBF.vhd
|
20
|
8869
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
|
2
|
41321
|
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
write : in std_logic := '0'; -- write.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
sop : in std_logic := '0'; -- sop.wire
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire
eop : in std_logic := '0'; -- eop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNLF52SJQ3 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLF52SJQ3;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- wire
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
thr : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_out : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module;
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_cast_GNZ5LMFB5D is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNZ5LMFB5D;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion6:input]
signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> [Decoder2:data, Decoder:data]
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input
signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input
signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:thr
signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast2:input]
signal bus_conversion6_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion6:output -> Delay5:input
signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> Delay6:input
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Decoder1:data, Decoder3:data, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:data_in, If_Statement1:a, Multiplexer:in0]
signal gray_binarization_gray_binarization_module_gray_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:data_out -> [Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:data_in, Multiplexer2:in0]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator:data1]
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1]
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay5:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay6:ena
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast4:input]
signal delay6_output_wire : std_logic_vector(0 downto 0); -- Delay6:output -> Multiplexer2:sel
signal gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:data_out -> Multiplexer2:in1
signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer:in1
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast1:input
signal cast1_output_wire : std_logic; -- cast1:output -> Delay:sclr
signal cast2_output_wire : std_logic; -- cast2:output -> Delay:ena
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast3:input
signal cast3_output_wire : std_logic_vector(0 downto 0); -- cast3:output -> Delay4:input
signal cast4_output_wire : std_logic; -- cast4:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast5:input
signal cast5_output_wire : std_logic_vector(0 downto 0); -- cast5:output -> Delay1:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay:aclr, Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:aclr, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:aclr, Multiplexer2:aclr, Multiplexer:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay:clock, Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:Clock, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:Clock, Multiplexer2:clock, Multiplexer:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNLF52SJQ3
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => multiplexer2_result_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
gray_binarization_gray_binarization_module_binarization_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module
port map (
data_out => gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire, -- data_out.wire
data_in => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire, -- data_in.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
thr => delay3_output_wire -- thr.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast1_output_wire, -- sclr.wire
ena => cast2_output_wire -- ena.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast4_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
delay6 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => bus_conversion6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => delay4enavcc_output_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay4enavcc_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay6_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire, -- in0.wire
in1 => gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
gray_binarization_gray_binarization_module_gray_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module
port map (
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => data_in_0_output_wire, -- data_in.wire
data_out => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire -- data_out.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNEQGKKPXW
generic map (
decode => "10",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GNZ5LMFB5D
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_cast.vhd
|
10
|
637
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_sMultAltr.vhd
|
12
|
3026
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sMultAltr is
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end alt_dspbuilder_sMultAltr;
architecture synth of alt_dspbuilder_sMultAltr is
signal FullPrecisionResult : std_logic_vector(lpm_widtha+lpm_widthb-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gcomb: if pipeline=0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint
)
PORT MAP (
dataa => dataa,
datab => datab,
result => FullPrecisionResult
);
end generate gcomb;
greg: if pipeline>0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint,
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
datab => datab,
clken=> ena,
aclr => aclr_i,
clock => clock,
result => FullPrecisionResult);
end generate greg;
g:for i in OutputLsb to OutputMsb generate
result(i-OutputLsb) <= FullPrecisionResult(i);
end generate g;
end synth;
|
mit
|
Nic30/hwtLib
|
hwtLib/examples/statements/IfStatementPartiallyEnclosed.vhd
|
1
|
1068
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY IfStatementPartiallyEnclosed IS
PORT(
a : OUT STD_LOGIC;
b : OUT STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
d : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF IfStatementPartiallyEnclosed IS
SIGNAL a_reg : STD_LOGIC;
SIGNAL a_reg_next : STD_LOGIC;
SIGNAL b_reg : STD_LOGIC;
SIGNAL b_reg_next : STD_LOGIC;
BEGIN
a <= a_reg;
assig_process_a_reg_next: PROCESS(b_reg, c, d)
BEGIN
IF c = '1' THEN
a_reg_next <= '1';
b_reg_next <= '1';
ELSIF d = '1' THEN
a_reg_next <= '0';
b_reg_next <= b_reg;
ELSE
a_reg_next <= '1';
b_reg_next <= '1';
END IF;
END PROCESS;
b <= b_reg;
assig_process_b_reg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
b_reg <= b_reg_next;
a_reg <= a_reg_next;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/common_porta_registers/_primary.vhd
|
5
|
1111
|
library verilog;
use verilog.vl_types.all;
entity common_porta_registers is
generic(
addr_register_width: integer := 1;
datain_register_width: integer := 1;
byteena_register_width: integer := 1
);
port(
addr_d : in vl_logic_vector;
datain_d : in vl_logic_vector;
byteena_d : in vl_logic_vector;
clk : in vl_logic;
aclr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
ena : in vl_logic;
stall : in vl_logic;
addr_q : out vl_logic_vector;
datain_q : out vl_logic_vector;
byteena_q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of addr_register_width : constant is 1;
attribute mti_svvh_generic_type of datain_register_width : constant is 1;
attribute mti_svvh_generic_type of byteena_register_width : constant is 1;
end common_porta_registers;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_sdecoderaltr.vhd
|
17
|
2703
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_clock_GNF343OQUJ.vhd
|
16
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/common_28nm_ram_register/_primary.vhd
|
5
|
799
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_register is
generic(
width : integer := 1;
preset : vl_logic := Hi0
);
port(
d : in vl_logic_vector;
clk : in vl_logic;
aclr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
stall : in vl_logic;
ena : in vl_logic;
q : out vl_logic_vector;
aclrout : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of preset : constant is 1;
end common_28nm_ram_register;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/altera_stratixv_pll/_primary.vhd
|
5
|
70300
|
library verilog;
use verilog.vl_types.all;
entity altera_stratixv_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_stratixv_pll;
|
mit
|
Nic30/hwtLib
|
hwtLib/examples/specialIntfTypes/InterfaceWithVHDLUnconstrainedArrayImportedType2.vhd
|
1
|
615
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din_0 : IN UNSIGNED(7 DOWNTO 0);
din_1 : IN UNSIGNED(7 DOWNTO 0);
din_2 : IN UNSIGNED(7 DOWNTO 0);
dout : OUT mem(0 TO 3)(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
BEGIN
dout(0) <= din_0;
dout(1) <= din_1;
dout(2) <= din_2;
ASSERT SIZE_X = 3 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_decoder.vhd
|
7
|
1660
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_testbench_capture.vhd
|
10
|
676
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_BarrelShiftAltr.vhd
|
8
|
7592
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_decoder.vhd
|
1
|
3360
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
begin
alt_dspbuilder_decoder_GNM4LOIHXZ_0: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_0: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNSCEXJCJK_1: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_1: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNEQGKKPXW_2: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_2: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/Gray_Binarization_GN.vhd
|
2
|
10796
|
-- Gray_Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN is
port (
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire
Avalon_ST_Source_endofpacket : out std_logic; -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write : in std_logic := '0' -- Avalon_MM_Slave_write.wire
);
end entity Gray_Binarization_GN;
architecture rtl of Gray_Binarization_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
sop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_out : out std_logic_vector(23 downto 0); -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
eop : in std_logic := 'X'; -- wire
write : in std_logic := 'X' -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Gray_Binarization_Gray_Binarization_Module_0:addr
signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Gray_Binarization_Gray_Binarization_Module_0:write
signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Gray_Binarization_Gray_Binarization_Module_0:writedata
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Gray_Binarization_Gray_Binarization_Module_0:data_in
signal gray_binarization_gray_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Gray_Binarization_Gray_Binarization_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Gray_Binarization_Gray_Binarization_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => Avalon_MM_Slave_address, -- input.wire
output => avalon_mm_slave_address_0_output_wire -- output.wire
);
avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => Avalon_MM_Slave_writedata, -- input.wire
output => avalon_mm_slave_writedata_0_output_wire -- output.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
gray_binarization_gray_binarization_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
port map (
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire
data_out => gray_binarization_gray_binarization_module_0_data_out_wire, -- data_out.wire
writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire
addr => avalon_mm_slave_address_0_output_wire, -- addr.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
write => avalon_mm_slave_write_0_output_wire -- write.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_MM_Slave_write, -- input.wire
output => avalon_mm_slave_write_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => gray_binarization_gray_binarization_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_delay_GNUECIBFDH.vhd
|
16
|
1088
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNUECIBFDH is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNUECIBFDH is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Nic30/hwtLib
|
hwtLib/examples/mem/DReg.vhd
|
1
|
885
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Basic d flip flop
--
-- :attention: using this unit is pointless because HWToolkit can automatically
-- generate such a register for any interface and datatype
--
-- .. hwt-autodoc::
--
ENTITY DReg IS
PORT(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF DReg IS
SIGNAL internReg : STD_LOGIC := '0';
SIGNAL internReg_next : STD_LOGIC;
BEGIN
dout <= internReg;
assig_process_internReg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
internReg <= '0';
ELSE
internReg <= internReg_next;
END IF;
END IF;
END PROCESS;
internReg_next <= din;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_port_GNEPKLLZKY.vhd
|
17
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_delay_GNHYCSAEGT.vhd
|
16
|
1037
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNHYCSAEGT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNHYCSAEGT is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_eq/fp_cmp_eq/dspba_library_package.vhd
|
12
|
2231
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
mit
|
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_div/fp_div_sim/dspba_library_package.vhd
|
12
|
2231
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
mit
|
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_eq/fp_cmp_eq_sim/dspba_library_package.vhd
|
12
|
2231
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
mit
|
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/altera_lnsim/pll_dps_lcell_comb/_primary.vhd
|
5
|
1143
|
library verilog;
use verilog.vl_types.all;
entity pll_dps_lcell_comb is
generic(
family : string := "Stratix V";
lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0);
dont_touch : string := "on"
);
port(
dataa : in vl_logic;
datab : in vl_logic;
datac : in vl_logic;
datad : in vl_logic;
datae : in vl_logic;
dataf : in vl_logic;
combout : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of family : constant is 1;
attribute mti_svvh_generic_type of lut_mask : constant is 1;
attribute mti_svvh_generic_type of dont_touch : constant is 1;
end pll_dps_lcell_comb;
|
mit
|
Nic30/hwtLib
|
hwtLib/examples/specialIntfTypes/InterfaceWithVHDLUnconstrainedArrayImportedType.vhd
|
1
|
617
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din : IN mem(0 TO 3)(7 DOWNTO 0);
dout_0 : OUT UNSIGNED(7 DOWNTO 0);
dout_1 : OUT UNSIGNED(7 DOWNTO 0);
dout_2 : OUT UNSIGNED(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF InterfaceWithVHDLUnconstrainedArrayImportedType IS
BEGIN
dout_0 <= din(0);
dout_1 <= din(1);
dout_2 <= din(2);
ASSERT SIZE_X = 3 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_if_statement_GNYT6HZJI5.vhd
|
9
|
1396
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 8);
port(
true : out std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNYT6HZJI5 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(7 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
|
mit
|
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_gt/fp_cmp_gt/fp_cmp_gt_0002.vhd
|
1
|
13698
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_cmp_gt_0002
-- VHDL created on Thu Feb 15 17:02:54 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cmp_gt_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end fp_cmp_gt_0002;
architecture normal of fp_cmp_gt_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid6_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid7_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid8_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_x_uid9_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid10_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid11_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid12_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid13_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid14_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid16_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_y_uid23_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_y_uid24_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid25_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid26_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid27_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid28_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid30_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsNaN_uid34_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xNotZero_uid39_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yNotZero_uid40_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXPS_uid41_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXPS_uid41_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expFracX_uid43_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid45_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal efxGTefy_uid47_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal efxLTefy_uid48_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signX_uid52_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid53_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal two_uid54_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal concSYSX_uid55_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal sxGTsy_uid56_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xorSigns_uid57_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsy_uid58_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneNonZero_uid62_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rc2_uid63_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsyExpFracCompMux_uid64_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid65_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- GND(CONSTANT,0)
GND_q <= "0";
-- cstAllZWE_uid8_fpCompareTest(CONSTANT,7)
cstAllZWE_uid8_fpCompareTest_q <= "00000000";
-- exp_y_uid23_fpCompareTest(BITSELECT,22)@0
exp_y_uid23_fpCompareTest_b <= b(30 downto 23);
-- excZ_y_uid25_fpCompareTest(LOGICAL,24)@0
excZ_y_uid25_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- yNotZero_uid40_fpCompareTest(LOGICAL,39)@0
yNotZero_uid40_fpCompareTest_q <= not (excZ_y_uid25_fpCompareTest_q);
-- exp_x_uid9_fpCompareTest(BITSELECT,8)@0
exp_x_uid9_fpCompareTest_b <= a(30 downto 23);
-- excZ_x_uid11_fpCompareTest(LOGICAL,10)@0
excZ_x_uid11_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- xNotZero_uid39_fpCompareTest(LOGICAL,38)@0
xNotZero_uid39_fpCompareTest_q <= not (excZ_x_uid11_fpCompareTest_q);
-- oneNonZero_uid62_fpCompareTest(LOGICAL,61)@0
oneNonZero_uid62_fpCompareTest_q <= xNotZero_uid39_fpCompareTest_q or yNotZero_uid40_fpCompareTest_q;
-- two_uid54_fpCompareTest(CONSTANT,53)
two_uid54_fpCompareTest_q <= "10";
-- signY_uid53_fpCompareTest(BITSELECT,52)@0
signY_uid53_fpCompareTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid52_fpCompareTest(BITSELECT,51)@0
signX_uid52_fpCompareTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- concSYSX_uid55_fpCompareTest(BITJOIN,54)@0
concSYSX_uid55_fpCompareTest_q <= signY_uid53_fpCompareTest_b & signX_uid52_fpCompareTest_b;
-- sxGTsy_uid56_fpCompareTest(LOGICAL,55)@0
sxGTsy_uid56_fpCompareTest_q <= "1" WHEN concSYSX_uid55_fpCompareTest_q = two_uid54_fpCompareTest_q ELSE "0";
-- rc2_uid63_fpCompareTest(LOGICAL,62)@0
rc2_uid63_fpCompareTest_q <= sxGTsy_uid56_fpCompareTest_q and oneNonZero_uid62_fpCompareTest_q;
-- frac_y_uid24_fpCompareTest(BITSELECT,23)@0
frac_y_uid24_fpCompareTest_b <= b(22 downto 0);
-- fracYPS_uid42_fpCompareTest(LOGICAL,41)@0
fracYPS_uid42_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => yNotZero_uid40_fpCompareTest_q(0)) & yNotZero_uid40_fpCompareTest_q));
fracYPS_uid42_fpCompareTest_q <= frac_y_uid24_fpCompareTest_b and fracYPS_uid42_fpCompareTest_b;
-- expFracY_uid45_fpCompareTest(BITJOIN,44)@0
expFracY_uid45_fpCompareTest_q <= exp_y_uid23_fpCompareTest_b & fracYPS_uid42_fpCompareTest_q;
-- frac_x_uid10_fpCompareTest(BITSELECT,9)@0
frac_x_uid10_fpCompareTest_b <= a(22 downto 0);
-- fracXPS_uid41_fpCompareTest(LOGICAL,40)@0
fracXPS_uid41_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => xNotZero_uid39_fpCompareTest_q(0)) & xNotZero_uid39_fpCompareTest_q));
fracXPS_uid41_fpCompareTest_q <= frac_x_uid10_fpCompareTest_b and fracXPS_uid41_fpCompareTest_b;
-- expFracX_uid43_fpCompareTest(BITJOIN,42)@0
expFracX_uid43_fpCompareTest_q <= exp_x_uid9_fpCompareTest_b & fracXPS_uid41_fpCompareTest_q;
-- efxLTefy_uid48_fpCompareTest(COMPARE,47)@0
efxLTefy_uid48_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxLTefy_uid48_fpCompareTest_a) - UNSIGNED(efxLTefy_uid48_fpCompareTest_b));
efxLTefy_uid48_fpCompareTest_c(0) <= efxLTefy_uid48_fpCompareTest_o(32);
-- efxGTefy_uid47_fpCompareTest(COMPARE,46)@0
efxGTefy_uid47_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxGTefy_uid47_fpCompareTest_a) - UNSIGNED(efxGTefy_uid47_fpCompareTest_b));
efxGTefy_uid47_fpCompareTest_c(0) <= efxGTefy_uid47_fpCompareTest_o(32);
-- expFracCompMux_uid59_fpCompareTest(MUX,58)@0
expFracCompMux_uid59_fpCompareTest_s <= signX_uid52_fpCompareTest_b;
expFracCompMux_uid59_fpCompareTest_combproc: PROCESS (expFracCompMux_uid59_fpCompareTest_s, efxGTefy_uid47_fpCompareTest_c, efxLTefy_uid48_fpCompareTest_c)
BEGIN
CASE (expFracCompMux_uid59_fpCompareTest_s) IS
WHEN "0" => expFracCompMux_uid59_fpCompareTest_q <= efxGTefy_uid47_fpCompareTest_c;
WHEN "1" => expFracCompMux_uid59_fpCompareTest_q <= efxLTefy_uid48_fpCompareTest_c;
WHEN OTHERS => expFracCompMux_uid59_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xorSigns_uid57_fpCompareTest(LOGICAL,56)@0
xorSigns_uid57_fpCompareTest_q <= signX_uid52_fpCompareTest_b xor signY_uid53_fpCompareTest_b;
-- sxEQsy_uid58_fpCompareTest(LOGICAL,57)@0
sxEQsy_uid58_fpCompareTest_q <= not (xorSigns_uid57_fpCompareTest_q);
-- sxEQsyExpFracCompMux_uid64_fpCompareTest(LOGICAL,63)@0
sxEQsyExpFracCompMux_uid64_fpCompareTest_q <= sxEQsy_uid58_fpCompareTest_q and expFracCompMux_uid59_fpCompareTest_q;
-- r_uid65_fpCompareTest(LOGICAL,64)@0
r_uid65_fpCompareTest_q <= sxEQsyExpFracCompMux_uid64_fpCompareTest_q or rc2_uid63_fpCompareTest_q;
-- cstZeroWF_uid7_fpCompareTest(CONSTANT,6)
cstZeroWF_uid7_fpCompareTest_q <= "00000000000000000000000";
-- fracXIsZero_uid27_fpCompareTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_y_uid24_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid28_fpCompareTest(LOGICAL,27)@0
fracXIsNotZero_uid28_fpCompareTest_q <= not (fracXIsZero_uid27_fpCompareTest_q);
-- cstAllOWE_uid6_fpCompareTest(CONSTANT,5)
cstAllOWE_uid6_fpCompareTest_q <= "11111111";
-- expXIsMax_uid26_fpCompareTest(LOGICAL,25)@0
expXIsMax_uid26_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_y_uid30_fpCompareTest(LOGICAL,29)@0
excN_y_uid30_fpCompareTest_q <= expXIsMax_uid26_fpCompareTest_q and fracXIsNotZero_uid28_fpCompareTest_q;
-- fracXIsZero_uid13_fpCompareTest(LOGICAL,12)@0
fracXIsZero_uid13_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_x_uid10_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid14_fpCompareTest(LOGICAL,13)@0
fracXIsNotZero_uid14_fpCompareTest_q <= not (fracXIsZero_uid13_fpCompareTest_q);
-- expXIsMax_uid12_fpCompareTest(LOGICAL,11)@0
expXIsMax_uid12_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_x_uid16_fpCompareTest(LOGICAL,15)@0
excN_x_uid16_fpCompareTest_q <= expXIsMax_uid12_fpCompareTest_q and fracXIsNotZero_uid14_fpCompareTest_q;
-- oneIsNaN_uid34_fpCompareTest(LOGICAL,33)@0
oneIsNaN_uid34_fpCompareTest_q <= excN_x_uid16_fpCompareTest_q or excN_y_uid30_fpCompareTest_q;
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- rPostExc_uid66_fpCompareTest(MUX,65)@0
rPostExc_uid66_fpCompareTest_s <= oneIsNaN_uid34_fpCompareTest_q;
rPostExc_uid66_fpCompareTest_combproc: PROCESS (rPostExc_uid66_fpCompareTest_s, r_uid65_fpCompareTest_q, GND_q)
BEGIN
CASE (rPostExc_uid66_fpCompareTest_s) IS
WHEN "0" => rPostExc_uid66_fpCompareTest_q <= r_uid65_fpCompareTest_q;
WHEN "1" => rPostExc_uid66_fpCompareTest_q <= GND_q;
WHEN OTHERS => rPostExc_uid66_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xOut(GPOUT,4)@0
q <= rPostExc_uid66_fpCompareTest_q;
END normal;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_delay_GNVTJPHWYT.vhd
|
9
|
1102
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVTJPHWYT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "01111111";
width : positive := 8);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVTJPHWYT is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 8,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "01111111")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg3d.vhd
|
1
|
1763
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Only a small fragment assigned and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3d IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3d IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto16 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_31downto16 <= r(31 DOWNTO 16);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_31downto16 <= X"0000";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_SBitLogical.vhd
|
20
|
3567
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBitLogical is
generic (
lpm_width : positive := 8 ;
lop : LogicalOperator := AltAND
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end alt_dspbuilder_SBitLogical;
architecture SBitLogical_SYNTH of alt_dspbuilder_SBitLogical is
signal worand : std_logic_vector(lpm_width-1 downto 0);
signal ndataa : std_logic_vector(lpm_width-1 downto 0);
signal result_int : std_logic;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => result_int, r => result);
------------------AND--------------------------------
go1p:if lop = AltAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '1' when (worand=dataa) else '0';
end generate;
------------------OR--------------------------------
go2p:if lop = AltOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '0' when (ndataa=worand) else '1';
end generate;
------------------XOR--------------------------------
go3p:if lop = AltXOR generate
gif:if (lpm_width>2) generate
process(dataa)
variable interes : std_logic ;
begin
interes := dataa(0) xor dataa(1);
for i in 2 to lpm_width-1 loop
interes := dataa(i) xor interes;
end loop;
result_int <= interes;
end process;
end generate;
gif2:if (lpm_width<3) generate
result_int <= dataa(0) xor dataa(1);
end generate;
end generate;
------------------NOR--------------------------------
go4p:if lop = AltNOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '1' when (ndataa=worand) else '0';
end generate;
------------------NAND--------------------------------
go5p:if lop = AltNAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '0' when (worand=dataa) else '1';
end generate;
------------------NOT (Single Bit only)---------------
go6p:if lop = AltNOT generate
result_int <= not (dataa(0));
end generate;
end SBitLogical_SYNTH;
|
mit
|
kevintownsend/R3
|
coregen/fifo_69x512_hf/simulation/fg_tb_top.vhd
|
2
|
5679
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 72
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
Wynjones1/VHDL-Tests
|
src/memory.vhd
|
1
|
879
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
port( clk : in std_logic;
address : in std_logic_vector;
we : in std_logic;
data_in : in std_logic_vector;
data_out : out std_logic_vector);
end entity;
architecture rtl of memory is
constant MEM_WIDTH : integer := address'length;
constant MEM_MAX_ADDR : integer := 2 ** MEM_WIDTH - 1;
type ram_t is array(0 to MEM_MAX_ADDR) of std_logic_vector(data_in'length - 1 downto 0);
signal ram : ram_t;
signal read_address : std_logic_vector(address'length - 1 downto 0);
begin
process(clk, address, we, data_in)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= data_in;
end if;
read_address <= address;
end if;
end process;
data_out <= ram(to_integer(unsigned(read_address)));
end rtl;
|
mit
|
kevintownsend/R3
|
coregen/fifo_37x512_hf/simulation/fg_tb_dgen.vhd
|
36
|
4510
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
kevintownsend/R3
|
coregen/fifo_64x512_hf/simulation/fg_tb_top.vhd
|
1
|
5679
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 65
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
kevintownsend/R3
|
coregen/fifo_32x512/simulation/fg_tb_dverif.vhd
|
11
|
5803
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
kevintownsend/R3
|
coregen/block_ram_64x1024/example_design/block_ram_64x1024_top.vhd
|
1
|
5421
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY block_ram_64x1024_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END block_ram_64x1024_top;
ARCHITECTURE xilinx OF block_ram_64x1024_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT block_ram_64x1024 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : block_ram_64x1024
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
mit
|
kevintownsend/R3
|
coregen/fifo_37x512/simulation/fg_tb_rng.vhd
|
54
|
3878
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
kevintownsend/R3
|
coregen/fifo_69x512/simulation/fg_tb_rng.vhd
|
54
|
3878
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
kevintownsend/R3
|
coregen/fifo_64x512_hf/example_design/fifo_64x512_hf_top.vhd
|
1
|
5116
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_64x512_hf_top;
architecture xilinx of fifo_64x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_64x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_64x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
kevintownsend/R3
|
coregen/fifo_138x512/simulation/fg_tb_top.vhd
|
1
|
5679
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 13
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
agreatfool/Cart
|
dart-version/web/src/bower/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
Wynjones1/VHDL-Tests
|
simu/test.vhd
|
1
|
1034
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test is
end test;
architecture rtl of test is
component top is
port( clk : in std_logic;
reset : in std_logic;
vs : out std_logic;
hs : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0));
end component;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal HS : std_logic;
signal VS : std_logic;
signal clk : std_logic;
signal s_reset : std_logic;
begin
top0 : top port map(clk => clk,
reset => s_reset,
red => red,
blue => blue,
green => green,
HS => HS,
VS => VS);
process
begin
s_reset <= '1';
wait for 20 ns;
s_reset <= '0';
wait;
end process;
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
end rtl;
|
mit
|
TMU-VHDL-team2/sqrt
|
components/test_mem.vhd
|
1
|
1116
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity test_mem is
port(clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0);
TB_switch : in std_logic;
TB_addr : in std_logic_vector(7 downto 0);
TB_w_data : in std_logic_vector(15 downto 0));
end test_mem;
architecture BEHAVIOR of test_mem is
subtype RAM_WORD is std_logic_vector(15 downto 0);
type RAM_TYPE is array (0 to 255) of RAM_WORD;
signal RAM_DATA : RAM_TYPE;
signal addr : std_logic_vector(7 downto 0);
begin
data <= RAM_DATA(conv_integer(addr));
process(clk) begin
if clk'event and clk = '1' then
if TB_switch = '1' then
RAM_DATA(conv_integer(TB_addr)) <= TB_w_data;
elsif write = '1' then
RAM_DATA(conv_integer(S_MAR_F)) <= S_MDR_F;
elsif read = '1' then
addr <= S_MAR_F;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
|
mit
|
TMU-VHDL-team2/sqrt
|
fpga/MAR.vhd
|
2
|
614
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
architecture BEHAVIOR of MAR is
signal rst:std_logic_vector(15 downto 0);
begin
M_ad16 <= rst;
M_ad8 <= rst(7 downto 0);
process(clk)begin
if (clk'event and (clk = '1') and (lat ='1')) then
rst <= busC;
else
null;
end if;
end process;
end BEHAVIOR;
|
mit
|
TMU-VHDL-team2/sqrt
|
fpga/mdr.vhd
|
2
|
886
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end mdr;
architecture BEHAVIOR of mdr is
begin
process(clock) begin
if(clock'event and clock = '1')then
if(latch = '1')then
if(sel = '0')then
data <= busC;
elsif(sel = '1')then
data <= memo;
else
null;
end if;
else
null;
end if;
else
null;
end if;
end process;
end BEHAVIOR;
|
mit
|
TMU-VHDL-team2/sqrt
|
components/bB.vhd
|
2
|
644
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bB is
port(S_GRB, S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0));
end bB;
architecture BEHAVIOR of bB is
begin
S_BUS_B <= S_GRB when S_s_ctl = "10000"
else S_PR_F when S_s_ctl = "01000"
else S_MAR_F when S_s_ctl = "00100"
else S_MDR_F when S_s_ctl = "00010"
else "00000000" & addr when S_s_ctl = "00001"
else "XXXXXXXXXXXXXXXX";
end BEHAVIOR;
|
mit
|
TMU-VHDL-team2/sqrt
|
components/bC.vhd
|
2
|
206
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bC is
port( S_BUS_C : inout std_logic_vector(15 downto 0));
end bC;
architecture BEHAVIOR of bC is
begin
end BEHAVIOR;
|
mit
|
kevintownsend/R3
|
coregen/fifo_69x512/simulation/fg_tb_pkg.vhd
|
1
|
11247
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_69x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
mit
|
TMU-VHDL-team2/sqrt
|
components/fr.vhd
|
2
|
851
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end fr;
architecture BEHAVIOR of fr is
-- Definitions --
signal ZFG : std_logic;
signal SFG : std_logic;
signal OFG : std_logic;
-- Main --
begin
process(clk) begin
if(clk'event and (clk = '1') and (latch = '1')) then
ZFG <= inZF;
SFG <= inSF;
OFG <= inOF;
else
null;
end if;
end process;
outZF <= ZFG;
outSF <= SFG;
outOF <= OFG;
end BEHAVIOR;
|
mit
|
TMU-VHDL-team2/sqrt
|
components/mem.vhd
|
1
|
1241
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity mem is
port(clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0));
end mem;
architecture BEHAVIOR of mem is
subtype RAM_WORD is std_logic_vector(15 downto 0);
type RAM_TYPE is array (0 to 255) of RAM_WORD;
impure function init_ram_file(RAM_FILE_NAME : in string) return RAM_TYPE is
file RAM_FILE : TEXT is in RAM_FILE_NAME;
variable RAM_FILE_LINE : line;
variable RAM_DIN : RAM_TYPE;
begin
for I in RAM_TYPE'range loop
readline(RAM_FILE, RAM_FILE_LINE);
hread(RAM_FILE_LINE, RAM_DIN(I));
end loop;
return RAM_DIN;
end function;
signal RAM_DATA : RAM_TYPE := init_ram_file("mem2.txt");
signal addr : std_logic_vector(7 downto 0);
begin
data <= RAM_DATA(conv_integer(addr));
process(clk) begin
if clk'event and clk = '1' then
if write = '1' then
RAM_DATA(conv_integer(S_MAR_F)) <= S_MDR_F;
elsif read = '1' then
addr <= S_MAR_F;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
|
mit
|
dugagjinll/MIPS
|
MIPS/tb_MIPS.vhd
|
1
|
657
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_MIPS IS
END tb_MIPS;
ARCHITECTURE behavior OF tb_MIPS IS
--Inputs
SIGNAL tb_clk : std_logic := '0';
SIGNAL tb_reset : std_logic := '0';
-- Clock period definitions
CONSTANT clk_period : TIME := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Test : ENTITY work.MIPS(Behavioral)
PORT MAP(
clk => tb_clk,
reset => tb_reset
);
clk_process : PROCESS
BEGIN
tb_clk <= '0';
WAIT FOR clk_period/2;
tb_clk <= '1';
WAIT FOR clk_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
WAIT FOR 400 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END;
|
mit
|
kevintownsend/R3
|
coregen/fifo_64x512_hf/simulation/fg_tb_dgen.vhd
|
11
|
4510
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 12 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
dugagjinll/MIPS
|
MIPS/shiftLeft.vhd
|
1
|
441
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shiftLeft IS
GENERIC (
N : INTEGER := 2;
W : INTEGER := 32
);
PORT (
input : IN STD_LOGIC_VECTOR(W - 1 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(W - 1 DOWNTO 0)
);
END shiftLeft;
ARCHITECTURE Behavioral OF shiftLeft IS
BEGIN
output(W - 1) <= input(W - 1);
output(W - 2 DOWNTO N) <= input(W - 2 - N DOWNTO 0);
output(N - 1 DOWNTO 0) <= (OTHERS => '0');
END Behavioral;
|
mit
|
kevintownsend/R3
|
coregen/fifo_fwft_64x512/simulation/fg_tb_pctrl.vhd
|
10
|
15357
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
dugagjinll/MIPS
|
MIPS/Controller.vhd
|
1
|
2453
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Controller IS
PORT (
opcode : IN std_logic_vector(5 DOWNTO 0); -- instruction 31-26
regDst : OUT std_logic;
jump : OUT std_logic;
branch : OUT std_logic;
memRead : OUT std_logic;
memToRegister : OUT std_logic;
ALUop : OUT std_logic_vector(1 DOWNTO 0);
memWrite : OUT std_logic;
ALUsrc : OUT std_logic;
regWrite : OUT std_logic
);
END Controller;
ARCHITECTURE Behavioral OF Controller IS
BEGIN
PROCESS (opcode)
BEGIN
regWrite <= '0'; --Deassert for next command
CASE opcode IS
WHEN "000000" => -- and, or, add, sub, slt: 0x00
regDst <= '1';
jump <= '0';
branch <= '0';
memRead <= '0';
memToRegister <= '0';
ALUop <= "10";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '1' AFTER 10 ns;
WHEN "100011" => -- load word(lw): 0x23
regDst <= '0';
jump <= '0';
branch <= '0';
memRead <= '1';
memToRegister <= '1';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '1';
regWrite <= '1' AFTER 10 ns;
WHEN "101011" => -- store word(beq): 0x2B
regDst <= 'X'; -- don't care
jump <= '0';
branch <= '0' AFTER 2 ns;
memRead <= '0';
memToRegister <= 'X'; -- don't care
ALUop <= "00";
memWrite <= '1';
ALUsrc <= '1';
regWrite <= '0';
WHEN "000100" => -- branch equal(beq): 0x04
regDst <= 'X'; -- don't care
jump <= '0';
branch <= '1' AFTER 2 ns;
memRead <= '0';
memToRegister <= 'X'; -- don't care
ALUop <= "01";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
WHEN "000010" => -- jump(j): 0x02
regDst <= 'X';
jump <= '1';
branch <= '0';
memRead <= '0';
memToRegister <= 'X';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
WHEN OTHERS => NULL; --implement other commands down here
regDst <= '0';
jump <= '0';
branch <= '0';
memRead <= '0';
memToRegister <= '0';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
END CASE;
END PROCESS;
END Behavioral;
|
mit
|
laurivosandi/vhdl-exercise
|
alu_testbench.vhd
|
1
|
6446
|
use work.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_testbench is
end;
architecture behavioral of alu_testbench is
signal a, b, q : std_logic_vector(3 downto 0);
signal ctrl : std_logic_vector (1 DOWNTO 0);
signal cout, cin : std_logic := '0';
component alu
port (
n : in std_logic_vector (3 downto 0);
m : in std_logic_vector (3 downto 0);
opcode : in std_logic_vector ( 1 downto 0);
cout : out std_logic;
d : out std_logic_vector (3 downto 0));
end component;
function to_std_logicvector(a: integer; length: natural) return std_logic_vector IS
begin
return std_logic_vector(to_signed(a,length));
end;
procedure behave_alu(a: integer; b: integer; ctrl: integer; q: out std_logic_vector(3 downto 0); cout: out std_logic) is
variable ret: std_logic_vector(4 downto 0);
begin
case ctrl is
when 0 => ret := std_logic_vector(to_signed(a+b, 5));
when 1 => ret := std_logic_vector(to_signed(a-b, 5));
when 2 => ret := '0' & (std_logic_vector(to_signed(a,4))) nand std_logic_vector(to_signed(b,4));
when 3 => ret := '0' & (std_logic_vector(to_signed(a,4))) nor std_logic_vector(to_signed(b,4));
when others =>
assert false
report "ctrl out of range, testbench error"
severity error;
end case;
q := ret(3 downto 0);
cout := ret(4);
end;
begin process
variable res: std_logic_vector ( 3 downto 0);
variable c: std_logic;
begin
ctrl <= "00";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7-i loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
behave_alu(i,j,0,res,c);
--assert "0" & q = "1" & res
assert q = res
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=add" &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(res)))
severity warning;
assert cout = c
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=add" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected:" & std_logic'image(c)
severity warning;
end loop;
end loop;
report "Finished testing addition operation of ALU";
ctrl <= "01";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
behave_alu(i,j,1,res,c);
--assert "0" & q = "1" & res
assert q = res
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=sub" &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(res)))
severity warning;
assert cout = c
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=sub" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected:" & std_logic'image(c)
severity warning;
end loop;
end loop;
report "Finished testing subtraction operation of ALU";
ctrl <= "10";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
assert (a nand b) = q
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nand " &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(a nand b)))
severity warning;
assert cout = '0'
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nand" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected: 0"
severity warning;
end loop;
end loop;
report "Finished testing NAND operation of ALU";
ctrl <= "11";
for i in 0 to 7 loop
a <= std_logic_vector(to_unsigned(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_unsigned(j,4));
wait for 10 ns;
assert (a nor b) = q
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nor " &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(a nor b)))
severity warning;
assert cout = '0'
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nor" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected: 0"
severity warning;
end loop;
end loop;
report "Finished testing NOR operation of ALU";
wait;
end process;
uut: alu port map (a, b, ctrl, cout, q);
end behavioral;
|
mit
|
dugagjinll/MIPS
|
MIPS/programCounterAdder.vhd
|
1
|
460
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY programCounterAdder IS
PORT (
programCounterIn : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
programCounterOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END programCounterAdder;
ARCHITECTURE Behavioral OF programCounterAdder IS
BEGIN
add4 : PROCESS (programCounterIn)
BEGIN
programCounterOut <= programCounterIn + 4;
END PROCESS add4;
END Behavioral;
|
mit
|
kevintownsend/R3
|
coregen/fifo_fwft_64x1024/example_design/fifo_fwft_64x1024_top.vhd
|
1
|
4974
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x1024_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x1024_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_64x1024_top;
architecture xilinx of fifo_fwft_64x1024_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x1024 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_64x1024 PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
kevintownsend/R3
|
coregen/fifo_37x512/example_design/fifo_37x512_top.vhd
|
1
|
4780
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_37x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_37x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_37x512_top;
architecture xilinx of fifo_37x512_top is
SIGNAL clk_i : std_logic;
component fifo_37x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_37x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd
|
3
|
18754
|
------------------------------------------------------------------------------
-- axi_i2s_adi.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_i2s_adi.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Apr 26 17:49:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.user_logic;
Library UNISIM;
use UNISIM.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity axi_i2s_adi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_DATA_WIDTH : integer := 24;
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
-- MEM_RD_O for debugging
MEM_RD_O : out std_logic;
--
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "CLK";
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_i2s_adi;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_i2s_adi is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 12;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
-- bufg
signal LRCLK_BUFG_I : std_logic;
signal BCLK_BUFG_I : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_i2s_adi_v1_00_a.user_logic
generic map
(
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => C_DATA_WIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK_O => BCLK_BUFG_I,
LRCLK_O => LRCLK_BUFG_I,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
-- debug only
MEM_RD_O => MEM_RD_O,
--
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
S_AXIS_ACLK => ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
----- bufg
BUFG_inst_BCLK : BUFG
port map (
O => LRCLK_O, -- 1-bit Clock buffer output
I => LRCLK_BUFG_I -- 1-bit Clock buffer input
);
BUFG_inst_LRCLK : BUFG
port map (
O => BCLK_O, -- 1-bit Clock buffer output
I => BCLK_BUFG_I -- 1-bit Clock buffer input
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
mit
|
UdayanSinha/Code_Blocks
|
VHDL/Projects/work/data_bus.vhd
|
1
|
1185
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY data_bus IS
PORT(data_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --data bus
data_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="ZZZZ";
en0, en1, rd_wr0, rd_wr1, clk, rst: IN STD_LOGIC); --register read-write select, clock, register select
END data_bus;
ARCHITECTURE behave of data_bus IS
COMPONENT register_generic IS
GENERIC(size: INTEGER);
PORT(d: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
SIGNAL d0, d1, q0, q1: STD_LOGIC_VECTOR(3 DOWNTO 0); --register internal outputs and inputs
BEGIN
R0: register_generic GENERIC MAP(4) PORT MAP (d0, clk, rst, q0);
R1: register_generic GENERIC MAP(4) PORT MAP (d1, clk, rst, q1);
data_out<=q0 WHEN en0='1' AND rd_wr0='0' else others=>'Z';
data_out<=q1 WHEN en1='1' AND rd_wr1='0' else others=>'Z';
d0<=data_in WHEN en0='1' AND rd_wr0='1';
d1<=data_in WHEN en1='1' AND rd_wr1='1';
END behave;
|
mit
|
UdayanSinha/Code_Blocks
|
VHDL/Projects/work/tb_manchester_decode.vhd
|
1
|
731
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_manchester_decode IS END tb_manchester_decode;
ARCHITECTURE test OF tb_manchester_decode IS
COMPONENT manchester_decode IS
PORT(input: IN STD_LOGIC;
output: OUT STD_LOGIC:='0');
END COMPONENT;
SIGNAL input: STD_LOGIC:='0';
SIGNAL output: STD_LOGIC;
BEGIN
T1: manchester_decode PORT MAP(input, output);
input<='0',
'1' AFTER 5 ns,
'0' AFTER 10 ns,
'1' AFTER 15 ns,
'1' AFTER 20 ns,
'0' AFTER 25 ns,
'1' AFTER 30 ns,
'0' AFTER 35 ns;
END test;
|
mit
|
diecaptain/fuzzy_kalman_mppt
|
kr_fuzman_Vtminus.vhd
|
1
|
1479
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vtminus is
port
( clock : in std_logic;
Vtminusone : in std_logic_vector (31 downto 0);
Vref : in std_logic_vector (31 downto 0);
koft : in std_logic_vector (31 downto 0);
Vtminus : out std_logic_vector (31 downto 0)
);
end kr_fuzman_Vtminus;
architecture struct of kr_fuzman_Vtminus is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector (31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vref, datab => Vtminusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => koft, datab => Z1, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Z2, datab => Vtminusone, result => Vtminus);
end struct;
|
mit
|
alifazel/16-bit-risc
|
vhdl/mux4x4.vhd
|
4
|
403
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when "00",
d1 when "01",
d2 when "10",
d3 when "11";
end logic;
|
mit
|
mjl152/usmt_uarch
|
smt_control_unit.vhd
|
1
|
14227
|
-- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT control unit
-- Michael Lancaster <[email protected]>
-- 4 October 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity smt_control_unit is
Port ( CLOCK : in STD_LOGIC;
INSTRUCTION_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000110";
INSTRUCTION_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000111";
INSTRUCTION_POINTER_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
INSTRUCTION_POINTER_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG1_0 : out STD_LOGIC_VECTOR (7 downto 0) := "01000100";
ARG1_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG3_0 : out STD_LOGIC_VECTOR (7 downto 0 ):= "00000000";
ARG3_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000");
type smt_thread_register is array (1 downto 0) of std_logic_vector(7 downto 0);
function is_instruction(INSTRUCTION_REGISTER : in std_logic_vector(7 downto 0);
INSTRUCTION : in integer range 0 to 7)
return STD_LOGIC is
begin
if (INSTRUCTION_REGISTER = std_logic_vector(to_unsigned(INSTRUCTION, 8))) then
return '1';
end if;
return '0';
end is_instruction;
function initialize_register_1 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(6, 8));
temp(1) := std_logic_vector(to_signed(7, 8));
return temp;
end initialize_register_1;
function initialize_register_2 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(36, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_register_2;
function initialize_zeros return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(0, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_zeros;
function increment_instruction_pointer(instruction_pointer : in std_logic_vector (7 downto 0))
return std_logic_vector is
begin
return std_logic_vector(signed(instruction_pointer) + 4);
end increment_instruction_pointer;
end smt_control_unit;
architecture Behavioral of smt_control_unit is
component smt_adder_unit
Port ( ADDER_A, ADDER_B : in STD_LOGIC_VECTOR (7 downto 0);
ADDER_S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_multiplier_unit
Port (MULTIPLIER_A, MULTIPLIER_B : in STD_LOGIC_VECTOR (7 downto 0);
MULTIPLIER_C : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_ram is
port
(
DATA0 : in std_logic_vector(7 downto 0);
DATA1 : in std_logic_vector(7 downto 0);
ADDR0 : in std_logic_vector(7 downto 0);
ADDR1 : in std_logic_vector(7 downto 0);
SET0 : in std_logic := '1';
SET1 : in std_logic := '1';
RAM_CLOCK : in std_logic;
OUT0 : out std_logic_vector(7 downto 0);
OUT1 : out std_logic_vector(7 downto 0);
OUT2 : out std_logic_vector(7 downto 0);
OUT3 : out std_logic_vector(7 downto 0);
OUT4 : out std_logic_vector(7 downto 0) := "00000111";
OUT5 : out std_logic_vector(7 downto 0);
OUT6 : out std_logic_vector(7 downto 0);
OUT7 : out std_logic_vector(7 downto 0);
OUTADDR0 : in std_logic_vector(7 downto 0);
OUTADDR1 : in std_logic_vector(7 downto 0)
);
end component;
component smt_instruction_handler
Port (HANDLER_INSTRUCTION : in std_logic_vector(7 downto 0);
HANDLER_INSTRUCTION_POINTER : in std_logic_vector(7 downto 0);
HANDLER_ADDR1 : in std_logic_vector(7 downto 0);
HANDLER_ADDR2 : in std_logic_vector(7 downto 0);
HANDLER_ADDR3 : in std_logic_vector(7 downto 0);
HANDLER_CLOCK : in std_logic;
HANDLER_OUTPUT : out std_logic_vector(7 downto 0);
HANDLER_INDEX : out std_logic_vector(7 downto 0);
HANDLER_SET : out std_logic;
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : out std_logic_vector(7 downto 0));
end component;
shared variable smt_thread_instruction_pointer : smt_thread_register := initialize_zeros;
shared variable smt_thread_instruction : smt_thread_register := initialize_register_1;
shared variable smt_thread_arg1 : smt_thread_register := initialize_register_2;
shared variable smt_thread_arg2 : smt_thread_register := initialize_zeros;
shared variable smt_thread_arg3 : smt_thread_register := initialize_zeros;
shared variable starting : std_logic := '1';
signal ADDER_A, ADDER_B, ADDER_S, MULTIPLIER_A, MULTIPLIER_B, MULTIPLIER_C,
HANDLER_INSTRUCTION, HANDLER_INSTRUCTION_POINTER, HANDLER_ADDR1, HANDLER_ADDR2,
HANDLER_ADDR3, HANDLER_OUTPUT, HANDLER_INDEX, DATA0, DATA1, ADDR0, ADDR1, OUT0,
OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUTADDR0, OUTADDR1 : std_logic_vector(7 downto 0);
signal SET0, SET1, RAM_CLOCK, HANDLER_SET, MULTIPLIER_CLOCK, ADDER_C, HANDLER_CLOCK : std_logic;
signal HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : std_logic_vector(7 downto 0);
begin
adder1 : smt_adder_unit Port Map (ADDER_A => ADDER_A, ADDER_B => ADDER_B, ADDER_S => ADDER_S);
multiplier1 : smt_multiplier_unit Port Map (MULTIPLIER_A => MULTIPLIER_A,
MULTIPLIER_B => MULTIPLIER_B,
MULTIPLIER_C => MULTIPLIER_C);
handler1 : smt_instruction_handler Port Map (HANDLER_INSTRUCTION => HANDLER_INSTRUCTION,
HANDLER_INSTRUCTION_POINTER => HANDLER_INSTRUCTION_POINTER,
HANDLER_ADDR1 => HANDLER_ADDR1,
HANDLER_ADDR2 => HANDLER_ADDR2,
HANDLER_ADDR3 => HANDLER_ADDR3,
HANDLER_CLOCK => HANDLER_CLOCK,
HANDLER_OUTPUT => HANDLER_OUTPUT,
HANDLER_INDEX => HANDLER_INDEX,
HANDLER_SET => HANDLER_SET,
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE =>
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE);
ram1 : smt_ram Port Map (DATA0 => DATA0, DATA1=>DATA1, ADDR0 => ADDR0,
ADDR1 => ADDR1, SET0 => SET0, SET1 => SET1,
RAM_CLOCK => RAM_CLOCK, OUT0 => OUT0,
OUT1 => OUT1, OUT2 => OUT2, OUT3 => OUT3,
OUT4 => OUT4, OUT5 => OUT5, OUT6 => OUT6,
OUT7 => OUT7, OUTADDR0 => OUTADDR0,
OUTADDR1 => OUTADDR1);
process (CLOCK) is
begin
RAM_CLOCK <= CLOCK;
HANDLER_CLOCK <= CLOCK;
if rising_edge(CLOCK) then
if starting = '0' then
smt_thread_instruction(0) := OUT0;
smt_thread_instruction(1) := OUT4;
smt_thread_arg1(0) := OUT1;
smt_thread_arg2(0) := OUT2;
smt_thread_arg3(0) := OUT3;
smt_thread_arg1(1) := OUT5;
smt_thread_arg2(1) := OUT6;
smt_thread_arg3(1) := OUT7;
else
starting := '0';
end if;
INSTRUCTION_0 <= smt_thread_instruction(0);
INSTRUCTION_1 <= smt_thread_instruction(1);
INSTRUCTION_POINTER_0 <= smt_thread_instruction_pointer(0);
INSTRUCTION_POINTER_1 <= smt_thread_instruction_pointer(1);
ARG1_0 <= smt_thread_arg1(0);
ARG1_1 <= smt_thread_arg1(1);
ARG2_0 <= smt_thread_arg2(0);
ARG2_1 <= smt_thread_arg2(1);
ARG3_0 <= smt_thread_arg3(0);
ARG3_1 <= smt_thread_arg3(1);
case smt_thread_instruction(0) is
when "00000000" =>
ADDER_A <= smt_thread_arg1(0);
ADDER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= ADDER_S;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
case smt_thread_instruction(1) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(1) = smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(1) > smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000100" =>
-- thread 0 set
DATA1 <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg1(1);
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
when "00000101" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(1);
when others =>
end case;
when "00000001" =>
MULTIPLIER_A <= smt_thread_arg1(0);
MULTIPLIER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= MULTIPLIER_C;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when others =>
case smt_thread_instruction(0) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(0) = smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(0) > smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000100" =>
-- thread 0 set
DATA0 <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg1(0);
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000101" =>
smt_thread_instruction_pointer(0) := smt_thread_arg1(0);
when "00000110" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(0);
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000111" =>
when others =>
end case;
if smt_thread_instruction(1) = "00000000" then
ADDER_A <= smt_thread_arg1(1);
ADDER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= ADDER_S;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
elsif smt_thread_instruction(1) = "00000001" then
MULTIPLIER_A <= smt_thread_arg1(1);
MULTIPLIER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= MULTIPLIER_C;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
end case;
end if;
OUTADDR0 <= smt_thread_instruction_pointer(0);
OUTADDR1 <= smt_thread_instruction_pointer(1);
end process;
end Behavioral;
|
mit
|
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