repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/clk_32to25_dcm.vhd
|
13
|
6302
|
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to25_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to25_dcm;
architecture xilinx of clk_32to25_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to25_dcm,clk_wiz_v3_6,{component_name=clk_32to25_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Benchy/receiver.vhd
|
13
|
6114
|
----------------------------------------------------------------------------------
-- receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycles
-- on the op and data outputs. A valid command can be detected by checking if the
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY);
-- constant BITLENGTH : integer := FREQ / RATE;
constant BITLENGTH : integer := 16;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command
signal state, nstate : UART_STATES; -- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
process(clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
ndataBuf <= dataBuf;
else
nbytecount <= bytecount;
if bytecount = 0 then
nopcode <= rx & opcode(7 downto 1);
ndataBuf <= dataBuf;
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nbitcount <= bitcount;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
nstate <= state;
end if;
-- check if long or short command has been fully received
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
ncounter <= counter + 1;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/receiver.vhd
|
13
|
6114
|
----------------------------------------------------------------------------------
-- receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycles
-- on the op and data outputs. A valid command can be detected by checking if the
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY);
-- constant BITLENGTH : integer := FREQ / RATE;
constant BITLENGTH : integer := 16;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command
signal state, nstate : UART_STATES; -- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
process(clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
ndataBuf <= dataBuf;
else
nbytecount <= bytecount;
if bytecount = 0 then
nopcode <= rx & opcode(7 downto 1);
ndataBuf <= dataBuf;
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nbitcount <= bitcount;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
nstate <= state;
end if;
-- check if long or short command has been fully received
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
ncounter <= counter + 1;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/receiver.vhd
|
13
|
6114
|
----------------------------------------------------------------------------------
-- receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycles
-- on the op and data outputs. A valid command can be detected by checking if the
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY);
-- constant BITLENGTH : integer := FREQ / RATE;
constant BITLENGTH : integer := 16;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command
signal state, nstate : UART_STATES; -- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
process(clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
ndataBuf <= dataBuf;
else
nbytecount <= bytecount;
if bytecount = 0 then
nopcode <= rx & opcode(7 downto 1);
ndataBuf <= dataBuf;
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nbitcount <= bitcount;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
nstate <= state;
end if;
-- check if long or short command has been fully received
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
ncounter <= counter + 1;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/BRAM6k36bit.vhd
|
13
|
3666
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Benchy/BRAM6k36bit.vhd
|
13
|
3666
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/BRAM6k36bit.vhd
|
13
|
3666
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to960_pll.vhd
|
13
|
5860
|
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___960.000______0.000______50.0______153.093____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to960_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to960_pll;
architecture xilinx of clk_32to960_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to960_pll,clk_wiz_v3_6,{component_name=clk_32to960_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/clk_32to960_pll.vhd
|
13
|
5860
|
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___960.000______0.000______50.0______153.093____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to960_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to960_pll;
architecture xilinx of clk_32to960_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to960_pll,clk_wiz_v3_6,{component_name=clk_32to960_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/clk_32to960_pll.vhd
|
13
|
5860
|
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___960.000______0.000______50.0______153.093____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to960_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to960_pll;
architecture xilinx of clk_32to960_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to960_pll,clk_wiz_v3_6,{component_name=clk_32to960_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/wbarb2_1.vhd
|
13
|
3656
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end entity wbarb2_1;
architecture behave of wbarb2_1 is
signal current_master: std_logic;
signal next_master: std_logic;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
current_master <= '0';
else
current_master <= next_master;
end if;
end if;
end process;
process(current_master, m0_wb_cyc_i, m1_wb_cyc_i)
begin
next_master <= current_master;
case current_master is
when '0' =>
if m0_wb_cyc_i='0' then
if m1_wb_cyc_i='1' then
next_master <= '1';
end if;
end if;
when '1' =>
if m1_wb_cyc_i='0' then
if m0_wb_cyc_i='1' then
next_master <= '0';
end if;
end if;
when others =>
end case;
end process;
-- Muxers for slave
process(current_master,
m0_wb_dat_i, m0_wb_adr_i, m0_wb_sel_i, m0_wb_cti_i, m0_wb_we_i, m0_wb_cyc_i, m0_wb_stb_i,
m1_wb_dat_i, m1_wb_adr_i, m1_wb_sel_i, m1_wb_cti_i, m1_wb_we_i, m1_wb_cyc_i, m1_wb_stb_i)
begin
case current_master is
when '0' =>
s0_wb_dat_o <= m0_wb_dat_i;
s0_wb_adr_o <= m0_wb_adr_i;
s0_wb_sel_o <= m0_wb_sel_i;
s0_wb_cti_o <= m0_wb_cti_i;
s0_wb_we_o <= m0_wb_we_i;
s0_wb_cyc_o <= m0_wb_cyc_i;
s0_wb_stb_o <= m0_wb_stb_i;
when '1' =>
s0_wb_dat_o <= m1_wb_dat_i;
s0_wb_adr_o <= m1_wb_adr_i;
s0_wb_sel_o <= m1_wb_sel_i;
s0_wb_cti_o <= m1_wb_cti_i;
s0_wb_we_o <= m1_wb_we_i;
s0_wb_cyc_o <= m1_wb_cyc_i;
s0_wb_stb_o <= m1_wb_stb_i;
when others =>
null;
end case;
end process;
-- Muxers/sel for masters
m0_wb_dat_o <= s0_wb_dat_i;
m1_wb_dat_o <= s0_wb_dat_i;
-- Ack
m0_wb_ack_o <= s0_wb_ack_i when current_master='0' else '0';
m1_wb_ack_o <= s0_wb_ack_i when current_master='1' else '0';
m0_wb_stall_o <= s0_wb_stall_i when current_master='0' else '1';
m1_wb_stall_o <= s0_wb_stall_i when current_master='1' else '1';
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8.vhd
|
13
|
6645
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8 is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic;
rx : in std_logic;
tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic;
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8 is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => '0',
speed => SPEED,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
-- Inst_spi_slave: spi_slave
-- port map(
-- clock => clock,
-- data => output,
-- send => send,
-- mosi => mosi,
-- sclk => sclk,
-- cs => cs,
-- miso => miso,
-- cmd => cmd,
-- execute => execute,
-- busy => busy,
-- dataReady => dataReady,
-- tx_bytes => tx_bytes
-- );
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Benchy/core.vhd
|
13
|
14437
|
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity core is
port(
clock : in std_logic;
cmd : in std_logic_vector (39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector (31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector (35 downto 0);
memoryOut : out std_logic_vector (35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end core;
architecture behavioral of core is
component decoder
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end component;
component flags
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end component;
component sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end component;
component testmode is
port(
clock : in std_logic;
enable : in std_logic;
la_input : in std_logic_vector (31 downto 0);
output : out std_logic_vector (31 downto 0)
);
end component;
component sampler
port(
la_input : in std_logic_vector(31 downto 0);
clock : in std_logic;
exClock : in std_logic;
external : in std_logic;
data : in std_logic_vector(23 downto 0);
wrDivider : in std_logic;
sample : out std_logic_vector(31 downto 0);
ready : out std_logic;
trig_delay : out std_logic_vector(1 downto 0);
num_scheme : in std_logic
);
end component;
component trigger
port(
la_input : in std_logic_vector(31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic_vector(3 downto 0);
wrValue : in std_logic_vector(3 downto 0);
wrConfig : in std_logic_vector(3 downto 0);
arm : in std_logic;
demuxed : in std_logic;
run : out std_logic;
ExtTriggerIn : in std_logic
);
end component;
component group_selector
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end component;
component rle
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end component;
component controller
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end component;
component muldex
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end component;
signal opcode : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal sample, syncedla_input : std_logic_vector (31 downto 0);
signal sampleClock, run : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted : std_logic;
signal wrFlags, sampleReady, flagRLE, flagTest : std_logic;
signal armLEDreg : std_logic := '0';
signal triggerLEDreg : std_logic := '0';
signal data_rd, data_wr, controller_la_inputReady : std_logic;
signal rle_busy, rle_inp_valid, raw_inp_ready : std_logic;
signal data_size : std_logic_vector(1 downto 0);
signal disabledGroups : std_logic_vector (3 downto 0);
signal la_input_sampler : std_logic_vector(31 downto 0);
signal controller_memoryIn, raw_inp : std_logic_vector (31 downto 0);
signal data_inp, controller_la_input, rle_inp : std_logic_vector (32 downto 0);
signal data_ready, raw_ready, rdstate : std_logic := '0';
signal trig_delay : std_logic_vector(1 downto 0);
signal num_scheme, abort, ident, meta : std_logic;
signal output_i : std_logic_vector (31 downto 0);
signal outputSend_i : std_logic;
signal tx_bytes_i : integer range 0 to 4;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= resetCmd;
--armLED <= not armLEDreg; --Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on.
--triggerLED <= not triggerLEDreg;
--extClockOut <= sampleClock;
--extTriggerOut <= run;
tx_bytes_i <=
1 when data_size = "01" else
2 when data_size = "10" else
3 when disabledGroups = "1000" and flagRLE = '0' else
3 when disabledGroups = "0100" and flagRLE = '0' else
3 when disabledGroups = "0010" and flagRLE = '0' else
3 when disabledGroups = "0001" and flagRLE = '0' else
4;
-- process commands
process_cmd_block : block
constant rom_size : natural := 18;
type states is (IDLE, IDENTIFY, METADATA, BUSYWAIT);
type rom_type is array (rom_size-1 downto 0) of
std_logic_vector (31 downto 0);
constant rom : rom_type := (
0 => x"00000020", 1 => x"00002120", -- 0x20 0x00000020
2 => x"00220018", 3 => x"23001800", -- 0x21 0x00001800
4 => x"00e1f505", 5 => x"00000024", -- 0x22 0x00001800
6 => x"41204002", 7 => x"704f0102", -- 0x23 0x05f5e100
8 => x"65626e65", 9 => x"2068636e", -- 0x24 0x00000002
10 => x"69676f4c", 11 => x"6e532063", -- 0x40 0x20
12 => x"65666669", 13 => x"31762072", -- 0x41 0x02
14 => x"0031302e", 15 => x"302e3302",
16 => x"48560300", others => x"00004c44"
);
-- 0x01 "Openbench Logic Sniffer v1.01"
-- 0x02 "3.0"
-- 0x03 "VHDL"
signal state : states;
signal send_cmd : std_logic;
signal cmd_output : std_logic_vector (31 downto 0);
signal addr : integer range 0 to rom_size + 1;
begin
tx_bytes <= 4 when send_cmd = '1' else tx_bytes_i;
output <= cmd_output when send_cmd = '1' else output_i;
outputSend <= '1' when send_cmd = '1' else outputSend_i;
process(clock)
begin
if rising_edge(clock) then
case state is
when IDLE =>
if outputBusy = '0' then
if ident = '1' then
state <= IDENTIFY;
end if;
--Disabled, this was wreaking havoc with SPI slave
-- if meta = '1' then
-- state <= METADATA;
-- end if;
end if;
send_cmd <= '0';
addr <= 0;
when IDENTIFY =>
send_cmd <= '1';
cmd_output <= x"534c4131"; -- "SLA1"
state <= IDLE;
when METADATA =>
send_cmd <= '1';
cmd_output <= rom(addr);
addr <= addr + 1;
state <= BUSYWAIT;
when BUSYWAIT =>
send_cmd <= '0';
if outputBusy = '0' and send_cmd = '0' then
if addr = rom_size then
state <= IDLE;
else
state <= METADATA;
end if;
end if;
end case;
end if;
end process;
end block;
--Generates observable trigger and arm LED signals
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if arm = '1' then
-- armLEDreg <= '1';
-- triggerLEDreg <= '0';
-- elsif run = '1' then
-- armLEDreg <= '0';
-- triggerLEDreg <= '1';
-- end if;
-- end if;
-- end process;
-- select between internal and external sampling clock
-- BUFGMUX_intex: BUFGMUX
-- port map (
-- O => sampleClock, -- Clock MUX output
-- I0 => clock, -- Clock0 la_input
-- I1 => la_inputClock, -- Clock1 la_input
-- S => flagExternal -- Clock select la_input
-- );
sampleClock <= clock;
Inst_decoder: decoder
port map(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd,
abort => abort,
ident => ident,
meta => meta
);
Inst_flags: flags
port map(
data => data(10 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
disabledGroups => disabledGroups,
rle => flagRLE,
test_mode => flagTest,
data_size => data_size,
num_scheme => num_scheme
);
Inst_sync: sync
port map(
la_input => la_input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedla_input
);
-- Inst_testmode: testmode
-- port map(
-- clock => clock,
-- enable => flagTest,
-- la_input => syncedla_input,
-- output => la_input_sampler
-- );
Inst_sampler: sampler
port map(
la_input => syncedla_input,
clock => clock,
exClock => la_inputClock,
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
trig_delay => trig_delay,
num_scheme => num_scheme
);
Inst_trigger: trigger
port map(
la_input => sample,
la_inputReady => sampleReady,
data => data,
clock => clock,
reset => resetCmd,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run,
extTriggerIn => extTriggerIn
);
Inst_group_selector: group_selector
port map(
clock => clock,
la_input => sample,
la_input_ready => sampleReady,
output => raw_inp,
output_ready => raw_inp_ready,
disabledGroups => disabledGroups
);
Inst_rle: rle
port map(
clock => clock,
reset => resetCmd,
raw_inp => raw_inp,
fmt_out => controller_memoryIn,
enable => flagRLE,
raw_inp_valid => raw_inp_ready,
rle_inp_valid => rle_inp_valid,
-- start_count => run,
data_size => data_size,
rle_out => controller_la_input,
rle_inp => rle_inp,
rle_out_valid => controller_la_inputReady,
busy => rle_busy,
rle_ready => data_ready,
raw_ready => raw_ready
);
Inst_controller: controller
port map(
clock => clock,
reset => resetCmd,
la_input => controller_la_input,
la_inputReady => controller_la_inputReady,
run => run,
wrSize => wrSize,
data => data,
busy => outputBusy,
send => outputSend_i,
output => output_i,
memoryIn => controller_memoryIn,
memoryOut => data_inp,
memoryRead => data_rd,
memoryWrite => data_wr,
rle_busy => rle_busy,
rle_read => rle_inp_valid,
rle_mode => flagRLE,
rdstate => rdstate,
data_ready => data_ready,
trig_delay => trig_delay,
abort => abort
);
Inst_muldex : muldex
port map(
clock => clock,
reset => resetCmd,
data_inp => data_inp,
data_out => rle_inp,
data_rd => data_rd,
data_wr => data_wr,
mem_inp => memoryIn,
mem_out => memoryOut,
mem_rd => memoryRead,
mem_wr => memoryWrite,
data_size => data_size,
rdstate => rdstate,
data_ready => raw_ready
);
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/zpuino_uart_mv_filter.vhd
|
13
|
2522
|
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity zpuino_uart_mv_filter;
architecture behave of zpuino_uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/zpuino_uart_mv_filter.vhd
|
13
|
2522
|
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity zpuino_uart_mv_filter;
architecture behave of zpuino_uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_intr.vhd
|
13
|
10649
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/zpuino_intr.vhd
|
13
|
10649
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/Wishbone_Empty_Slot.vhd
|
13
|
3505
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library zpuino;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
entity Wishbone_Empty_Slot is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity Wishbone_Empty_Slot;
architecture behave of Wishbone_Empty_Slot is
-- signal wishbone_in_record : wishbone_bus_in_type;
-- signal wishbone_out_record : wishbone_bus_out_type;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Actual code for the module
-- wishbone_out_record.wb_ack_o <= wishbone_in_record.wb_cyc_i and wishbone_in_record.wb_stb_i;
wishbone_out(1) <= wishbone_in(1) and wishbone_in(0);
-- wishbone_out_record.wb_inta_o <= '0';
wishbone_out(0) <= '0';
-- wishbone_out_record.wb_dat_o <= (others => DontCareValue);
wishbone_out(33 downto 2) <= (others => DontCareValue);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_Pro/clkgen.vhd
|
13
|
7033
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clk_1Mhz_out
);
clkin_i_1mhz <= clkout_i;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/clkgen.vhd
|
13
|
7033
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clk_1Mhz_out
);
clkin_i_1mhz <= clkout_i;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd
|
13
|
4021
|
--
-- Audio Passthrough
--
-- Copyright 2008,2009,2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.1: First version, adapted from sigma-delta.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpupkg.all;
use board.zpu_config.all;
use board.zpuinopkg.all;
entity AUDIO_zpuino_wb_passthrough is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_passthrough;
architecture behave of AUDIO_zpuino_wb_passthrough is
signal dat_q1: unsigned(17 downto 0);
signal dat_q2: unsigned(17 downto 0);
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o <= (others => '0');
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0));
raw_out(1 downto 0)<=(others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dat_q1 <= (others =>'0');
dat_q1(15) <= '1';
dat_q2 <= (others =>'0');
dat_q2(15) <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(2) is
when '1' =>
dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0));
dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16));
when others =>
end case;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd
|
13
|
4021
|
--
-- Audio Passthrough
--
-- Copyright 2008,2009,2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.1: First version, adapted from sigma-delta.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpupkg.all;
use board.zpu_config.all;
use board.zpuinopkg.all;
entity AUDIO_zpuino_wb_passthrough is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_passthrough;
architecture behave of AUDIO_zpuino_wb_passthrough is
signal dat_q1: unsigned(17 downto 0);
signal dat_q2: unsigned(17 downto 0);
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o <= (others => '0');
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0));
raw_out(1 downto 0)<=(others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dat_q1 <= (others =>'0');
dat_q1(15) <= '1';
dat_q2 <= (others =>'0');
dat_q2(15) <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(2) is
when '1' =>
dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0));
dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16));
when others =>
end case;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Wishbone_Peripherals/sid_6581.vhd
|
13
|
16739
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/sid_6581.vhd
|
13
|
16739
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/Wing_Analog.vhd
|
13
|
1476
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/uart_brgen.vhd
|
15
|
2186
|
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end entity uart_brgen;
architecture behave of uart_brgen is
signal cnt: integer range 0 to 65535;
begin
process (clk)
begin
if rising_edge(clk) then
clkout <= '0';
if rst='1' then
cnt <= conv_integer(count);
elsif en='1' then
if cnt=0 then
clkout <= '1';
cnt <= conv_integer(count);
else
cnt <= cnt - 1;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/uart_brgen.vhd
|
15
|
2186
|
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end entity uart_brgen;
architecture behave of uart_brgen is
signal cnt: integer range 0 to 65535;
begin
process (clk)
begin
if rising_edge(clk) then
clkout <= '0';
if rst='1' then
cnt <= conv_integer(count);
elsif en='1' then
if cnt=0 then
clkout <= '1';
cnt <= conv_integer(count);
else
cnt <= cnt - 1;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
Oblomov/pocl
|
examples/accel/rtl/platform/xilinx_dp_blockram.vhdl
|
2
|
9101
|
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx dual-port BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_do_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_dp_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- PORT A -------------------------------------------------------
-- Access channel
a_avalid_in : in std_logic;
a_aready_out : out std_logic;
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_awren_in : in std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
a_rvalid_out : out std_logic;
a_rready_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
-- PORT B -------------------------------------------------------
-- Access channel
b_avalid_in : in std_logic;
b_aready_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_awren_in : in std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
b_rvalid_out : out std_logic;
b_rready_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_dp_blockram;
architecture rtl of xilinx_dp_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
constant adata_padding_c : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal a_addr, b_addr : unsigned(addrw_g-1 downto 0);
signal a_wdata, b_wdata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_ram_rdata_r, b_ram_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_enable, b_enable : std_logic;
signal a_strb, b_strb : std_logic_vector(astrb_width_c-1 downto 0);
signal a_adata, b_adata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_aready_r, b_aready_r : std_logic;
signal a_live_read, b_live_read : std_logic;
signal a_live_read_r, b_live_read_r : std_logic;
signal a_rdata_r, b_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_rdata_valid_r, b_rdata_valid_r : std_logic;
signal a_rvalid, b_rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
shared variable RAM_ARR : ram_type;
begin
control_comb_a : process(a_aaddr_in, a_avalid_in, a_aready_r, a_awren_in,
a_astrb_in, a_live_read_r, a_rdata_valid_r)
begin
if a_avalid_in = '1' and a_aready_r = '1' then
a_enable <= '1';
if a_awren_in = '1' then
a_strb <= a_astrb_in;
a_live_read <= '0';
else
a_strb <= (others => '0');
a_live_read <= '1';
end if;
else
a_strb <= (others => '0');
a_enable <= '0';
a_live_read <= '0';
end if;
a_addr <= unsigned(a_aaddr_in);
a_rvalid <= a_live_read_r or a_rdata_valid_r;
end process;
control_comb_b : process(b_aaddr_in, b_avalid_in, b_aready_r, b_awren_in,
b_astrb_in, b_live_read_r, b_rdata_valid_r)
begin
if b_avalid_in = '1' and b_aready_r = '1' then
b_enable <= '1';
if b_awren_in = '1' then
b_strb <= b_astrb_in;
b_live_read <= '0';
else
b_strb <= (others => '0');
b_live_read <= '1';
end if;
else
b_strb <= (others => '0');
b_enable <= '0';
b_live_read <= '0';
end if;
b_addr <= unsigned(b_aaddr_in);
b_rvalid <= b_live_read_r or b_rdata_valid_r;
end process;
control_sync_a : process(clk, rstx)
begin
if rstx = '0' then
a_live_read_r <= '0';
a_aready_r <= '0';
a_rdata_valid_r <= '0';
a_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if a_rvalid = '1' and a_rready_in = '1' then
a_rdata_valid_r <= '0';
end if;
if a_rvalid = '1' and a_rready_in = '0' then
a_aready_r <= '0';
else
a_aready_r <= '1';
end if;
a_live_read_r <= a_live_read or a_live_read_r;
if a_live_read_r = '1' and (a_rready_in = '1' or a_rdata_valid_r = '0') then
a_live_read_r <= a_live_read;
if a_rready_in = '0' or a_rdata_valid_r = '1' then
a_rdata_valid_r <= '1';
a_rdata_r <= a_ram_rdata_r;
end if;
end if;
end if;
end process;
control_sync_b : process(clk, rstx)
begin
if rstx = '0' then
b_live_read_r <= '0';
b_aready_r <= '0';
b_rdata_valid_r <= '0';
b_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if b_rvalid = '1' and b_rready_in = '1' then
b_rdata_valid_r <= '0';
end if;
if b_rvalid = '1' and b_rready_in = '0' then
b_aready_r <= '0';
else
b_aready_r <= '1';
end if;
b_live_read_r <= b_live_read or b_live_read_r;
if b_live_read_r = '1' and (b_rready_in = '1' or b_rdata_valid_r = '0') then
b_live_read_r <= b_live_read;
if b_rready_in = '0' or b_rdata_valid_r = '1' then
b_rdata_valid_r <= '1';
b_rdata_r <= b_ram_rdata_r;
end if;
end if;
end if;
end process;
a_wdata <= adata_padding_c & a_adata_in;
b_wdata <= adata_padding_c & b_adata_in;
RAM_A : process(clk)
begin
if rising_edge(clk) then
if a_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if a_strb(i) = '1' then
RAM_ARR(to_integer(a_addr))((i+1)*8-1 downto i*8)
:= a_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
a_ram_rdata_r <= RAM_ARR(to_integer(a_addr));
end if;
end if;
end process;
RAM_B : process(clk)
begin
if rising_edge(clk) then
if b_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if b_strb(i) = '1' then
RAM_ARR(to_integer(b_addr))((i+1)*8-1 downto i*8)
:= b_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
b_ram_rdata_r <= RAM_ARR(to_integer(b_addr));
end if;
end if;
end process;
a_rdata_out <= a_ram_rdata_r(a_rdata_out'range) when a_rdata_valid_r = '0'
else a_rdata_r(a_rdata_out'range);
b_rdata_out <= b_ram_rdata_r(b_rdata_out'range) when b_rdata_valid_r = '0'
else b_rdata_r(b_rdata_out'range);
a_aready_out <= a_aready_r;
a_rvalid_out <= a_rvalid;
b_aready_out <= b_aready_r;
b_rvalid_out <= b_rvalid;
end architecture rtl;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/zpuino_top_hyperion.vhd
|
13
|
16489
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/zpuino_uart_rx.vhd
|
13
|
4937
|
--
-- UART for ZPUINO - Receiver unit
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end entity zpuino_uart_rx;
architecture behave of zpuino_uart_rx is
component zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end component zpuino_uart_mv_filter;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxf: std_logic;
signal baudtick: std_logic;
signal rxd: std_logic_vector(7 downto 0);
signal datacount: unsigned(2 downto 0);
signal baudreset: std_logic;
signal filterreset: std_logic;
signal datao: std_logic_vector(7 downto 0);
signal dataready: std_logic;
signal start: std_logic;
signal debug_synctick_q: std_logic;
signal debug_baudreset_q: std_logic;
-- State
type uartrxstate is (
rx_idle,
rx_start,
rx_data,
rx_end
);
signal state: uartrxstate;
begin
data <= datao;
data_av <= dataready;
rxmvfilter: zpuino_uart_mv_filter
generic map (
bits => 4,
threshold => 10
)
port map (
clk => clk,
rst => rst,
sin => rx,
sout => rxf,
clear => filterreset,
enable => rxclk
);
filterreset <= baudreset or baudtick;
--istart <= start;
baudgen: uart_brgen
port map (
clk => clk,
rst => baudreset,
en => rxclk,
count => x"000f",
clkout => baudtick
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
state <= rx_idle;
dataready <= '0';
baudreset <= '0';
start<='0';
else
baudreset <= '0';
start<='0';
if read='1' then
dataready <= '0';
end if;
case state is
when rx_idle =>
if rx='0' then -- Start bit
state <= rx_start;
baudreset <= '1';
start <='1';
end if;
when rx_start =>
if baudtick='1' then
-- Check filtered output.
if rxf='0' then
datacount <= b"111";
state <= rx_data; -- Valid start bit.
else
state <= rx_idle;
end if;
end if;
when rx_data =>
if baudtick='1' then
rxd(7) <= rxf;
rxd(6 downto 0) <= rxd(7 downto 1);
datacount <= datacount - 1;
if datacount=0 then
state <= rx_end;
end if;
end if;
when rx_end =>
-- Check for framing errors ?
-- Do fast recovery here.
if rxf='1' then
dataready<='1';
datao <= rxd;
state <= rx_idle;
end if;
if baudtick='1' then
-- Framing error.
state <= rx_idle;
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Wishbone_Peripherals/sid_coeffs.vhd
|
13
|
18880
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end entity;
architecture beh of sid_coeffs is
type mtype is array(0 to 2047) of std_logic_vector(15 downto 0);
constant coef: mtype := (
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d5",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02d8",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02db",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02df",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e2",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e5",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02e8",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ec",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02ef",
x"02f2",
x"02f2",
x"02f2",
x"02f2",
x"02f2",
x"02f2",
x"02f2",
x"02f2",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f6",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02f9",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"02fc",
x"0300",
x"0300",
x"0300",
x"0300",
x"0300",
x"0300",
x"0300",
x"0300",
x"0300",
x"0303",
x"0303",
x"0303",
x"0303",
x"0303",
x"0303",
x"0303",
x"0303",
x"0303",
x"0306",
x"0306",
x"0306",
x"0306",
x"0306",
x"0306",
x"0306",
x"0306",
x"0309",
x"0309",
x"0309",
x"0309",
x"0309",
x"0309",
x"0309",
x"0309",
x"030d",
x"030d",
x"030d",
x"030d",
x"030d",
x"030d",
x"030d",
x"0310",
x"0310",
x"0310",
x"0310",
x"0310",
x"0310",
x"0310",
x"0313",
x"0313",
x"0313",
x"0313",
x"0313",
x"0313",
x"0317",
x"0317",
x"0317",
x"0317",
x"0317",
x"0317",
x"031a",
x"031a",
x"031a",
x"031a",
x"031a",
x"031a",
x"031d",
x"031d",
x"031d",
x"031d",
x"031d",
x"0320",
x"0320",
x"0320",
x"0320",
x"0320",
x"0324",
x"0324",
x"0324",
x"0324",
x"0324",
x"0327",
x"0327",
x"0327",
x"0327",
x"0327",
x"032a",
x"032a",
x"032a",
x"032a",
x"032e",
x"032e",
x"032e",
x"032e",
x"0331",
x"0331",
x"0331",
x"0331",
x"0334",
x"0334",
x"0334",
x"0338",
x"0338",
x"0338",
x"0338",
x"033b",
x"033b",
x"033b",
x"033b",
x"033e",
x"033e",
x"033e",
x"033e",
x"0341",
x"0341",
x"0341",
x"0345",
x"0345",
x"0345",
x"0345",
x"0348",
x"0348",
x"0348",
x"0348",
x"034b",
x"034b",
x"034b",
x"034f",
x"034f",
x"034f",
x"034f",
x"0352",
x"0352",
x"0352",
x"0355",
x"0355",
x"0355",
x"0355",
x"0358",
x"0358",
x"0358",
x"035c",
x"035c",
x"035c",
x"035c",
x"035f",
x"035f",
x"035f",
x"0362",
x"0362",
x"0362",
x"0366",
x"0366",
x"0366",
x"0369",
x"0369",
x"0369",
x"036c",
x"036c",
x"036c",
x"0370",
x"0370",
x"0370",
x"0373",
x"0373",
x"0373",
x"0376",
x"0376",
x"0376",
x"0379",
x"0379",
x"0379",
x"037d",
x"037d",
x"0380",
x"0380",
x"0380",
x"0383",
x"0383",
x"0383",
x"0387",
x"0387",
x"038a",
x"038a",
x"038d",
x"038d",
x"038d",
x"0390",
x"0390",
x"0394",
x"0394",
x"0397",
x"0397",
x"0397",
x"039a",
x"039a",
x"039e",
x"039e",
x"03a1",
x"03a1",
x"03a4",
x"03a4",
x"03a8",
x"03a8",
x"03ab",
x"03ab",
x"03ae",
x"03ae",
x"03b1",
x"03b1",
x"03b5",
x"03b8",
x"03b8",
x"03bb",
x"03bb",
x"03bf",
x"03bf",
x"03c2",
x"03c5",
x"03c5",
x"03c8",
x"03c8",
x"03cc",
x"03cf",
x"03cf",
x"03d2",
x"03d6",
x"03d6",
x"03d9",
x"03dc",
x"03dc",
x"03e0",
x"03e0",
x"03e3",
x"03e6",
x"03e6",
x"03e9",
x"03ed",
x"03ed",
x"03f0",
x"03f0",
x"03f3",
x"03f7",
x"03f7",
x"03fa",
x"03fd",
x"03fd",
x"0400",
x"0400",
x"0404",
x"0404",
x"0407",
x"040a",
x"040a",
x"040e",
x"040e",
x"0411",
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x"b0f9",
x"b13b",
x"b17a",
x"b1b8",
x"b1fa",
x"b239",
x"b277",
x"b2b6",
x"b2f4",
x"b333",
x"b372",
x"b3b0",
x"b3eb",
x"b42a",
x"b465",
x"b4a4",
x"b4df",
x"b51b",
x"b559",
x"b594",
x"b5d0",
x"b60b",
x"b643",
x"b67e",
x"b6ba",
x"b6f2",
x"b72d",
x"b765",
x"b79d",
x"b7d8",
x"b810",
x"b848",
x"b87d",
x"b8b5",
x"b8ed",
x"b922",
x"b95a",
x"b98e",
x"b9c3",
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x"ba2c",
x"ba61",
x"ba96",
x"bac7",
x"bafc",
x"bb2d",
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x"bb90",
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x"bcb9",
x"bce7",
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x"bda6",
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x"be89",
x"beb7",
x"bee5",
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x"c018",
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x"d3d8",
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x"d431",
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x"d4a8",
x"d4c6",
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x"d501",
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x"d5ca",
x"d5e7",
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x"d61f",
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x"d657",
x"d675",
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x"dc36",
x"dc49",
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x"dc8b",
x"dc9f",
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x"dd68",
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x"ddcb",
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x"e6ac",
x"e6b2",
x"e6b9",
x"e6c0",
x"e6c6",
x"e6cd",
x"e6d3",
x"e6da",
x"e6dd",
x"e6e4",
x"e6ea",
x"e6f1",
x"e6f8",
x"e6fe",
x"e705",
x"e708",
x"e70f",
x"e715",
x"e71c",
x"e722",
x"e729",
x"e72c",
x"e733",
x"e739",
x"e740",
x"e747",
x"e74d",
x"e751",
x"e757",
x"e75e",
x"e764",
x"e768",
x"e76e",
x"e775",
x"e77b",
x"e782",
x"e785",
x"e78c",
x"e792",
x"e799",
x"e7a0");
begin
process(clk)
begin
if rising_edge(clk) then
val <= coef(addr);
end if;
end process;
end beh;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/papilio_stepper.vhd
|
13
|
7399
|
--**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget Factory (www.gadgetfactory.net)
-- This work is licensed under the Creative Commons Attribution 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
-- use work.zpuino_config.all;
-- use work.zpu_config.all;
-- use work.zpupkg.all;
entity papilio_stepper is
Generic (
timebase_g : std_logic_vector(15 downto 0) := (others => '0');
period_g : std_logic_vector(15 downto 0) := (others => '0')
);
port (
wb_clk_i: in std_logic; -- Wishbone clock
wb_rst_i: in std_logic; -- Wishbone reset (synchronous)
wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: in std_logic; -- Wishbone write enable signal
wb_cyc_i: in std_logic; -- Wishbone cycle signal
wb_stb_i: in std_logic; -- Wishbone strobe signal
wb_ack_o: out std_logic; -- Wishbone acknowledge out signal
-- External connections
st_home : in std_logic;
st_dir : out std_logic;
st_ms2 : out std_logic;
st_ms1 : out std_logic;
st_rst : out std_logic;
st_step : out std_logic;
st_enable : out std_logic;
st_sleep : out std_logic;
-- IRQ
st_irq : out std_logic
);
end entity papilio_stepper;
architecture rtl of papilio_stepper is
signal prescale_o : std_logic;
signal halfperiod_o : std_logic;
signal step_o : std_logic;
signal irq_o : std_logic;
signal Control_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Timebase_reg : std_logic_vector(15 downto 0) := timebase_g;
signal Period_reg : std_logic_vector(15 downto 0) := period_g;
signal StepCnt_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Steps_reg : std_logic_vector(15 downto 0) := (others => '0');
signal PrescaleCnt : std_logic_vector(15 downto 0);
signal HalfPeriodCnt : std_logic_vector(15 downto 0);
signal ack_i: std_logic; -- Internal ACK signal (flip flop)
begin
-- This example uses fully synchronous outputs.
-- General Output signals
st_dir <= Control_reg(3);
st_ms2 <= Control_reg(1);
st_ms1 <= Control_reg(0);
st_rst <= Control_reg(4);
st_step <= step_o;
st_sleep <= Control_reg(7);
st_enable <= not Control_reg(8);
st_irq <= irq_o;
wb_ack_o <= ack_i; -- Tie ACK output to our flip flop
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
-- Always set output data on rising edge, even if reset is set.
Control_reg(14) <= st_home;
Control_reg(15) <= irq_o;
wb_dat_o <= (others => 'X'); -- Return undefined by omission
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(Control_reg'RANGE) <= Control_reg;
when "001" =>
wb_dat_o(Timebase_reg'RANGE) <= Timebase_reg;
when "010" =>
wb_dat_o(Period_reg'RANGE) <= Period_reg;
when "011" =>
wb_dat_o(StepCnt_reg'RANGE) <= StepCnt_reg;
when "100" =>
wb_dat_o(Steps_reg'RANGE) <= Steps_reg;
when others =>
end case;
ack_i <= '0'; -- Reset ACK value by default
if wb_rst_i='1' then
Control_reg <= "0000000010010000";
Timebase_reg <= timebase_g;
Period_reg <= period_g;
StepCnt_reg <= (others => '0');
else -- Not reset
-- See if we did not acknowledged a cycle, otherwise we need to ignore
-- the apparent request, because wishbone signals are still set
if ack_i='0' then
-- Check if someone is accessing
if wb_cyc_i='1' and wb_stb_i='1' then
ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above.
if wb_we_i='1' then
-- It's a write. See for which register based on address
case wb_adr_i(4 downto 2) is
when "000" =>
Control_reg(8 downto 0) <= wb_dat_i(8 downto 0); -- Set register
when "001" =>
Timebase_reg <= wb_dat_i(Timebase_reg'RANGE);
when "010" =>
Period_reg <= wb_dat_i(Period_reg'RANGE);
when "011" =>
StepCnt_reg <= wb_dat_i(StepCnt_reg'RANGE);
when others =>
null; -- Nothing to do for other addresses
end case;
end if; -- if wb_we_i='1'
end if; -- if wb_cyc_i='1' and wb_stb_i='1'
end if; -- if ack_i='0'
end if; -- if wb_rst_i='1'
end if; -- if rising_edge(wb_clk_i)
end process;
-- Prescaler
Prescaler:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if(wb_rst_i='1') then
PrescaleCnt <= (others => '0');
else
if (Control_reg(8)='1') then
if (PrescaleCnt=Timebase_reg) then
PrescaleCnt <= "0000000000000001";
else
PrescaleCnt <= PrescaleCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Half period counter
Halfperiod:process(wb_clk_i,prescale_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
HalfPeriodCnt <= (others => '0');
elsif (PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
if (HalfPeriodCnt=('0'&Period_reg(15 downto 1))) then
HalfPeriodCnt <= "0000000000000001";
else
HalfPeriodCnt <= HalfPeriodCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Step output
Step_out:process(wb_clk_i,halfperiod_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
step_o <= '1';
Steps_reg <= (others => '0');
elsif (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
step_o <= not step_o;
if (step_o = '1') then
Steps_reg <= Steps_reg+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Stepper interrupt
Int_out:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
irq_o <= '0';
if (wb_rst_i='1') then
irq_o <= '0';
else
--elsif (wb_clk_i='1' and wb_clk_i'event) then
case (Control_reg(6 downto 5)) is
when "01" =>
--if (halfperiod_o='1') then
if (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
irq_o <= '1';
end if;
when "10" =>
if (Control_reg(14)='1') then
irq_o <= '1';
end if;
when "11" =>
if (Steps_reg = StepCnt_reg) then
irq_o <= '1';
end if;
when others =>
--irq_o <= '0';
end case;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
end rtl;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/papilio_stepper.vhd
|
13
|
7399
|
--**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget Factory (www.gadgetfactory.net)
-- This work is licensed under the Creative Commons Attribution 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
-- use work.zpuino_config.all;
-- use work.zpu_config.all;
-- use work.zpupkg.all;
entity papilio_stepper is
Generic (
timebase_g : std_logic_vector(15 downto 0) := (others => '0');
period_g : std_logic_vector(15 downto 0) := (others => '0')
);
port (
wb_clk_i: in std_logic; -- Wishbone clock
wb_rst_i: in std_logic; -- Wishbone reset (synchronous)
wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: in std_logic; -- Wishbone write enable signal
wb_cyc_i: in std_logic; -- Wishbone cycle signal
wb_stb_i: in std_logic; -- Wishbone strobe signal
wb_ack_o: out std_logic; -- Wishbone acknowledge out signal
-- External connections
st_home : in std_logic;
st_dir : out std_logic;
st_ms2 : out std_logic;
st_ms1 : out std_logic;
st_rst : out std_logic;
st_step : out std_logic;
st_enable : out std_logic;
st_sleep : out std_logic;
-- IRQ
st_irq : out std_logic
);
end entity papilio_stepper;
architecture rtl of papilio_stepper is
signal prescale_o : std_logic;
signal halfperiod_o : std_logic;
signal step_o : std_logic;
signal irq_o : std_logic;
signal Control_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Timebase_reg : std_logic_vector(15 downto 0) := timebase_g;
signal Period_reg : std_logic_vector(15 downto 0) := period_g;
signal StepCnt_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Steps_reg : std_logic_vector(15 downto 0) := (others => '0');
signal PrescaleCnt : std_logic_vector(15 downto 0);
signal HalfPeriodCnt : std_logic_vector(15 downto 0);
signal ack_i: std_logic; -- Internal ACK signal (flip flop)
begin
-- This example uses fully synchronous outputs.
-- General Output signals
st_dir <= Control_reg(3);
st_ms2 <= Control_reg(1);
st_ms1 <= Control_reg(0);
st_rst <= Control_reg(4);
st_step <= step_o;
st_sleep <= Control_reg(7);
st_enable <= not Control_reg(8);
st_irq <= irq_o;
wb_ack_o <= ack_i; -- Tie ACK output to our flip flop
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
-- Always set output data on rising edge, even if reset is set.
Control_reg(14) <= st_home;
Control_reg(15) <= irq_o;
wb_dat_o <= (others => 'X'); -- Return undefined by omission
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(Control_reg'RANGE) <= Control_reg;
when "001" =>
wb_dat_o(Timebase_reg'RANGE) <= Timebase_reg;
when "010" =>
wb_dat_o(Period_reg'RANGE) <= Period_reg;
when "011" =>
wb_dat_o(StepCnt_reg'RANGE) <= StepCnt_reg;
when "100" =>
wb_dat_o(Steps_reg'RANGE) <= Steps_reg;
when others =>
end case;
ack_i <= '0'; -- Reset ACK value by default
if wb_rst_i='1' then
Control_reg <= "0000000010010000";
Timebase_reg <= timebase_g;
Period_reg <= period_g;
StepCnt_reg <= (others => '0');
else -- Not reset
-- See if we did not acknowledged a cycle, otherwise we need to ignore
-- the apparent request, because wishbone signals are still set
if ack_i='0' then
-- Check if someone is accessing
if wb_cyc_i='1' and wb_stb_i='1' then
ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above.
if wb_we_i='1' then
-- It's a write. See for which register based on address
case wb_adr_i(4 downto 2) is
when "000" =>
Control_reg(8 downto 0) <= wb_dat_i(8 downto 0); -- Set register
when "001" =>
Timebase_reg <= wb_dat_i(Timebase_reg'RANGE);
when "010" =>
Period_reg <= wb_dat_i(Period_reg'RANGE);
when "011" =>
StepCnt_reg <= wb_dat_i(StepCnt_reg'RANGE);
when others =>
null; -- Nothing to do for other addresses
end case;
end if; -- if wb_we_i='1'
end if; -- if wb_cyc_i='1' and wb_stb_i='1'
end if; -- if ack_i='0'
end if; -- if wb_rst_i='1'
end if; -- if rising_edge(wb_clk_i)
end process;
-- Prescaler
Prescaler:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if(wb_rst_i='1') then
PrescaleCnt <= (others => '0');
else
if (Control_reg(8)='1') then
if (PrescaleCnt=Timebase_reg) then
PrescaleCnt <= "0000000000000001";
else
PrescaleCnt <= PrescaleCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Half period counter
Halfperiod:process(wb_clk_i,prescale_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
HalfPeriodCnt <= (others => '0');
elsif (PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
if (HalfPeriodCnt=('0'&Period_reg(15 downto 1))) then
HalfPeriodCnt <= "0000000000000001";
else
HalfPeriodCnt <= HalfPeriodCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Step output
Step_out:process(wb_clk_i,halfperiod_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
step_o <= '1';
Steps_reg <= (others => '0');
elsif (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
step_o <= not step_o;
if (step_o = '1') then
Steps_reg <= Steps_reg+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Stepper interrupt
Int_out:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
irq_o <= '0';
if (wb_rst_i='1') then
irq_o <= '0';
else
--elsif (wb_clk_i='1' and wb_clk_i'event) then
case (Control_reg(6 downto 5)) is
when "01" =>
--if (halfperiod_o='1') then
if (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
irq_o <= '1';
end if;
when "10" =>
if (Control_reg(14)='1') then
irq_o <= '1';
end if;
when "11" =>
if (Steps_reg = StepCnt_reg) then
irq_o <= '1';
end if;
when others =>
--irq_o <= '0';
end case;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
end rtl;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd
|
13
|
8035
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_UART is
generic (
bits: integer := 4
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
enabled: out std_logic; --An output that is active high when the UART is not in a reset state
tx: out std_logic; --UART Transmit pin
rx: in std_logic --UART Receive pin
);
end entity COMM_zpuino_wb_UART;
architecture behave of COMM_zpuino_wb_UART is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd
|
13
|
8035
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_UART is
generic (
bits: integer := 4
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
enabled: out std_logic; --An output that is active high when the UART is not in a reset state
tx: out std_logic; --UART Transmit pin
rx: in std_logic --UART Receive pin
);
end entity COMM_zpuino_wb_UART;
architecture behave of COMM_zpuino_wb_UART is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd
|
13
|
8035
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_UART is
generic (
bits: integer := 4
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
enabled: out std_logic; --An output that is active high when the UART is not in a reset state
tx: out std_logic; --UART Transmit pin
rx: in std_logic --UART Receive pin
);
end entity COMM_zpuino_wb_UART;
architecture behave of COMM_zpuino_wb_UART is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Benchy/rle.vhd
|
13
|
7423
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Benchy/rle.vhd
|
13
|
7423
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/wb_rom_ram_hyperion.vhd
|
13
|
6196
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram_hyperion is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram_hyperion;
architecture behave of wb_rom_ram_hyperion is
component dualport_ram_hyperion is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram_hyperion;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram_hyperion
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/zpuino_gpio.vhd
|
13
|
8192
|
--
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end entity zpuino_gpio;
architecture behave of zpuino_gpio is
signal gpio_q: std_logic_vector(127 downto 0); -- GPIO output data FFs
signal gpio_tris_q: std_logic_vector(127 downto 0); -- Tristate FFs
signal ppspin_q: std_logic_vector(127 downto 0); -- SPP pin mode FFs
subtype input_number is integer range 0 to 127;
type mapper_q_type is array(0 to 127) of input_number;
signal input_mapper_q: mapper_q_type; -- Mapper for output pins (input data)
signal output_mapper_q: mapper_q_type; -- Mapper for input pins (output data)
signal gpio_r_i: std_logic_vector(127 downto 0);
signal gpio_tris_r_i: std_logic_vector(127 downto 0);
signal gpio_i_q: std_logic_vector(127 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
gpio_t <= gpio_tris_q(gpio_count-1 downto 0);
-- Generate muxers for output.
tgen: for i in 0 to gpio_count-1 generate
process( wb_clk_i )
begin
if rising_edge(wb_clk_i) then -- synchronous output
-- Enforce RST on gpio_o
if wb_rst_i='1' then
gpio_o(i)<='1';
else
if ppspin_q(i)='1' and spp_cap_out(i)='1' then
gpio_o(i) <= spp_data( input_mapper_q(i));
else
gpio_o(i) <= gpio_q(i);
end if;
end if;
end if;
end process;
end generate;
-- Generate muxers for input
spprgen: for i in 0 to gpio_count-1 generate
gpio_i_q(i) <= gpio_i(i) when spp_cap_in(i)='1' else DontCareValue;
process( gpio_i_q(i), output_mapper_q(i) )
begin
spp_read(i) <= gpio_i_q( output_mapper_q(i) );
end process;
end generate;
ilink1: for i in 0 to gpio_count-1 generate
gpio_r_i(i) <= gpio_i(i);
gpio_tris_r_i(i) <= gpio_tris_q(i);
end generate;
ilink2: for i in gpio_count to 127 generate
gpio_r_i(i) <= DontCareValue;
gpio_tris_r_i(i) <= DontCareValue;
end generate;
process(wb_adr_i,gpio_r_i,gpio_tris_r_i,ppspin_q)
begin
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_r_i(127 downto 96);
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_tris_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_tris_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_tris_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_tris_r_i(127 downto 96);
when others =>
end case;
when "10" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= ppspin_q(31 downto 0);
when "01" =>
wb_dat_o <= ppspin_q(63 downto 32);
when "10" =>
wb_dat_o <= ppspin_q(95 downto 64);
when "11" =>
wb_dat_o <= ppspin_q(127 downto 96);
when others =>
end case;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
gpio_tris_q <= (others => '1');
ppspin_q <= (others => '0');
gpio_q <= (others => DontCareValue);
-- Default values for input/output mapper
--for i in 0 to 127 loop
-- input_mapper_q(i) <= 0;
-- output_mapper_q(i) <= 0;
--end loop;
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(10 downto 9) is
when "00" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_tris_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_tris_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_tris_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_tris_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "10" =>
if zpuino_pps_enabled then
case wb_adr_i(3 downto 2) is
when "00" =>
ppspin_q(31 downto 0) <= wb_dat_i;
when "01" =>
ppspin_q(63 downto 32) <= wb_dat_i;
when "10" =>
ppspin_q(95 downto 64) <= wb_dat_i;
when "11" =>
ppspin_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
if zpuino_pps_enabled then
input_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when "10" =>
if zpuino_pps_enabled then
output_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_gpio.vhd
|
13
|
8192
|
--
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end entity zpuino_gpio;
architecture behave of zpuino_gpio is
signal gpio_q: std_logic_vector(127 downto 0); -- GPIO output data FFs
signal gpio_tris_q: std_logic_vector(127 downto 0); -- Tristate FFs
signal ppspin_q: std_logic_vector(127 downto 0); -- SPP pin mode FFs
subtype input_number is integer range 0 to 127;
type mapper_q_type is array(0 to 127) of input_number;
signal input_mapper_q: mapper_q_type; -- Mapper for output pins (input data)
signal output_mapper_q: mapper_q_type; -- Mapper for input pins (output data)
signal gpio_r_i: std_logic_vector(127 downto 0);
signal gpio_tris_r_i: std_logic_vector(127 downto 0);
signal gpio_i_q: std_logic_vector(127 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
gpio_t <= gpio_tris_q(gpio_count-1 downto 0);
-- Generate muxers for output.
tgen: for i in 0 to gpio_count-1 generate
process( wb_clk_i )
begin
if rising_edge(wb_clk_i) then -- synchronous output
-- Enforce RST on gpio_o
if wb_rst_i='1' then
gpio_o(i)<='1';
else
if ppspin_q(i)='1' and spp_cap_out(i)='1' then
gpio_o(i) <= spp_data( input_mapper_q(i));
else
gpio_o(i) <= gpio_q(i);
end if;
end if;
end if;
end process;
end generate;
-- Generate muxers for input
spprgen: for i in 0 to gpio_count-1 generate
gpio_i_q(i) <= gpio_i(i) when spp_cap_in(i)='1' else DontCareValue;
process( gpio_i_q(i), output_mapper_q(i) )
begin
spp_read(i) <= gpio_i_q( output_mapper_q(i) );
end process;
end generate;
ilink1: for i in 0 to gpio_count-1 generate
gpio_r_i(i) <= gpio_i(i);
gpio_tris_r_i(i) <= gpio_tris_q(i);
end generate;
ilink2: for i in gpio_count to 127 generate
gpio_r_i(i) <= DontCareValue;
gpio_tris_r_i(i) <= DontCareValue;
end generate;
process(wb_adr_i,gpio_r_i,gpio_tris_r_i,ppspin_q)
begin
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_r_i(127 downto 96);
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_tris_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_tris_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_tris_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_tris_r_i(127 downto 96);
when others =>
end case;
when "10" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= ppspin_q(31 downto 0);
when "01" =>
wb_dat_o <= ppspin_q(63 downto 32);
when "10" =>
wb_dat_o <= ppspin_q(95 downto 64);
when "11" =>
wb_dat_o <= ppspin_q(127 downto 96);
when others =>
end case;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
gpio_tris_q <= (others => '1');
ppspin_q <= (others => '0');
gpio_q <= (others => DontCareValue);
-- Default values for input/output mapper
--for i in 0 to 127 loop
-- input_mapper_q(i) <= 0;
-- output_mapper_q(i) <= 0;
--end loop;
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(10 downto 9) is
when "00" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_tris_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_tris_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_tris_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_tris_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "10" =>
if zpuino_pps_enabled then
case wb_adr_i(3 downto 2) is
when "00" =>
ppspin_q(31 downto 0) <= wb_dat_i;
when "01" =>
ppspin_q(63 downto 32) <= wb_dat_i;
when "10" =>
ppspin_q(95 downto 64) <= wb_dat_i;
when "11" =>
ppspin_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
if zpuino_pps_enabled then
input_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when "10" =>
if zpuino_pps_enabled then
output_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
ZPUino_miniSpartan6_plus/ipcore_dir/shifter.vhd
|
14
|
3771
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lshifter is
generic (
stages: integer := 3
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end lshifter;
architecture behave of lshifter is
subtype word is signed(63 downto 0);
type mregtype is array(0 to stages-1) of word;
signal rq: mregtype;
signal d: std_logic_vector(0 to stages -1);
begin
process(clk,inputA,inputB)
variable r: signed(63 downto 0);
variable idx: signed(31 downto 0);
begin
if rising_edge(clk) then
if rst='1' then
done <= '0';
else
d <= (others =>'0');
if enable='1' then
if multorshift='1' then
idx := signed(inputB);
else
case inputB(4 downto 0) is
when "00000" => idx := "00000000000000000000000000000001";
when "00001" => idx := "00000000000000000000000000000010";
when "00010" => idx := "00000000000000000000000000000100";
when "00011" => idx := "00000000000000000000000000001000";
when "00100" => idx := "00000000000000000000000000010000";
when "00101" => idx := "00000000000000000000000000100000";
when "00110" => idx := "00000000000000000000000001000000";
when "00111" => idx := "00000000000000000000000010000000";
when "01000" => idx := "00000000000000000000000100000000";
when "01001" => idx := "00000000000000000000001000000000";
when "01010" => idx := "00000000000000000000010000000000";
when "01011" => idx := "00000000000000000000100000000000";
when "01100" => idx := "00000000000000000001000000000000";
when "01101" => idx := "00000000000000000010000000000000";
when "01110" => idx := "00000000000000000100000000000000";
when "01111" => idx := "00000000000000001000000000000000";
when "10000" => idx := "00000000000000010000000000000000";
when "10001" => idx := "00000000000000100000000000000000";
when "10010" => idx := "00000000000001000000000000000000";
when "10011" => idx := "00000000000010000000000000000000";
when "10100" => idx := "00000000000100000000000000000000";
when "10101" => idx := "00000000001000000000000000000000";
when "10110" => idx := "00000000010000000000000000000000";
when "10111" => idx := "00000000100000000000000000000000";
when "11000" => idx := "00000001000000000000000000000000";
when "11001" => idx := "00000010000000000000000000000000";
when "11010" => idx := "00000100000000000000000000000000";
when "11011" => idx := "00001000000000000000000000000000";
when "11100" => idx := "00010000000000000000000000000000";
when "11101" => idx := "00100000000000000000000000000000";
when "11110" => idx := "01000000000000000000000000000000";
when "11111" => idx := "10000000000000000000000000000000";
when others =>
end case;
end if;
r := signed(inputA) * idx;
rq(0) <= r(63 downto 0);
d(0) <= '1';
for i in 1 to stages-1 loop
rq(i) <= rq(i-1);
d(i) <= d(i-1);
end loop;
done <= d(stages-1);
output <= std_logic_vector(rq(stages-1));
else
done <= '0';
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/shifter.vhd
|
14
|
3771
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lshifter is
generic (
stages: integer := 3
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end lshifter;
architecture behave of lshifter is
subtype word is signed(63 downto 0);
type mregtype is array(0 to stages-1) of word;
signal rq: mregtype;
signal d: std_logic_vector(0 to stages -1);
begin
process(clk,inputA,inputB)
variable r: signed(63 downto 0);
variable idx: signed(31 downto 0);
begin
if rising_edge(clk) then
if rst='1' then
done <= '0';
else
d <= (others =>'0');
if enable='1' then
if multorshift='1' then
idx := signed(inputB);
else
case inputB(4 downto 0) is
when "00000" => idx := "00000000000000000000000000000001";
when "00001" => idx := "00000000000000000000000000000010";
when "00010" => idx := "00000000000000000000000000000100";
when "00011" => idx := "00000000000000000000000000001000";
when "00100" => idx := "00000000000000000000000000010000";
when "00101" => idx := "00000000000000000000000000100000";
when "00110" => idx := "00000000000000000000000001000000";
when "00111" => idx := "00000000000000000000000010000000";
when "01000" => idx := "00000000000000000000000100000000";
when "01001" => idx := "00000000000000000000001000000000";
when "01010" => idx := "00000000000000000000010000000000";
when "01011" => idx := "00000000000000000000100000000000";
when "01100" => idx := "00000000000000000001000000000000";
when "01101" => idx := "00000000000000000010000000000000";
when "01110" => idx := "00000000000000000100000000000000";
when "01111" => idx := "00000000000000001000000000000000";
when "10000" => idx := "00000000000000010000000000000000";
when "10001" => idx := "00000000000000100000000000000000";
when "10010" => idx := "00000000000001000000000000000000";
when "10011" => idx := "00000000000010000000000000000000";
when "10100" => idx := "00000000000100000000000000000000";
when "10101" => idx := "00000000001000000000000000000000";
when "10110" => idx := "00000000010000000000000000000000";
when "10111" => idx := "00000000100000000000000000000000";
when "11000" => idx := "00000001000000000000000000000000";
when "11001" => idx := "00000010000000000000000000000000";
when "11010" => idx := "00000100000000000000000000000000";
when "11011" => idx := "00001000000000000000000000000000";
when "11100" => idx := "00010000000000000000000000000000";
when "11101" => idx := "00100000000000000000000000000000";
when "11110" => idx := "01000000000000000000000000000000";
when "11111" => idx := "10000000000000000000000000000000";
when others =>
end case;
end if;
r := signed(inputA) * idx;
rq(0) <= r(63 downto 0);
d(0) <= '1';
for i in 1 to stages-1 loop
rq(i) <= rq(i-1);
d(i) <= d(i-1);
end loop;
done <= d(stages-1);
output <= std_logic_vector(rq(stages-1));
else
done <= '0';
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config.vhd
|
13
|
2676
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 14;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd
|
13
|
5860
|
-- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___800.000______0.000______50.0______170.542____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to800_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to800_pll;
architecture xilinx of clk_32to800_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to800_pll,clk_wiz_v3_6,{component_name=clk_32to800_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd
|
13
|
5860
|
-- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___800.000______0.000______50.0______170.542____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to800_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to800_pll;
architecture xilinx of clk_32to800_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to800_pll,clk_wiz_v3_6,{component_name=clk_32to800_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/wb_master_np_to_slave_p.vhd
|
13
|
2103
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end entity wb_master_np_to_slave_p;
architecture behave of wb_master_np_to_slave_p is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if m_wb_cyc_i='1' and m_wb_stb_i='1' and s_wb_stall_i='0' then
state <= wait_for_ack;
end if;
when wait_for_ack =>
if s_wb_ack_i='1' then
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
s_wb_stb_o <= m_wb_stb_i when state=idle else '0';
s_wb_dat_o <= m_wb_dat_i;
s_wb_adr_o <= m_wb_adr_i;
s_wb_sel_o <= m_wb_sel_i;
s_wb_cti_o <= m_wb_cti_i;
s_wb_we_o <= m_wb_we_i;
s_wb_cyc_o <= m_wb_cyc_i;
m_wb_dat_o <= s_wb_dat_i;
m_wb_ack_o <= s_wb_ack_i;
end behave;
|
mit
|
chcbaram/FPGA
|
ZPUino_miniSpartan6_plus/ipcore_dir/I2C/i2c_master_top.vhdl
|
1
|
27032
|
------------------------------------------------------------------------------
---- ----
---- I2C Master Core (Top Level) ----
---- ----
---- Internal file, can't be downloaded. ----
---- Based on code from: http://www.opencores.org/projects/i2c/ ----
---- ----
---- Description: ----
---- I2C master peripheral for the Wishbone bus. ----
---- Top level of the core. ----
---- I added various generics to customize the core: ----
---- * DEBUG enable debug registers ----
---- * MUX_BETTER true if using MUX is better than using tri-states ----
---- * FULL_SYNC true if you need full synchronous behavior, ----
---- introduces 1 WS ----
---- * FIXED_PRER assigning a value removes the PRER and uses it as ----
---- pre-scaler ----
---- * USE_IEN false if interrupts are always enabled (masked in ----
---- another component) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Richard Herveille, [email protected] ----
---- - Salvador E. Tropea, salvador en inti gov ar (additions & optim.)----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnolog Industrial ----
---- Copyright (c) 2000 Richard Herveille <[email protected]> ----
---- ----
---- Covered by the GPL license. ----
---- ----
---- Original distribution policy: ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_MasterTop(Structural) (Entity and architecture)----
---- File name: i2c_master_top.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- c.stdio_h ----
---- Target FPGA: Spartan II (XC2S100-5-PQ208) ----
---- Language: VHDL ----
---- Wishbone: SLAVE (rev B.2) ----
---- Synthesis tools: Xilinx Release 6.2.03i - xst G.31a ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: i2c_master_top.vhdl,v 1.12 2006/04/18 13:37:08 salvador Exp $
--
-- $Date: 2006/04/18 13:37:08 $
-- $Revision: 1.12 $
-- $Author: salvador $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_top.vhdl,v $
-- Revision 1.12 2006/04/18 13:37:08 salvador
-- * Modificado: Peques retoques al indentado.
--
-- Revision 1.11 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.10 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.9 2005/05/18 14:50:19 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
-- Revision 1.8 2005/05/11 22:39:18 salvador
-- * Modificado: Pasado por el bakalint 0.3.5.
--
-- Revision 1.7 2005/03/29 20:35:44 salvador
-- * Modificado: Encerrado con "translate off/on" el cigo de simulaci para
-- que el XST no moleste.
-- * Agregado: Un generic para que las interrupciones esten siempre
-- habilitadas.
-- * Agregado: Default para wb_cyc_i de manera tal que no sea necesario
-- conectarlo.
-- * Modificado: Para ahorrar algunos F/F en registros que tienen bits sin
-- usar. A consecuencia de esto el bit "iack" se corri
--
-- Revision 1.6 2005/03/10 19:40:07 salvador
-- * Modificado: Para usar "rising_edge" que hace m legible el cigo.
-- * Agregado: MUX_BETTER para elegir que use muxs en lugar de tri-states.
-- Por defecto es falso con lo que ahorra unos 12 slice.
-- * Agregado: FULL_SYNC para lograr el comportamiento original con 1 WS.
-- * Agregado: FIXED_PRER con lo que se puede fijar el valor del prescaler lo
-- que ahorra unos 11 slice.
-- * Modificado: Los case de lectura/escritura de los registros por if/elsif
-- que permite controlar mejor el uso de los generic.
-- * Modificado: El testbench para que soporte FIXED_PRER.
--
-- Revision 1.5 2005/03/09 20:32:24 salvador
-- * Arreglado: Colisi entre los nombres de las constantes y las seles.
-- XST tiene un bug que lo hace volverse loco con esto.
--
-- Revision 1.4 2005/03/09 19:24:32 salvador
-- * Agregado: Script para generar un .h y un .inc a partir del package
-- exportando los neros de los registros.
-- * Modificado: Para que los registros PRER_LO/HI no sean 0 y 1 sino 3 y 4.
-- * Corregido: El core para no usar "magics" sino los valores definidos en
-- el package para los neros de registros.
-- * Verificado con el testbench del core y del PIC.
--
-- Revision 1.3 2005/03/09 17:41:16 salvador
-- * Agregado: Hojas de datos del 24LC02B.
-- * Modificado: Reemplazo de Report por Assert porque las herramientas de
-- Xilinx no lo soportan.
-- * Modificado: Comentado los printf en core porque no tengo el equivalente
-- para Xilinx.
-- * Corregido: El TB de la memoria no contestaba ACK luego de la escritura.
-- Ahora si y adem el TB verifica que no falten ACKs.
--
-- Revision 1.2 2005/03/08 20:42:40 salvador
-- * Corregido: El core I2C insertaba un estado de espera en el Wishbone,
-- eliminado. Al mismo tiempo la sel TIP estaba siendo generada con un F/F
-- en lugar de ser combinacional (no es necesario ya que CR se borra con RST).
-- Ambos cambios hacen que el core use so 1 clock para Wishbone y reducen
-- en 2 F/F el uso (estimado, no verificado).
-- * Agregado: Generic DEBUG al core y que cuando esthabilitado informe las
-- lecturas y escrituras Wishbone.
--
-- Revision 1.1 2005/03/08 15:57:36 salvador
-- * Movido al repositorio CVS.
-- * Agregado: TestBench en VHDL.
--
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.I2C_Master.all;
--synopsys translate off
library c;
use c.stdio_h.all;
--synopsys translate on
entity I2C_MasterTop is
generic(
ARST_LVL : std_logic := '0'; -- asynchronous reset level
DEBUG : boolean := false; -- enable debug registers
MUX_BETTER : boolean := false; -- true if using MUX is better than using tri-states
FULL_SYNC : boolean := false; -- true if you need full synchronous behavior, introduces 1 WS
FIXED_PRER : integer := -1; -- assigning a value removes the PRER and uses it as pre-scaler
USE_IEN : boolean := true -- false if interrupts are always enabled (masked in another component)
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic:='1'; -- Valid bus cycle input. Optional. Needed?
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity I2C_MasterTop;
architecture Structural of I2C_MasterTop is
component I2C_MasterByteCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nreset_i : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start_i,
stop_i,
read_i,
write_i,
ack_in_i : in std_logic;
din_i : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack_o : out std_logic;
ack_out_o : out std_logic;
i2c_busy_o : out std_logic;
i2c_al_o : out std_logic;
dout_o : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end component I2C_MasterByteCtrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 6); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 2); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal irst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta : std_logic;
signal sto : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal ack : std_logic;
signal iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy_o : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al_o, al_o : std_logic; -- arbitration lost
begin
-- generate internal reset signal
irst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o_ws:
if FULL_SYNC generate
gen_ack_o:
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
end generate gen_ack_o_ws;
gen_ack_o:
if not(FULL_SYNC) generate
-- SET: The above code generates 1 WS in the Wishbone bus.
-- The following should be enough.
iack_o <= wb_cyc_i and wb_stb_i;
end generate gen_ack_o;
wb_ack_o <= iack_o;
-- end of acknowledge output signal
-- generate wishbone write access signal
wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
-- pre-scaler register
-- when FIXED_PRER is assigned we use it as divisor
fixed_prer_assign:
if not(FIXED_PRER=-1) generate
prer <= to_unsigned(FIXED_PRER,16);
end generate fixed_prer_assign;
-- generate pre-scaler register
prer_assign:
if FIXED_PRER=-1 generate
gen_prer:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
prer <= (others => '1');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
elsif (wb_wacc = '1') then
if wb_adr_i=I2C_UPRER_LO then
prer(7 downto 0) <= unsigned(wb_dat_i);
elsif wb_adr_i=I2C_UPRER_HI then
prer(15 downto 8) <= unsigned(wb_dat_i);
end if;
end if;
end if;
end process gen_prer;
end generate prer_assign;
-- end of pre-scaler register
-------------------------------------------------------------------------
-- Register decoding. Two versions one for tri-states (less cells for
-- FPGAs) and another using muxs.
-------------------------------------------------------------------------
reg_decoder_bus:
if not(MUX_BETTER) generate
wb_dat_o <= std_logic_vector(prer( 7 downto 0))
when wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1
else (others => 'Z');
wb_dat_o <= std_logic_vector(prer(15 downto 8))
when wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1
else (others => 'Z');
wb_dat_o(ctr'range) <= ctr
when wb_adr_i=I2C_UCTR
else (others => 'Z');
wb_dat_o <= rxr
when wb_adr_i=I2C_URXR
else (others => 'Z');
wb_dat_o <= sr(7 downto 5) & "000" & sr(1 downto 0)
when wb_adr_i=I2C_USR
else (others => 'Z');
wb_dat_o <= txr
when wb_adr_i=I2C_UTXR_R and DEBUG
else (others => 'Z');
wb_dat_o(cr'range) <= cr
when wb_adr_i=I2C_UCR_R and DEBUG
else (others => 'Z');
end generate reg_decoder_bus;
reg_decoder_mux:
if MUX_BETTER generate
-- assign wb_dat_o
assign_dato:
process(wb_clk_i)
variable dat_o : std_logic_vector(7 downto 0);
begin
if rising_edge(wb_clk_i) then
dat_o := (others => '0');
if wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1 then
dat_o := std_logic_vector(prer(7 downto 0));
elsif wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1 then
dat_o := std_logic_vector(prer(15 downto 8));
elsif wb_adr_i=I2C_UCTR then
dat_o(ctr'range) := ctr;
elsif wb_adr_i=I2C_URXR then
dat_o := rxr; -- write is transmit register TxR
elsif wb_adr_i=I2C_USR then
dat_o := sr(7 downto 5) & "000" & sr(1 downto 0); -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
elsif wb_adr_i=I2C_UTXR_R and DEBUG then
dat_o := txr;
elsif wb_adr_i=I2C_UCR_R and DEBUG then
dat_o(cr'range) := cr;
elsif wb_adr_i=I2C_UXXX_R and DEBUG then
dat_o := (others => '0');
else
dat_o := (others => 'X'); -- for simulation only
end if;
end if;
wb_dat_o <= dat_o;
--synopsys translate off
if DEBUG and wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' then
printf("Reading register %d ",to_integer(unsigned(wb_adr_i)));
printf("(=0x%X)\n",to_integer(unsigned(dat_o)));
end if;
--synopsys translate on
end process assign_dato;
end generate reg_decoder_mux;
-- end of register decoding
-- generate registers (CR, SR see below)
gen_regs:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
ctr <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
if wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1 then
null; --write to CR, avoid executing the others clause
elsif wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1 then
null; --write to PRER, avoid executing the others clause
elsif wb_adr_i=I2C_UCTR then
ctr <= wb_dat_i(ctr'range);
elsif wb_adr_i=I2C_UTXR then
txr <= wb_dat_i;
elsif wb_adr_i=I2C_UCR then
null; --write to CR, avoid executing the others clause
else -- illegal cases, for simulation only
--synopsys translate off
assert false
report "Illegal write address, setting all registers to unknown."
severity failure;
--synopsys translate on
ctr <= (others => 'X');
txr <= (others => 'X');
end if;
--synopsys translate off
if DEBUG then
printf("Writing register %d ",to_integer(unsigned(wb_adr_i)));
printf(" with 0x%X\n",to_integer(unsigned(wb_dat_i)));
end if;
--synopsys translate on
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
cr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = I2C_UCR) ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i(cr'range);
end if;
else
if (done = '1' or i2c_al_o= '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(2);
-- TIP bit generation
gen_tip:
if not(FULL_SYNC) generate
-- SET: tip is just (rd or wr), the reset signals affects cr, we don't
-- need to generate another F/F for it.
tip <= (rd or wr);
end generate gen_tip;
gen_tip_sync:
if FULL_SYNC generate
gen_tip_proc:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
tip <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
tip <= '0';
else
tip <= (rd or wr);
end if;
end if;
end process gen_tip_proc;
end generate gen_tip_sync;
-- end of TIP bit generation
-- decode control register
core_en <= ctr(7);
ien <= ctr(6) when USE_IEN else '1';
-- hookup byte controller block
byte_ctrl: I2C_MasterByteCtrl
port map(
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
nreset_i => irst_i,
ena_i => core_en,
clk_cnt_i=> prer,
start_i => sta,
stop_i => sto,
read_i => rd,
write_i => wr,
ack_in_i => ack,
i2c_busy_o=> i2c_busy_o,
i2c_al_o => i2c_al_o,
din_i => txr,
cmd_ack_o=> done,
ack_out_o=> irxack,
dout_o => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen_o=> scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen_o=> sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block:
block
begin
-- generate status register bits
gen_sr_bits:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
al_o <= '0';
rxack <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al_o <= '0';
rxack <= '0';
irq_flag <= '0';
else
al_o <= i2c_al_o or (al_o and not sta);
rxack <= irxack;
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al_o or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
wb_inta_o <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy_o;
sr(5) <= al_o;
--sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block st_irq_block;
end architecture Structural;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Benchy/BRAM8k36bit.vhd
|
13
|
2520
|
--
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BRAM8k36bit is
generic (
address_bits: integer := 13;
data_bits: integer := 36
);
port (
clka: in std_logic;
-- ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dina: in std_logic_vector(data_bits-1 downto 0);
douta: out std_logic_vector(data_bits-1 downto 0)
);
end entity BRAM8k36bit;
architecture behave of BRAM8k36bit is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
signal ena : std_logic;
begin
ena <= '1';
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dina;
end if;
douta <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Benchy/BRAM8k36bit.vhd
|
13
|
2520
|
--
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BRAM8k36bit is
generic (
address_bits: integer := 13;
data_bits: integer := 36
);
port (
clka: in std_logic;
-- ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dina: in std_logic_vector(data_bits-1 downto 0);
douta: out std_logic_vector(data_bits-1 downto 0)
);
end entity BRAM8k36bit;
architecture behave of BRAM8k36bit is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
signal ena : std_logic;
begin
ena <= '1';
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dina;
end if;
douta <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Benchy/controller.vhd
|
13
|
6873
|
----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end controller;
architecture behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic;
signal output_i : std_logic_vector (31 downto 0);
begin
rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0';
ctr_delay <=
"00" & x"0000" when trig_delay = "01" else
"11" & x"fffe" when trig_delay = "10" else
"11" & x"fffd";
-- synchronization and reset logic
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= SAMPLE;
else
state <= nstate;
counter <= ncounter;
end if;
-- register outputs
output <= output_i;
memoryOut <= la_input;
memoryWrite <= memoryWrite_i;
memoryRead <= memoryRead_i;
send_i <= sendReg;
send <= sendReg;
rle_read <= rle_read_i;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy,
data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn)
begin
case state is
-- default mode: sample data from la_input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= ctr_delay;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if (counter = fwd & "00") or (abort = '1') then
ncounter <= (others => '1');
nstate <= READ;
else
if la_inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
if rle_busy = '1' then
ncounter <= counter;
nstate <= DATAWAIT;
rle_read_i <= '1';
else
ncounter <= (others => '0');
if rle_mode = '1' then
nstate <= RLE_POSTSCRIPT;
else
nstate <= SAMPLE;
end if;
rle_read_i <= '0';
end if;
memoryRead_i <= '0';
else
if rle_busy = '1' then
ncounter <= counter;
memoryRead_i <= '0';
else
ncounter <= counter + 1;
memoryRead_i <= '1';
end if;
nstate <= DATAWAIT;
rle_read_i <= '1';
end if;
memoryWrite_i <= '0';
sendReg <= '0';
output_i <= memoryIn;
when DATAWAIT =>
if data_ready = '1' then
nstate <= READWAIT;
sendReg <= '1';
else
nstate <= state;
sendReg <= '0';
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and send_i = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data
when RLE_POSTSCRIPT =>
if busy = '0' then
if counter = 5 then
sendReg <= '0';
ncounter <= (others => '0');
nstate <= SAMPLE;
output_i <= (others => '0');
elsif counter = 4 and send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= x"00000055";
elsif send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= (others => '0');
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd
|
26
|
7843
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd
|
26
|
7843
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd
|
26
|
7843
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd
|
26
|
7843
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/board_Papilio_One_250k/zpu_config.vhd
|
13
|
2676
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_250k/zpu_config.vhd
|
13
|
2676
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/board_Papilio_Pro/bootloader.vhd
|
13
|
13706
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity bootloader_dp_32;
architecture behave of bootloader_dp_32 is
subtype RAM_WORD is STD_LOGIC_VECTOR (31 downto 0);
type RAM_TABLE is array (0 to 1023) of RAM_WORD;
shared variable RAM: RAM_TABLE := RAM_TABLE'(
x"0b0b0b98",x"c0040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b98",x"a1040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fd0608",x"72830609",x"81058205",x"832b2a83",x"ffff0652",x"04000000",x"00000000",x"00000000",x"71fd0608",x"83ffff73",x"83060981",x"05820583",x"2b2b0906",x"7383ffff",x"0b0b0b0b",x"83a70400",x"72098105",x"72057373",x"09060906",x"73097306",x"070a8106",x"53510400",x"00000000",x"00000000",x"72722473",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71737109",x"71068106",x"30720a10",x"0a720a10",x"0a31050a",x"81065151",x"53510400",x"00000000",x"72722673",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"cc040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"720a722b",x"0a535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72729f06",x"0981050b",x"0b0b88af",x"05040000",x"00000000",x"00000000",x"00000000",x"00000000",x"72722aff",x"739f062a",x"0974090a",x"8106ff05",x"06075351",x"04000000",x"00000000",x"00000000",x"71715351",x"020d0406",x"73830609",x"81058205",x"832b0b2b",x"0772fc06",x"0c515104",x"00000000",x"72098105",x"72050970",x"81050906",x"0a810653",x"51040000",x"00000000",x"00000000",x"00000000",x"72098105",x"72050970",x"81050906",x"0a098106",x"53510400",x"00000000",x"00000000",x"00000000",x"71098105",x"52040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72720981",x"05055351",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097206",x"73730906",x"07535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fc0608",x"72830609",x"81058305",x"1010102a",x"81ff0652",x"04000000",x"00000000",x"00000000",x"71fc0608",x"0b0b0b9e",x"ec738306",x"10100508",x"060b0b0b",x"88b20400",x"00000000",x"00000000",x"0b0b0b89",x"80040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"e8040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097081",x"0509060a",x"8106ff05",x"70547106",x"73097274",x"05ff0506",x"07515151",x"04000000",x"72097081",x"0509060a",x"098106ff",x"05705471",x"06730972",x"7405ff05",x"06075151",x"51040000",x"05ff0504",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"810b0b0b",x"0b9fb40c",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71810552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"02840572",x"10100552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"717105ff",x"05715351",x"020d0400",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"81dd3f96",x"ba3f0400",x"00000000",x"00000000",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101053",x"51047381",x"ff067383",x"06098105",x"83051010",x"102b0772",x"fc060c51",x"51043c04",x"72728072",x"8106ff05",x"09720605",x"71105272",x"0a100a53",x"72ed3851",x"51535104",x"88088c08",x"90087575",x"99ed2d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90087575",x"99a92d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90088dff",x"2d900c8c",x"0c880c04",x"ff3d0d0b",x"0b0b9fc4",x"335170a6",x"389fc008",x"70085252",x"70802e92",x"3884129f",x"c00c702d",x"9fc00870",x"08525270",x"f038810b",x"0b0b0b9f",x"c434833d",x"0d040480",x"3d0d0b0b",x"0b9ff008",x"802e8e38",x"0b0b0b0b",x"800b802e",x"09810685",x"38823d0d",x"040b0b0b",x"9ff0510b",x"0b0bf5f8",x"3f823d0d",x"0404ff3d",x"0d80c480",x"80845271",x"0870822a",x"70810651",x"515170f3",x"38833d0d",x"04ff3d0d",x"80c48080",x"84527108",x"70812a70",x"81065151",x"5170f338",x"7382900a",x"0c833d0d",x"04fe3d0d",x"747080dc",x"8080880c",x"7081ff06",x"ff831154",x"51537181",x"268d3880",x"fd518aa9",x"2d72a032",x"51833972",x"518aa92d",x"843d0d04",x"803d0d83",x"ffff0b83",x"d00a0c80",x"fe518aa9",x"2d823d0d",x"04ff3d0d",x"83d00a08",x"70882a52",x"528ac92d",x"7181ff06",x"518ac92d",x"80fe518a",x"a92d833d",x"0d0482f6",x"ff0b80cc",x"8080880c",x"800b80cc",x"8080840c",x"9f0b8390",x"0a0c04ff",x"3d0d7370",x"08515180",x"c8808084",x"70087084",x"80800772",x"0c525283",x"3d0d04ff",x"3d0d80c8",x"80808470",x"0870fbff",x"ff06720c",x"5252833d",x"0d04a090",x"0ba0800c",x"9fc80ba0",x"840c98d9",x"2dff3d0d",x"73518b71",x"0c901152",x"98808072",x"0c80720c",x"700883ff",x"ff06880c",x"833d0d04",x"fa3d0d78",x"7a7dff1e",x"57575853",x"73ff2ea7",x"38805684",x"5275730c",x"72088818",x"0cff1252",x"71f33874",x"84167408",x"720cff16",x"56565273",x"ff2e0981",x"06dd3888",x"3d0d04f8",x"3d0d80c0",x"80808457",x"83d00a59",x"8be32d76",x"518c892d",x"9fc87088",x"08101098",x"80840571",x"70840553",x"0c5656fb",x"8084a1ad",x"750c9fa4",x"0b88170c",x"8070780c",x"770c7608",x"83ffff06",x"5683ffdf",x"800b8808",x"278338ff",x"3983ffff",x"790ca080",x"54880853",x"78527651",x"8ca82d76",x"518bc72d",x"78085574",x"762e8938",x"80c3518a",x"a92dff39",x"a0840855",x"74faa090",x"ae802e89",x"3880c251",x"8aa92dff",x"39900a70",x"0870ffbf",x"06720c56",x"568a8e2d",x"8bfa2dff",x"3d0d9fd4",x"0881119f",x"d40c5183",x"900a7008",x"70feff06",x"720c5252",x"833d0d04",x"803d0d8a",x"f82d7281",x"8007518a",x"c92d8b8d",x"2d823d0d",x"04fe3d0d",x"80c08080",x"84538be3",x"2d85730c",x"80730c72",x"087081ff",x"06745351",x"528bc72d",x"71880c84",x"3d0d04fc",x"3d0d7681",x"11338212",x"33718180",x"0a297184",x"80802905",x"83143370",x"82802912",x"84163352",x"7105a080",x"05861685",x"17335752",x"53535557",x"5553ff13",x"5372ff2e",x"91387370",x"81055533",x"52717570",x"81055734",x"e9398951",x"8e9c2d86",x"3d0d04f9",x"3d0d7957",x"80c08080",x"84568be3",x"2d811733",x"82183371",x"82802905",x"53537180",x"2e943885",x"17725553",x"72708105",x"5433760c",x"ff145473",x"f3388317",x"33841833",x"71828029",x"05565280",x"54737527",x"97387358",x"77760c73",x"17760853",x"53717334",x"81145474",x"7426ed38",x"75518bc7",x"2d8af82d",x"8184518a",x"c92d7488",x"2a518ac9",x"2d74518a",x"c92d8054",x"7375278f",x"38731770",x"3352528a",x"c92d8114",x"54ee398b",x"8d2d893d",x"0d04f93d",x"0d795680",x"c0808084",x"558be32d",x"86750c74",x"518bc72d",x"8be32d81",x"ad70760c",x"81173382",x"18337182",x"80290583",x"1933780c",x"84193378",x"0c851933",x"780c5953",x"53805473",x"7727b338",x"72587380",x"2e87388b",x"e32d7775",x"0c731686",x"1133760c",x"87113376",x"0c527451",x"8bc72d8e",x"b12d8808",x"81065271",x"f6388214",x"54767426",x"d1388be3",x"2d84750c",x"74518bc7",x"2d8af82d",x"8187518a",x"c92d8b8d",x"2d893d0d",x"04fc3d0d",x"76811133",x"82123371",x"902b7188",x"2b078314",x"33707207",x"882b8416",x"33710751",x"52535757",x"54528851",x"8e9c2d81",x"ff518aa9",x"2d80c480",x"80845372",x"0870812a",x"70810651",x"515271f3",x"38738480",x"800780c4",x"8080840c",x"863d0d04",x"fe3d0d8e",x"b12d8808",x"88088106",x"535371f3",x"388af82d",x"8183518a",x"c92d7251",x"8ac92d8b",x"8d2d843d",x"0d04fe3d",x"0d800b9f",x"d40c8af8",x"2d818151",x"8ac92d9f",x"a4538f52",x"72708105",x"5433518a",x"c92dff12",x"5271ff2e",x"098106ec",x"388b8d2d",x"843d0d04",x"fe3d0d80",x"0b9fd40c",x"8af82d81",x"82518ac9",x"2d80c080",x"8084528b",x"e32d81f9",x"0a0b80c0",x"80809c0c",x"71087252",x"538bc72d",x"729fdc0c",x"72902a51",x"8ac92d9f",x"dc08882a",x"518ac92d",x"9fdc0851",x"8ac92d8e",x"b12d8808",x"518ac92d",x"8b8d2d84",x"3d0d0480",x"3d0d810b",x"9fd80c80",x"0b83900a",x"0c85518e",x"9c2d823d",x"0d04803d",x"0d800b9f",x"d80c8bae",x"2d86518e",x"9c2d823d",x"0d04fd3d",x"0d80c080",x"8084548a",x"518e9c2d",x"8be32d9f",x"c8745253",x"8c892d72",x"88081010",x"98808405",x"71708405",x"530c52fb",x"8084a1ad",x"720c9fa4",x"0b88140c",x"73518bc7",x"2d8a8e2d",x"8bfa2dfc",x"3d0d80c0",x"80808470",x"52558bc7",x"2d8be32d",x"8b750c76",x"80c08080",x"940c8075",x"0ca08054",x"775383d0",x"0a527451",x"8ca82d74",x"518bc72d",x"8a8e2d8b",x"fa2dffab",x"3d0d800b",x"9fd80c80",x"0b9fd40c",x"800b8dff",x"0ba0800c",x"5780c480",x"80845584",x"80b3750c",x"80c88080",x"a453fbff",x"ff730870",x"7206750c",x"535480c8",x"80809470",x"08707606",x"720c5353",x"a8709aa5",x"71708405",x"530c9b82",x"710c539c",x"9b0b8812",x"0c9daa0b",x"8c120c94",x"bb0b9012",x"0c53880b",x"80d08080",x"840c80d0",x"0a538173",x"0c8bae2d",x"8288880b",x"80dc8080",x"840c81f2",x"0b900a0c",x"80c08080",x"84705252",x"8bc72d8b",x"e32d7151",x"8bc72d8b",x"e32d8472",x"0c71518b",x"c72d7677",x"7675933d",x"41415b5b",x"5b83d00a",x"5c780870",x"81065152",x"719d389f",x"d8085372",x"f0389fd4",x"085287e8",x"7227e638",x"727e0c72",x"83900a0c",x"98d12d82",x"900a0853",x"79802e81",x"b4387280",x"fe2e0981",x"0680f438",x"76802ec1",x"38807d78",x"58565a82",x"7727ffb5",x"3883ffff",x"7c0c79fe",x"18535379",x"72279838",x"80dc8080",x"88725558",x"72157033",x"790c5281",x"13537373",x"26f238ff",x"16751154",x"7505ff05",x"70337433",x"7072882b",x"077f0853",x"51555152",x"71732e09",x"8106feed",x"38743353",x"728a26fe",x"e4387210",x"109ef805",x"75527008",x"5152712d",x"fed33972",x"80fd2e09",x"81068638",x"815bfec5",x"3976829f",x"269e387a",x"802e8738",x"8073a032",x"545b80d7",x"3d7705fd",x"e0055272",x"72348117",x"57fea239",x"805afe9d",x"397280fe",x"2e098106",x"fe933879",x"5783ffff",x"7c0c8177",x"5c5afe85",x"39803d0d",x"88088c08",x"9008a080",x"0851702d",x"900c8c0c",x"8a0c810b",x"80d00a0c",x"823d0d04",x"ff3d0d98",x"fd2d8052",x"805194f2",x"2d833d0d",x"0483ffff",x"f80d8ce3",x"0483ffff",x"f80da088",x"04000000",x"00000000",x"00000000",x"00000000",x"820b80d0",x"8080900c",x"0b0b0b04",x"0083f00a",x"0b800ba0",x"80721208",x"720c8412",x"5271712e",x"ff05f238",x"028c050d",x"98f00400",x"00000000",x"00000000",x"00000000",x"00fb3d0d",x"77795555",x"80567575",x"24ab3880",x"74249d38",x"80537352",x"745180e1",x"3f880854",x"75802e85",x"38880830",x"5473880c",x"873d0d04",x"73307681",x"325754dc",x"39743055",x"81567380",x"25d238ec",x"39fa3d0d",x"787a5755",x"80577675",x"24a43875",x"9f2c5481",x"53757432",x"74315274",x"519b3f88",x"08547680",x"2e853888",x"08305473",x"880c883d",x"0d047430",x"558157d7",x"39fc3d0d",x"76785354",x"81538074",x"73265255",x"72802e98",x"3870802e",x"a9388072",x"24a43871",x"10731075",x"72265354",x"5272ea38",x"73517883",x"38745170",x"880c863d",x"0d047281",x"2a72812a",x"53537280",x"2ee63871",x"7426ef38",x"73723175",x"74077481",x"2a74812a",x"55555654",x"e539fc3d",x"0d767079",x"7b555555",x"558f7227",x"8c387275",x"07830651",x"70802ea7",x"38ff1252",x"71ff2e98",x"38727081",x"05543374",x"70810556",x"34ff1252",x"71ff2e09",x"8106ea38",x"74880c86",x"3d0d0474",x"51727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0cf01252",x"718f26c9",x"38837227",x"95387270",x"84055408",x"71708405",x"530cfc12",x"52718326",x"ed387054",x"ff8339fc",x"3d0d7679",x"71028c05",x"9f053357",x"55535583",x"72278a38",x"74830651",x"70802ea2",x"38ff1252",x"71ff2e93",x"38737370",x"81055534",x"ff125271",x"ff2e0981",x"06ef3874",x"880c863d",x"0d047474",x"882b7507",x"7071902b",x"07515451",x"8f7227a5",x"38727170",x"8405530c",x"72717084",x"05530c72",x"71708405",x"530c7271",x"70840553",x"0cf01252",x"718f26dd",x"38837227",x"90387271",x"70840553",x"0cfc1252",x"718326f2",x"387053ff",x"9039fb3d",x"0d777970",x"72078306",x"53545270",x"93387173",x"73085456",x"54717308",x"2e80c438",x"73755452",x"71337081",x"ff065254",x"70802e9d",x"38723355",x"70752e09",x"81069538",x"81128114",x"71337081",x"ff065456",x"545270e5",x"38723355",x"7381ff06",x"7581ff06",x"71713188",x"0c525287",x"3d0d0471",x"0970f7fb",x"fdff1406",x"70f88482",x"81800651",x"51517097",x"38841484",x"16710854",x"56547175",x"082edc38",x"73755452",x"ff963980",x"0b880c87",x"3d0d04ff",x"3d0d9fe4",x"0bfc0570",x"08525270",x"ff2e9138",x"702dfc12",x"70085252",x"70ff2e09",x"8106f138",x"833d0d04",x"04eac13f",x"04000000",x"00ffffff",x"ff00ffff",x"ffff00ff",x"ffffff00",x"00000946",x"00000978",x"00000920",x"000007ab",x"000009cf",x"000009e6",x"0000083e",x"000008cd",x"00000757",x"000009fa",x"01090600",x"007fef80",x"05b8d800",x"a4041700",x"00000000",x"00000000",x"00000000",x"00000fec",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"ffffffff",x"00000000",x"ffffffff",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if WEA='1' then
RAM(conv_integer(ADDRA) ) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if WEB='1' then
RAM( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/zpu_core_extreme_hyperion.vhd
|
13
|
42758
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg_hyperion.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_hyperion;
architecture behave of zpu_core_extreme_hyperion is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_Store,
State_StoreB,
State_StoreB2,
State_Load,
State_LoadMemory,
State_LoadStack,
State_Loadb,
State_Resync1,
State_Resync2,
State_LoadSP,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := 10;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
dbg_out.stacka <= std_logic_vector(exr.tos);
dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(rom_wb_dat_i, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(rom_wb_dat_i(31 downto 24));
when 1 => tOpcode := std_logic_vector(rom_wb_dat_i(23 downto 16));
when 2 => tOpcode := std_logic_vector(rom_wb_dat_i(15 downto 8));
when 3 => tOpcode := std_logic_vector(rom_wb_dat_i(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
sampledOpWillFreeze<='1';
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
rom_wb_stb_o <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, rom_wb_ack_i, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, rom_wb_stall_i
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
rom_wb_adr_o <= std_logic_vector(pc_to_memaddr(decr.fetchpc));
rom_wb_cti_o <= CTI_CYCLE_INCRADDR;
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
rom_wb_cyc_o <= '0';
else
rom_wb_cyc_o <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and rom_wb_stall_i='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o <='0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
w.valid := rom_wb_ack_i;
end if;
if rom_wb_ack_i='1' then
w.im := sampledOpcode(7);
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and rom_wb_stall_i='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
if rom_wb_stall_i='0' then
w.opcode := sampledOpcode;
end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
w.valid := decr.valid;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
| Decoded_Load
| Decoded_Store
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(10 downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(10 downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
wb_adr_o(maxAddrBitIncIO downto 0) <= std_logic_vector(exr.tos_save(maxAddrBitIncIO downto 0));
wb_cyc_o <= exr.wb_cyc;
wb_stb_o <= exr.wb_stb;
wb_we_o <= exr.wb_we;
wb_dat_o <= std_logic_vector( exr.nos_save );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= '0';
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= '0';
wroteback := wroteback_q;
stack_b_writeenable <= '0';
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
case exr.state is
when State_Resync1 =>
exu_busy <= '1';
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(10 downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<='1';
wroteback:='1';
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= '1';
when Decoded_StoreSP =>
stack_a_writeenable <= '1';
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<='1';
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store =>
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(nos);
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_StoreB =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(10 downto 2));
stack_a_enable<='1';
w.state := State_LoadStack;
else
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
w.wb_we :='0';
w.wb_cyc :='1';
w.wb_stb :='1';
w.state := State_Load;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Store =>
exu_busy <= '1';
-- Keep writeback flag
wroteback := wroteback_q;
if wb_ack_i='1' then
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
stack_b_enable<='1';
wroteback := '0';
--exu_busy <= '1';
w.wb_cyc := '0';
w.state := State_Resync2;
else
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_enable<='0';
stack_b_enable<='0';
end if;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Load =>
if wb_ack_i='0' then
exu_busy<='1';
else
w.tos := unsigned(wb_dat_i);
w.wb_cyc := '0';
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state := State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state := State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
end if;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state:=State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when State_StoreB =>
exu_busy <= '1';
--
-- At this point, we have loaded the 32-bit, and it's in TOS
-- The IO address is still saved in save_TOS.
-- The original write value is still at save_NOS
--
-- So we mangle the write value, and update save_NOS, and restore
-- the IO address to TOS
--
-- This is still buggy - don't use. Problems arise when writing to stack.
--
w.nos_save := exr.tos;
case exr.tos_save(1 downto 0) is
when "00" =>
w.nos_save(31 downto 24) := exr.nos_save(7 downto 0);
when "01" =>
w.nos_save(23 downto 16) := exr.nos_save(7 downto 0);
when "10" =>
w.nos_save(15 downto 8) := exr.nos_save(7 downto 0);
when "11" =>
w.nos_save(7 downto 0) := exr.nos_save(7 downto 0);
when others =>
null;
end case;
w.tos := exr.tos_save;
w.state := State_StoreB2;
when State_StoreB2 =>
exu_busy <= '1';
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(exr.nos_save); -- hmm I don't like this
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/zpu_core_extreme_hyperion.vhd
|
13
|
42758
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg_hyperion.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_hyperion;
architecture behave of zpu_core_extreme_hyperion is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_Store,
State_StoreB,
State_StoreB2,
State_Load,
State_LoadMemory,
State_LoadStack,
State_Loadb,
State_Resync1,
State_Resync2,
State_LoadSP,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := 10;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
dbg_out.stacka <= std_logic_vector(exr.tos);
dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(rom_wb_dat_i, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(rom_wb_dat_i(31 downto 24));
when 1 => tOpcode := std_logic_vector(rom_wb_dat_i(23 downto 16));
when 2 => tOpcode := std_logic_vector(rom_wb_dat_i(15 downto 8));
when 3 => tOpcode := std_logic_vector(rom_wb_dat_i(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
sampledOpWillFreeze<='1';
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
rom_wb_stb_o <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, rom_wb_ack_i, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, rom_wb_stall_i
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
rom_wb_adr_o <= std_logic_vector(pc_to_memaddr(decr.fetchpc));
rom_wb_cti_o <= CTI_CYCLE_INCRADDR;
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
rom_wb_cyc_o <= '0';
else
rom_wb_cyc_o <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and rom_wb_stall_i='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o <='0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
w.valid := rom_wb_ack_i;
end if;
if rom_wb_ack_i='1' then
w.im := sampledOpcode(7);
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and rom_wb_stall_i='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
if rom_wb_stall_i='0' then
w.opcode := sampledOpcode;
end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
w.valid := decr.valid;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
| Decoded_Load
| Decoded_Store
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(10 downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(10 downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
wb_adr_o(maxAddrBitIncIO downto 0) <= std_logic_vector(exr.tos_save(maxAddrBitIncIO downto 0));
wb_cyc_o <= exr.wb_cyc;
wb_stb_o <= exr.wb_stb;
wb_we_o <= exr.wb_we;
wb_dat_o <= std_logic_vector( exr.nos_save );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= '0';
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= '0';
wroteback := wroteback_q;
stack_b_writeenable <= '0';
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
case exr.state is
when State_Resync1 =>
exu_busy <= '1';
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(10 downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<='1';
wroteback:='1';
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= '1';
when Decoded_StoreSP =>
stack_a_writeenable <= '1';
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<='1';
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store =>
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(nos);
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_StoreB =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(10 downto 2));
stack_a_enable<='1';
w.state := State_LoadStack;
else
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
w.wb_we :='0';
w.wb_cyc :='1';
w.wb_stb :='1';
w.state := State_Load;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Store =>
exu_busy <= '1';
-- Keep writeback flag
wroteback := wroteback_q;
if wb_ack_i='1' then
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
stack_b_enable<='1';
wroteback := '0';
--exu_busy <= '1';
w.wb_cyc := '0';
w.state := State_Resync2;
else
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_enable<='0';
stack_b_enable<='0';
end if;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Load =>
if wb_ack_i='0' then
exu_busy<='1';
else
w.tos := unsigned(wb_dat_i);
w.wb_cyc := '0';
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state := State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state := State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
end if;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state:=State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when State_StoreB =>
exu_busy <= '1';
--
-- At this point, we have loaded the 32-bit, and it's in TOS
-- The IO address is still saved in save_TOS.
-- The original write value is still at save_NOS
--
-- So we mangle the write value, and update save_NOS, and restore
-- the IO address to TOS
--
-- This is still buggy - don't use. Problems arise when writing to stack.
--
w.nos_save := exr.tos;
case exr.tos_save(1 downto 0) is
when "00" =>
w.nos_save(31 downto 24) := exr.nos_save(7 downto 0);
when "01" =>
w.nos_save(23 downto 16) := exr.nos_save(7 downto 0);
when "10" =>
w.nos_save(15 downto 8) := exr.nos_save(7 downto 0);
when "11" =>
w.nos_save(7 downto 0) := exr.nos_save(7 downto 0);
when others =>
null;
end case;
w.tos := exr.tos_save;
w.state := State_StoreB2;
when State_StoreB2 =>
exu_busy <= '1';
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(exr.nos_save); -- hmm I don't like this
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/wb_rom_ram.vhd
|
13
|
6124
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
mit
|
chcbaram/FPGA
|
ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/example_design/frame_buffer_exdes.vhd
|
1
|
5000
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: frame_buffer_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY frame_buffer_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END frame_buffer_exdes;
ARCHITECTURE xilinx OF frame_buffer_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT frame_buffer IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : frame_buffer
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_YM2149.vhd
|
13
|
18360
|
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
-- accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
data_out: out std_logic_vector(17 downto 0) --Digital data out - this should be fed into an audio mixer or Delta-Sigma DAC.
);
end;
architecture RTL of AUDIO_zpuino_wb_YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
-- signal addr : std_logic_vector(7 downto 0);
-- signal busctrl_addr : std_logic;
-- signal busctrl_we : std_logic;
-- signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0);
signal audio_mix : std_logic_vector(9 downto 0) := (others => '0');
signal audio_final : std_logic_vector(9 downto 0) := (others => '0');
signal O_AUDIO : std_logic_vector(7 downto 0) := (others => '0');
signal I_SEL_L : std_logic;
signal ENA : std_logic;
signal TEST_tone0: std_logic;
signal TEST_tone1: std_logic;
signal TEST_tone2: std_logic;
signal TEST_chan: unsigned(1 downto 0);
signal divclken: std_logic := '0';
signal predivcnt: integer;
constant PRE_CLOCK_DIVIDER: integer := (FREQMHZ/2)-1;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
TEST_chan <= unsigned( cnt_div(1 downto 0) );
TEST_tone0<=tone_gen_op(1);
TEST_tone1<=tone_gen_op(2);
TEST_tone2<=tone_gen_op(3);
-- wishbone signals
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
I_SEL_L <= '1';
ENA <= '1';
data_out <= O_AUDIO & "0000000000";
p_wdata : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
reg <= (others => (others => '0'));
else
if wb_cyc_i='1' and wb_we_i='1' and wb_stb_i='1' then
reg(conv_integer(wb_adr_i(5 downto 2))) <= wb_dat_i(7 downto 0);
end if;
end if;
-- Envelope reset
env_reset <= '0';
if (wb_we_i = '1' and wb_cyc_i='1' and wb_stb_i='1') and (wb_adr_i(5 downto 2) = x"D") then
env_reset <= '1';
end if;
end if;
end process;
p_rdata : process(wb_adr_i, reg)
begin
wb_dat_o <= (others => '0'); -- 'X'
-- if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case wb_adr_i(5 downto 2) is
when x"0" => wb_dat_o(7 downto 0) <= reg(0) ;
when x"1" => wb_dat_o(7 downto 0) <= "0000" & reg(1)(3 downto 0) ;
when x"2" => wb_dat_o(7 downto 0) <= reg(2) ;
when x"3" => wb_dat_o(7 downto 0) <= "0000" & reg(3)(3 downto 0) ;
when x"4" => wb_dat_o(7 downto 0) <= reg(4) ;
when x"5" => wb_dat_o(7 downto 0) <= "0000" & reg(5)(3 downto 0) ;
when x"6" => wb_dat_o(7 downto 0) <= "000" & reg(6)(4 downto 0) ;
when x"7" => wb_dat_o(7 downto 0) <= reg(7) ;
when x"8" => wb_dat_o(7 downto 0) <= "000" & reg(8)(4 downto 0) ;
when x"9" => wb_dat_o(7 downto 0) <= "000" & reg(9)(4 downto 0) ;
when x"A" => wb_dat_o(7 downto 0) <= "000" & reg(10)(4 downto 0) ;
when x"B" => wb_dat_o(7 downto 0) <= reg(11);
when x"C" => wb_dat_o(7 downto 0) <= reg(12);
when x"D" => wb_dat_o(7 downto 0) <= "0000" & reg(13)(3 downto 0);
when others => null;
end case;
end process;
--
--
-- First divider.
--
predivider: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
divclken <= '0';
predivcnt <= PRE_CLOCK_DIVIDER;
else
divclken<='0';
if predivcnt=0 then
divclken<='1';
predivcnt <= PRE_CLOCK_DIVIDER;
else
predivcnt <= predivcnt -1 ;
end if;
end if;
end if;
end process;
p_divider : process
begin
wait until rising_edge(wb_clk_i);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if divclken='1' then
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(wb_clk_i);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(wb_clk_i);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(wb_clk_i);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, wb_clk_i)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if rising_edge(wb_clk_i) then
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
else
--if divclken='1' then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1'; tone_src <= '1';
noise_ena_l <= '1'; chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(wb_clk_i);
if (ENA = '1' and divclken='1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := "00000";
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= x"00";
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
if (cnt_div(1 downto 0) = "10") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & dac_amp);
end if;
end if;
if (wb_rst_i='1') then
O_AUDIO(7 downto 0) <= "00000000";
else
if divclken='1' then
if (audio_final(9) = '0') then
O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
else -- clip
O_AUDIO(7 downto 0) <= x"FF";
end if;
end if;
end if;
end process;
end architecture RTL;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/dp_sqr.vhd
|
10
|
8540
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** DP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 57 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY dp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_sqr;
ARCHITECTURE rtl OF dp_sqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 54
-- top latency = core + 1 (input) + 2 (output) = 57
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_normfp2x.vhd
|
10
|
13893
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_lnrnd.vhd
|
10
|
5431
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_addpipes.vhd
|
10
|
2515
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPES.VHD ***
--*** ***
--*** Function: Synthesizable Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipes IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipes;
ARCHITECTURE syn of hcc_addpipes IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_inv_core.vhd
|
10
|
9935
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - CORE ***
--*** ***
--*** DP_INV_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublepeed ***
--*** SIII Latency = 18 + doublespeed ***
--***************************************************
ENTITY dp_inv_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
END dp_inv_core;
ARCHITECTURE rtl OF dp_inv_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaleden : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal twonode, subscaleden : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessone : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteval : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal absolutevalff, absoluteff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal abscarryff : STD_LOGIC;
signal iteratenumnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal iteratenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteerror : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal mulabsguessff : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal mulabsguess : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(54 DOWNTO 36),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8+speed
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(54 DOWNTO 1);
gta: FOR k IN 1 TO 54 GENERATE
subscaleden(k) <= NOT(scaleden(k));
END GENERATE;
subscaleden(55) <= '1';
-- in level 8+doublespeed, outlevel 9+2*doublespeed
addtwoone: dp_fxadd
GENERIC MAP (width=>55,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>twonode,bb=>subscaleden,carryin=>'1',
cc=>guessone);
guessonevec <= guessone(54 DOWNTO 1);
-- absolute value of guess lower 36 bits
-- this is still correct, because (for positive), value will be 1.(17 zeros)error
-- can also be calculated from guessonevec (code below)
-- gabs: FOR k IN 1 TO 36 GENERATE
-- absoluteval(k) <= guessonevec(k) XOR NOT(guessonevec(54));
-- END GENERATE;
gabs: FOR k IN 1 TO 36 GENERATE
absoluteval(k) <= scaleden(k) XOR NOT(scaleden(54));
END GENERATE;
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
absolutevalff(k) <= '0';
absoluteff(k) <= '0';
END LOOP;
abscarryff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absolutevalff <= absoluteval; -- out level 9+speed
abscarryff <= NOT(scaleden(54));
absoluteff <= absolutevalff + (zerovec(35 DOWNTO 1) & abscarryff); -- out level 10+speed
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>18,pipes=>4+2*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invdivisor,
cc=>delinvdivisor);
-- in level 9+2*doublespeed, out level 12+3*doublespeed
muloneone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>delinvdivisor,
result=>iteratenumnode);
-- in level 10+doublespeed, out level 13+doublespeed
mulonetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>absoluteff,databb=>absoluteff,
result=>absoluteerror);
-- if speed = 0, delay absoluteerror 1 clock, else 2
-- this guess always positive (check??)
-- change here, error can be [19:1], not [18:1] - this is because (1.[17 zeros].error)^2
-- gives 1.[34 zeros].error
pgaa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 19 LOOP
mulabsguessff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulabsguessff <= absoluteerror(72 DOWNTO 54) +
(zerovec(18 DOWNTO 1) & absoluteerror(53));
END IF;
END IF;
END PROCESS;
mulabsguess(19 DOWNTO 1) <= mulabsguessff;
gmga: FOR k IN 20 TO 53 GENERATE
mulabsguess(k) <= '0';
END GENERATE;
mulabsguess(54) <= '1';
-- mulabsguess at 14+doublespeed depth
-- iteratenum at 12+3*doublespeed depth
-- mulabsguess 5 (5)clocks from absolutevalff
-- iteratenum 3+2doublespeed (3/5)clocks from abssolutevalff
-- delay iterate num
gdoa: IF (doublespeed = 0) GENERATE
delonetwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>iteratenumnode,
cc=>iteratenum);
END GENERATE;
gdob: IF (doublespeed = 1) GENERATE
iteratenum <= iteratenumnode;
END GENERATE;
--*********************
--*** OUTPUT SCALE ***
--*********************
-- in level 14+doublespeed
-- SII out level 19+2*doublespeed
-- SIII/IV out level 18+doublespeed
mulout: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>iteratenum,databb=>mulabsguess,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 17);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_subb.vhd
|
10
|
3154
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_acos.vhd
|
10
|
10938
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output 0 to pi
ENTITY fp_acos IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_acos ;
ARCHITECTURE rtl OF fp_acos IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type acos_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (43 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi_term, acos_term, acos_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal acos_sumff : acos_sumfftype;
signal acos_shift, acos_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal shiftzeroout : STD_LOGIC;
signal acos_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexponentff : STD_LOGIC;
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pi <= x"C90FDAA22";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
gpa: FOR k IN 1 TO 36 GENERATE
pi_term(k) <= pi(k) AND signff(41);
acos_term(k) <= acos_fixedpoint(k) XOR signff(41);
END GENERATE;
acos_sum <= pi_term + acos_term + signff(41);
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 43 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
acos_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
acos_sumff(1)(k) <= '0';
acos_sumff(2)(k) <= '0';
acos_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
zeroexponentff <= '0';
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 43 LOOP
signff(k) <= signff(k-1);
END LOOP;
acos_sumff(1)(36 DOWNTO 1) <= acos_sum; -- level 50
acos_sumff(2)(36 DOWNTO 1) <= acos_sumff(1)(36 DOWNTO 1); -- level 51
acos_shiftff <= acos_shift; -- level 51
acos_mantissaff <= acos_mantissabus; -- level 52
-- check for overflow not needed?
mantissaoutff <= acos_mantissaff(35 DOWNTO 13) + acos_mantissaff(12); -- level 52
-- if CLZ output = 0 and positive input, output = 0
zeroexponentff <= NOT(signff(43)) AND shiftzeroout;
exponentadjustff <= 128 - ("00" & acos_shiftff); -- level 52
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k) AND NOT(zeroexponentff); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
czo: fp_clz36
PORT MAP (mantissa=>acos_sumff(1)(36 DOWNTO 1),
leading=>acos_shift);
clso: fp_lsft36
PORT MAP (inbus=>acos_sumff(2)(36 DOWNTO 1),
shift=>acos_shiftff,
outbus=>acos_mantissabus);
shiftzeroout <= NOT(acos_shiftff(6) OR acos_shiftff(5) OR acos_shiftff(4) OR
acos_shiftff(3) OR acos_shiftff(2) OR acos_shiftff(1));
--*** OUTPUTS ***
signout <= '0';
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_mulfp1x.vhd
|
10
|
5226
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1X.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp1x;
ARCHITECTURE rtl OF hcc_mulfp1x IS
signal mulinaa, mulinbb : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal mulinaasat, mulinaazip, mulinbbsat, mulinbbzip : STD_LOGIC;
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfppn3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** ieee754 input when multiplier input is from cast ***
--*** cast now creates different ***
--*** formats for multiplier, divider, and alu ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
mulinaa <= aa;
mulinbb <= bb;
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
gma: IF (outputscale = 0) GENERATE
mulone: hcc_mulfp3236
GENERIC MAP (mantissa=>mantissa,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,aasat=>mulinaasat,aazip=>mulinaazip,
bb=>mulinbb,bbsat=>mulinbbsat,bbzip=>mulinbbzip,
cc=>ccnode,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
gmb: IF (outputscale = 1) GENERATE
multwo: hcc_mulfppn3236
GENERIC MAP (mantissa=>mantissa,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,aasat=>mulinaasat,aazip=>mulinaazip,
bb=>mulinbb,bbsat=>mulinbbsat,bbzip=>mulinbbzip,
cc=>ccnode,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
--*** OUTPUTS ***
cc <= ccnode;
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= ccnode(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
|
mit
|
NixOS/nixpkgs
|
pkgs/development/compilers/ghdl/simple.vhd
|
1
|
958
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.or_reduce;
entity simple is
port (
CLK, RESET : in std_ulogic;
DATA_OUT : out std_ulogic_vector(7 downto 0);
DONE_OUT : out std_ulogic
);
end simple;
architecture beh of simple is
signal data : std_ulogic_vector(7 downto 0);
signal done: std_ulogic;
begin
proc_ctr : process(CLK)
begin
if (CLK = '1' and CLK'event) then
if (RESET = '1') then
data <= "01011111";
done <= '0';
else
case data is
when "00100000" => data <= "01001110";
when "01001110" => data <= "01101001";
when "01101001" => data <= "01111000";
when "01111000" => data <= "01001111";
when "01001111" => data <= "01010011";
when others => data <= "00100000";
end case;
done <= not or_reduce(data xor "01010011");
end if;
end if;
end process;
DATA_OUT <= data;
DONE_OUT <= done;
end beh;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_tan.vhd
|
10
|
24604
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TAN1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Tangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** 1. for very top of range (last 256 mantissa lsbs before pi/2), use seperate ROM, not
--*** calculation
--*** 2. if round up starting when X.49999, errors reduce about 25%, need to tweak this, still getting
--*** all -1 errors with bX.111111111. less errors with less tail bits for smaller exponents (like 122)
--*** more for exponent = 126
ENTITY fp_tan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
signout : OUT STD_LOGIC;
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_tan;
ARCHITECTURE rtl of fp_tan IS
-- input section
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal argumentff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topargumentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal middleargumentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanhighmantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmiddleff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanlowsumff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal shiftin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal shiftinbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal argumentbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanmiddle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal deltwo_tailnode : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal tantailnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowsumnode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal tanlowmantissabus : STD_LOGIC_VECTOR (56 DOWNTO 1);
-- numerator section
signal tanlowff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsumff : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal tanlowshift : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal numeratormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delone_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delthr_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowbus : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsum : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal numeratorlead, numeratorleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
-- denominator section
signal lowleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inverseexponentff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lowleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_tanlowsum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal lowmantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delthr_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal delfor_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_lowlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
-- divider section
signal tanexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanmantissanormff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundbitff : STD_LOGIC;
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overff : STD_LOGIC;
signal denominatorinverse : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multiplier_tan : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal tanmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmantissanorm : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal tanmantissatail : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal overcheck : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal del_inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal del_numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanexponent, tanexponentnorm : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutnode : STD_LOGIC_VECTOR (23 DOWNTO 1);
-- small inputs
signal signff : STD_LOGIC_VECTOR (30 DOWNTO 1);
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (28 DOWNTO 1);
signal mantissabase : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (8 DOWNTO 1);
component fp_tanlut1
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_tanlut2
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_clz36x6
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft56x20
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
end component;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- convert to fixed point
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
argumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
topargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
middleargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
tanhighmantissaff(k) <= '0';
tanmiddleff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanhighexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanlowsumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain;
exponentinff <= exponentin;
argumentff <= argumentbus;
topargumentff <= argumentff(36 DOWNTO 28);
middleargumentff <= argumentff(27 DOWNTO 20);
tanhighmantissaff <= tanhighmantissa;
tanhighexponentff <= tanhighexponent;
tanmiddleff <= tanmiddle;
tanlowsumff <= tanlowsumnode;
END IF;
END IF;
END PROCESS;
shiftin <= 127 - exponentinff;
shiftinbus <= '1' & mantissainff & zerovec(12 DOWNTO 1);
csftin: fp_rsft36
PORT MAP (inbus=>shiftinbus,shift=>shiftin(6 DOWNTO 1),
outbus=>argumentbus);
chtt: fp_tanlut1
PORT MAP (add=>topargumentff,
mantissa=>tanhighmantissa,
exponent=>tanhighexponent);
cltt: fp_tanlut2
PORT MAP (add=>middleargumentff,
tanfraction=>tanmiddle);
-- in level 2, out level 4
dtail: fp_del
GENERIC MAP (width=>19,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>argumentff(19 DOWNTO 1),
cc=>deltwo_tailnode);
tantailnode <= zerovec(8 DOWNTO 1) & deltwo_tailnode & zerovec(9 DOWNTO 1);
tanlowsumnode <= ('0' & tanmiddleff(36 DOWNTO 1)) + ('0' & tantailnode);
tanlowmantissabus <= tanlowsumff & zerovec(19 DOWNTO 1);
--*********************************************
--*** Align two tangent values for addition ***
--*********************************************
padd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 56 LOOP
tanlowff(k) <= '0';
END LOOP;
FOR k IN 1 TO 57 LOOP
numeratorsumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numeratormantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
numeratorexponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanlowff <= tanlowbus;
numeratorsumff <= numeratorsum;
numeratormantissaff <= numeratormantissa;
numeratorexponentff <= numeratorexponent;
END IF;
END IF;
END PROCESS;
-- in level 4, out level 5
dhxa: fp_del
GENERIC MAP (width=>5,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighexponentff,
cc=>delone_tanhighexponent);
-- in level 5, out level 7
dhxb: fp_del
GENERIC MAP (width=>5,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delthr_tanhighexponent);
-- in level 4, out level 6
dhm: fp_del
GENERIC MAP (width=>36,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighmantissaff,
cc=>deltwo_tanhighmantissa);
-- tan high mantissa format 1.XXX, tan low mantissa format 0.XXXXX
-- tan high exponent base is 119 (top of middle range)
tanlowshift <= delone_tanhighexponent;
crsadd: fp_rsft56x20
PORT MAP (inbus=>tanlowmantissabus,
shift=>tanlowshift,
outbus=>tanlowbus);
numeratorsum <= ('0' & deltwo_tanhighmantissa & zerovec(20 DOWNTO 1)) + ('0' & tanlowff);
-- level 8
-- no pipe between clz and shift as only 6 bit shift
-- middle exponent is 119, and 2 overflow bits in numerator sum, so this will
-- cover downto (119+2-6) = 115 exponent
-- below 115 exponent, output mantissa = input mantissa
clznuma: fp_clz36x6
PORT MAP (mantissa=>numeratorsumff(57 DOWNTO 22),
leading=>numeratorlead);
numeratorleadnode <= "000" & numeratorlead(3 DOWNTO 1); -- force [6:4] to 0 to optimize away logic in LSFT
clsnuma: fp_lsft36
PORT MAP (inbus=>numeratorsumff(57 DOWNTO 22),shift=>numeratorleadnode,
outbus=>numeratormantissa);
numeratorexponent <= delthr_tanhighexponent - numeratorlead(5 DOWNTO 1) + 1;
--gnnadd: FOR k IN 1 TO 36 GENERATE
-- numeratormantissa(k) <= (numeratorsumff(k+20) AND NOT(numeratorsumff(57))) OR
-- (numeratorsumff(k+21) AND numeratorsumff(57));
--END GENERATE;
--numeratorexponent <= delthr_tanhighexponent + ("0000" & numeratorsumff(57));
--***************************************************
--*** Align two tangent values for multiplication ***
--***************************************************
pmul: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 6 LOOP
lowleadff(k) <= '0';
denominatorleadff(k) <= '0';
inverseexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
multshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
denominatorproductff(k) <= '0';
denominatorff(k) <= '0';
denominatormantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowleadff <= lowleadnode;
multshiftff <= multshiftnode;
denominatorproductff <= denominatorproductbus;
denominatorff <= denominator;
denominatorleadff <= denominatorlead;
denominatormantissaff <= denominatormantissa;
inverseexponentff <= inverseexponent;
END IF;
END IF;
END PROCESS;
clzmula: fp_clz36
PORT MAP (mantissa=>tanlowsumff(37 DOWNTO 2),
leading=>lowleadnode);
-- in level 5, out level 6
dlm: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanlowsumff(37 DOWNTO 2),
cc=>delone_tanlowsum);
clsmula: fp_lsft36
PORT MAP (inbus=>delone_tanlowsum,shift=>lowleadff,
outbus=>lowmantissabus);
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>deltwo_tanhighmantissa,
databb=>lowmantissabus,
result=>multipliernode);
-- in level 5, out level 8
dhxc: fp_del
GENERIC MAP (width=>5,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delfor_tanhighexponent);
-- in level 6, out level 8
dlla: fp_del
GENERIC MAP (width=>6,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>lowleadff,
cc=>deltwo_lowlead);
-- msb of lowmantissa(37) is at exponent 0 for highmantissa
multexponent <= ('0' & delfor_tanhighexponent);
--multshiftnode <= "001000" - multexponent + 8 - 1 + lowlead;
multshiftnode <= "001111" - multexponent + deltwo_lowlead;
-- '1.0' is at exponent 8 compared to highmantissa
crsmul: fp_rsft36
PORT MAP (inbus=>multipliernode(72 DOWNTO 37),shift=>multshiftff,
outbus=>denominatorproductbus);
denominator <= ('1' & zerovec(35 DOWNTO 1)) - denominatorproductff;
-- in level 11, out level 12
dda: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>denominatorff,
cc=>delone_denominator);
clzmulb: fp_clz36
PORT MAP (mantissa=>denominatorff,
leading=>denominatorlead);
-- denominatormantissa level 12, (denominatormantissaff level 13)
clsmulb: fp_lsft36
PORT MAP (inbus=>delone_denominator,shift=>denominatorleadff,
outbus=>denominatormantissa);
denominatorexponent <= denominatorleadff; -- actually inverse of exponent i.e. 4 => -4, so sign does not have to change after inverting
-- inverseexponentff level 13
inverseexponent <= denominatorexponent - 1;
--****************************
--*** main divider section ***
--****************************
pdiv: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
tanexponentff(k) <= '0';
tanexponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 24 LOOP
tanmantissanormff(k) <= '0';
END LOOP;
roundbitff <= '0';
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
overff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanexponentff <= tanexponent;
tanmantissanormff <= tanmantissanorm; -- level 29
tanexponentnormff <= tanexponentnorm; -- level 29
overff <= overcheck(24);
-- round up if 0.4999
roundbitff <= tanmantissanorm(1) OR
(tanmantissatail(9) AND
tanmantissatail(8) AND tanmantissatail(7) AND
tanmantissatail(6) AND tanmantissatail(5) AND
tanmantissatail(4) AND tanmantissatail(3) AND
tanmantissatail(2) AND tanmantissatail(1));
mantissaoutff <= mantissaoutnode; -- level 30
exponentoutff <= exponentoutnode; -- level 30
END IF;
END IF;
END PROCESS;
-- latency 12
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
-- level 13 in, level 25 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>denominatormantissaff,
quotient=>denominatorinverse);
-- level 8 in, level 25 out
dnuma: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratormantissaff,
cc=>del_numeratormantissa);
-- level 25 in, level 28 out
cmt: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numeratormantissa,
databb=>denominatorinverse,
result=>multiplier_tan);
tanmantissa <= multiplier_tan(72 DOWNTO 37);
gmna: FOR k IN 1 TO 24 GENERATE
tanmantissanorm(k) <= (tanmantissa(k+9) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+10) AND tanmantissa(35));
END GENERATE;
gmnb: FOR k IN 1 TO 9 GENERATE
tanmantissatail(k) <= (tanmantissa(k) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+1) AND tanmantissa(35));
END GENERATE;
overcheck(1) <= tanmantissanorm(1);
gova: FOR k IN 2 TO 24 GENERATE
overcheck(k) <= overcheck(k-1) AND tanmantissanorm(k);
END GENERATE;
-- level 13 in, level 27 out
ddena: fp_del
GENERIC MAP (width=>6,pipes=>14)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>inverseexponentff,
cc=>del_inverseexponent);
-- level 8 in, level 27 out
dnumb: fp_del
GENERIC MAP (width=>5,pipes=>19)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratorexponentff,
cc=>del_numeratorexponent);
tanexponent <= "01110111" +
(del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent) +
(del_inverseexponent(6) & del_inverseexponent(6) & del_inverseexponent); -- 119 + exponent
tanexponentnorm <= tanexponentff + tanmantissa(35);
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 30 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 28 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 30 LOOP
signff(k) <= signff(k-1);
END LOOP;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 28 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--mantissabase(1) <= (tanmantissanormff(1) AND NOT(small_inputff(28)));
mantissabase(1) <= (roundbitff AND NOT(small_inputff(28)));
gmba: FOR k IN 2 TO 24 GENERATE
mantissabase(k) <= (small_mantissa(k-1) AND small_inputff(28)) OR
(tanmantissanormff(k) AND NOT(small_inputff(28)));
END GENERATE;
gxba: FOR k IN 1 TO 8 GENERATE
exponentbase(k) <= (small_exponent(k) AND small_inputff(28)) OR
(tanexponentnormff(k) AND NOT(small_inputff(28)));
END GENERATE;
mantissaoutnode <= mantissabase(24 DOWNTO 2) + mantissabase(1);
exponentoutnode <= exponentbase + (overff AND NOT(small_inputff(28)));
--***************
--*** OUTPUTS ***
--***************
signout <= signff(30);
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_invsqr_lut0.vhd
|
10
|
37363
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse Root ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_invsqr_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_invsqr_lut0;
ARCHITECTURE rtl OF fp_invsqr_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1047553,20);
WHEN "000000010" => data <= conv_std_logic_vector(1046534,20);
WHEN "000000011" => data <= conv_std_logic_vector(1045517,20);
WHEN "000000100" => data <= conv_std_logic_vector(1044503,20);
WHEN "000000101" => data <= conv_std_logic_vector(1043493,20);
WHEN "000000110" => data <= conv_std_logic_vector(1042485,20);
WHEN "000000111" => data <= conv_std_logic_vector(1041480,20);
WHEN "000001000" => data <= conv_std_logic_vector(1040478,20);
WHEN "000001001" => data <= conv_std_logic_vector(1039479,20);
WHEN "000001010" => data <= conv_std_logic_vector(1038483,20);
WHEN "000001011" => data <= conv_std_logic_vector(1037490,20);
WHEN "000001100" => data <= conv_std_logic_vector(1036500,20);
WHEN "000001101" => data <= conv_std_logic_vector(1035512,20);
WHEN "000001110" => data <= conv_std_logic_vector(1034527,20);
WHEN "000001111" => data <= conv_std_logic_vector(1033545,20);
WHEN "000010000" => data <= conv_std_logic_vector(1032566,20);
WHEN "000010001" => data <= conv_std_logic_vector(1031589,20);
WHEN "000010010" => data <= conv_std_logic_vector(1030616,20);
WHEN "000010011" => data <= conv_std_logic_vector(1029645,20);
WHEN "000010100" => data <= conv_std_logic_vector(1028677,20);
WHEN "000010101" => data <= conv_std_logic_vector(1027711,20);
WHEN "000010110" => data <= conv_std_logic_vector(1026749,20);
WHEN "000010111" => data <= conv_std_logic_vector(1025789,20);
WHEN "000011000" => data <= conv_std_logic_vector(1024831,20);
WHEN "000011001" => data <= conv_std_logic_vector(1023877,20);
WHEN "000011010" => data <= conv_std_logic_vector(1022925,20);
WHEN "000011011" => data <= conv_std_logic_vector(1021975,20);
WHEN "000011100" => data <= conv_std_logic_vector(1021029,20);
WHEN "000011101" => data <= conv_std_logic_vector(1020084,20);
WHEN "000011110" => data <= conv_std_logic_vector(1019143,20);
WHEN "000011111" => data <= conv_std_logic_vector(1018204,20);
WHEN "000100000" => data <= conv_std_logic_vector(1017268,20);
WHEN "000100001" => data <= conv_std_logic_vector(1016334,20);
WHEN "000100010" => data <= conv_std_logic_vector(1015403,20);
WHEN "000100011" => data <= conv_std_logic_vector(1014474,20);
WHEN "000100100" => data <= conv_std_logic_vector(1013548,20);
WHEN "000100101" => data <= conv_std_logic_vector(1012625,20);
WHEN "000100110" => data <= conv_std_logic_vector(1011704,20);
WHEN "000100111" => data <= conv_std_logic_vector(1010785,20);
WHEN "000101000" => data <= conv_std_logic_vector(1009869,20);
WHEN "000101001" => data <= conv_std_logic_vector(1008956,20);
WHEN "000101010" => data <= conv_std_logic_vector(1008045,20);
WHEN "000101011" => data <= conv_std_logic_vector(1007136,20);
WHEN "000101100" => data <= conv_std_logic_vector(1006230,20);
WHEN "000101101" => data <= conv_std_logic_vector(1005327,20);
WHEN "000101110" => data <= conv_std_logic_vector(1004425,20);
WHEN "000101111" => data <= conv_std_logic_vector(1003527,20);
WHEN "000110000" => data <= conv_std_logic_vector(1002630,20);
WHEN "000110001" => data <= conv_std_logic_vector(1001736,20);
WHEN "000110010" => data <= conv_std_logic_vector(1000845,20);
WHEN "000110011" => data <= conv_std_logic_vector(999955,20);
WHEN "000110100" => data <= conv_std_logic_vector(999068,20);
WHEN "000110101" => data <= conv_std_logic_vector(998184,20);
WHEN "000110110" => data <= conv_std_logic_vector(997302,20);
WHEN "000110111" => data <= conv_std_logic_vector(996422,20);
WHEN "000111000" => data <= conv_std_logic_vector(995544,20);
WHEN "000111001" => data <= conv_std_logic_vector(994669,20);
WHEN "000111010" => data <= conv_std_logic_vector(993796,20);
WHEN "000111011" => data <= conv_std_logic_vector(992926,20);
WHEN "000111100" => data <= conv_std_logic_vector(992057,20);
WHEN "000111101" => data <= conv_std_logic_vector(991191,20);
WHEN "000111110" => data <= conv_std_logic_vector(990327,20);
WHEN "000111111" => data <= conv_std_logic_vector(989466,20);
WHEN "001000000" => data <= conv_std_logic_vector(988607,20);
WHEN "001000001" => data <= conv_std_logic_vector(987750,20);
WHEN "001000010" => data <= conv_std_logic_vector(986895,20);
WHEN "001000011" => data <= conv_std_logic_vector(986042,20);
WHEN "001000100" => data <= conv_std_logic_vector(985192,20);
WHEN "001000101" => data <= conv_std_logic_vector(984344,20);
WHEN "001000110" => data <= conv_std_logic_vector(983498,20);
WHEN "001000111" => data <= conv_std_logic_vector(982654,20);
WHEN "001001000" => data <= conv_std_logic_vector(981812,20);
WHEN "001001001" => data <= conv_std_logic_vector(980973,20);
WHEN "001001010" => data <= conv_std_logic_vector(980135,20);
WHEN "001001011" => data <= conv_std_logic_vector(979300,20);
WHEN "001001100" => data <= conv_std_logic_vector(978467,20);
WHEN "001001101" => data <= conv_std_logic_vector(977636,20);
WHEN "001001110" => data <= conv_std_logic_vector(976807,20);
WHEN "001001111" => data <= conv_std_logic_vector(975980,20);
WHEN "001010000" => data <= conv_std_logic_vector(975156,20);
WHEN "001010001" => data <= conv_std_logic_vector(974333,20);
WHEN "001010010" => data <= conv_std_logic_vector(973513,20);
WHEN "001010011" => data <= conv_std_logic_vector(972694,20);
WHEN "001010100" => data <= conv_std_logic_vector(971878,20);
WHEN "001010101" => data <= conv_std_logic_vector(971063,20);
WHEN "001010110" => data <= conv_std_logic_vector(970251,20);
WHEN "001010111" => data <= conv_std_logic_vector(969441,20);
WHEN "001011000" => data <= conv_std_logic_vector(968633,20);
WHEN "001011001" => data <= conv_std_logic_vector(967827,20);
WHEN "001011010" => data <= conv_std_logic_vector(967022,20);
WHEN "001011011" => data <= conv_std_logic_vector(966220,20);
WHEN "001011100" => data <= conv_std_logic_vector(965420,20);
WHEN "001011101" => data <= conv_std_logic_vector(964622,20);
WHEN "001011110" => data <= conv_std_logic_vector(963826,20);
WHEN "001011111" => data <= conv_std_logic_vector(963031,20);
WHEN "001100000" => data <= conv_std_logic_vector(962239,20);
WHEN "001100001" => data <= conv_std_logic_vector(961449,20);
WHEN "001100010" => data <= conv_std_logic_vector(960660,20);
WHEN "001100011" => data <= conv_std_logic_vector(959874,20);
WHEN "001100100" => data <= conv_std_logic_vector(959089,20);
WHEN "001100101" => data <= conv_std_logic_vector(958307,20);
WHEN "001100110" => data <= conv_std_logic_vector(957526,20);
WHEN "001100111" => data <= conv_std_logic_vector(956747,20);
WHEN "001101000" => data <= conv_std_logic_vector(955970,20);
WHEN "001101001" => data <= conv_std_logic_vector(955195,20);
WHEN "001101010" => data <= conv_std_logic_vector(954422,20);
WHEN "001101011" => data <= conv_std_logic_vector(953651,20);
WHEN "001101100" => data <= conv_std_logic_vector(952882,20);
WHEN "001101101" => data <= conv_std_logic_vector(952114,20);
WHEN "001101110" => data <= conv_std_logic_vector(951348,20);
WHEN "001101111" => data <= conv_std_logic_vector(950585,20);
WHEN "001110000" => data <= conv_std_logic_vector(949823,20);
WHEN "001110001" => data <= conv_std_logic_vector(949062,20);
WHEN "001110010" => data <= conv_std_logic_vector(948304,20);
WHEN "001110011" => data <= conv_std_logic_vector(947548,20);
WHEN "001110100" => data <= conv_std_logic_vector(946793,20);
WHEN "001110101" => data <= conv_std_logic_vector(946040,20);
WHEN "001110110" => data <= conv_std_logic_vector(945289,20);
WHEN "001110111" => data <= conv_std_logic_vector(944539,20);
WHEN "001111000" => data <= conv_std_logic_vector(943792,20);
WHEN "001111001" => data <= conv_std_logic_vector(943046,20);
WHEN "001111010" => data <= conv_std_logic_vector(942302,20);
WHEN "001111011" => data <= conv_std_logic_vector(941560,20);
WHEN "001111100" => data <= conv_std_logic_vector(940819,20);
WHEN "001111101" => data <= conv_std_logic_vector(940081,20);
WHEN "001111110" => data <= conv_std_logic_vector(939344,20);
WHEN "001111111" => data <= conv_std_logic_vector(938608,20);
WHEN "010000000" => data <= conv_std_logic_vector(937875,20);
WHEN "010000001" => data <= conv_std_logic_vector(937143,20);
WHEN "010000010" => data <= conv_std_logic_vector(936413,20);
WHEN "010000011" => data <= conv_std_logic_vector(935684,20);
WHEN "010000100" => data <= conv_std_logic_vector(934957,20);
WHEN "010000101" => data <= conv_std_logic_vector(934232,20);
WHEN "010000110" => data <= conv_std_logic_vector(933509,20);
WHEN "010000111" => data <= conv_std_logic_vector(932787,20);
WHEN "010001000" => data <= conv_std_logic_vector(932067,20);
WHEN "010001001" => data <= conv_std_logic_vector(931349,20);
WHEN "010001010" => data <= conv_std_logic_vector(930632,20);
WHEN "010001011" => data <= conv_std_logic_vector(929917,20);
WHEN "010001100" => data <= conv_std_logic_vector(929204,20);
WHEN "010001101" => data <= conv_std_logic_vector(928492,20);
WHEN "010001110" => data <= conv_std_logic_vector(927782,20);
WHEN "010001111" => data <= conv_std_logic_vector(927073,20);
WHEN "010010000" => data <= conv_std_logic_vector(926367,20);
WHEN "010010001" => data <= conv_std_logic_vector(925661,20);
WHEN "010010010" => data <= conv_std_logic_vector(924958,20);
WHEN "010010011" => data <= conv_std_logic_vector(924256,20);
WHEN "010010100" => data <= conv_std_logic_vector(923555,20);
WHEN "010010101" => data <= conv_std_logic_vector(922856,20);
WHEN "010010110" => data <= conv_std_logic_vector(922159,20);
WHEN "010010111" => data <= conv_std_logic_vector(921463,20);
WHEN "010011000" => data <= conv_std_logic_vector(920769,20);
WHEN "010011001" => data <= conv_std_logic_vector(920077,20);
WHEN "010011010" => data <= conv_std_logic_vector(919386,20);
WHEN "010011011" => data <= conv_std_logic_vector(918696,20);
WHEN "010011100" => data <= conv_std_logic_vector(918008,20);
WHEN "010011101" => data <= conv_std_logic_vector(917322,20);
WHEN "010011110" => data <= conv_std_logic_vector(916637,20);
WHEN "010011111" => data <= conv_std_logic_vector(915954,20);
WHEN "010100000" => data <= conv_std_logic_vector(915272,20);
WHEN "010100001" => data <= conv_std_logic_vector(914592,20);
WHEN "010100010" => data <= conv_std_logic_vector(913913,20);
WHEN "010100011" => data <= conv_std_logic_vector(913236,20);
WHEN "010100100" => data <= conv_std_logic_vector(912560,20);
WHEN "010100101" => data <= conv_std_logic_vector(911886,20);
WHEN "010100110" => data <= conv_std_logic_vector(911213,20);
WHEN "010100111" => data <= conv_std_logic_vector(910542,20);
WHEN "010101000" => data <= conv_std_logic_vector(909872,20);
WHEN "010101001" => data <= conv_std_logic_vector(909204,20);
WHEN "010101010" => data <= conv_std_logic_vector(908537,20);
WHEN "010101011" => data <= conv_std_logic_vector(907872,20);
WHEN "010101100" => data <= conv_std_logic_vector(907208,20);
WHEN "010101101" => data <= conv_std_logic_vector(906545,20);
WHEN "010101110" => data <= conv_std_logic_vector(905884,20);
WHEN "010101111" => data <= conv_std_logic_vector(905225,20);
WHEN "010110000" => data <= conv_std_logic_vector(904567,20);
WHEN "010110001" => data <= conv_std_logic_vector(903910,20);
WHEN "010110010" => data <= conv_std_logic_vector(903255,20);
WHEN "010110011" => data <= conv_std_logic_vector(902601,20);
WHEN "010110100" => data <= conv_std_logic_vector(901949,20);
WHEN "010110101" => data <= conv_std_logic_vector(901298,20);
WHEN "010110110" => data <= conv_std_logic_vector(900648,20);
WHEN "010110111" => data <= conv_std_logic_vector(900000,20);
WHEN "010111000" => data <= conv_std_logic_vector(899353,20);
WHEN "010111001" => data <= conv_std_logic_vector(898708,20);
WHEN "010111010" => data <= conv_std_logic_vector(898064,20);
WHEN "010111011" => data <= conv_std_logic_vector(897421,20);
WHEN "010111100" => data <= conv_std_logic_vector(896780,20);
WHEN "010111101" => data <= conv_std_logic_vector(896140,20);
WHEN "010111110" => data <= conv_std_logic_vector(895501,20);
WHEN "010111111" => data <= conv_std_logic_vector(894864,20);
WHEN "011000000" => data <= conv_std_logic_vector(894228,20);
WHEN "011000001" => data <= conv_std_logic_vector(893594,20);
WHEN "011000010" => data <= conv_std_logic_vector(892961,20);
WHEN "011000011" => data <= conv_std_logic_vector(892329,20);
WHEN "011000100" => data <= conv_std_logic_vector(891699,20);
WHEN "011000101" => data <= conv_std_logic_vector(891070,20);
WHEN "011000110" => data <= conv_std_logic_vector(890442,20);
WHEN "011000111" => data <= conv_std_logic_vector(889816,20);
WHEN "011001000" => data <= conv_std_logic_vector(889191,20);
WHEN "011001001" => data <= conv_std_logic_vector(888567,20);
WHEN "011001010" => data <= conv_std_logic_vector(887944,20);
WHEN "011001011" => data <= conv_std_logic_vector(887323,20);
WHEN "011001100" => data <= conv_std_logic_vector(886703,20);
WHEN "011001101" => data <= conv_std_logic_vector(886085,20);
WHEN "011001110" => data <= conv_std_logic_vector(885467,20);
WHEN "011001111" => data <= conv_std_logic_vector(884851,20);
WHEN "011010000" => data <= conv_std_logic_vector(884237,20);
WHEN "011010001" => data <= conv_std_logic_vector(883623,20);
WHEN "011010010" => data <= conv_std_logic_vector(883011,20);
WHEN "011010011" => data <= conv_std_logic_vector(882400,20);
WHEN "011010100" => data <= conv_std_logic_vector(881791,20);
WHEN "011010101" => data <= conv_std_logic_vector(881182,20);
WHEN "011010110" => data <= conv_std_logic_vector(880575,20);
WHEN "011010111" => data <= conv_std_logic_vector(879969,20);
WHEN "011011000" => data <= conv_std_logic_vector(879365,20);
WHEN "011011001" => data <= conv_std_logic_vector(878762,20);
WHEN "011011010" => data <= conv_std_logic_vector(878159,20);
WHEN "011011011" => data <= conv_std_logic_vector(877559,20);
WHEN "011011100" => data <= conv_std_logic_vector(876959,20);
WHEN "011011101" => data <= conv_std_logic_vector(876361,20);
WHEN "011011110" => data <= conv_std_logic_vector(875763,20);
WHEN "011011111" => data <= conv_std_logic_vector(875167,20);
WHEN "011100000" => data <= conv_std_logic_vector(874573,20);
WHEN "011100001" => data <= conv_std_logic_vector(873979,20);
WHEN "011100010" => data <= conv_std_logic_vector(873387,20);
WHEN "011100011" => data <= conv_std_logic_vector(872796,20);
WHEN "011100100" => data <= conv_std_logic_vector(872206,20);
WHEN "011100101" => data <= conv_std_logic_vector(871617,20);
WHEN "011100110" => data <= conv_std_logic_vector(871030,20);
WHEN "011100111" => data <= conv_std_logic_vector(870443,20);
WHEN "011101000" => data <= conv_std_logic_vector(869858,20);
WHEN "011101001" => data <= conv_std_logic_vector(869274,20);
WHEN "011101010" => data <= conv_std_logic_vector(868691,20);
WHEN "011101011" => data <= conv_std_logic_vector(868110,20);
WHEN "011101100" => data <= conv_std_logic_vector(867529,20);
WHEN "011101101" => data <= conv_std_logic_vector(866950,20);
WHEN "011101110" => data <= conv_std_logic_vector(866372,20);
WHEN "011101111" => data <= conv_std_logic_vector(865795,20);
WHEN "011110000" => data <= conv_std_logic_vector(865219,20);
WHEN "011110001" => data <= conv_std_logic_vector(864644,20);
WHEN "011110010" => data <= conv_std_logic_vector(864070,20);
WHEN "011110011" => data <= conv_std_logic_vector(863498,20);
WHEN "011110100" => data <= conv_std_logic_vector(862927,20);
WHEN "011110101" => data <= conv_std_logic_vector(862357,20);
WHEN "011110110" => data <= conv_std_logic_vector(861788,20);
WHEN "011110111" => data <= conv_std_logic_vector(861220,20);
WHEN "011111000" => data <= conv_std_logic_vector(860653,20);
WHEN "011111001" => data <= conv_std_logic_vector(860087,20);
WHEN "011111010" => data <= conv_std_logic_vector(859523,20);
WHEN "011111011" => data <= conv_std_logic_vector(858959,20);
WHEN "011111100" => data <= conv_std_logic_vector(858397,20);
WHEN "011111101" => data <= conv_std_logic_vector(857836,20);
WHEN "011111110" => data <= conv_std_logic_vector(857276,20);
WHEN "011111111" => data <= conv_std_logic_vector(856717,20);
WHEN "100000000" => data <= conv_std_logic_vector(856159,20);
WHEN "100000001" => data <= conv_std_logic_vector(855602,20);
WHEN "100000010" => data <= conv_std_logic_vector(855046,20);
WHEN "100000011" => data <= conv_std_logic_vector(854491,20);
WHEN "100000100" => data <= conv_std_logic_vector(853938,20);
WHEN "100000101" => data <= conv_std_logic_vector(853385,20);
WHEN "100000110" => data <= conv_std_logic_vector(852834,20);
WHEN "100000111" => data <= conv_std_logic_vector(852283,20);
WHEN "100001000" => data <= conv_std_logic_vector(851734,20);
WHEN "100001001" => data <= conv_std_logic_vector(851186,20);
WHEN "100001010" => data <= conv_std_logic_vector(850638,20);
WHEN "100001011" => data <= conv_std_logic_vector(850092,20);
WHEN "100001100" => data <= conv_std_logic_vector(849547,20);
WHEN "100001101" => data <= conv_std_logic_vector(849003,20);
WHEN "100001110" => data <= conv_std_logic_vector(848460,20);
WHEN "100001111" => data <= conv_std_logic_vector(847918,20);
WHEN "100010000" => data <= conv_std_logic_vector(847377,20);
WHEN "100010001" => data <= conv_std_logic_vector(846837,20);
WHEN "100010010" => data <= conv_std_logic_vector(846298,20);
WHEN "100010011" => data <= conv_std_logic_vector(845761,20);
WHEN "100010100" => data <= conv_std_logic_vector(845224,20);
WHEN "100010101" => data <= conv_std_logic_vector(844688,20);
WHEN "100010110" => data <= conv_std_logic_vector(844153,20);
WHEN "100010111" => data <= conv_std_logic_vector(843619,20);
WHEN "100011000" => data <= conv_std_logic_vector(843087,20);
WHEN "100011001" => data <= conv_std_logic_vector(842555,20);
WHEN "100011010" => data <= conv_std_logic_vector(842024,20);
WHEN "100011011" => data <= conv_std_logic_vector(841494,20);
WHEN "100011100" => data <= conv_std_logic_vector(840966,20);
WHEN "100011101" => data <= conv_std_logic_vector(840438,20);
WHEN "100011110" => data <= conv_std_logic_vector(839911,20);
WHEN "100011111" => data <= conv_std_logic_vector(839385,20);
WHEN "100100000" => data <= conv_std_logic_vector(838861,20);
WHEN "100100001" => data <= conv_std_logic_vector(838337,20);
WHEN "100100010" => data <= conv_std_logic_vector(837814,20);
WHEN "100100011" => data <= conv_std_logic_vector(837292,20);
WHEN "100100100" => data <= conv_std_logic_vector(836771,20);
WHEN "100100101" => data <= conv_std_logic_vector(836251,20);
WHEN "100100110" => data <= conv_std_logic_vector(835733,20);
WHEN "100100111" => data <= conv_std_logic_vector(835215,20);
WHEN "100101000" => data <= conv_std_logic_vector(834698,20);
WHEN "100101001" => data <= conv_std_logic_vector(834182,20);
WHEN "100101010" => data <= conv_std_logic_vector(833666,20);
WHEN "100101011" => data <= conv_std_logic_vector(833152,20);
WHEN "100101100" => data <= conv_std_logic_vector(832639,20);
WHEN "100101101" => data <= conv_std_logic_vector(832127,20);
WHEN "100101110" => data <= conv_std_logic_vector(831616,20);
WHEN "100101111" => data <= conv_std_logic_vector(831105,20);
WHEN "100110000" => data <= conv_std_logic_vector(830596,20);
WHEN "100110001" => data <= conv_std_logic_vector(830087,20);
WHEN "100110010" => data <= conv_std_logic_vector(829580,20);
WHEN "100110011" => data <= conv_std_logic_vector(829073,20);
WHEN "100110100" => data <= conv_std_logic_vector(828568,20);
WHEN "100110101" => data <= conv_std_logic_vector(828063,20);
WHEN "100110110" => data <= conv_std_logic_vector(827559,20);
WHEN "100110111" => data <= conv_std_logic_vector(827056,20);
WHEN "100111000" => data <= conv_std_logic_vector(826554,20);
WHEN "100111001" => data <= conv_std_logic_vector(826053,20);
WHEN "100111010" => data <= conv_std_logic_vector(825553,20);
WHEN "100111011" => data <= conv_std_logic_vector(825053,20);
WHEN "100111100" => data <= conv_std_logic_vector(824555,20);
WHEN "100111101" => data <= conv_std_logic_vector(824058,20);
WHEN "100111110" => data <= conv_std_logic_vector(823561,20);
WHEN "100111111" => data <= conv_std_logic_vector(823065,20);
WHEN "101000000" => data <= conv_std_logic_vector(822571,20);
WHEN "101000001" => data <= conv_std_logic_vector(822077,20);
WHEN "101000010" => data <= conv_std_logic_vector(821584,20);
WHEN "101000011" => data <= conv_std_logic_vector(821092,20);
WHEN "101000100" => data <= conv_std_logic_vector(820600,20);
WHEN "101000101" => data <= conv_std_logic_vector(820110,20);
WHEN "101000110" => data <= conv_std_logic_vector(819621,20);
WHEN "101000111" => data <= conv_std_logic_vector(819132,20);
WHEN "101001000" => data <= conv_std_logic_vector(818644,20);
WHEN "101001001" => data <= conv_std_logic_vector(818157,20);
WHEN "101001010" => data <= conv_std_logic_vector(817671,20);
WHEN "101001011" => data <= conv_std_logic_vector(817186,20);
WHEN "101001100" => data <= conv_std_logic_vector(816702,20);
WHEN "101001101" => data <= conv_std_logic_vector(816219,20);
WHEN "101001110" => data <= conv_std_logic_vector(815736,20);
WHEN "101001111" => data <= conv_std_logic_vector(815254,20);
WHEN "101010000" => data <= conv_std_logic_vector(814774,20);
WHEN "101010001" => data <= conv_std_logic_vector(814294,20);
WHEN "101010010" => data <= conv_std_logic_vector(813814,20);
WHEN "101010011" => data <= conv_std_logic_vector(813336,20);
WHEN "101010100" => data <= conv_std_logic_vector(812859,20);
WHEN "101010101" => data <= conv_std_logic_vector(812382,20);
WHEN "101010110" => data <= conv_std_logic_vector(811906,20);
WHEN "101010111" => data <= conv_std_logic_vector(811431,20);
WHEN "101011000" => data <= conv_std_logic_vector(810957,20);
WHEN "101011001" => data <= conv_std_logic_vector(810484,20);
WHEN "101011010" => data <= conv_std_logic_vector(810012,20);
WHEN "101011011" => data <= conv_std_logic_vector(809540,20);
WHEN "101011100" => data <= conv_std_logic_vector(809069,20);
WHEN "101011101" => data <= conv_std_logic_vector(808599,20);
WHEN "101011110" => data <= conv_std_logic_vector(808130,20);
WHEN "101011111" => data <= conv_std_logic_vector(807662,20);
WHEN "101100000" => data <= conv_std_logic_vector(807194,20);
WHEN "101100001" => data <= conv_std_logic_vector(806727,20);
WHEN "101100010" => data <= conv_std_logic_vector(806261,20);
WHEN "101100011" => data <= conv_std_logic_vector(805796,20);
WHEN "101100100" => data <= conv_std_logic_vector(805332,20);
WHEN "101100101" => data <= conv_std_logic_vector(804869,20);
WHEN "101100110" => data <= conv_std_logic_vector(804406,20);
WHEN "101100111" => data <= conv_std_logic_vector(803944,20);
WHEN "101101000" => data <= conv_std_logic_vector(803483,20);
WHEN "101101001" => data <= conv_std_logic_vector(803023,20);
WHEN "101101010" => data <= conv_std_logic_vector(802563,20);
WHEN "101101011" => data <= conv_std_logic_vector(802104,20);
WHEN "101101100" => data <= conv_std_logic_vector(801646,20);
WHEN "101101101" => data <= conv_std_logic_vector(801189,20);
WHEN "101101110" => data <= conv_std_logic_vector(800733,20);
WHEN "101101111" => data <= conv_std_logic_vector(800277,20);
WHEN "101110000" => data <= conv_std_logic_vector(799822,20);
WHEN "101110001" => data <= conv_std_logic_vector(799368,20);
WHEN "101110010" => data <= conv_std_logic_vector(798915,20);
WHEN "101110011" => data <= conv_std_logic_vector(798462,20);
WHEN "101110100" => data <= conv_std_logic_vector(798011,20);
WHEN "101110101" => data <= conv_std_logic_vector(797560,20);
WHEN "101110110" => data <= conv_std_logic_vector(797109,20);
WHEN "101110111" => data <= conv_std_logic_vector(796660,20);
WHEN "101111000" => data <= conv_std_logic_vector(796211,20);
WHEN "101111001" => data <= conv_std_logic_vector(795763,20);
WHEN "101111010" => data <= conv_std_logic_vector(795316,20);
WHEN "101111011" => data <= conv_std_logic_vector(794870,20);
WHEN "101111100" => data <= conv_std_logic_vector(794424,20);
WHEN "101111101" => data <= conv_std_logic_vector(793979,20);
WHEN "101111110" => data <= conv_std_logic_vector(793535,20);
WHEN "101111111" => data <= conv_std_logic_vector(793092,20);
WHEN "110000000" => data <= conv_std_logic_vector(792649,20);
WHEN "110000001" => data <= conv_std_logic_vector(792207,20);
WHEN "110000010" => data <= conv_std_logic_vector(791766,20);
WHEN "110000011" => data <= conv_std_logic_vector(791325,20);
WHEN "110000100" => data <= conv_std_logic_vector(790885,20);
WHEN "110000101" => data <= conv_std_logic_vector(790446,20);
WHEN "110000110" => data <= conv_std_logic_vector(790008,20);
WHEN "110000111" => data <= conv_std_logic_vector(789571,20);
WHEN "110001000" => data <= conv_std_logic_vector(789134,20);
WHEN "110001001" => data <= conv_std_logic_vector(788698,20);
WHEN "110001010" => data <= conv_std_logic_vector(788262,20);
WHEN "110001011" => data <= conv_std_logic_vector(787828,20);
WHEN "110001100" => data <= conv_std_logic_vector(787394,20);
WHEN "110001101" => data <= conv_std_logic_vector(786960,20);
WHEN "110001110" => data <= conv_std_logic_vector(786528,20);
WHEN "110001111" => data <= conv_std_logic_vector(786096,20);
WHEN "110010000" => data <= conv_std_logic_vector(785665,20);
WHEN "110010001" => data <= conv_std_logic_vector(785235,20);
WHEN "110010010" => data <= conv_std_logic_vector(784805,20);
WHEN "110010011" => data <= conv_std_logic_vector(784376,20);
WHEN "110010100" => data <= conv_std_logic_vector(783948,20);
WHEN "110010101" => data <= conv_std_logic_vector(783520,20);
WHEN "110010110" => data <= conv_std_logic_vector(783093,20);
WHEN "110010111" => data <= conv_std_logic_vector(782667,20);
WHEN "110011000" => data <= conv_std_logic_vector(782242,20);
WHEN "110011001" => data <= conv_std_logic_vector(781817,20);
WHEN "110011010" => data <= conv_std_logic_vector(781393,20);
WHEN "110011011" => data <= conv_std_logic_vector(780969,20);
WHEN "110011100" => data <= conv_std_logic_vector(780547,20);
WHEN "110011101" => data <= conv_std_logic_vector(780125,20);
WHEN "110011110" => data <= conv_std_logic_vector(779703,20);
WHEN "110011111" => data <= conv_std_logic_vector(779283,20);
WHEN "110100000" => data <= conv_std_logic_vector(778863,20);
WHEN "110100001" => data <= conv_std_logic_vector(778443,20);
WHEN "110100010" => data <= conv_std_logic_vector(778025,20);
WHEN "110100011" => data <= conv_std_logic_vector(777607,20);
WHEN "110100100" => data <= conv_std_logic_vector(777189,20);
WHEN "110100101" => data <= conv_std_logic_vector(776773,20);
WHEN "110100110" => data <= conv_std_logic_vector(776357,20);
WHEN "110100111" => data <= conv_std_logic_vector(775942,20);
WHEN "110101000" => data <= conv_std_logic_vector(775527,20);
WHEN "110101001" => data <= conv_std_logic_vector(775113,20);
WHEN "110101010" => data <= conv_std_logic_vector(774700,20);
WHEN "110101011" => data <= conv_std_logic_vector(774287,20);
WHEN "110101100" => data <= conv_std_logic_vector(773875,20);
WHEN "110101101" => data <= conv_std_logic_vector(773464,20);
WHEN "110101110" => data <= conv_std_logic_vector(773053,20);
WHEN "110101111" => data <= conv_std_logic_vector(772643,20);
WHEN "110110000" => data <= conv_std_logic_vector(772234,20);
WHEN "110110001" => data <= conv_std_logic_vector(771825,20);
WHEN "110110010" => data <= conv_std_logic_vector(771417,20);
WHEN "110110011" => data <= conv_std_logic_vector(771010,20);
WHEN "110110100" => data <= conv_std_logic_vector(770603,20);
WHEN "110110101" => data <= conv_std_logic_vector(770197,20);
WHEN "110110110" => data <= conv_std_logic_vector(769791,20);
WHEN "110110111" => data <= conv_std_logic_vector(769387,20);
WHEN "110111000" => data <= conv_std_logic_vector(768982,20);
WHEN "110111001" => data <= conv_std_logic_vector(768579,20);
WHEN "110111010" => data <= conv_std_logic_vector(768176,20);
WHEN "110111011" => data <= conv_std_logic_vector(767774,20);
WHEN "110111100" => data <= conv_std_logic_vector(767372,20);
WHEN "110111101" => data <= conv_std_logic_vector(766971,20);
WHEN "110111110" => data <= conv_std_logic_vector(766570,20);
WHEN "110111111" => data <= conv_std_logic_vector(766171,20);
WHEN "111000000" => data <= conv_std_logic_vector(765772,20);
WHEN "111000001" => data <= conv_std_logic_vector(765373,20);
WHEN "111000010" => data <= conv_std_logic_vector(764975,20);
WHEN "111000011" => data <= conv_std_logic_vector(764578,20);
WHEN "111000100" => data <= conv_std_logic_vector(764181,20);
WHEN "111000101" => data <= conv_std_logic_vector(763785,20);
WHEN "111000110" => data <= conv_std_logic_vector(763390,20);
WHEN "111000111" => data <= conv_std_logic_vector(762995,20);
WHEN "111001000" => data <= conv_std_logic_vector(762601,20);
WHEN "111001001" => data <= conv_std_logic_vector(762207,20);
WHEN "111001010" => data <= conv_std_logic_vector(761814,20);
WHEN "111001011" => data <= conv_std_logic_vector(761422,20);
WHEN "111001100" => data <= conv_std_logic_vector(761030,20);
WHEN "111001101" => data <= conv_std_logic_vector(760639,20);
WHEN "111001110" => data <= conv_std_logic_vector(760248,20);
WHEN "111001111" => data <= conv_std_logic_vector(759858,20);
WHEN "111010000" => data <= conv_std_logic_vector(759469,20);
WHEN "111010001" => data <= conv_std_logic_vector(759080,20);
WHEN "111010010" => data <= conv_std_logic_vector(758692,20);
WHEN "111010011" => data <= conv_std_logic_vector(758304,20);
WHEN "111010100" => data <= conv_std_logic_vector(757917,20);
WHEN "111010101" => data <= conv_std_logic_vector(757531,20);
WHEN "111010110" => data <= conv_std_logic_vector(757145,20);
WHEN "111010111" => data <= conv_std_logic_vector(756760,20);
WHEN "111011000" => data <= conv_std_logic_vector(756375,20);
WHEN "111011001" => data <= conv_std_logic_vector(755991,20);
WHEN "111011010" => data <= conv_std_logic_vector(755608,20);
WHEN "111011011" => data <= conv_std_logic_vector(755225,20);
WHEN "111011100" => data <= conv_std_logic_vector(754843,20);
WHEN "111011101" => data <= conv_std_logic_vector(754461,20);
WHEN "111011110" => data <= conv_std_logic_vector(754080,20);
WHEN "111011111" => data <= conv_std_logic_vector(753699,20);
WHEN "111100000" => data <= conv_std_logic_vector(753319,20);
WHEN "111100001" => data <= conv_std_logic_vector(752940,20);
WHEN "111100010" => data <= conv_std_logic_vector(752561,20);
WHEN "111100011" => data <= conv_std_logic_vector(752183,20);
WHEN "111100100" => data <= conv_std_logic_vector(751805,20);
WHEN "111100101" => data <= conv_std_logic_vector(751428,20);
WHEN "111100110" => data <= conv_std_logic_vector(751051,20);
WHEN "111100111" => data <= conv_std_logic_vector(750675,20);
WHEN "111101000" => data <= conv_std_logic_vector(750300,20);
WHEN "111101001" => data <= conv_std_logic_vector(749925,20);
WHEN "111101010" => data <= conv_std_logic_vector(749551,20);
WHEN "111101011" => data <= conv_std_logic_vector(749177,20);
WHEN "111101100" => data <= conv_std_logic_vector(748804,20);
WHEN "111101101" => data <= conv_std_logic_vector(748431,20);
WHEN "111101110" => data <= conv_std_logic_vector(748059,20);
WHEN "111101111" => data <= conv_std_logic_vector(747687,20);
WHEN "111110000" => data <= conv_std_logic_vector(747317,20);
WHEN "111110001" => data <= conv_std_logic_vector(746946,20);
WHEN "111110010" => data <= conv_std_logic_vector(746576,20);
WHEN "111110011" => data <= conv_std_logic_vector(746207,20);
WHEN "111110100" => data <= conv_std_logic_vector(745838,20);
WHEN "111110101" => data <= conv_std_logic_vector(745470,20);
WHEN "111110110" => data <= conv_std_logic_vector(745102,20);
WHEN "111110111" => data <= conv_std_logic_vector(744735,20);
WHEN "111111000" => data <= conv_std_logic_vector(744369,20);
WHEN "111111001" => data <= conv_std_logic_vector(744002,20);
WHEN "111111010" => data <= conv_std_logic_vector(743637,20);
WHEN "111111011" => data <= conv_std_logic_vector(743272,20);
WHEN "111111100" => data <= conv_std_logic_vector(742908,20);
WHEN "111111101" => data <= conv_std_logic_vector(742544,20);
WHEN "111111110" => data <= conv_std_logic_vector(742180,20);
WHEN "111111111" => data <= conv_std_logic_vector(741817,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fpc_library_sv.vhd
|
10
|
100780
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_lnlutpow.vhd
|
10
|
230947
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlutpow;
ARCHITECTURE rtl OF dp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "0000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "0000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1023,11);
WHEN "0000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN others =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
|
mit
|
LorhanSohaky/UFSCar
|
2017/lab_cd/projetoPessoal/verilog/simulation/modelsim/rtl_work/projeto@pessoal_@t@b/_primary.vhd
|
1
|
94
|
library verilog;
use verilog.vl_types.all;
entity projetoPessoal_TB is
end projetoPessoal_TB;
|
mit
|
SLongofono/Senior_Design_Capstone
|
Utility/test1.vhd
|
1
|
845
|
(0 + 0) => x"17", (0 + 1) => x"01", (0 + 2) => x"00", (0 + 3) => x"00", (0 + 4) => x"13", (0 + 5) => x"01", (0 + 6) => x"01", (0 + 7) => x"0b", (0 + 8) => x"6f", (0 + 9) => x"00", (0 + 10) => x"40", (0 + 11) => x"00", (0 + 12) => x"13", (0 + 13) => x"01", (0 + 14) => x"01", (0 + 15) => x"ff", (0 + 16) => x"23", (0 + 17) => x"34", (0 + 18) => x"81", (0 + 19) => x"00", (0 + 20) => x"13", (0 + 21) => x"04", (0 + 22) => x"01", (0 + 23) => x"01", (0 + 24) => x"93", (0 + 25) => x"07", (0 + 26) => x"90", (0 + 27) => x"00", (0 + 28) => x"93", (0 + 29) => x"97", (0 + 30) => x"c7", (0 + 31) => x"01", (0 + 32) => x"13", (0 + 33) => x"07", (0 + 34) => x"f0", (0 + 35) => x"ff", (0 + 36) => x"23", (0 + 37) => x"90", (0 + 38) => x"e7", (0 + 39) => x"00", (0 + 40) => x"6f", (0 + 41) => x"00", (0 + 42) => x"00", (0 + 43) => x"00", (0 + 44) => x"00",
|
mit
|
fabioperez/space-invaders-vhdl
|
lib/controllers/shot.vhd
|
1
|
2539
|
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- SHOT CONTROLLING ENTITY
--------------------------------------------------------------------------------
entity shot is
generic
(
res_x : integer := 15;
res_y : integer := 15;
aux_x : integer := 0;
aux_y : integer := 0;
flag_up : std_logic := '1';
clock_div : integer := 1
);
port
(
clock_i,
reset_i,
trigger_i : in std_logic;
position_x_i : in integer range 0 to res_x;
position_y_i : in integer range 0 to res_y;
enable_o : buffer std_logic;
position_x_o : buffer integer range 0 to res_x;
position_y_o : buffer integer range 0 to res_y
);
end entity;
architecture behavior of shot is
signal clock_s: std_logic;
begin
shot_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
shot_movement:
process (reset_i, trigger_i, clock_s, position_y_i, position_x_i)
variable trigger_v: std_logic := '0';
begin
trigger_v := trigger_i;
if reset_i = '1' then
enable_o <= '0';
trigger_v := '0';
position_y_o <= position_y_i;
position_x_o <= position_x_i+aux_x/2;
elsif rising_edge(clock_s) then
-- If triggered and there is no bullet in the screen
if trigger_v = '1' and enable_o = '0' then
enable_o <= '1';
trigger_v := '0';
position_y_o <= position_y_i;
position_x_o <= position_x_i+aux_x/2;
-- If the bullet is enabled
elsif enable_o = '1' and position_y_o > 0 and position_y_o < res_y then
-- player shoot
if flag_up = '1' then
position_y_o <= position_y_o - 1;
if position_y_o < 4 then
enable_o <= '0';
end if;
-- enemy shoot
else
position_y_o <= position_y_o + 1;
if position_y_o = res_y then
enable_o <= '0';
end if;
end if;
elsif trigger_v = '0' then
position_x_o <= 0; --
position_y_o <= 0;
enable_o <= '0';
else
position_x_o <= position_x_i+aux_x/2; --
position_y_o <= position_y_i; --
end if;
end if;
end process;
end architecture;
|
mit
|
SLongofono/Senior_Design_Capstone
|
Demo/config.vhd
|
1
|
30841
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector;
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
if(unsigned(word) < 10) then
return "0011" & word;
elsif(unsigned(word) = 11) then
return "01100001";
elsif(unsigned(word) = 12) then
return "01100010";
elsif(unsigned(word) = 13) then
return "01100011";
elsif(unsigned(word) = 14) then
return "01100100";
elsif(unsigned(word) = 15) then
return "01100100";
else
return "00110000";
end if;
end;
-- Takes an ASCII character and returns an integer value
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer is
begin
if(unsigned(word) > 47 AND unsigned(word) < 58) then
return to_integer(unsigned(word)) - 48;
elsif(unsigned(word) > 96 AND unsigned(word) < 103) then
-- We want to return 11 for a, 12 for b, so on
return to_integer(unsigned(word)) - 86;
else --Which happens when the user puts garbage in
return 99;
end if;
end;
end config;
|
mit
|
fabioperez/space-invaders-vhdl
|
lib/general/conv_7seg_int.vhd
|
1
|
654
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity conv_7seg_int is
port(digit: in integer;
seg: out std_logic_vector(6 downto 0));
end conv_7seg_int;
architecture Behavior of conv_7seg_int is
begin
with digit select
seg <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
"0110000" when 3,
"0011001" when 4,
"0010010" when 5,
"0000010" when 6,
"1111000" when 7,
"0000000" when 8,
"0010000" when 9,
"0001000" when 10,
"0000011" when 11,
"1000110" when 12,
"0100001" when 13,
"0000110" when 14,
"0001110" when 15,
"1000000" when others;
end Behavior;
|
mit
|
fabioperez/space-invaders-vhdl
|
lib/io/vgacon.vhd
|
1
|
15703
|
-------------------------------------------------------------------------------
-- Title : VGA Controller for DE1 boards
-- Project :
-------------------------------------------------------------------------------
-- File : vgacontop.vhd
-- Author : Rafael Auler
-- Company :
-- Created : 2010-03-21
-- Last update: 2010-03-26
-- Platform :
-- Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-03-21 1.0 Rafael Auler Created
-- 2010-03-26 1.1 Rafael Auler Working 64x60 display w/ internal mem.
-- 2010-03-26 1.2 Rafael Auler Working with arbitrary res. (up to
-- 640x480, tied to on-chip memory
-- availability). Defaults to 128x96.
-------------------------------------------------------------------------------
-- How sync signals are generated for 640x480
-- Note: sync signals are active low
-------------------------------------------------------------------------------
-- Horizontal sync:
-- -------------------__--------
-- | | | |
-- <----------->
-- 640
-- <---------------->
-- 660
-- <------------------->
-- 756
-- <-------------------------->
-- 800
-------------------------------------------------------------------------------
-- Vertical sync:
-- -----------------__-------
--
-- | | | |
-- <--------->
-- 480
-- <-------------->
-- 494
-- <----------------->
-- 495
-- <----------------------->
-- 525
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Notes:
-- write_clk, write_addr, write_enable and data_in are input signals used to
-- write to this controller memory and thus altering the displayed image on VGA.
--
-- "data_in" has 3 bits and represents a single image pixel.
-- (high bit for RED, middle for GREEN and lower for BLUE - total of 8 colors).
--
-- These signals follow simple memory write protocol (we=1 writes
-- data_in to address (pixel number) write_addr. This last signal may assume
-- NUM_HORZ_PIXELS * NUM_VERT_PIXELS different values, corresponding to each
-- one of the displayable pixels.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity vgacon is
generic (
-- When changing this, remember to keep 4:3 aspect ratio
-- Must also keep in mind that our native resolution is 640x480, and
-- you can't cross these bounds (although you will seldom have enough
-- on-chip memory to instantiate this module with higher res).
NUM_HORZ_PIXELS : natural := 128; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96); -- Number of vertical pixels
port (
clk27M, rstn : in std_logic;
write_clk, write_enable : in std_logic;
write_addr : in integer range 0 to
NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
data_in : in std_logic_vector(2 downto 0);
vga_clk : buffer std_logic; -- Ideally 25.175 MHz
red, green, blue : out std_logic_vector(3 downto 0);
hsync, vsync : out std_logic);
end vgacon;
architecture behav of vgacon is
-- Two signals: one is delayed by one clock cycle. The monitor control uses
-- the delayed one. We need a counter 1 clock cycle earlier, relative
-- to the monitor signal, in order to index the memory contents
-- for the next cycle, when the pixel is in fact sent to the monitor.
signal h_count, h_count_d : integer range 0 to 799; -- horizontal counter
signal v_count, v_count_d : integer range 0 to 524; -- vertical counter
-- We only want to address HORZ*VERT pixels in memory
signal read_addr : integer range 0 to NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
signal h_drawarea, v_drawarea, drawarea : std_logic;
signal data_out : std_logic_vector(2 downto 0);
begin -- behav
-- This is our PLL (Phase Locked Loop) to divide the DE1 27 MHz
-- clock and produce a 25.2MHz clock adequate to our VGA controller
divider: work.vga_pll port map (clk27M, vga_clk);
-- This is our dual clock RAM. We use our VGA clock to read contents from
-- memory (pixel color value). The user of this module may use any clock
-- to write contents to this memory, modifying pixels individually.
vgamem : work.dual_clock_ram
generic map (
MEMSIZE => NUM_HORZ_PIXELS * NUM_VERT_PIXELS)
port map (
read_clk => vga_clk,
write_clk => write_clk,
read_address => read_addr,
write_address => write_addr,
data_in => data_in,
data_out => data_out,
we => write_enable);
-- purpose: Increments the current horizontal position counter
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: h_count, h_count_d
horz_counter: process (vga_clk, rstn)
begin -- process horz_counter
if rstn = '0' then -- asynchronous reset (active low)
h_count <= 0;
h_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
h_count_d <= h_count; -- 1 clock cycle delayed counter
if h_count = 799 then
h_count <= 0;
else
h_count <= h_count + 1;
end if;
end if;
end process horz_counter;
-- purpose: Determines if we are in the horizontal "drawable" area
-- type : combinational
-- inputs : h_count_d
-- outputs: h_drawarea
horz_sync: process (h_count_d)
begin -- process horz_sync
if h_count_d < 640 then
h_drawarea <= '1';
else
h_drawarea <= '0';
end if;
end process horz_sync;
-- purpose: Increments the current vertical counter position
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: v_count, v_count_d
vert_counter: process (vga_clk, rstn)
begin -- process vert_counter
if rstn = '0' then -- asynchronous reset (active low)
v_count <= 0;
v_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
v_count_d <= v_count; -- 1 clock cycle delayed counter
if h_count = 699 then
if v_count = 524 then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
end if;
end if;
end process vert_counter;
-- purpose: Updates information based on vertical position
-- type : combinational
-- inputs : v_count_d
-- outputs: v_drawarea
vert_sync: process (v_count_d)
begin -- process vert_sync
if v_count_d < 480 then
v_drawarea <= '1';
else
v_drawarea <= '0';
end if;
end process vert_sync;
-- purpose: Generates synchronization signals
-- type : combinational
-- inputs : v_count_d, h_count_d
-- outputs: hsync, vsync
sync: process (v_count_d, h_count_d)
begin -- process sync
if (h_count_d >= 659) and (h_count_d <= 755) then
hsync <= '0';
else
hsync <= '1';
end if;
if (v_count_d >= 493) and (v_count_d <= 494) then
vsync <= '0';
else
vsync <= '1';
end if;
end process sync;
-- determines whether we are in drawable area on screen a.t.m.
drawarea <= v_drawarea and h_drawarea;
-- purpose: calculates the controller memory address to read pixel data
-- type : combinational
-- inputs : h_count, v_count
-- outputs: read_addr
gen_r_addr: process (h_count, v_count)
begin -- process gen_r_addr
read_addr <= h_count / (640 / NUM_HORZ_PIXELS)
+ ((v_count/(480 / NUM_VERT_PIXELS))
* NUM_HORZ_PIXELS);
end process gen_r_addr;
-- Build color signals based on memory output and "drawarea" signal
-- (if we are not in the drawable area of 640x480, must deassert all
-- color signals).
red <= (others => data_out(2) and drawarea);
green <= (others => data_out(1) and drawarea);
blue <= (others => data_out(0) and drawarea);
end behav;
-------------------------------------------------------------------------------
-- The following entity is a dual clock RAM (read operates at different
-- clock from write). This is used to isolate two clock domains. The first
-- is the 25.2 MHz clock domain in which our VGA controller needs to operate.
-- This is the read clock, because we read from this memory to determine
-- the color of a pixel. The second is the clock domain of the user of this
-- module, writing in the memory the contents it wants to display in the VGA.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dual_clock_ram is
generic (
MEMSIZE : natural);
port (
read_clk, write_clk : in std_logic; -- support different clocks
data_in : in std_logic_vector(2 downto 0);
write_address, read_address : in integer range 0 to MEMSIZE - 1;
we : in std_logic; -- write enable
data_out : out std_logic_vector(2 downto 0));
end dual_clock_ram;
architecture behav of dual_clock_ram is
-- we only want to address (store) MEMSIZE elements
subtype addr is integer range 0 to MEMSIZE - 1;
type mem is array (addr) of std_logic_vector(2 downto 0);
signal ram_block : mem;
-- we don't care with read after write behavior (whether ram reads
-- old or new data in the same cycle).
attribute ramstyle : string;
attribute ramstyle of dual_clock_ram : entity is "no_rw_check";
--attribute ram_init_file : string;
--attribute ram_init_file of ram_block : signal is "vga_mem.mif";
begin -- behav
-- purpose: Reads data from RAM
-- type : sequential
-- inputs : read_clk, read_address
-- outputs: data_out
read: process (read_clk)
begin -- process read
if read_clk'event and read_clk = '1' then -- rising clock edge
data_out <= ram_block(read_address);
end if;
end process read;
-- purpose: Writes data to RAM
-- type : sequential
-- inputs : write_clk, write_address
-- outputs: ram_block
write: process (write_clk)
begin -- process write
if write_clk'event and write_clk = '1' then -- rising clock edge
if we = '1' then
ram_block(write_address) <= data_in;
end if;
end if;
end process write;
end behav;
-------------------------------------------------------------------------------
-- The following entity is automatically generated by Quartus (a megafunction).
-- As Altera DE1 board does not have a 25.175 MHz, but a 27 Mhz, we
-- instantiate a PLL (Phase Locked Loop) to divide out 27 MHz clock
-- and reach a satisfiable 25.2MHz clock for our VGA controller (14/15 ratio)
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vga_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END vga_pll;
ARCHITECTURE SYN OF vga_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 15,
clk0_duty_cycle => 50,
clk0_multiply_by => 14,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=vga_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
|
mit
|
fabioperez/space-invaders-vhdl
|
lib/io/kbd_input.vhd
|
1
|
3269
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lib;
USE lib.io.all;
entity kbd_input is
port
(
clock_i : in std_logic;
reset_i : in std_logic;
hold_i : in std_logic;
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
shot_o : buffer std_logic;
move_o : buffer std_logic;
control_o : buffer std_logic_vector(2 downto 0)
);
end;
architecture struct of kbd_input is
component kbdex_ctrl
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
lights : in std_logic_vector(2 downto 0); -- lights(Caps, Nun, Scroll)
key_on : out std_logic_vector(2 downto 0);
key_code : out std_logic_vector(47 downto 0)
);
end component;
signal CLOCKHZ, resetn : std_logic;
signal keys : std_logic_vector(31 downto 0);
signal control_s1, control_s2 : std_logic_vector(2 downto 0);
signal lights : std_logic_vector(2 downto 0);
begin
resetn <= reset_i;
kbd_ctrl : kbdex_ctrl generic map(24000) port map(
PS2_DAT, PS2_CLK, clock_i, hold_i, resetn, lights,
open, key_code(31 downto 0) => keys
);
-- Clock divider
process(clock_i)
constant F_HZ : integer := 5;
constant DIVIDER : integer := 24000000/F_HZ;
variable count : integer range 0 to DIVIDER := 0;
begin
if rising_edge(clock_i) then
if count < DIVIDER / 2 then
CLOCKHZ <= '1';
else
CLOCKHZ <= '0';
end if;
if count = DIVIDER then
count := 0;
end if;
count := count + 1;
end if;
end process;
---------------------------------------------
-- MUX FOR KEYBOARD CONTROL --
-- NUMERIC KEYPAD:
-- 4: Move left
-- 5: Shoot
-- 6: Move right
-- SPACE: Shoot
-- This component can handle two commands at
-- the same time, such as a movement key and
-- a shooting key.
---------------------------------------------
-- MUX for the first pressed key
with keys(15 downto 0) select
control_s1 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
-- MUX for the second pressed key
with keys(31 downto 16) select
control_s2 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
shot_o <= control_s1(1) or control_s2(1); -- Shot
move_o <= (control_s1(2) or control_s1(0)) xor (control_s2(2) or control_s2(0)); -- Movement
control_o <= control_s1 xor control_s2; -- Controls
end struct;
|
mit
|
fabioperez/space-invaders-vhdl
|
lib/io/ps2_iobase.vhd
|
1
|
6163
|
-------------------------------------------------------------------------------
-- Title : MC613
-- Project : PS2 Basic Protocol
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : ps2_base.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/04/12
-------------------------------------------------------------------------------
-- Description:
-- PS2 basic control
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity ps2_iobase is
generic(
clkfreq : integer -- This is the system clock value in kHz
);
port(
ps2_data : inout std_logic; -- PS2 data pin
ps2_clk : inout std_logic; -- PS2 clock pin
clk : in std_logic; -- system clock (same frequency as defined in
-- 'clkfreq' generic)
en : in std_logic; -- Enable
resetn : in std_logic; -- Reset when '0'
idata_rdy : in std_logic; -- Rise this to signal data is ready to be sent
-- to device
idata : in std_logic_vector(7 downto 0); -- Data to be sent to device
send_rdy : out std_logic; -- '1' if data can be sent to device (wait for
-- this before rising 'idata_rdy'
odata_rdy : out std_logic; -- '1' when data from device has arrived
odata : out std_logic_vector(7 downto 0) -- Data from device
);
end;
architecture rtl of ps2_iobase is
constant CLKSSTABLE : integer := clkfreq / 150;
signal sdata, hdata : std_logic_vector(7 downto 0);
signal sigtrigger, parchecked, sigsending,
sigsendend, sigclkreleased, sigclkheld : std_logic;
begin
-- Trigger for state change to eliminate noise
process(clk, ps2_clk, en, resetn)
variable fcount, rcount : integer range CLKSSTABLE downto 0;
begin
if(rising_edge(clk) and en = '1') then
-- Falling edge noise
if ps2_clk = '0' then
rcount := 0;
if fcount >= CLKSSTABLE then
sigtrigger <= '1';
else
fcount := fcount + 1;
end if;
-- Rising edge noise
elsif ps2_clk = '1' then
fcount := 0;
if rcount >= CLKSSTABLE then
sigtrigger <= '0';
else
rcount := rcount + 1;
end if;
end if;
end if;
if resetn = '0' then
fcount := 0;
rcount := 0;
sigtrigger <= '0';
end if;
end process;
FROMPS2:
process(sigtrigger, sigsending, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigsending = '0') then
if count > 0 and count < 9 then
sdata(count - 1) <= ps2_data;
end if;
if count = 9 then
if (not (sdata(0) xor sdata(1) xor sdata(2) xor sdata(3)
xor sdata(4) xor sdata(5) xor sdata(6) xor sdata(7))) = ps2_data then
parchecked <= '1';
else
parchecked <= '0';
end if;
end if;
count := count + 1;
if count = 11 then
count := 0;
parchecked <= '0';
end if;
end if;
if resetn = '0' or sigsending = '1' then
sdata <= (others => '0');
parchecked <= '0';
count := 0;
end if;
end process;
odata_rdy <= en and parchecked;
odata <= sdata;
-- Edge triggered send register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
sigsending <= '1';
end if;
if resetn = '0' or sigsendend = '1' then
sigsending <= '0';
end if;
end process;
-- Wait for at least 11ms before allowing to send again
process(clk, sigsending, resetn)
-- clkfreq is the number of clocks within a milisecond
variable countclk : integer range 0 to (12 * clkfreq);
begin
if(rising_edge(clk) and sigsending = '0') then
if countclk = (11 * clkfreq) then
send_rdy <= '1';
else
countclk := countclk + 1;
end if;
end if;
if sigsending = '1' then
send_rdy <= '0';
countclk := 0;
end if;
if resetn = '0' then
send_rdy <= '1';
countclk := 0;
end if;
end process;
-- Host input data register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
hdata <= idata;
end if;
if resetn = '0' or sigsendend = '1' then
hdata <= (others => '0');
end if;
end process;
-- PS2 clock control
process(clk, sigsendend, resetn)
constant US100CNT : integer := clkfreq / 10;
variable count : integer range 0 to US100CNT + 101;
begin
if(rising_edge(clk) and sigsending = '1') then
if count < US100CNT + 50 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '0';
elsif count < US100CNT + 100 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '1';
else
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
end if;
end if;
if resetn = '0' or sigsendend = '1' then
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
count := 0;
end if;
end process;
-- Sending control
TOPS2:
process(sigtrigger, sigsending, sigclkheld, sigclkreleased, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigclkreleased = '1'
and sigsending = '1') then
if count >= 0 and count < 8 then
ps2_data <= hdata(count);
sigsendend <= '0';
end if;
if count = 8 then
ps2_data <= (not (hdata(0) xor hdata(1) xor hdata(2) xor hdata(3)
xor hdata(4) xor hdata(5) xor hdata(6) xor hdata(7)));
sigsendend <= '0';
end if;
if count = 9 then
ps2_data <= 'Z';
sigsendend <= '0';
end if;
if count = 10 then
ps2_data <= 'Z';
sigsendend <= '1';
count := 0;
end if;
count := count + 1;
end if;
if sigclkheld = '1' then
ps2_data <= '0';
sigsendend <= '0';
count := 0;
end if;
if resetn = '0' or sigsending = '0' then
ps2_data <= 'Z';
sigsendend <= '0';
count := 0;
end if;
end process;
end rtl;
|
mit
|
tcsiwula/java_code
|
classes/cs345/code_examples/antlr_github_copy/grammars/vhdl/examples/std_logic_1164.vhd
|
6
|
9546
|
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; --V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector; --V93
FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;--V93
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
|
mit
|
SLongofono/Senior_Design_Capstone
|
Demo/Shifter.vhd
|
1
|
20681
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Left/Right shifter arithmetic/logic 32/64 bits.
--!
--! @details Vivado synthesizer (2016.2) doesn't support shift
--! from dynamic value, so implement this mux.
-- Modified to remove custom types.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library config;
use work.config.all;
entity Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end;
architecture arch_Shifter of Shifter is
signal o_sll : doubleword;
signal o_sllw : doubleword;
signal o_srl : doubleword;
signal o_sra : doubleword;
signal o_srlw : doubleword;
signal o_sraw : doubleword;
begin
comb : process(clk) -- not edge sensitive to ensure result is ready at next rising edge
variable wb_sll : std_logic_vector(63 downto 0);
variable wb_srl : std_logic_vector(63 downto 0);
variable wb_sra : std_logic_vector(63 downto 0);
variable wb_srlw : std_logic_vector(31 downto 0);
variable wb_sraw : std_logic_vector(63 downto 0);
variable v64 : std_logic_vector(63 downto 0);
variable v32 : std_logic_vector(31 downto 0);
variable msk64 : std_logic_vector(63 downto 0);
variable msk32 : std_logic_vector(63 downto 0);
variable shift64 : integer range 0 to 63;
variable shift32 : integer range 0 to 31;
begin
v64 := i_a1;
v32 := i_a1(31 downto 0);
msk64 := (others => i_a1(63));
msk32 := (others => i_a1(31));
shift64 := to_integer(unsigned(i_a2));
shift32 := to_integer(unsigned(i_a2(4 downto 0)));
case shift64 is
when 0 =>
wb_sll := v64;
wb_srl := v64;
wb_sra := v64;
when 1 =>
wb_sll := v64(62 downto 0) & "0";
wb_srl := "0" & v64(63 downto 1);
wb_sra := (msk64(63 downto 63) & v64(63 downto 1));
when 2 =>
wb_sll := v64(61 downto 0) & "00";
wb_srl := "00" & v64(63 downto 2);
wb_sra := (msk64(63 downto 62) & v64(63 downto 2));
when 3 =>
wb_sll := v64(60 downto 0) & "000";
wb_srl := "000" & v64(63 downto 3);
wb_sra := (msk64(63 downto 61) & v64(63 downto 3));
when 4 =>
wb_sll := v64(59 downto 0) & X"0";
wb_srl := X"0" & v64(63 downto 4);
wb_sra := (msk64(63 downto 60) & v64(63 downto 4));
when 5 =>
wb_sll := v64(58 downto 0) & X"0" & "0";
wb_srl := X"0" & "0" & v64(63 downto 5);
wb_sra := (msk64(63 downto 59) & v64(63 downto 5));
when 6 =>
wb_sll := v64(57 downto 0) & X"0" & "00";
wb_srl := X"0" & "00" & v64(63 downto 6);
wb_sra := (msk64(63 downto 58) & v64(63 downto 6));
when 7 =>
wb_sll := v64(56 downto 0) & X"0" & "000";
wb_srl := X"0" & "000" & v64(63 downto 7);
wb_sra := (msk64(63 downto 57) & v64(63 downto 7));
when 8 =>
wb_sll := v64(55 downto 0) & X"00";
wb_srl := X"00" & v64(63 downto 8);
wb_sra := (msk64(63 downto 56) & v64(63 downto 8));
when 9 =>
wb_sll := v64(54 downto 0) & X"00" & "0";
wb_srl := X"00" & "0" & v64(63 downto 9);
wb_sra := (msk64(63 downto 55) & v64(63 downto 9));
when 10 =>
wb_sll := v64(53 downto 0) & X"00" & "00";
wb_srl := X"00" & "00" & v64(63 downto 10);
wb_sra := (msk64(63 downto 54) & v64(63 downto 10));
when 11 =>
wb_sll := v64(52 downto 0) & X"00" & "000";
wb_srl := X"00" & "000" & v64(63 downto 11);
wb_sra := (msk64(63 downto 53) & v64(63 downto 11));
when 12 =>
wb_sll := v64(51 downto 0) & X"000";
wb_srl := X"000" & v64(63 downto 12);
wb_sra := (msk64(63 downto 52) & v64(63 downto 12));
when 13 =>
wb_sll := v64(50 downto 0) & X"000" & "0";
wb_srl := X"000" & "0" & v64(63 downto 13);
wb_sra := (msk64(63 downto 51) & v64(63 downto 13));
when 14 =>
wb_sll := v64(49 downto 0) & X"000" & "00";
wb_srl := X"000" & "00" & v64(63 downto 14);
wb_sra := (msk64(63 downto 50) & v64(63 downto 14));
when 15 =>
wb_sll := v64(48 downto 0) & X"000" & "000";
wb_srl := X"000" & "000" & v64(63 downto 15);
wb_sra := (msk64(63 downto 49) & v64(63 downto 15));
when 16 =>
wb_sll := v64(47 downto 0) & X"0000";
wb_srl := X"0000" & v64(63 downto 16);
wb_sra := (msk64(63 downto 48) & v64(63 downto 16));
when 17 =>
wb_sll := v64(46 downto 0) & X"0000" & "0";
wb_srl := X"0000" & "0" & v64(63 downto 17);
wb_sra := (msk64(63 downto 47) & v64(63 downto 17));
when 18 =>
wb_sll := v64(45 downto 0) & X"0000" & "00";
wb_srl := X"0000" & "00" & v64(63 downto 18);
wb_sra := (msk64(63 downto 46) & v64(63 downto 18));
when 19 =>
wb_sll := v64(44 downto 0) & X"0000" & "000";
wb_srl := X"0000" & "000" & v64(63 downto 19);
wb_sra := (msk64(63 downto 45) & v64(63 downto 19));
when 20 =>
wb_sll := v64(43 downto 0) & X"00000";
wb_srl := X"00000" & v64(63 downto 20);
wb_sra := (msk64(63 downto 44) & v64(63 downto 20));
when 21 =>
wb_sll := v64(42 downto 0) & X"00000" & "0";
wb_srl := X"00000" & "0" & v64(63 downto 21);
wb_sra := (msk64(63 downto 43) & v64(63 downto 21));
when 22 =>
wb_sll := v64(41 downto 0) & X"00000" & "00";
wb_srl := X"00000" & "00" & v64(63 downto 22);
wb_sra := (msk64(63 downto 42) & v64(63 downto 22));
when 23 =>
wb_sll := v64(40 downto 0) & X"00000" & "000";
wb_srl := X"00000" & "000" & v64(63 downto 23);
wb_sra := (msk64(63 downto 41) & v64(63 downto 23));
when 24 =>
wb_sll := v64(39 downto 0) & X"000000";
wb_srl := X"000000" & v64(63 downto 24);
wb_sra := (msk64(63 downto 40) & v64(63 downto 24));
when 25 =>
wb_sll := v64(38 downto 0) & X"000000" & "0";
wb_srl := X"000000" & "0" & v64(63 downto 25);
wb_sra := (msk64(63 downto 39) & v64(63 downto 25));
when 26 =>
wb_sll := v64(37 downto 0) & X"000000" & "00";
wb_srl := X"000000" & "00" & v64(63 downto 26);
wb_sra := (msk64(63 downto 38) & v64(63 downto 26));
when 27 =>
wb_sll := v64(36 downto 0) & X"000000" & "000";
wb_srl := X"000000" & "000" & v64(63 downto 27);
wb_sra := (msk64(63 downto 37) & v64(63 downto 27));
when 28 =>
wb_sll := v64(35 downto 0) & X"0000000";
wb_srl := X"0000000" & v64(63 downto 28);
wb_sra := (msk64(63 downto 36) & v64(63 downto 28));
when 29 =>
wb_sll := v64(34 downto 0) & X"0000000" & "0";
wb_srl := X"0000000" & "0" & v64(63 downto 29);
wb_sra := (msk64(63 downto 35) & v64(63 downto 29));
when 30 =>
wb_sll := v64(33 downto 0) & X"0000000" & "00";
wb_srl := X"0000000" & "00" & v64(63 downto 30);
wb_sra := (msk64(63 downto 34) & v64(63 downto 30));
when 31 =>
wb_sll := v64(32 downto 0) & X"0000000" & "000";
wb_srl := X"0000000" & "000" & v64(63 downto 31);
wb_sra := (msk64(63 downto 33) & v64(63 downto 31));
when 32 =>
wb_sll := v64(31 downto 0) & X"00000000";
wb_srl := X"00000000" & v64(63 downto 32);
wb_sra := (msk64(63 downto 32) & v64(63 downto 32));
when 33 =>
wb_sll := v64(30 downto 0) & X"00000000" & "0";
wb_srl := X"00000000" & "0" & v64(63 downto 33);
wb_sra := (msk64(63 downto 31) & v64(63 downto 33));
when 34 =>
wb_sll := v64(29 downto 0) & X"00000000" & "00";
wb_srl := X"00000000" & "00" & v64(63 downto 34);
wb_sra := (msk64(63 downto 30) & v64(63 downto 34));
when 35 =>
wb_sll := v64(28 downto 0) & X"00000000" & "000";
wb_srl := X"00000000" & "000" & v64(63 downto 35);
wb_sra := (msk64(63 downto 29) & v64(63 downto 35));
when 36 =>
wb_sll := v64(27 downto 0) & X"000000000";
wb_srl := X"000000000" & v64(63 downto 36);
wb_sra := (msk64(63 downto 28) & v64(63 downto 36));
when 37 =>
wb_sll := v64(26 downto 0) & X"000000000" & "0";
wb_srl := X"000000000" & "0" & v64(63 downto 37);
wb_sra := (msk64(63 downto 27) & v64(63 downto 37));
when 38 =>
wb_sll := v64(25 downto 0) & X"000000000" & "00";
wb_srl := X"000000000" & "00" & v64(63 downto 38);
wb_sra := (msk64(63 downto 26) & v64(63 downto 38));
when 39 =>
wb_sll := v64(24 downto 0) & X"000000000" & "000";
wb_srl := X"000000000" & "000" & v64(63 downto 39);
wb_sra := (msk64(63 downto 25) & v64(63 downto 39));
when 40 =>
wb_sll := v64(23 downto 0) & X"0000000000";
wb_srl := X"0000000000" & v64(63 downto 40);
wb_sra := (msk64(63 downto 24) & v64(63 downto 40));
when 41 =>
wb_sll := v64(22 downto 0) & X"0000000000" & "0";
wb_srl := X"0000000000" & "0" & v64(63 downto 41);
wb_sra := (msk64(63 downto 23) & v64(63 downto 41));
when 42 =>
wb_sll := v64(21 downto 0) & X"0000000000" & "00";
wb_srl := X"0000000000" & "00" & v64(63 downto 42);
wb_sra := (msk64(63 downto 22) & v64(63 downto 42));
when 43 =>
wb_sll := v64(20 downto 0) & X"0000000000" & "000";
wb_srl := X"0000000000" & "000" & v64(63 downto 43);
wb_sra := (msk64(63 downto 21) & v64(63 downto 43));
when 44 =>
wb_sll := v64(19 downto 0) & X"00000000000";
wb_srl := X"00000000000" & v64(63 downto 44);
wb_sra := (msk64(63 downto 20) & v64(63 downto 44));
when 45 =>
wb_sll := v64(18 downto 0) & X"00000000000" & "0";
wb_srl := X"00000000000" & "0" & v64(63 downto 45);
wb_sra := (msk64(63 downto 19) & v64(63 downto 45));
when 46 =>
wb_sll := v64(17 downto 0) & X"00000000000" & "00";
wb_srl := X"00000000000" & "00" & v64(63 downto 46);
wb_sra := (msk64(63 downto 18) & v64(63 downto 46));
when 47 =>
wb_sll := v64(16 downto 0) & X"00000000000" & "000";
wb_srl := X"00000000000" & "000" & v64(63 downto 47);
wb_sra := (msk64(63 downto 17) & v64(63 downto 47));
when 48 =>
wb_sll := v64(15 downto 0) & X"000000000000";
wb_srl := X"000000000000" & v64(63 downto 48);
wb_sra := (msk64(63 downto 16) & v64(63 downto 48));
when 49 =>
wb_sll := v64(14 downto 0) & X"000000000000" & "0";
wb_srl := X"000000000000" & "0" & v64(63 downto 49);
wb_sra := (msk64(63 downto 15) & v64(63 downto 49));
when 50 =>
wb_sll := v64(13 downto 0) & X"000000000000" & "00";
wb_srl := X"000000000000" & "00" & v64(63 downto 50);
wb_sra := (msk64(63 downto 14) & v64(63 downto 50));
when 51 =>
wb_sll := v64(12 downto 0) & X"000000000000" & "000";
wb_srl := X"000000000000" & "000" & v64(63 downto 51);
wb_sra := (msk64(63 downto 13) & v64(63 downto 51));
when 52 =>
wb_sll := v64(11 downto 0) & X"0000000000000";
wb_srl := X"0000000000000" & v64(63 downto 52);
wb_sra := (msk64(63 downto 12) & v64(63 downto 52));
when 53 =>
wb_sll := v64(10 downto 0) & X"0000000000000" & "0";
wb_srl := X"0000000000000" & "0" & v64(63 downto 53);
wb_sra := (msk64(63 downto 11) & v64(63 downto 53));
when 54 =>
wb_sll := v64(9 downto 0) & X"0000000000000" & "00";
wb_srl := X"0000000000000" & "00" & v64(63 downto 54);
wb_sra := (msk64(63 downto 10) & v64(63 downto 54));
when 55 =>
wb_sll := v64(8 downto 0) & X"0000000000000" & "000";
wb_srl := X"0000000000000" & "000" & v64(63 downto 55);
wb_sra := (msk64(63 downto 9) & v64(63 downto 55));
when 56 =>
wb_sll := v64(7 downto 0) & X"00000000000000";
wb_srl := X"00000000000000" & v64(63 downto 56);
wb_sra := (msk64(63 downto 8) & v64(63 downto 56));
when 57 =>
wb_sll := v64(6 downto 0) & X"00000000000000" & "0";
wb_srl := X"00000000000000" & "0" & v64(63 downto 57);
wb_sra := (msk64(63 downto 7) & v64(63 downto 57));
when 58 =>
wb_sll := v64(5 downto 0) & X"00000000000000" & "00";
wb_srl := X"00000000000000" & "00" & v64(63 downto 58);
wb_sra := (msk64(63 downto 6) & v64(63 downto 58));
when 59 =>
wb_sll := v64(4 downto 0) & X"00000000000000" & "000";
wb_srl := X"00000000000000" & "000" & v64(63 downto 59);
wb_sra := (msk64(63 downto 5) & v64(63 downto 59));
when 60 =>
wb_sll := v64(3 downto 0) & X"000000000000000";
wb_srl := X"000000000000000" & v64(63 downto 60);
wb_sra := (msk64(63 downto 4) & v64(63 downto 60));
when 61 =>
wb_sll := v64(2 downto 0) & X"000000000000000" & "0";
wb_srl := X"000000000000000" & "0" & v64(63 downto 61);
wb_sra := (msk64(63 downto 3) & v64(63 downto 61));
when 62 =>
wb_sll := v64(1 downto 0) & X"000000000000000" & "00";
wb_srl := X"000000000000000" & "00" & v64(63 downto 62);
wb_sra := (msk64(63 downto 2) & v64(63 downto 62));
when 63 =>
wb_sll := v64(0) & X"000000000000000" & "000";
wb_srl := X"000000000000000" & "000" & v64(63);
wb_sra := (msk64(63 downto 1) & v64(63));
when others =>
wb_sll := (others => '0');
wb_srl := (others => '0');
wb_sra := (others => '0');
end case;
case shift32 is
when 0 =>
wb_srlw := v32;
wb_sraw := (msk32(63 downto 32) & v32);
when 1 =>
wb_srlw := "0" & v32(31 downto 1);
wb_sraw := (msk32(63 downto 31) & v32(31 downto 1));
when 2 =>
wb_srlw := "00" & v32(31 downto 2);
wb_sraw := (msk32(63 downto 30) & v32(31 downto 2));
when 3 =>
wb_srlw := "000" & v32(31 downto 3);
wb_sraw := (msk32(63 downto 29) & v32(31 downto 3));
when 4 =>
wb_srlw := X"0" & v32(31 downto 4);
wb_sraw := (msk32(63 downto 28) & v32(31 downto 4));
when 5 =>
wb_srlw := X"0" & "0" & v32(31 downto 5);
wb_sraw := (msk32(63 downto 27) & v32(31 downto 5));
when 6 =>
wb_srlw := X"0" & "00" & v32(31 downto 6);
wb_sraw := (msk32(63 downto 26) & v32(31 downto 6));
when 7 =>
wb_srlw := X"0" & "000" & v32(31 downto 7);
wb_sraw := (msk32(63 downto 25) & v32(31 downto 7));
when 8 =>
wb_srlw := X"00" & v32(31 downto 8);
wb_sraw := (msk32(63 downto 24) & v32(31 downto 8));
when 9 =>
wb_srlw := X"00" & "0" & v32(31 downto 9);
wb_sraw := (msk32(63 downto 23) & v32(31 downto 9));
when 10 =>
wb_srlw := X"00" & "00" & v32(31 downto 10);
wb_sraw := (msk32(63 downto 22) & v32(31 downto 10));
when 11 =>
wb_srlw := X"00" & "000" & v32(31 downto 11);
wb_sraw := (msk32(63 downto 21) & v32(31 downto 11));
when 12 =>
wb_srlw := X"000" & v32(31 downto 12);
wb_sraw := (msk32(63 downto 20) & v32(31 downto 12));
when 13 =>
wb_srlw := X"000" & "0" & v32(31 downto 13);
wb_sraw := (msk32(63 downto 19) & v32(31 downto 13));
when 14 =>
wb_srlw := X"000" & "00" & v32(31 downto 14);
wb_sraw := (msk32(63 downto 18) & v32(31 downto 14));
when 15 =>
wb_srlw := X"000" & "000" & v32(31 downto 15);
wb_sraw := (msk32(63 downto 17) & v32(31 downto 15));
when 16 =>
wb_srlw := X"0000" & v32(31 downto 16);
wb_sraw := (msk32(63 downto 16) & v32(31 downto 16));
when 17 =>
wb_srlw := X"0000" & "0" & v32(31 downto 17);
wb_sraw := (msk32(63 downto 15) & v32(31 downto 17));
when 18 =>
wb_srlw := X"0000" & "00" & v32(31 downto 18);
wb_sraw := (msk32(63 downto 14) & v32(31 downto 18));
when 19 =>
wb_srlw := X"0000" & "000" & v32(31 downto 19);
wb_sraw := (msk32(63 downto 13) & v32(31 downto 19));
when 20 =>
wb_srlw := X"00000" & v32(31 downto 20);
wb_sraw := (msk32(63 downto 12) & v32(31 downto 20));
when 21 =>
wb_srlw := X"00000" & "0" & v32(31 downto 21);
wb_sraw := (msk32(63 downto 11) & v32(31 downto 21));
when 22 =>
wb_srlw := X"00000" & "00" & v32(31 downto 22);
wb_sraw := (msk32(63 downto 10) & v32(31 downto 22));
when 23 =>
wb_srlw := X"00000" & "000" & v32(31 downto 23);
wb_sraw := (msk32(63 downto 9) & v32(31 downto 23));
when 24 =>
wb_srlw := X"000000" & v32(31 downto 24);
wb_sraw := (msk32(63 downto 8) & v32(31 downto 24));
when 25 =>
wb_srlw := X"000000" & "0" & v32(31 downto 25);
wb_sraw := (msk32(63 downto 7) & v32(31 downto 25));
when 26 =>
wb_srlw := X"000000" & "00" & v32(31 downto 26);
wb_sraw := (msk32(63 downto 6) & v32(31 downto 26));
when 27 =>
wb_srlw := X"000000" & "000" & v32(31 downto 27);
wb_sraw := (msk32(63 downto 5) & v32(31 downto 27));
when 28 =>
wb_srlw := X"0000000" & v32(31 downto 28);
wb_sraw := (msk32(63 downto 4) & v32(31 downto 28));
when 29 =>
wb_srlw := X"0000000" & "0" & v32(31 downto 29);
wb_sraw := (msk32(63 downto 3) & v32(31 downto 29));
when 30 =>
wb_srlw := X"0000000" & "00" & v32(31 downto 30);
wb_sraw := (msk32(63 downto 2) & v32(31 downto 30));
when 31 =>
wb_srlw := X"0000000" & "000" & v32(31 downto 31);
wb_sraw := (msk32(63 downto 1) & v32(31 downto 31));
when others =>
wb_srlw := (others => '0');
wb_sraw := (others => '0');
end case;
o_sll <= wb_sll;
o_sllw(31 downto 0) <= wb_sll(31 downto 0);
o_sllw(63 downto 32) <= (others => wb_sll(31));
o_srl <= wb_srl;
o_sra <= wb_sra;
o_srlw <= X"00000000" & wb_srlw;
o_sraw <= wb_sraw;
end process;
result <= o_sll when ctrl = instr_SLL or ctrl = instr_SLLI else
o_srl when ctrl = instr_SRL or ctrl = instr_SRLI else
o_sra when ctrl = instr_SRA or ctrl = instr_SRAI else
o_sllw when ctrl = instr_SLLW or ctrl = instr_SLLIW else
o_srlw when ctrl = instr_SRLW or ctrl = instr_SRLIW else
o_sraw when ctrl = instr_SRAW or ctrl = instr_SRAIW else
(others => '0');
end;
|
mit
|
SLongofono/Senior_Design_Capstone
|
Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ddr.vhd
|
1
|
9704
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Wrapper module for the user design top level file. This module can be
-- instantiated in the system and interconnect as shown in example design
-- (example_top module).
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end entity ddr;
architecture arch_ddr of ddr is
-- Start of IP top component
component ddr_mig
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr_mig;
-- End of IP top component
begin
-- Start of IP top instance
u_ddr_mig : ddr_mig
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_ref_req => app_ref_req,
app_zq_req => app_zq_req,
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of IP top instance
end architecture arch_ddr;
|
mit
|
ziweiwu/ziweiwu.github.io
|
vendor/cache/ruby/2.4.0/gems/pygments.rb-0.6.3/vendor/pygments-main/tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
mit
|
SLongofono/Senior_Design_Capstone
|
Demo/RAM_Controller.vhd
|
1
|
8148
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
write, read: in STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
component ram2ddrxadc
port(
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
-- The RAM is accessing 2 bytes per access
ram_a : in std_logic_vector(26 downto 0); -- input address
ram_dq_i : in std_logic_vector(15 downto 0); -- input data
ram_dq_o : out std_logic_vector(15 downto 0); -- output data
ram_cen : in std_logic; -- chip enable
ram_oen : in std_logic; -- output enable
ram_wen : in std_logic; -- write enable
ram_ub : in std_logic; -- upper byte
ram_lb : in std_logic; -- lower byte
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
-- Physical RAM Pin Signals
signal ram_cen, ram_oen, ram_wen, ram_ub, ram_lb: std_logic;
signal ram_dq_o, ram_dq_i: std_logic_vector (15 downto 0);
type memory_states IS (IDLE_STATE, PREPARE_STATE, READ_STATE, WRITE_STATE, INTERMITENT_STATE);
-- Where current state and next_state are pretty self-forward, last state will check
signal current_state, next_state, last_state: memory_states := IDLE_STATE;
signal temp_data_write, temp_data_read: std_logic_vector(63 downto 0);
signal ram_a: std_logic_vector(26 downto 0);
-- Result
signal read_out: std_logic_vector(15 downto 0) := (others => '0');
-- Counters
signal hundred_nano_seconds_elapsed, wait_counter : integer range 0 to 150 := 0;
signal s_read : std_logic := '0';
signal writeOnce, readOnce : std_logic := '0';
begin
ram2ddr: ram2ddrxadc
port map(
clk_200MHz_i=>clk_200,
rst_i=>rst,
device_temp_i=>"000000000000",
ram_a=>ram_a,
ram_dq_i=>ram_dq_o,
ram_dq_o=>ram_dq_i,
ram_cen=>ram_cen,
ram_oen=>ram_oen,
ram_wen=>ram_wen,
ram_ub=>ram_ub,
ram_lb=>ram_lb,
ddr2_addr=>ddr2_addr,
ddr2_ba=>ddr2_ba,
ddr2_ras_n=>ddr2_ras_n,
ddr2_cas_n=>ddr2_cas_n,
ddr2_we_n=>ddr2_we_n,
ddr2_ck_p=>ddr2_ck_p,
ddr2_ck_n=>ddr2_ck_n,
ddr2_cke=>ddr2_cke,
ddr2_cs_n=>ddr2_cs_n,
ddr2_dm=>ddr2_dm,
ddr2_odt=>ddr2_odt,
ddr2_dq=>ddr2_dq,
ddr2_dqs_p=>ddr2_dqs_p,
ddr2_dqs_n=>ddr2_dqs_n
);
process(clk_100,rst) begin
if(rst = '1') then
current_state <= IDLE_STATE;
elsif(rising_edge(clk_100)) then
current_state <= next_state;
end if;
end process;
process(current_state, rst, clk_100) begin
if(rst = '1') then
read_out <= (others => '0');
readOnce <= '0';
writeOnce <= '0';
elsif(rising_edge(clk_100)) then
next_state <= current_state;
case current_state is
-- State IDLE_STATE: Disable chip enable, write and read
when IDLE_STATE =>
ram_cen <= '1';
ram_oen <= '1';
ram_wen <= '1';
if(read = '1') then
s_read <= '1';
next_state <= PREPARE_STATE;
elsif(write = '1') then
s_read <= '0';
next_state <= PREPARE_STATE;
end if;
-- State PREPARE_STATE: Assert whatever needs to be asserted
when PREPARE_STATE =>
-- Reset the counters
hundred_nano_seconds_elapsed <= 0;
wait_counter <= 0;
-- Read
if(s_read = '1') then
readOnce <= '1';
ram_oen <= '0';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '1';
next_state <= READ_STATE;
-- Write
else
writeOnce <= '1';
ram_oen <= '1';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '0';
next_state <= WRITE_STATE;
end if;
-- State READ_STATE: Waits until the delta time indicated by the
-- data sheet has elapsed to finish reading
when READ_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
-- Wait till the necessary clock cycles elapsed while it's recording the data
if(hundred_nano_seconds_elapsed > 22) then
read_out <= ram_dq_i;
next_state <= INTERMITENT_STATE;
end if;
-- Once we're at the write state, the upper and lower byte masks had been asserted
-- to start writing, after which we are free to select the mask combination we need.
when WRITE_STATE =>
ram_lb <= mask_lb;
ram_ub <= mask_ub;
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
if(hundred_nano_seconds_elapsed > 27) then
next_state <= INTERMITENT_STATE;
-- Dummy read_out to signal we are done writing
read_out <= (5 => '1', others => '0');
end if;
-- State INTERMITENT_STATE: The done flag will be raised to allow the MMU
-- to continue onto the next byte
when INTERMITENT_STATE =>
read_out <= ram_dq_i;
next_state <= IDLE_STATE;
when others =>
next_state <= IDLE_STATE;
end case;
end if;
end process;
ram_dq_o <= data_in;
ram_a <= contr_addr_in;
data_out <= read_out;
done <= '1' when current_state = INTERMITENT_STATE else '0';
end Behavioral;
|
mit
|
SLongofono/Senior_Design_Capstone
|
solid_C/MMU.vhd
|
1
|
27386
|
----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MMU is
Port(
clk_100: in std_logic; -- 100 Mhz Clock
clk: in std_logic;
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
r_type: in std_logic_vector(1 downto 0); -- High to toggle store
done: out std_logic; -- High when busy
request: in std_logic; -- CPU request
num_bytes: in std_logic_vector(1 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
error: out std_logic_vector(6 downto 0); -- Error
debug_phys: out doubleword;
debug_virt: out doubleword;
SUM: in std_logic;
MXR: in std_logic;
MTIP: out std_logic;
MSIP: out std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end MMU;
architecture Behavioral of MMU is
-- Components --
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Signals --
type MMU_state is ( INIT, IDLE, SETUP, FINISH, FAULT, ALIGN_FAULT,
PAGE_WALK, PAGE_DECODE, PAGE_FAULT, PAGE_LEAF,
BUS_ACCESS, ACCESS_MSIP, ACCESS_TIME_CMP, ACCESS_TIME,
ACCESS_UART, ACCESS_LEDS, ACCESS_ROM, ACCESS_RAM,
ACCESS_MEM_WRITE, ACCESS_MEM_WRITE_WAIT, ACCESS_MEM_WRITE_WAIT_B,
ACCESS_MEM_READ, ACCESS_MEM_READ_WAIT, ACCESS_MEM_READ_WAIT_B );
signal curr_state, bus_ret_state, bus_err_ret_state : MMU_state;
signal init_counter : integer := 0;
signal m_time : doubleword;
signal m_time_cmp : doubleword;
signal s_MSIP : std_logic;
-- latched input request
signal s_addr_in: doubleword;
signal s_data_in: doubleword;
signal s_mode: std_logic_vector(1 downto 0);
signal s_r_type: std_logic_vector(1 downto 0);
signal s_num_bytes: std_logic_vector(1 downto 0);
-- Page Walk Signals --
signal vpn : vpn_arr;
signal pt_base : doubleword;
signal pte : doubleword;
signal page_index : integer;
-- Bus request --
signal bus_address : doubleword;
signal bus_num_bytes : std_logic_vector(1 downto 0);
signal bus_data_write : doubleword;
signal bus_data_read : doubleword;
signal bus_write : std_logic;
-- UART SIGNALS --
signal uart_send : std_logic;
signal uart_data_out : std_logic_vector(7 downto 0);
signal uart_ready : std_logic;
signal uart_data_in : std_logic_vector(7 downto 0);
signal uart_data_available : std_logic;
signal uart_reset_read : std_logic;
-- EXTERNAL MEMORY SIGNALS
signal mem_buff : byte_arr;
signal mem_buff_index : integer;
signal mem_buff_max : integer;
signal s_MEM_addr : std_logic_vector(26 downto 0);
begin
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => clk_100,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => clk_100,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
MSIP <= s_MSIP;
MMU_FSM: process( clk )
variable bus_address_top : doubleword;
begin if(rising_edge(clk)) then
m_time <= m_time + 1;
if( m_time >= m_time_cmp ) then
MTIP <= '1';
else
MTIP <= '0';
end if;
case curr_state is
when INIT =>
init_counter <= init_counter + 1;
if( init_counter > INIT_WAIT ) then
curr_state <= idle;
end if;
done <= '0';
LED <= (others => '0');
MEM_request <= '0';
m_time <= ALL_ZERO;
m_time_cmp <= ALL_ZERO;
uart_send <= '0';
uart_reset_read <= '0';
debug_phys <= ALL_ZERO;
debug_virt <= ALL_ZERO;
data_out <= ALL_ZERO;
MTIP <= '0';
s_MSIP <= '0';
when idle =>
done <= '0';
if(request = '1') then
curr_state <= SETUP;
end if;
when SETUP =>
s_addr_in <= addr_in;
s_data_in <= data_in;
s_mode <= mode;
s_r_type <= r_type;
s_num_bytes <= num_bytes;
if( r_type = MEM_FETCH ) then
debug_virt <= addr_in;
end if;
case satp(SATP_MODE_H downto SATP_MODE_L) is
when SATP_MODE_SV39 =>
page_index <= 2;
vpn(2) <= s_addr_in(38 downto 30);
vpn(1) <= s_addr_in(29 downto 21);
vpn(0) <= s_addr_in(20 downto 12);
pt_base <= zero_byte & satp(SATP_PPN_H downto SATP_PPN_L) & zero_byte & "0000";
curr_state <= PAGE_WALK;
when others =>
bus_address <= addr_in;
bus_num_bytes <= num_bytes;
bus_ret_state <= FINISH;
bus_err_ret_state <= FAULT;
curr_state <= BUS_ACCESS;
if( r_type = MEM_STORE ) then
bus_write <= '1';
bus_data_write <= data_in;
else
bus_write <= '0';
end if;
end case;
when PAGE_FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_PAGE_FAULT;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_PAGE_FAULT;
else
error <= CAUSE_STORE_AMO_PAGE_FAULT;
end if;
done <= '1';
when ALIGN_FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_ADDRESS_MISALIGNED;
else
error <= CAUSE_STORE_AMO_ADDRESS_MISALIGNED;
end if;
done <= '1';
when FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_ACCESS_FAULT;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_ACCESS_FAULT;
else
error <= CAUSE_STORE_AMO_ACCESS_FAULT;
end if;
done <= '1';
when PAGE_WALK =>
bus_address <= pt_base(63 downto 12) & vpn(page_index) & "000";
bus_num_bytes <= MEM_BYTES_8;
bus_write <= '0';
bus_ret_state <= PAGE_DECODE;
bus_err_ret_state <= PAGE_FAULT;
curr_state <= BUS_ACCESS;
when PAGE_DECODE =>
if( (bus_data_read(PTE_V) = '0')
or ((bus_data_read(PTE_R) = '0') and (bus_data_read(PTE_W) = '1')))
then
curr_state <= PAGE_FAULT;
elsif( (bus_data_read(PTE_R) = '1') or (bus_data_read(PTE_X) = '1') ) then
pte <= bus_data_read;
curr_state <= PAGE_LEAF;
else
-- node
pt_base <= zero_byte & bus_data_read(PTE_PPN_H downto PTE_PPN_L) & zero_byte & "0000";
page_index <= page_index - 1;
if( page_index = 0 ) then
curr_state <= PAGE_FAULT;
else
curr_state <= PAGE_WALK;
end if;
end if;
when PAGE_LEAF =>
if( (s_r_type = MEM_FETCH) and (pte(PTE_X) = '0') ) then
curr_state <= PAGE_FAULT;
elsif( ((s_r_type = MEM_LOAD ) and (pte(PTE_R) = '0'))
and ((MXR = '0') or ((MXR = '1') and (pte(PTE_X) = '0'))) )
then
curr_state <= PAGE_FAULT;
elsif( (s_r_type = MEM_STORE) and (pte(PTE_W) = '0')) then
curr_state <= PAGE_FAULT;
elsif( (s_mode = USER_MODE) and (pte(PTE_U) = '0') ) then
curr_state <= PAGE_FAULT;
elsif( (s_mode = SUPERVISOR_MODE) and (pte(PTE_U) = '1') and (SUM = '0') ) then
curr_state <= PAGE_FAULT;
else
if( (page_index = 1) and ( pte(18 downto 10) /= "000000000" ) ) then
curr_state <= PAGE_FAULT;
elsif( (page_index = 2) and ( pte(27 downto 10) /= "000000000000000000" ) ) then
curr_state <= PAGE_FAULT;
elsif( (pte(PTE_A) = '0') or ( (pte(PTE_D) = '0') and (s_r_type = MEM_LOAD) ) ) then
curr_state <= PAGE_FAULT;
else
bus_address(63 downto 56) <= zero_byte;
if( page_index = 0 ) then
bus_address(55 downto 12) <= pte(53 downto 10);
elsif( page_index = 1 ) then
bus_address(55 downto 12) <= pte(53 downto 19) & "000000000";
else
bus_address(55 downto 12) <= pte(53 downto 28) & "000000000000000000";
end if;
bus_address(11 downto 0) <= s_addr_in(11 downto 0);
bus_num_bytes <= s_num_bytes;
bus_ret_state <= FINISH;
bus_err_ret_state <= FAULT;
curr_state <= BUS_ACCESS;
if( s_r_type = MEM_STORE ) then
bus_write <= '1';
else
bus_write <= '0';
bus_data_write <= s_data_in;
end if;
end if;
end if;
when BUS_ACCESS =>
if( (bus_num_bytes = MEM_BYTES_8) and (bus_address(2 downto 0) /= "000") ) then
curr_state <= ALIGN_FAULT;
elsif( (bus_num_bytes = MEM_BYTES_4) and (bus_address(1 downto 0) /= "00" ) ) then
curr_state <= ALIGN_FAULT;
elsif( (bus_num_bytes = MEM_BYTES_2) and (bus_address(0) /= '0' ) ) then
curr_state <= ALIGN_FAULT;
else
if( bus_num_bytes = MEM_BYTES_8 ) then
bus_address_top := bus_address + 7;
elsif( bus_num_bytes = MEM_BYTES_4 ) then
bus_address_top := bus_address + 3;
elsif( bus_num_bytes = MEM_BYTES_2 ) then
bus_address_top := bus_address + 1;
else
bus_address_top := bus_address;
end if;
if( bus_address(63 downto 32) /= x"00000000" ) then
curr_state <= bus_err_ret_state;
elsif( bus_address(31 downto 16) = x"0200" ) then
if( ( bus_address(15 downto 0) >= x"0000" ) and ( bus_address_top(15 downto 0) < x"0004" ) ) then
curr_state <= ACCESS_MSIP;
elsif(( bus_address(15 downto 0) >= x"4000" ) and ( bus_address_top(15 downto 0) < x"4008" ) ) then
curr_state <= ACCESS_TIME_CMP;
elsif(( bus_address(15 downto 0) >= x"bff8" ) and ( bus_address_top(15 downto 0) < x"c000" ) ) then
curr_state <= ACCESS_TIME;
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address = x"000000008FFFFFFC" ) then
bus_data_read(31 downto 0) <= x"00000013";
curr_state <= FINISH;
elsif( bus_address(31 downto 20) = x"980" ) then
if( ( bus_address(19 downto 0) >= x"10000" ) and ( bus_address_top(19 downto 0) < x"10006" ) ) then
curr_state <= ACCESS_UART;
elsif(( bus_address(19 downto 0) >= x"00000" ) and ( bus_address_top(19 downto 0) < x"00002" ) ) then
curr_state <= ACCESS_LEDS;
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address(31 downto 28) = x"9" ) then
if( ( bus_address(27 downto 24) >= x"0" ) and ( bus_address_top(27 downto 24) < x"8" ) ) then
curr_state <= ACCESS_ROM;
MEM_ram <= '0';
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address(31 downto 28) = x"8" ) then
if( ( bus_address(27 downto 24) >= x"0" ) and ( bus_address_top(27 downto 24) < x"8" ) ) then
curr_state <= ACCESS_RAM;
MEM_ram <= '1';
else
curr_state <= bus_err_ret_state;
end if;
else
curr_state <= bus_err_ret_state;
end if;
end if;
when FINISH =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( bus_write = '0') then
data_out <= bus_data_read;
end if;
uart_send <= '0';
uart_reset_read <= '0';
if( s_r_type = MEM_FETCH ) then
debug_phys <= bus_address;
end if;
done <= '1';
error <= MEM_ERR_NONE;
when ACCESS_MSIP =>
if( bus_write = '1') then
if( bus_data_write(0) = '1' ) then
s_MSIP <= '1';
else
s_MSIP <= '0';
end if;
else
bus_data_read(63 downto 1) <= ALL_ZERO(63 downto 1);
if( s_MSIP = '1' ) then
bus_data_read(0) <= '1';
else
bus_data_read(0) <= '0';
end if;
end if;
curr_state <= bus_ret_state;
when ACCESS_TIME_CMP =>
if( bus_num_bytes = MEM_BYTES_8 ) then
if( bus_write = '1') then
m_time_cmp <= bus_data_write;
else
bus_data_read <= m_time_cmp;
end if;
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_TIME =>
if( bus_num_bytes = MEM_BYTES_8 ) then
if( bus_write = '1') then
m_time <= bus_data_write;
else
bus_data_read <= m_time;
end if;
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_UART =>
if( bus_num_bytes = MEM_BYTES_1 ) then
if( bus_write = '1') then
case bus_address(3 downto 0) is
when X"0" => curr_state <= bus_err_ret_state;
when X"1" => curr_state <= bus_err_ret_state;
when X"2" => uart_reset_read <= '1';
curr_state <= bus_ret_state;
when X"3" => uart_data_out <= bus_data_write(7 downto 0);
curr_state <= bus_ret_state;
when X"4" => curr_state <= bus_err_ret_state;
when X"5" => uart_send <= '1';
curr_state <= bus_ret_state;
when others => curr_state <= bus_err_ret_state;
end case;
else
case bus_address(3 downto 0) is
when X"0" => bus_data_read(7 downto 0) <= uart_data_in;
curr_state <= bus_ret_state;
when X"1" =>
if( uart_data_available = '1' ) then
bus_data_read(7 downto 0) <= x"01";
else
bus_data_read(7 downto 0) <= x"00";
end if;
curr_state <= bus_ret_state;
when X"2" => curr_state <= bus_err_ret_state;
when X"3" => curr_state <= bus_err_ret_state;
when X"4" =>
if( uart_ready = '1' ) then
bus_data_read(7 downto 0) <= x"01";
else
bus_data_read(7 downto 0) <= x"00";
end if;
curr_state <= bus_ret_state;
when X"5" => curr_state <= bus_err_ret_state;
when others => curr_state <= bus_err_ret_state;
end case;
end if;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_LEDS =>
if( ( bus_num_bytes = MEM_BYTES_2 ) and ( bus_write = '1' ) ) then
LED <= bus_data_write(15 downto 0);
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_ROM | ACCESS_RAM =>
mem_buff_index <= 0;
s_MEM_addr <= bus_address(26 downto 0);
if( bus_num_bytes = MEM_BYTES_8 ) then
mem_buff_max <= 8;
elsif( bus_num_bytes = MEM_BYTES_4 ) then
mem_buff_max <= 4;
elsif( bus_num_bytes = MEM_BYTES_2 ) then
mem_buff_max <= 2;
else
mem_buff_max <= 1;
end if;
if( bus_write = '1' ) then
MEM_write <= '1';
if( bus_num_bytes = MEM_BYTES_8 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
mem_buff(2) <= bus_data_write(23 downto 16); mem_buff(3) <= bus_data_write(31 downto 24);
mem_buff(4) <= bus_data_write(39 downto 32); mem_buff(5) <= bus_data_write(47 downto 40);
mem_buff(6) <= bus_data_write(55 downto 48); mem_buff(7) <= bus_data_write(63 downto 56);
elsif( bus_num_bytes = MEM_BYTES_4 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
mem_buff(2) <= bus_data_write(23 downto 16); mem_buff(3) <= bus_data_write(31 downto 24);
elsif( bus_num_bytes = MEM_BYTES_2 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
else
mem_buff(0) <= bus_data_write(7 downto 0);
end if;
curr_state <= ACCESS_MEM_WRITE;
else
MEM_write <= '0';
curr_state <= ACCESS_MEM_READ;
end if;
when ACCESS_MEM_WRITE =>
if( mem_buff_index = mem_buff_max ) then
curr_state <= bus_ret_state;
else
if( MEM_status = '0' ) then
mem_buff_index <= mem_buff_index + 1;
s_MEM_addr <= s_MEM_addr + 1;
MEM_addr <= s_MEM_addr;
MEM_data_in <= mem_buff(mem_buff_index);
MEM_request <= '1';
curr_state <= ACCESS_MEM_WRITE_WAIT;
end if;
end if;
when ACCESS_MEM_WRITE_WAIT =>
if( MEM_status = '1' ) then
curr_state <= ACCESS_MEM_WRITE_WAIT_B;
end if;
when ACCESS_MEM_WRITE_WAIT_B =>
MEM_request <= '0';
if( MEM_err = '1') then
curr_state <= bus_err_ret_state;
else
curr_state <= ACCESS_MEM_WRITE;
end if;
when ACCESS_MEM_READ =>
if( mem_buff_index = mem_buff_max ) then
curr_state <= bus_ret_state;
if( bus_num_bytes = MEM_BYTES_8 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
bus_data_read(23 downto 16) <= mem_buff(2); bus_data_read(31 downto 24) <= mem_buff(3);
bus_data_read(39 downto 32) <= mem_buff(4); bus_data_read(47 downto 40) <= mem_buff(5);
bus_data_read(55 downto 48) <= mem_buff(6); bus_data_read(63 downto 56) <= mem_buff(7);
elsif( bus_num_bytes = MEM_BYTES_4 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
bus_data_read(23 downto 16) <= mem_buff(2); bus_data_read(31 downto 24) <= mem_buff(3);
elsif( bus_num_bytes = MEM_BYTES_2 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
else
bus_data_read(7 downto 0) <= mem_buff(0);
end if;
else
if( MEM_status = '0' ) then
MEM_addr <= s_MEM_addr;
MEM_request <= '1';
curr_state <= ACCESS_MEM_READ_WAIT;
end if;
end if;
when ACCESS_MEM_READ_WAIT =>
if( MEM_status = '1' ) then
curr_state <= ACCESS_MEM_READ_WAIT_B;
end if;
when ACCESS_MEM_READ_WAIT_B =>
MEM_request <= '0';
if( MEM_err = '1') then
curr_state <= bus_err_ret_state;
else
curr_state <= ACCESS_MEM_READ;
s_MEM_addr <= s_MEM_addr + 1;
mem_buff_index <= mem_buff_index + 1;
mem_buff(mem_buff_index) <= MEM_data_out;
end if;
end case;
if('1' = rst) then
curr_state <= INIT;
init_counter <= 0;
end if;
end if; end process;
end Behavioral;
|
mit
|
SLongofono/Senior_Design_Capstone
|
simple_core/regfile.vhd
|
2
|
2369
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end regfile;
architecture Behavioral of regfile is
-- Contents of regfile, all zeros
signal reggie: regfile_arr := (others => (others => '0'));
begin
-- Synchronous write
process(clk, rst)
begin
if('1' = halt) then
-- Do nothing
else
write_error <= '0';
if('1' = rst) then
reggie <= (others => (others => '0'));
elsif(rising_edge(clk)) then
if('1' = write_en) then
if("00000" = write_addr) then
write_error <= '1';
else
reggie(to_integer(unsigned(write_addr))) <= write_data;
end if; -- write_error
end if; -- write_en
end if; -- rst
end if; -- halt
end process;
-- Asynchronous read
read_data_1 <= reggie(to_integer(unsigned(read_addr_1)));
read_data_2 <= reggie(to_integer(unsigned(read_addr_2)));
-- Asynchronous debug out
debug_out <= reggie;
end Behavioral;
|
mit
|
eiglss/VHDL
|
UART/txControler.vhd
|
1
|
2096
|
--******************************************************************************
-- @TITRE : txControler.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY txControler IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
datReady : IN STD_LOGIC;
tick : IN STD_LOGIC;
count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
shEn : OUT STD_LOGIC;
ldEn : OUT STD_LOGIC;
txBusy : OUT STD_LOGIC
);
END ENTITY txControler;
ARCHITECTURE mealy OF txControler IS
TYPE state_t IS (idle, send);
SIGNAL state : state_t;
BEGIN
Transition : PROCESS(clk, aNRst) IS
BEGIN
IF aNRst = '0' THEN
state <= idle;
ELSIF RISING_EDGE(clk) THEN
CASE state IS
WHEN idle =>
IF datReady = '1' THEN
state <= send;
END IF;
WHEN send =>
IF tick = '1' AND UNSIGNED(count) >= (dataLength+0+stop) AND parity = N THEN
state <= idle;
ELSIF tick = '1' AND UNSIGNED(count) >= (dataLength+1+stop) AND parity /= N THEN
state <= idle;
END IF;
END CASE;
END IF;
END PROCESS Transition;
shEn <= '1' WHEN state = send AND tick = '1' ELSE
'0';
ldEn <= '1' WHEN state = idle AND datReady = '1' ELSE
'0';
txBusy <= '1' WHEN state = send ELSE
'0';
END ARCHITECTURE mealy;
|
mit
|
akshayp/college-projects
|
vhdl/pong/video_PLL.vhd
|
1
|
9568
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: video_PLL.vhd
-- Megafunction Name(s):
-- altpll
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.2 Build 156 11/29/2004 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY video_PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END video_PLL;
ARCHITECTURE SYN OF video_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_duty_cycle : NATURAL;
lpm_type : STRING;
clk0_multiply_by : NATURAL;
inclk0_input_frequency : NATURAL;
clk0_divide_by : NATURAL;
pll_type : STRING;
intended_device_family : STRING;
operation_mode : STRING;
compensate_clock : STRING;
clk0_phase_shift : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_duty_cycle => 50,
lpm_type => "altpll",
clk0_multiply_by => 1007,
inclk0_input_frequency => 20833,
clk0_divide_by => 1920,
pll_type => "AUTO",
intended_device_family => "Cyclone",
operation_mode => "NORMAL",
compensate_clock => "CLK0",
clk0_phase_shift => "0"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.175"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1920"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL_inst.vhd TRUE FALSE
|
mit
|
AmitThakur/vhdl
|
moore/Moore1.vhd
|
2
|
884
|
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Moore1 is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
w : in STD_LOGIC;
z : out STD_LOGIC);
end Moore1;
architecture Behavioral of Moore1 is
type state_type is (A, B, C);
signal y: state_type;
begin
process(reset, clock)
begin
if reset = '0' then
y <= A;
elsif (clock' event and clock = '1') then
case y is
when A => -- state A
if w = '0' then
y <= A;
else
y <= B;
end if;
when B =>
if w = '0' then
y <= A;
else
y <= C;
end if;
when C =>
if w = '0' then
y <= A;
else
y <= C;
end if;
end case;
end if;
end process;
z <= '1' when y = C else '0';
end Behavioral;
|
mit
|
eiglss/VHDL
|
UART/uart.vhd
|
1
|
6746
|
--******************************************************************************
-- @TITRE : uart.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY uart IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
tick : IN STD_LOGIC;
-- tx
txDatReady : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0);
txBusy : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
-- rx
rx : IN STD_LOGIC;
rxDatReady : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
datOut : OUT STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0)
);
END uart;
ARCHITECTURE Structural OF uart IS
-- TX
SIGNAL iCountTx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iTxShEn : STD_LOGIC;
SIGNAL iTxLdEn : STD_LOGIC;
SIGNAL iDataTx : STD_LOGIC_VECTOR(sel(parity = N, 1+dataLength+stop, 1+dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iTx : STD_LOGIC;
SIGNAL iTxBusy : STD_LOGIC;
-- RX
SIGNAL iRxStart : STD_LOGIC;
SIGNAL iRxBusy : STD_LOGIC;
SIGNAL iCountRx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iRxShEn : STD_LOGIC;
SIGNAL iRxDatOut : STD_LOGIC_VECTOR(sel(parity = N, dataLength+stop, dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iRxDatReady : STD_LOGIC;
BEGIN
-- TX
tx <= '1' WHEN iTxBusy = '0' OR aNRst = '0' ELSE
iTx;
txBusy <= iTxBusy;
dataTxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
iDataTx <= "1"&datIN&"0";
END GENERATE;
dataTxN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
iDataTx <= "11"&datIN&"0";
END GENERATE;
dataTxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
iDataTx <= "1"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
dataTxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
iDataTx <= "11"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
txControler_ci : txControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
datReady => txDatReady,
tick => tick,
count => iCountTx,
shEn => iTxShEn,
ldEn => iTxLdEn,
txBusy => iTxBusy
);
txCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iTxLdEn,
en => iTxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountTx
);
txShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, 1+dataLength+stop,1+dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iTxShEn,
ldEn => iTxLdEn,
serialIn => '0',
datIn => iDataTx,
datOut => OPEN,
serialOut => iTx
);
-- RX
iRxStart <= '1' WHEN rx = '0' AND iRxBusy = '0' ELSE
'0';
rxBusy <= iRxBusy;
rxControler_ci : rxControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
start => iRxStart,
tick => tick,
count => iCountRx,
shEn => iRxShEn,
rxBusy => iRxBusy,
dataReady => iRxDatReady
);
rxCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iRxStart,
en => iRxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountRx
);
rxShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, dataLength+stop,dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iRxShEn,
ldEn => iRxStart,
serialIn => rx,
datIn => (OTHERS => '0'),
datOut => iRxDatOut,
serialOut => open
);
datOut <= iRxDatOut(dataLength-1 DOWNTO 0);
datReadyRxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength) = '1' ELSE
'0';
END GENERATE;
datReadyExN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" ELSE
'0';
END GENERATE;
datReadyRxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1) = '1' AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
datReadyRxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
END Structural;
|
mit
|
wifidar/wifidar_fpga
|
src/adc_receiver.vhd
|
2
|
3083
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity adc_receiver is
port(
send_data: in std_logic;
busy: out std_logic;
spi_sck: out std_logic;
spi_miso: in std_logic;
ad_conv: out std_logic;
outputA: out std_logic_vector (13 downto 0);
outputB: out std_logic_vector (13 downto 0);
new_reading: out std_logic;
clk: in std_logic
);
end adc_receiver;
architecture Behavioral of adc_receiver is
type adc_read_type is (start_pulse,a_data,b_data,write_data);
signal adc_state: adc_read_type;
signal outputA_register: std_logic_vector(13 downto 0);
signal outputB_register: std_logic_vector(13 downto 0);
signal outputA_temp: std_logic_vector(15 downto 0);
signal outputB_temp: std_logic_vector(15 downto 0);
signal curr_pos: integer range 0 to 15 := 0;
signal spi_clk_en: std_logic;
signal new_reading_temp: std_logic;
signal en: std_logic;
begin
main_proc: process(clk)
begin
if(falling_edge(clk)) then
if(send_data = '1') then
en <= '1';
busy <= '1';
end if;
if(en = '1') then
ad_conv <= '0';
new_reading <= '0';
busy <= '1';
case adc_state is
when start_pulse =>
curr_pos <= curr_pos + 1;
new_reading_temp <= '1';
if(curr_pos = 0) then
ad_conv <= '1';
end if;
if(curr_pos = 3) then
spi_clk_en <= '1';
end if;
if(curr_pos = 4) then
adc_state <= a_data;
curr_pos <= 15;
end if;
when a_data =>
curr_pos <= curr_pos - 1;
outputA_temp(curr_pos) <= spi_miso;
if(curr_pos = 0) then
curr_pos <= 15;
adc_state <= b_data;
end if;
when b_data =>
curr_pos <= curr_pos - 1;
outputB_temp(curr_pos) <= spi_miso;
if(curr_pos = 0) then
curr_pos <= 0;
adc_state <= write_data;
end if;
when write_data =>
curr_pos <= curr_pos + 1;
outputA_register <= outputA_temp(13 downto 0);
outputB_register <= outputB_temp(15 downto 2);
if(new_reading_temp = '1') then
new_reading <= '1';
new_reading_temp <= '0';
end if;
if(curr_pos = 2) then
curr_pos <= 0;
adc_state <= start_pulse;
spi_clk_en <= '0';
en <= '0';
busy <= '0';
end if;
end case;
-- spi_clk_sig <= not spi_clk_sig;
--
-- if(spi_clk_sig = '1') then
-- if(curr_pos = 0) then
-- ad_conv <= '1';
-- outputA_register <= input_register(16 downto 3);
-- outputB_register <= input_register(32 downto 19);
-- else
-- ad_conv <= '0';
-- end if;
--
-- if((curr_pos > 1) and (curr_pos < 33)) then
-- input_register(curr_pos) <= spi_miso;
-- end if;
--
-- if(curr_pos = 36) then
-- curr_pos <= 0;
-- end if;
-- end if;
end if;
end if;
end process;
spi_sck <= clk when spi_clk_en = '1' else '0';
outputA <= outputA_register;
outputB <= outputB_register;
end Behavioral;
|
mit
|
hamsternz/FPGA_Webserver
|
hdl/udp/udp_add_udp_header.vhd
|
1
|
7834
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_add_udp_header - Behavioral
--
-- Description: Add the UDP header to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_add_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
udp_src_port : in std_logic_vector(15 downto 0);
udp_dst_port : in std_logic_vector(15 downto 0);
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end udp_add_udp_header;
architecture Behavioral of udp_add_udp_header is
type a_data_delay is array(0 to 8) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
----------------------------------------------------------------
-- Note: Set the initial state to pass the data striaght through
----------------------------------------------------------------
signal count : unsigned(3 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
signal udp_length : std_logic_vector(15 downto 0);
signal udp_checksum_u1a : unsigned(19 downto 0);
signal udp_checksum_u1b : unsigned(19 downto 0);
signal udp_checksum_u2 : unsigned(16 downto 0);
signal udp_checksum_u3 : unsigned(15 downto 0);
signal udp_checksum : std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- UDP checksum is calculated based on a pseudo header that includes
-- the source and destination IP addresses
--------------------------------------------------------------------
signal pseudohdr_0 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_2 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_3 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_4 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_5 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_6 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_7 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_8 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_9 : std_logic_vector(15 downto 0) := (others => '0');
begin
udp_length <= std_logic_vector(unsigned(data_length)+8);
pseudohdr_0 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
pseudohdr_1 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
pseudohdr_2 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
pseudohdr_3 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
pseudohdr_4 <= x"0011"; -- UDP Protocol
pseudohdr_5 <= udp_length;
pseudohdr_6 <= udp_src_port;
pseudohdr_7 <= udp_dst_port;
pseudohdr_8 <= udp_length;
pseudohdr_9 <= udp_checksum;
process(clk)
begin
if rising_edge(clk) then
case count is
when "0000" => data_out <= udp_src_port(15 downto 8); data_valid_out <= '1';
when "0001" => data_out <= udp_src_port( 7 downto 0); data_valid_out <= '1';
when "0010" => data_out <= udp_dst_port(15 downto 8); data_valid_out <= '1';
when "0011" => data_out <= udp_dst_port( 7 downto 0); data_valid_out <= '1';
when "0100" => data_out <= udp_length(15 downto 8); data_valid_out <= '1';
when "0101" => data_out <= udp_length( 7 downto 0); data_valid_out <= '1';
when "0110" => data_out <= udp_checksum(15 downto 8); data_valid_out <= '1';
when "0111" => data_out <= udp_checksum( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "1111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "1111" then
count <= count + 1;
end if;
end if;
data_valid_in_last <= data_valid_in;
-- Pipelined checksum calculation
udp_checksum_u1a <= to_unsigned(0,20) + unsigned(pseudohdr_0) + unsigned(pseudohdr_1)
+ unsigned(pseudohdr_2) + unsigned(pseudohdr_3)
+ unsigned(pseudohdr_4);
udp_checksum_u1b <= to_unsigned(0,20) + unsigned(pseudohdr_5)
+ unsigned(pseudohdr_6) + unsigned(pseudohdr_7)
+ unsigned(pseudohdr_8) + unsigned(data_checksum);
udp_checksum_u2 <= to_unsigned(0,17) + udp_checksum_u1a(15 downto 0) + udp_checksum_u1a(19 downto 16)
+ udp_checksum_u1b(15 downto 0) + udp_checksum_u1b(19 downto 16);
udp_checksum_u3 <= udp_checksum_u2(15 downto 0) + udp_checksum_u2(16 downto 16);
udp_checksum <= not std_logic_vector(udp_checksum_u3);
end if;
end process;
end Behavioral;
|
mit
|
wifidar/wifidar_fpga
|
src/dac_serial.vhd
|
1
|
5005
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end dac_serial;
architecture Behavioral of dac_serial is
signal current_bit: integer range 0 to 16 := 0;
signal ready_flag_sig: std_logic := '0';
signal spi_clk_delay: std_logic := '0';
signal dac_cs_delay: std_logic := '0';
begin
process(clk)
begin
if(rising_edge(clk)) then
if(send_data = '1') and (ready_flag_sig = '1') then
ready_flag_sig <= '0';
dac_cs_delay <= '0';
DAC_CS <= dac_cs_delay;
elsif ready_flag_sig = '0' then
if(spi_clk_delay = '1') then
spi_clk_delay <= '0';
else
spi_clk_delay <= '1';
current_bit <= current_bit + 1;
case current_bit is
-- don't cares
when 1 => SPI_MOSI_1 <= '0';
when 2 => SPI_MOSI_1 <= '0';
-- command
when 3 => SPI_MOSI_1 <= '0';
when 4 => SPI_MOSI_1 <= '0';
-- data
when 5 => SPI_MOSI_1 <= data_in_1(11);
when 6 => SPI_MOSI_1 <= data_in_1(10);
when 7 => SPI_MOSI_1 <= data_in_1(9);
when 8 => SPI_MOSI_1 <= data_in_1(8);
when 9 => SPI_MOSI_1 <= data_in_1(7);
when 10 => SPI_MOSI_1 <= data_in_1(6);
when 11 => SPI_MOSI_1 <= data_in_1(5);
when 12 => SPI_MOSI_1 <= data_in_1(4);
when 13 => SPI_MOSI_1 <= data_in_1(3);
when 14 => SPI_MOSI_1 <= data_in_1(2);
when 15 => SPI_MOSI_1 <= data_in_1(1);
when 16 => SPI_MOSI_1 <= data_in_1(0);
DAC_CS <= '1';
ready_flag_sig <= '1';
-- other
when others => SPI_MOSI_1 <= '0'; -- used for don't cares
end case;
end if;
else
DAC_CS <= '1';
current_bit <= 0;
spi_clk_delay <= '1';
end if;
--DAC_CS <= dac_cs_delay;
SPI_SCK <= not spi_clk_delay;
ready_flag <= ready_flag_sig;
end if;
end process;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--
--entity dac_serial is
-- port (
-- dac_clk: out std_logic;
-- dac_sync: out std_logic;
-- dac_data: out std_logic;
-- data_in: in std_logic_vector(11 downto 0);
-- ready: out std_logic;
-- send: in std_logic;
-- clk: in std_logic
-- );
--end dac_serial;
--
--architecture behavioral of dac_serial is
--
-- current_bit: unsigned(3 downto 0);
-- divide_counter: unsigned(3 downto 0);
-- sending: std_logic;
-- data_en: std_logic;
-- send_en: std_logic;
--
--begin
-- clk_divide:process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(divide_counter = to_unsigned(5,4)) then
-- divide_counter <= divide_counter + '1';
-- send_en <= '1';
-- elsif(divide_counter = to_unsigned(10,4)) then
-- divide_counter <= (others => '0');
-- data_en <= '1';
-- send_en <= '1';
-- else
-- divide_counter <= divide_counter + '1';
-- data_en <= '0';
-- send_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- serial_clk: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(sending = '1') then
--
-- end process;
--
-- serial_data: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(send = '1') and (sending = '0') then
-- sending <= '1';
-- sending <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- elsif(data_en = '1') then
-- if(sending = '1') then
-- current_bit <= current_bit + '1';
-- dac_sync <= '0';
-- case current_bit is
-- when "0000" =>
-- dac_data <= '0'; -- don't care
-- when "0001" =>
-- dac_data <= '0'; -- don't care
-- when "0010" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0011" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0100" =>
-- dac_data <= data_in(11);
-- when "0101" =>
-- dac_data <= data_in(10);
-- when "0110" =>
-- dac_data <= data_in(9);
-- when "0111" =>
-- dac_data <= data_in(8);
-- when "1000" =>
-- dac_data <= data_in(7);
-- when "1001" =>
-- dac_data <= data_in(6);
-- when "1010" =>
-- dac_data <= data_in(5);
-- when "1011" =>
-- dac_data <= data_in(4);
-- when "1100" =>
-- dac_data <= data_in(3);
-- when "1101" =>
-- dac_data <= data_in(2);
-- when "1110" =>
-- dac_data <= data_in(1);
-- when "1111" =>
-- dac_data <= data_in(0);
-- when others =>
-- dac_data <= '0';
-- end case;
-- else
-- dac_sync <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
--end behavioral;
|
mit
|
wifidar/wifidar_fpga
|
src/dac_section/buttonstructural.vhd
|
2
|
1691
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity buttonStructural is
port(
rot_a: in std_logic;
rot_b: in std_logic;
button_in: in std_logic_vector(3 downto 0);
current_mode: out std_logic_vector(1 downto 0);
current_channel: out std_logic_vector(1 downto 0);
adjust: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end buttonStructural;
architecture Structural of buttonStructural is
component rotary_control
port(
rotary_a: in std_logic;
rotary_b: in std_logic;
out_pulse: out std_logic;
direction: out std_logic;
clk: in std_logic
);
end component;
component pulse_sync
port(
A: in std_logic;
output: out std_logic;
clk: in std_logic
);
end component;
component buttons_to_switches
port(
adjust: out std_logic_vector(1 downto 0);
rotary_pulse: in std_logic;
rotary_direction: in std_logic;
buttons_in: in std_logic_vector(3 downto 0);
current_mode: out std_logic_vector(1 downto 0);
current_channel: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end component;
signal button_out: std_logic_vector(3 downto 0);
signal pulse: std_logic;
signal direction: std_logic;
begin
button_mapper: buttons_to_switches port map (adjust,pulse,direction,button_out,current_mode,current_channel,clk);
rotary: rotary_control port map (rot_a,rot_b,pulse,direction,clk);
buttonw: pulse_sync port map (button_in(3),button_out(3),clk);
buttonn: pulse_sync port map (button_in(1),button_out(1),clk);
buttone: pulse_sync port map (button_in(2),button_out(2),clk);
buttons: pulse_sync port map (button_in(0),button_out(0),clk);
end Structural;
|
mit
|
hamsternz/FPGA_Webserver
|
hdl/tcp_engine/tcp_engine_content_memory.vhd
|
1
|
1368
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.06.2016 23:01:07
-- Design Name:
-- Module Name: tcp_engine_content_memory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_content_memory is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (15 downto 0);
data : out STD_LOGIC_VECTOR (7 downto 0));
end tcp_engine_content_memory;
architecture Behavioral of tcp_engine_content_memory is
type a_mem is array(0 to 15) of std_logic_vector(7 downto 0);
-- For now, just the characters '0' to '9' and 'A' to 'F'
signal mem : a_mem := (x"46", x"50", x"47", x"41",
x"20", x"73", x"61", x"79",
x"73", x"20", x"22", x"48",
x"69", x"22", x"0D", x"0A");
begin
process(clk)
begin
if rising_edge(clk) then
data <= mem(to_integer(unsigned(address(3 downto 0))));
end if;
end process;
end Behavioral;
|
mit
|
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