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236
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stringclasses 54
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1.04M
⌀ | license
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|---|---|---|---|---|---|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl
|
1
|
2471690
| null |
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd
|
19
|
4781
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd
|
1
|
51660
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_10.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_10.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_10.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_10.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_10.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_10.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_10.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wr_status_cntl.vhd
|
1
|
57339
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd
|
1
|
25964
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_3.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_3.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_3.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
mit
|
xiadz/oscilloscope
|
ipcore_dir/char_rom_memory.vhd
|
1
|
5368
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file char_rom_memory.vhd when simulating
-- the core, char_rom_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY char_rom_memory IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END char_rom_memory;
ARCHITECTURE char_rom_memory_a OF char_rom_memory IS
-- synthesis translate_off
COMPONENT wrapped_char_rom_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_char_rom_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "char_rom_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 1,
c_read_width_b => 1,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 1,
c_write_width_b => 1,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_char_rom_memory
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END char_rom_memory_a;
|
mit
|
ringof/radiofist_audio
|
sinc3_filter.vhd
|
1
|
1894
|
-- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- Implementation is derived from p. 17 of Texas Instruments SBAA094
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity sinc3_filter is
port (
reset : in STD_LOGIC;
din : in STD_LOGIC;
in_clk : in STD_LOGIC;
out_clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (24 downto 0)
);
end sinc3_filter;
architecture RTL of sinc3_filter is
signal DN0, DN1, DN3, DN5 : STD_LOGIC_VECTOR(24 downto 0);
signal CN1, CN2, CN3, CN4 : STD_LOGIC_VECTOR(24 downto 0);
signal DELTA1 : STD_LOGIC_VECTOR(24 downto 0);
begin
-- process to clock in the sigma-delta bit stream into the first
-- integrator of filter
-- Clocked at orignal sample frequency
sd_stream_in : process(din, in_clk, reset)
begin
if reset = '1' then
DELTA1 <= (others => '0');
elsif rising_edge(in_clk) then
if din = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
-- process to move data and apply integration through
-- the successive two integrators of filter
-- Clocked at original sample frequency
sd_integration : process(in_clk, reset)
begin
if reset = '1' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif rising_edge(in_clk) then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
-- process to decimate and move data through the three differentiators
-- Clock at downsampling frequency
sd_differentiation : process(reset, out_clk)
begin
if reset = '1' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif rising_edge(out_clk) then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
-- Differentiation functions for filter
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
dout <= CN4 - DN5;
end RTL;
|
mit
|
ringof/radiofist_audio
|
ipcore_dir/dcm_6/example_design/dcm_6_exdes.vhd
|
1
|
6677
|
-- file: dcm_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_6_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end dcm_6_exdes;
architecture xilinx of dcm_6_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component dcm_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_ADC : out std_logic;
DEC_CLK : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : dcm_6
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_ADC => clk_int(1),
DEC_CLK => clk_int(2),
-- Status and control signals
RESET => RESET);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
|
mit
|
cfelton/musicbox_simple
|
pck_myhdl_09.vhd
|
1
|
3359
|
-- File: pck_myhdl_09.vhd
-- Generated by MyHDL 0.9dev
-- Date: Tue Dec 30 11:42:04 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_09 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_09;
package body pck_myhdl_09 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_09;
|
mit
|
lucascartaxo/dotfiles
|
atom/packages/file-icons/examples/vhdl.vhd
|
12226531
|
0
|
mit
|
|
AlexMitakos/DES-in-VHDL
|
vhdl/left_shift_by_1.vhdl
|
1
|
1233
|
library ieee;
use ieee.std_logic_1164.all;
--This is the initial implementation of a left shift function. There is also a ready function for left or right shift declared in ieee.numeric_std . But we found it out later so we kept our initial implementation.
entity left_shift_by_1 is
port( data_in: in std_logic_vector(0 to 27);
data_out: out std_logic_vector(0 to 27));
end left_shift_by_1;
architecture behavior of left_shift_by_1 is
begin
data_out(0)<=data_in(1);
data_out(1)<=data_in(2);
data_out(2)<=data_in(3);
data_out(3)<=data_in(4);
data_out(4)<=data_in(5);
data_out(5)<=data_in(6);
data_out(6)<=data_in(7);
data_out(7)<=data_in(8);
data_out(8)<=data_in(9);
data_out(9)<=data_in(10);
data_out(10)<=data_in(11);
data_out(11)<=data_in(12);
data_out(12)<=data_in(13);
data_out(13)<=data_in(14);
data_out(14)<=data_in(15);
data_out(15)<=data_in(16);
data_out(16)<=data_in(17);
data_out(17)<=data_in(18);
data_out(18)<=data_in(19);
data_out(19)<=data_in(20);
data_out(20)<=data_in(21);
data_out(21)<=data_in(22);
data_out(22)<=data_in(23);
data_out(23)<=data_in(24);
data_out(24)<=data_in(25);
data_out(25)<=data_in(26);
data_out(26)<=data_in(27);
data_out(27)<=data_in(0);
end behavior;
|
mit
|
AlexMitakos/DES-in-VHDL
|
vhdl/s6_box.vhdl
|
1
|
1182
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity s6_box is
port( data_in: in std_logic_vector(0 to 5);
data_out: out std_logic_vector(0 to 3));
end s6_box;
architecture behavior of s6_box is
type s6box is array(0 to 3, 0 to 15) of integer range 0 to 15;
constant box: s6box:=
((12,1,10,15,9,2,6,8,0,13,3,4,14,7,5,11),
(10,15,4,2,7,12,9,5,6,1,13,14,0,11,3,8),
(9,14,15,5,2,8,12,3,7,0,4,10,1,13,11,6),
(4,3,2,12,9,5,15,10,11,14,1,7,6,0,8,13));
begin
process(data_in) is
variable column: integer range 0 to 15;
variable row: integer range 0 to 3;
variable tmp: std_logic_vector(0 to 1); --this variable holds the first and last bit of the input that represents the row. It is usedto cast two separate bits into one vector of size two.
variable data_out_decimal: integer range 0 to 15; --this variable contains the output data in decimal representation
begin
column:=to_integer(unsigned(data_in(1 to 4)));
tmp:=data_in(0)&data_in(5);
row:=to_integer(unsigned(tmp));
data_out_decimal:=box(row,column);
data_out<=std_logic_vector(to_unsigned(data_out_decimal,data_out'length));
end process;
end behavior;
|
mit
|
equation314/PVZ
|
input/Input.vhd
|
1
|
2762
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library pvz;
use pvz.pvz_objects.all;
entity Input is
port(
clock, reset: in std_logic;
click: out std_logic;
game_state: in game_state;
ps2_clk: inout std_logic;
ps2_data: inout std_logic;
mousex, mousey: out std_logic_vector(9 downto 0); -- 鼠标坐标输出
state: out mouse_state := NO; -- 鼠标状态输出
plants: in plant_matrix; -- 输入输入
new_plant: out std_logic; -- 新植物信号
new_plant_type: out std_logic_vector(1 downto 0); -- 新植物类型
new_plant_x, new_plant_y: out integer range 0 to M-1 -- 新植物坐标
);
end entity;
architecture bhv of Input is
component ps2_mouse is
port(
clk_in: in std_logic;
reset_in: in std_logic;
ps2_clk: inout std_logic;
ps2_data: inout std_logic;
left_button: out std_logic;
right_button: out std_logic;
middle_button: out std_logic;
mousex: buffer std_logic_vector(9 downto 0);
mousey: buffer std_logic_vector(9 downto 0);
error_no_ack: out std_logic
);
end component;
signal left_button: std_logic;
signal s1, s2: mouse_state;
signal x, y: std_logic_vector(9 downto 0);
begin
mousex <= x;
mousey <= y;
click <= left_button;
mouse: ps2_mouse port map (
clk_in => clock,
reset_in => reset,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
left_button => left_button,
mousex => x, mousey => y
);
process(left_button)
variable px, py: integer range 0 to M-1;
begin
if (rising_edge(left_button)) then
if (6 <= y and y <= 62) then
if (164 <= x and x <= 202) then
s1 <= SUNFLOWER_DOWN;
elsif (207 <= x and x <= 245) then
s1 <= PEASHOOTER_DOWN;
elsif (250 <= x and x <= 288) then
s1 <= WALLNUT_DOWN;
else
s1 <= NO;
end if;
else
s1 <= NO;
end if;
elsif (falling_edge(left_button)) then
if (x < 576 and 72 <= y and y < 472) then
s2 <= UP;
px := conv_integer(x(9 downto 6));
py := conv_integer(y - 72) / 80;
new_plant_x <= px;
new_plant_y <= py;
if (s1 = NO and plants(py)(px).plant_type = "10") then
new_plant <= '1';
new_plant_type <= "10";
elsif (plants(py)(px).hp = 0) then
if (s1 = PEASHOOTER_DOWN) then
new_plant <= '1';
new_plant_type <= "00";
elsif (s1 = WALLNUT_DOWN) then
new_plant <= '1';
new_plant_type <= "01";
elsif (s1 = SUNFLOWER_DOWN) then
new_plant <= '1';
new_plant_type <= "10";
else
new_plant <= '0';
end if;
else
new_plant <= '0';
end if;
else
new_plant <= '0';
s2 <= NO;
end if;
end if;
if (left_button = '1') then
state <= s1;
else
state <= s2;
end if;
end process;
end architecture;
|
mit
|
chiranjeevjain/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_cast_GN7PRGDOVA.vhd
|
9
|
879
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN7PRGDOVA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN7PRGDOVA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_testbench_salt_GNOXVOQUET.vhd
|
16
|
1749
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/hdl/alt_dspbuilder_testbench_salt_GNOXVOQUET.vhd
|
16
|
1749
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
KaskMartin/Digiloogika_ALU
|
ALU/func_2.vhdl
|
2
|
441
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Fun2 = rol A (ringnihe vasakule)
entity func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func2;
architecture design of func2 is
signal a_sign, o_sign: signed(3 downto 0);
begin
a_sign <= signed(a);
o_sign <= rotate_left(a_sign, 1);
o <= std_logic_vector(o_sign);
end design;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/altera_lnsim/generic_cdr/_primary.vhd
|
5
|
1320
|
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in vl_logic;
ltr : in vl_logic;
pciel : in vl_logic;
pciem : in vl_logic;
ppmlock : in vl_logic;
refclk : in vl_logic;
rst : in vl_logic;
sd : in vl_logic;
rxp : in vl_logic;
clk90bdes : out vl_logic;
clk270bdes : out vl_logic;
clklow : out vl_logic;
deven : out vl_logic;
dodd : out vl_logic;
fref : out vl_logic;
pfdmodelock : out vl_logic;
rxplllock : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_debug_msg : constant is 1;
end generic_cdr;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/sim/vhdl/AESL_sim_pkg.vhd
|
2
|
8743
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
mit
|
APastorG/APG
|
average_calculator/average_calculator_u.vhd
|
1
|
4557
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_u is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_ufixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_u1 of average_calculator_u is
constant P : positive := input'length;
/* constant CHECKS : integer := average_calculator_CHECKS();*/
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_core_u1:
entity work.average_calculator_core_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dadd_3_full_dsp_64/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
20
|
94635
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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zWixxZrSiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
|
mit
|
ComputerArchitectureGroupPWr/SimulationCore
|
src/sysmon_v2.vhd
|
1
|
3560
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity toplevel is
Port (clk : in STD_LOGIC;
Vccint : out STD_LOGIC_VECTOR (15 downto 0);
temint : out STD_LOGIC_VECTOR (15 downto 0);
busy : out STD_LOGIC;
alarm : out STD_LOGIC);
end toplevel;
architecture Behavioral of toplevel is
signal dobus : std_logic_vector(15 downto 0);
signal vccint_temp : std_logic_vector(15 downto 0);
signal temint_temp : std_logic_vector(15 downto 0);
signal vccint_temp_next : std_logic_vector(15 downto 0);
signal temint_temp_next : std_logic_vector(15 downto 0);
signal addr : std_logic_vector(6 downto 0);
signal addr_next : std_logic_vector(6 downto 0);
signal alm: std_logic_vector(2 downto 0);
signal eos: std_logic;
signal rdy: std_logic;
type state_type is (read_vcc, store_vcc, read_tem, store_tem);
signal currState, nextState : state_type;
begin
process(clk)
begin
if rising_edge(clk) then
currState <= nextState;
vccint_temp <= vccint_temp_next;
temint_temp <= temint_temp_next;
addr <= addr_next;
end if;
end process;
process(currState, dobus, vccint_temp, temint_temp)
begin
case currState is
when read_vcc =>
nextState <= store_vcc;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000001";
when store_vcc =>
if rdy = '1' then
nextState <= read_tem;
vccint_temp_next <= "000000" & dobus(15 downto 6);
else
nextState <= store_vcc;
vccint_temp_next <= vccint_temp;
end if;
temint_temp_next <= temint_temp;
addr_next <= "0000001";
when read_tem =>
nextState <= store_tem;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000000";
when store_tem =>
if rdy = '1' then
nextState <= read_vcc;
temint_temp_next <= "000000" & dobus(15 downto 6);
else
nextState <= store_tem;
temint_temp_next <= temint_temp;
end if;
vccint_temp_next <= vccint_temp;
addr_next <= "0000000";
when others =>
nextState <= read_vcc;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000000";
end case;
end process;
vccint <= vccint_temp;
temint <= temint_temp;
-- Connect ALM[2] (Vccaux alarm) to output
alarm <= alm(2);
my_sysmon : SYSMON
generic map(
INIT_40 => X"0000",
INIT_41 => X"20C7",
INIT_42 => X"0A00",
INIT_43 => X"0000",
INIT_44 => X"0000",
INIT_45 => X"0000",
INIT_46 => X"0000",
INIT_47 => X"0000",
INIT_48 => X"0301",
INIT_49 => X"0000",
INIT_4A => X"0000", -- Sequence register 2
INIT_4B => X"0000", -- Sequence register 3
INIT_4C => X"0000", -- Sequence register 4
INIT_4D => X"0000", -- Sequence register 5
INIT_4E => X"0000", -- Sequence register 6
INIT_4F => X"0000", -- Sequence register 7
INIT_50 => X"0000", -- Alarm limit register 0
INIT_51 => X"0000", -- Alarm limit register 1
INIT_52 => X"E000", -- Alarm limit register 2
INIT_53 => X"0000", -- Alarm limit register 3
INIT_54 => X"0000", -- Alarm limit register 4
INIT_55 => X"0000", -- Alarm limit register 5
INIT_56 => X"CAAA", -- Alarm limit register 6
INIT_57 => X"0000", -- Alarm limit register 7
SIM_MONITOR_FILE => "vccaux_alarm.txt" --Stimulus file for analog simulation
)
port map (
DCLK => clk,
DWE => '0',
DEN => eos,
DRDY => rdy,
DADDR => addr,
DO => dobus,
CHANNEL => open,
EOS => eos,
BUSY => busy,
ALM => alm,
RESET=> '0',
CONVST => '0',
CONVSTCLK => '0',
DI => "0000000000000000",
VAUXN => "0000000000000000",
VAUXP=> "0000000000000000",
VN => '0',
VP => '0'
);
end Behavioral;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_serieseOg.vhd
|
4
|
3084
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_ddiv_29_no_dsp_64.vhd
|
6
|
10825
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64;
ARCHITECTURE sin_taylor_series_ap_ddiv_29_no_dsp_64_arch OF sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64_arch;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_ddiv_29_no_dsp_64/sim/sin_taylor_series_ap_ddiv_29_no_dsp_64.vhd
|
6
|
10825
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64;
ARCHITECTURE sin_taylor_series_ap_ddiv_29_no_dsp_64_arch OF sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64_arch;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dadd_3_full_dsp_64/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
20
|
30077
|
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`protect end_protected
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
20
|
30077
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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`protect end_protected
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
20
|
30077
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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BW4AL9d6yw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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/inOtmJ9dyw3SQwornQ=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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`protect end_protected
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/synth/sin_taylor_series_ap_dsub_3_full_dsp_64.vhd
|
4
|
12855
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
|
mit
|
APastorG/APG
|
general/common_data_types_pkg.vhd
|
1
|
5832
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains common data types
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package common_data_types_pkg is
subtype T_sulv_index is integer range -2**30 to 2**30-1;
type T_speed is (t_exc, t_min, t_low, t_medium, t_high, t_max);
--std_ulogic_vector vector
type sulv_v is array (natural range <>) of std_ulogic_vector;
--std_ulogic_vector vector of vectors
type sulv_vv is array (natural range <>) of sulv_v;
type natural_v is array (natural range <>) of natural;
type positive_v is array (natural range <>) of positive;
type integer_v is array (natural range <>) of integer;
type integer_vv is array (natural range <>) of integer_v;
type real_v is array (natural range <>) of real;
type boolean_v is array (natural range <>) of boolean;
--u_sfixed vector
type u_sfixed_v is array (integer range <>) of u_sfixed;
--vector u_sfixed vectors
type u_sfixed_vv is array (integer range <>) of u_sfixed_v;
--vector of vector of u_sfixed vectors
type u_sfixed_vvv is array (integer range <>) of u_sfixed_vv;
--u_ufixed vector
type u_ufixed_v is array (integer range <>) of u_ufixed;
--vector of u_ufixed vectors
type u_ufixed_vv is array (integer range <>) of u_ufixed_v;
--sfixed vector
type sfixed_v is array (integer range <>) of sfixed;
--ufixed vector
type ufixed_v is array (integer range <>) of ufixed;
--vector in canonical signed digit representation. Each bit has the possible values of 0, 1, or
-- -1, which are represented by 2 bits: 00, 01, or 11 respectively
type T_csd is array (integer range<>) of bit_vector(2 downto 1);
--types for describing the behavior of fixed and floating point data
alias T_round_style is fixed_round_style_type;
alias T_overflow_style is fixed_overflow_style_type;
--type used for exceptions of generics of type positive (possible values: positive + '0').
-- Exception will portrayed by value 0
type positive_exc is range 0 to integer'high;
--type used for exceptions of generics of type natural (possible values: natural + '-1').
-- Exception will portrayed by value -1
type natural_exc is range -1 to integer'high;
--subtype used for exceptions of generics of type integer.
-- Exception will portrayed by value integer'low
subtype integer_exc is integer;
--subtype used for exceptions of generics of type real
subtype real_exc is real;
--type used for exceptions of generics of type boolean (possible values: t_false, t_true, and
-- t_exc)
type boolean_exc is (t_exc, t_true, t_false);
--types to use in testbenches to ease the testing of defined/undefined generics. They allow
-- setting a value for a generic and whether the assignment has been done inside the instantiation
type T_round_style_tb is record
value : T_round_style;
is_defined : boolean;
end record;
type T_overflow_style_tb is record
value : T_overflow_style;
is_defined : boolean;
end record;
type T_speed_tb is record
value : T_speed;
is_defined : boolean;
end record;
type boolean_tb is record
value : boolean;
is_defined : boolean;
end record;
type boolean_exc_tb is record
value : boolean_exc;
is_defined : boolean;
end record;
type natural_tb is record
value : natural;
is_defined : boolean;
end record;
type natural_exc_tb is record
value : natural_exc;
is_defined : boolean;
end record;
type positive_tb is record
value : positive;
is_defined : boolean;
end record;
type positive_exc_tb is record
value : positive_exc;
is_defined : boolean;
end record;
type integer_tb is record
value : integer;
is_defined : boolean;
end record;
type integer_exc_tb is record
value : integer_exc;
is_defined : boolean;
end record;
type real_tb is record
value : real;
is_defined : boolean;
end record;
type real_exc_tb is record
value : real_exc;
is_defined : boolean;
end record;
/* functions 1 */
/**************************************************************************************************/
--function to convert boolean_exc to boolean to prevent errors in the elaboration phase
function to_boolean(
arg : boolean_exc)
return boolean;
end package;
package body common_data_types_pkg is
function to_boolean(
arg : boolean_exc)
return boolean is
begin
if arg = t_true then
return true;
else
return false;
end if;
end function;
end package body;
|
mit
|
benjmarshall/hls_scratchpad
|
hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_series.vhd
|
4
|
12640
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
|
mit
|
SoCdesign/inputboard
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Balance.vhd
|
2
|
5209
|
----------------------------------------------------------------------------------
-- Company: TTU_SoCDesign
-- Engineer: Mohamed Behery
--
-- Create Date: 16:51:21 04/29/2015
-- Design Name: Panning unit
-- Module Name: Balance - Behavioral
-- Project Name: Audio mixer
-- Target Devices: ZedBoard (Zynq7000)
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Balance is
generic(INTBIT_WIDTH : positive ;
FRACBIT_WIDTH : positive ;
N : positive ;
Attenuation_Const : positive ); -- This constant is for attenuating the input signals so that the signal is not chopped if amplified
Port(CLK_BAL : in std_logic;
RESET_BAL : in std_logic;
POINTER : in integer;
CH_L_IN, CH_R_IN : in signed(INTBIT_WIDTH - 1 downto 0);
CH_L_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
CH_R_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
READY_BAL : out std_logic := '0'
);
end Balance;
Architecture Behavioral of Balance is
type Coeff_Array is array (0 to N / 2) of signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
-- Coeffecients calculated via the Matlab m-file (check the Matlab code in the last code section)
-- constant Amp_Coeff : Coeff_Array := (500,667,767,867,909,923,937,951,962,967,972,977,982,986,991,995,1000); --The second half of the balance graph has it's amplification values placed in Amp_Coeff array
-- constant Att_Coeff : Coeff_Array := (500,333,233,133,91,77,63,49,38,33,28,23,18,14,9,5,0); --The second half of the balance graph has it's attenuation values placed in Att_Coeff array
constant Amp_Coeff : Coeff_Array := (x"0001F400", x"00029B00", x"0002FF00", x"00036300", x"00038D00", x"00039B00", x"0003A900", x"0003B700", x"0003C200", x"0003C700", x"0003CC00", x"0003D100", x"0003D600", x"0003DA00", x"0003DF00", x"0003E300", x"0003E800");
constant Att_Coeff : Coeff_Array := (x"0001F400", x"00014D00", x"0000E900", x"00008500", x"00005B00", x"00004D00", x"00003F00", x"00003100", x"00002600", x"00002100", x"00001C00", x"00001700", x"00001200", x"00000E00", x"00000900", x"00000500", x"00000000");
signal Coeff_Left : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal Coeff_Right : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal ready_signal_right : STD_LOGIC;
signal ready_signal_left : STD_LOGIC;
signal CH_R_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_R_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
component AmplifierFP
Port(
CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed((INTBIT_WIDTH + FRACBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifying coefficient
OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end component;
begin
Mult_Left : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_L_IN_signal,
IN_COEF => Coeff_Left,
OUT_AMP => CH_L_OUT_signal,
OUT_RDY => ready_signal_left
);
Mult_Right : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_R_IN_signal,
IN_COEF => Coeff_right,
OUT_AMP => CH_R_OUT_signal,
OUT_RDY => ready_signal_right
);
READY_BAL <= (ready_signal_right and ready_signal_left);
CH_L_IN_signal <= shift_right(CH_L_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
CH_R_IN_signal <= shift_right(CH_R_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
Combinational : process(POINTER) -- Here according to the value of the POINTER the coefficient graph "half" is either kept as it is or it's inverted
begin
if (POINTER > N / 2) then -- Case 1: Amplify Right and Attenuate Left
Coeff_Right <= Amp_Coeff(POINTER - N / 2); -- If the POINTER is above 50% the graph is kept as it is
Coeff_Left <= Att_Coeff(POINTER - N / 2);
elsif (POINTER < N / 2) then -- Case 2: Amplify Left and Attenuate Right
Coeff_Right <= Att_Coeff(N / 2 - POINTER); -- If the POINTER is below 50% the graph is inverted
Coeff_Left <= Amp_Coeff(N / 2 - POINTER);
else
Coeff_Right <= Att_Coeff(0); -- else: the POINTER = 50%, give the coefficients the 0th value in the array
Coeff_Left <= Amp_Coeff(0);
end if;
end process Combinational;
Sequential : process(CLK_BAL)
begin
if (CLK_BAL'event and CLK_BAL = '1') then
CH_L_OUT <= CH_L_OUT_signal;
CH_R_OUT <= CH_R_OUT_signal;
end if;
end process Sequential;
end Behavioral;
|
mit
|
ptracton/Picoblaze
|
Picoblaze/Miscellaneous/ROM_form_for_multiple_instances.vhd
|
1
|
143763
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
IMPORTANT - This file does not contain the actual definition of the JTAG Loader hardware
and is only intended for use in the definition of the program memory of any
subsequent instances of the KCPSM6 in the same design. This is to avoid the
warnings generated by having multiple definitions of the JTAG Loader circuit.
Ken Chapman (Xilinx Ltd)
19th March 2012
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_40}",
INIT_01 => X"{[8:0]_INIT_41}",
INIT_02 => X"{[8:0]_INIT_42}",
INIT_03 => X"{[8:0]_INIT_43}",
INIT_04 => X"{[8:0]_INIT_44}",
INIT_05 => X"{[8:0]_INIT_45}",
INIT_06 => X"{[8:0]_INIT_46}",
INIT_07 => X"{[8:0]_INIT_47}",
INIT_08 => X"{[8:0]_INIT_48}",
INIT_09 => X"{[8:0]_INIT_49}",
INIT_0A => X"{[8:0]_INIT_4A}",
INIT_0B => X"{[8:0]_INIT_4B}",
INIT_0C => X"{[8:0]_INIT_4C}",
INIT_0D => X"{[8:0]_INIT_4D}",
INIT_0E => X"{[8:0]_INIT_4E}",
INIT_0F => X"{[8:0]_INIT_4F}",
INIT_10 => X"{[8:0]_INIT_50}",
INIT_11 => X"{[8:0]_INIT_51}",
INIT_12 => X"{[8:0]_INIT_52}",
INIT_13 => X"{[8:0]_INIT_53}",
INIT_14 => X"{[8:0]_INIT_54}",
INIT_15 => X"{[8:0]_INIT_55}",
INIT_16 => X"{[8:0]_INIT_56}",
INIT_17 => X"{[8:0]_INIT_57}",
INIT_18 => X"{[8:0]_INIT_58}",
INIT_19 => X"{[8:0]_INIT_59}",
INIT_1A => X"{[8:0]_INIT_5A}",
INIT_1B => X"{[8:0]_INIT_5B}",
INIT_1C => X"{[8:0]_INIT_5C}",
INIT_1D => X"{[8:0]_INIT_5D}",
INIT_1E => X"{[8:0]_INIT_5E}",
INIT_1F => X"{[8:0]_INIT_5F}",
INIT_20 => X"{[8:0]_INIT_60}",
INIT_21 => X"{[8:0]_INIT_61}",
INIT_22 => X"{[8:0]_INIT_62}",
INIT_23 => X"{[8:0]_INIT_63}",
INIT_24 => X"{[8:0]_INIT_64}",
INIT_25 => X"{[8:0]_INIT_65}",
INIT_26 => X"{[8:0]_INIT_66}",
INIT_27 => X"{[8:0]_INIT_67}",
INIT_28 => X"{[8:0]_INIT_68}",
INIT_29 => X"{[8:0]_INIT_69}",
INIT_2A => X"{[8:0]_INIT_6A}",
INIT_2B => X"{[8:0]_INIT_6B}",
INIT_2C => X"{[8:0]_INIT_6C}",
INIT_2D => X"{[8:0]_INIT_6D}",
INIT_2E => X"{[8:0]_INIT_6E}",
INIT_2F => X"{[8:0]_INIT_6F}",
INIT_30 => X"{[8:0]_INIT_70}",
INIT_31 => X"{[8:0]_INIT_71}",
INIT_32 => X"{[8:0]_INIT_72}",
INIT_33 => X"{[8:0]_INIT_73}",
INIT_34 => X"{[8:0]_INIT_74}",
INIT_35 => X"{[8:0]_INIT_75}",
INIT_36 => X"{[8:0]_INIT_76}",
INIT_37 => X"{[8:0]_INIT_77}",
INIT_38 => X"{[8:0]_INIT_78}",
INIT_39 => X"{[8:0]_INIT_79}",
INIT_3A => X"{[8:0]_INIT_7A}",
INIT_3B => X"{[8:0]_INIT_7B}",
INIT_3C => X"{[8:0]_INIT_7C}",
INIT_3D => X"{[8:0]_INIT_7D}",
INIT_3E => X"{[8:0]_INIT_7E}",
INIT_3F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_08}",
INITP_01 => X"{[8:0]_INITP_09}",
INITP_02 => X"{[8:0]_INITP_0A}",
INITP_03 => X"{[8:0]_INITP_0B}",
INITP_04 => X"{[8:0]_INITP_0C}",
INITP_05 => X"{[8:0]_INITP_0D}",
INITP_06 => X"{[8:0]_INITP_0E}",
INITP_07 => X"{[8:0]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_40}",
INIT_01 => X"{[17:9]_INIT_41}",
INIT_02 => X"{[17:9]_INIT_42}",
INIT_03 => X"{[17:9]_INIT_43}",
INIT_04 => X"{[17:9]_INIT_44}",
INIT_05 => X"{[17:9]_INIT_45}",
INIT_06 => X"{[17:9]_INIT_46}",
INIT_07 => X"{[17:9]_INIT_47}",
INIT_08 => X"{[17:9]_INIT_48}",
INIT_09 => X"{[17:9]_INIT_49}",
INIT_0A => X"{[17:9]_INIT_4A}",
INIT_0B => X"{[17:9]_INIT_4B}",
INIT_0C => X"{[17:9]_INIT_4C}",
INIT_0D => X"{[17:9]_INIT_4D}",
INIT_0E => X"{[17:9]_INIT_4E}",
INIT_0F => X"{[17:9]_INIT_4F}",
INIT_10 => X"{[17:9]_INIT_50}",
INIT_11 => X"{[17:9]_INIT_51}",
INIT_12 => X"{[17:9]_INIT_52}",
INIT_13 => X"{[17:9]_INIT_53}",
INIT_14 => X"{[17:9]_INIT_54}",
INIT_15 => X"{[17:9]_INIT_55}",
INIT_16 => X"{[17:9]_INIT_56}",
INIT_17 => X"{[17:9]_INIT_57}",
INIT_18 => X"{[17:9]_INIT_58}",
INIT_19 => X"{[17:9]_INIT_59}",
INIT_1A => X"{[17:9]_INIT_5A}",
INIT_1B => X"{[17:9]_INIT_5B}",
INIT_1C => X"{[17:9]_INIT_5C}",
INIT_1D => X"{[17:9]_INIT_5D}",
INIT_1E => X"{[17:9]_INIT_5E}",
INIT_1F => X"{[17:9]_INIT_5F}",
INIT_20 => X"{[17:9]_INIT_60}",
INIT_21 => X"{[17:9]_INIT_61}",
INIT_22 => X"{[17:9]_INIT_62}",
INIT_23 => X"{[17:9]_INIT_63}",
INIT_24 => X"{[17:9]_INIT_64}",
INIT_25 => X"{[17:9]_INIT_65}",
INIT_26 => X"{[17:9]_INIT_66}",
INIT_27 => X"{[17:9]_INIT_67}",
INIT_28 => X"{[17:9]_INIT_68}",
INIT_29 => X"{[17:9]_INIT_69}",
INIT_2A => X"{[17:9]_INIT_6A}",
INIT_2B => X"{[17:9]_INIT_6B}",
INIT_2C => X"{[17:9]_INIT_6C}",
INIT_2D => X"{[17:9]_INIT_6D}",
INIT_2E => X"{[17:9]_INIT_6E}",
INIT_2F => X"{[17:9]_INIT_6F}",
INIT_30 => X"{[17:9]_INIT_70}",
INIT_31 => X"{[17:9]_INIT_71}",
INIT_32 => X"{[17:9]_INIT_72}",
INIT_33 => X"{[17:9]_INIT_73}",
INIT_34 => X"{[17:9]_INIT_74}",
INIT_35 => X"{[17:9]_INIT_75}",
INIT_36 => X"{[17:9]_INIT_76}",
INIT_37 => X"{[17:9]_INIT_77}",
INIT_38 => X"{[17:9]_INIT_78}",
INIT_39 => X"{[17:9]_INIT_79}",
INIT_3A => X"{[17:9]_INIT_7A}",
INIT_3B => X"{[17:9]_INIT_7B}",
INIT_3C => X"{[17:9]_INIT_7C}",
INIT_3D => X"{[17:9]_INIT_7D}",
INIT_3E => X"{[17:9]_INIT_7E}",
INIT_3F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_08}",
INITP_01 => X"{[17:9]_INITP_09}",
INITP_02 => X"{[17:9]_INITP_0A}",
INITP_03 => X"{[17:9]_INITP_0B}",
INITP_04 => X"{[17:9]_INITP_0C}",
INITP_05 => X"{[17:9]_INITP_0D}",
INITP_06 => X"{[17:9]_INITP_0E}",
INITP_07 => X"{[17:9]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
mit
|
ObKo/USBCore
|
Extra/blk_ep_out_ctl.vhdl
|
1
|
3966
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_out_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end blk_ep_out_ctl;
architecture blk_ep_out_ctl of blk_ep_out_ctl is
component blk_out_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
axis_prog_full : out std_logic
);
end component;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal prog_full : std_logic;
begin
FULL_LATCH: process(usb_clk) is
begin
if rising_edge(usb_clk) then
blk_xfer_out_ready_read <= NOT prog_full;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
FIFO: blk_out_fifo
port map (
m_aclk => axis_clk,
s_aclk => usb_clk,
s_aresetn => NOT rst,
s_axis_tvalid => blk_xfer_out_data_valid,
s_axis_tready => open,
s_axis_tdata => blk_xfer_out_data,
m_axis_tvalid => axis_tvalid,
m_axis_tready => axis_tready,
m_axis_tdata => axis_tdata,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 960
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => blk_xfer_out_data_valid,
s_axis_tready => open,
s_axis_tdata => blk_xfer_out_data,
s_axis_tlast => '0',
m_axis_tvalid => axis_tvalid,
m_axis_tready => axis_tready,
m_axis_tdata => axis_tdata,
m_axis_tlast => open,
prog_full => prog_full
);
end generate;
axis_tlast <= '0';
end blk_ep_out_ctl;
|
mit
|
ptracton/Picoblaze
|
Picoblaze/ROM_form_templates/ROM_form_128_14March13.vhd
|
1
|
14031
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 0.125K program (128 instructions) for KCPSM6 in a Spartan-6,
Virtex-6 or 7-Series device using 9 Slices.
Ken Chapman (Xilinx Ltd)
14th March 2013 - First Release
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production template for a 0.125K program (128 instructions) for KCPSM6 in a Spartan-6,
-- Virtex-6 or 7-Series device using 9 Slices.
--
-- Note: The full 12-bit KCPSM6 address is connected but only the lower 7-bits will be
-- employed. Likewise the 'bram_enable' should still be connected to 'enable'.
-- This minimises the changes required to the hardware description of a design
-- when moving between different memory types and selecting different sizes.
--
-- program_rom: your_program
-- port map( address => address,
-- instruction => instruction,
-- enable => bram_enable,
-- clk => clk);
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_128_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal rom_value : std_logic_vector(17 downto 0);
--
begin
--
instruction_bit: for i in 0 to 17 generate
begin
--
kcpsm6_rom_flop: FDRE
port map ( D => rom_value(i),
Q => instruction(i),
CE => enable,
R => address(7+(i/4)),
C => clk);
--
end generate instruction_bit;
--
--
kcpsm6_rom0: ROM128X1
generic map( INIT => X"{INIT128_0}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(0));
--
kcpsm6_rom1: ROM128X1
generic map( INIT => X"{INIT128_1}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(1));
--
kcpsm6_rom2: ROM128X1
generic map( INIT => X"{INIT128_2}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(2));
--
kcpsm6_rom3: ROM128X1
generic map( INIT => X"{INIT128_3}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(3));
--
kcpsm6_rom4: ROM128X1
generic map( INIT => X"{INIT128_4}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(4));
--
kcpsm6_rom5: ROM128X1
generic map( INIT => X"{INIT128_5}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(5));
--
kcpsm6_rom6: ROM128X1
generic map( INIT => X"{INIT128_6}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(6));
--
kcpsm6_rom7: ROM128X1
generic map( INIT => X"{INIT128_7}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(7));
--
kcpsm6_rom8: ROM128X1
generic map( INIT => X"{INIT128_8}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(8));
--
kcpsm6_rom9: ROM128X1
generic map( INIT => X"{INIT128_9}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(9));
--
kcpsm6_rom10: ROM128X1
generic map( INIT => X"{INIT128_10}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(10));
--
kcpsm6_rom11: ROM128X1
generic map( INIT => X"{INIT128_11}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(11));
--
kcpsm6_rom12: ROM128X1
generic map( INIT => X"{INIT128_12}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(12));
--
kcpsm6_rom13: ROM128X1
generic map( INIT => X"{INIT128_13}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(13));
--
kcpsm6_rom14: ROM128X1
generic map( INIT => X"{INIT128_14}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(14));
--
kcpsm6_rom15: ROM128X1
generic map( INIT => X"{INIT128_15}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(15));
--
kcpsm6_rom16: ROM128X1
generic map( INIT => X"{INIT128_16}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(16));
--
kcpsm6_rom17: ROM128X1
generic map( INIT => X"{INIT128_17}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(17));
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
mit
|
ptracton/Picoblaze
|
Picoblaze/ROM_form_templates/ROM_form_7S_1K5_with_ecc_5Dec13.vhd
|
1
|
31778
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 1.5K program (address range 000 to 5FF) for KCPSM6 in a 7-Series
device using a RAMB36E1 primitive with built-in Error Correcting Code (ECC) and 4.5 Slices.
PLEASE READ THE DESCRIPTIONS AND ADVICE LATER IN THIS TEMPLATE OR CONTAINED IN THE
ASSEMBLED FILE.
Ken Chapman (Xilinx Ltd)
5th December 2013 - Initial Release
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_1K5_with_ecc_5Dec13.vhd
--
--
-- Production definition of a 1.5K program (address range 000 to 5FF) for KCPSM6 in a
-- 7-Series device using a RAMB36E1 primitive with built-in Error Correcting Code (ECC)
-- and 4.5 Slices.
--
-- NOTE - Compared with any of the normal program memory definitions for KCPSM6 this
-- module has additional outputs associated with the error detection and
-- correction feature. Only use this module if there is a clear requirement to
-- perform error detection and correction and do consider all the factors
-- described below before incorporating it in a design.
--
-- The built-in ECC feature can only be used when the RAMB36E1 primitive is
-- configured to be 64 data bits wide plus 8 'parity' (ECC) bits. At this aspect
-- ratio the memory has 512 locations. In this KCPSM6 program memory, three
-- 18-bit instructions are packed into each 64-bit word resulting in the somewhat
-- unusual program size of 1.5K instructions. So please be very aware that the
-- address range is (000 to 5FF) as that is not a power of two!
--
-- When the built-in ECC feature is used, the clock to output time of the
-- RAMB36E1 is also increased. Furthermore, a multiplexer is then required to
-- select the required instruction from the three presented in each 64-bit word
-- which also increases the time taken for the instruction to reach KCPSM6. Hence
-- the maximum clock frequency that can be achieved when using this ECC protected
-- memory will be less than when using any of the standard memories. If highest
-- performance is critical to your application then...
-- i) Reconsider if error correction is really required.
-- ii) Consider using the program memory with CRC error detection only.
-- iii) The 'sleep' mode could be used to run KCPSM6 at a lower rate whilst
-- remaining synchronous the higher clock rate (see 'Slow down waveforms' on
-- page 39 of the 'KCPSM6_User_Guide'). One or more additional clock cycles
-- would then be available to read the ECC protected memory. Hint: You will
-- need to permanently enable the memory (i.e. tie 'enable' High) and
-- define a multi-cycle timing constraint to cover the path from the
-- program memory to KCPSM6. Adding a pipeline stage in the instruction
-- path would also be possible when using the slow down technique.
--
-- Error Detection and Correction Features
-- ---------------------------------------
--
-- In this application the BRAM is being used as a ROM and therefore the contents should
-- not change during normal operation. If for any reason the contents of the memory should
-- change then there is the potential for KCPSM6 to execute an instruction that is either
-- different to that expected or even an invalid op-code neither of which would be
-- desirable. Obviously this should not happen and in majority of cases it will be more
-- than acceptable to assume that it never will. However, designs in which extreme levels
-- of reliability are required may consider that the special error detection and correction
-- features provided in this memory definition are useful.
--
-- This memory uses the built-in Error Correcting Code (ECC) feature of the RAMB36E1
-- primitive. This requires that the memory is configured to be 512 locations each
-- containing a 64-bit data word and an 8-bit ECC. 'address[8:0]' from KCPM6 is supplied
-- directly to the RAMB36E1 primitive and reads a 64-bit word containing three 18-bit
-- instructions (i.e. 54-bits are actually used). A single bit error anywhere in the
-- 64-bit word or the 8-bit ECC value will be detected and corrected by the built-in
-- logic. 'address[10:9]' from KCPM6 is then used (via a pipeline compensation register)
-- to select the required instruction from the three presented.
--
-- The arrangement means that the three instructions packed into each memory location
-- are from different 'blocks' of the program address range.
--
-- BRAM Data Bits Instruction from address address [8:0]
-- KCPSM6 Address Range [11:9]
--
-- [57:40] 400 to 5FF 010 000000000 - 111111111
-- [37:20] 200 to 3FF 001 000000000 - 111111111
-- [17:0] 000 to 1FF 000 000000000 - 111111111
--
-- The ECC scheme can correct any single bit errors which, although rare, are the most
-- likely to occur. In the unlikely event that a double bit error should occur (in the
-- same 64+8 bits) then the ECC scheme will report its detection even though it can not
-- correct. The 'SBITERR' and 'DBITERR' status signals from the built-in ECC decoder and
-- correction logic are presented as outputs of this memory. In most cases 'SBITERR' can
-- be ignored but it is always interesting to log events (e.g. how often did KCPSM6
-- benefit from using this feature?). 'DBITERR' could mean that KCPSM6 has be presented
-- with a corrupted instruction so it would probably be time to perform some further
-- checks and/or mitigation at the system level.
--
-- Note - If a double bit error is detected and reported then there is a 75% probability
-- that is did not corrupt the instruction that KCPSM6 actually used (i.e. the
-- instruction used is only 18-bits out of the 72-bits read from the memory). At
-- the time that this particular KCPSM6 program memory was developed there were
-- ideas to implement an enhanced scheme capable of refining the error reporting
-- to only the instruction being selected. Please check to see if this scheme is
-- now available for your consideration.
--
--
-- SEU Mitigation
-- --------------
--
-- One concern for the very highest reliability systems are Single Event Upsets (SEU)
-- caused by radiation. FIT rates for BRAM are published and updated quarterly in UG116
-- and these should be used to evaluate the potential failure rates prior to using this
-- memory with its error detection and correction features.
--
-- UG116 (v9.6) published 19th November 2013 shows that the real time soft error rate for
-- Block RAM memory in a 7-Series device is 78 FIT/Mb. Based on this figure (you should
-- always use the latest version of UG116 in your own calculations), the nominal upset
-- rate for contents of this one RAMB36E1 (36kbits) is 1.44 FIT. That's equivalent to one
-- upset inside this memory every 79,274 years when operating at sea-level New York. Even
-- when flying at an altitude of 40,000ft anywhere around the world the upset rate would
-- be 158 years (and aircraft don't fly for that long!).
--
-- The analysis shows that it is most unlikely that multiple events would lead to the
-- accumulation of bit errors within the same KCPSM6 program memory. Even if two events
-- did lead to two upsets it is statistically unlikely (1 in 512) that they would both
-- occur in the same 64+8 bit location and hence the ECC scheme would be able to detect
-- and correct the single bit errors contained in any of the instructions as they were
-- being read.
--
-- Note - When an error is detected, it is only the word read from the memory is corrected.
-- The contents of the memory remain the same so any error will be detected and
-- corrected every time the same location is accessed. Hence the 'SBITERR' would be
-- seen to pulse High every time KCPSM6 accessed the memory location containing the
-- error. Hence, multiple 'SBITERR' pulses do NOT mean there are multiple errors.
-- It would be possible to implement a memory write-back or 'scrubbing' mechanism
-- but with such a low probability of multiple events leading to the accumulation
-- of errors such a scheme was considered to be unnecessary.
--
--
-- Mitigation of incorrect program execution using 'DEFAULT_JUMP' Directive
-- ------------------------------------------------------------------------
--
-- Even with an ECC protected program memory there is the possibility of an SEU impacting
-- the operation of KCPSM6 (i.e. an SEU flips a configuration cell that impacts either the
-- logic or interconnect associated with KCPSM6). There is also the potential for a PSM
-- program to be incorrect in some way (i.e. we all make mistakes!). As such, it is
-- possible that KCPSM6 could at some time attempt to fetch an instruction from an address
-- outside of the available memory range 000 to 5FF hex.
--
-- This memory will detect any address in the range 600 to FFF hex and force the 18-bit
-- instruction to be a predictable fixed value. The KCPSM6 Assembler supports a directive
-- called 'DEFAULT_JUMP' which is described in 'all_kcpsm6_syntax.psm'. This directive
-- is normally used to fill all otherwise unused locations in a memory with a 'JUMP'
-- instruction to a address defined by the user. The user would typically define a special
-- routine at this location to handle the otherwise unexpected case. When 'DEFAULT_JUMP'
-- is used with this memory it will fill all otherwise unused locations in the usual way
-- but it will also define the output instruction in the address range 600 to FFF hex.
--
-- Hint - In the interest of achieving maximum reliability it is recommended that the
-- 'DEFAULT_JUMP' directive be used. If it is not used then this memory will still
-- detect any address in the range 600 to FFF hex and force the output instruction
-- to '00000' equivalent to 'LOAD s0, s0' which is a 'no-operation' (which is also
-- the default for any unused locations in any program memory).
--
--
-- TESTING METHODS
-- ---------------
--
-- The error correction capability can be tested by deliberately corrupting any bit stored
-- in the memory by manually adjusting one of the INIT values before processing the design.
-- Then observe the SBITERR and DBITERR outputs when KCPSM6 fetches the corrupted word from
-- the memory.
--
-- Hints - Each hexadecimal digit in an INIT string represents 4 adjacent bits in the
-- same 64-bit word (or 8-bit ECC) read from the memory so only adjust a digit
-- in a way that would create a single bit error or an adjacent double bit error
-- (e.g. 'E' hex = 1110 binary so 'A' hex would be the single bit error 1010 but
-- '0' hex would be a 3-bit error 0000 and an unrealistic test case).
--
-- SBITERR or DBITERR will pulse when KCPSM6 reads a word from memory containing
-- an error. Each word is associated with three addresses in different 'blocks'
-- (see above). So consider where you locate the error and how your PSM program
-- will execute because each error relates to three addresses.
--
-- Single bit errors are corrected so KCPSM6 execution should always continue
-- to be correct when SBITERR pulses are observed. If a double bit error is
-- created and DBITERR pulse is observed then the instruction fetched could be
-- corrupted depending on where you created the error.
--
-- Each 64-bit word contains three 18-bit instructions and ten otherwise unused
-- bits (bits 18, 19, 38, 39, 58, 59, 60, 61, 62, 62 and 63). Errors created in
-- these unused bits will still result in SBITERR or DBITERR pulses but we
-- would know that all three instructions remain valid. Hence these are good
-- places to create double bit errors for test purposes.
--
-- With due care and attention paid to the fact that each 64-bit word contains
-- three instructions from different blocks, your PSM code could contain a test
-- routine located at a particular address range corresponding with the location
-- of the deliberate errors created in the INIT strings. In this way SBITERR and
-- DBITERR could be made to pulse when required for test purposes but normal
-- operation would never execute any of the instructions contained in the
-- corrupted word(s).
--
--
-------------------------------------------------------------------------------------------
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(63 downto 0);
signal data_out : std_logic_vector(63 downto 0);
signal data_in_p : std_logic_vector(7 downto 0);
--
signal pipe_address : std_logic_vector(11 downto 9);
--
--
constant default_jump : std_logic_vector(17 downto 0) := "{default_jump}";
--
--
begin
--
address_a <= '1' & address(8 downto 0) & "111111";
address_b <= "1111111111111111";
data_in <= data_out(63 downto 58) & "000000000000000000" & data_out(39 downto 38) & "000000000000000000" & data_out(19 downto 18)& "000000000000000000";
data_in_p <= "00000000";
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 72,
WRITE_WIDTH_A => 0,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 0,
WRITE_WIDTH_B => 72,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => TRUE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{ECC_7S_1K5_INIT_00}",
INIT_01 => X"{ECC_7S_1K5_INIT_01}",
INIT_02 => X"{ECC_7S_1K5_INIT_02}",
INIT_03 => X"{ECC_7S_1K5_INIT_03}",
INIT_04 => X"{ECC_7S_1K5_INIT_04}",
INIT_05 => X"{ECC_7S_1K5_INIT_05}",
INIT_06 => X"{ECC_7S_1K5_INIT_06}",
INIT_07 => X"{ECC_7S_1K5_INIT_07}",
INIT_08 => X"{ECC_7S_1K5_INIT_08}",
INIT_09 => X"{ECC_7S_1K5_INIT_09}",
INIT_0A => X"{ECC_7S_1K5_INIT_0A}",
INIT_0B => X"{ECC_7S_1K5_INIT_0B}",
INIT_0C => X"{ECC_7S_1K5_INIT_0C}",
INIT_0D => X"{ECC_7S_1K5_INIT_0D}",
INIT_0E => X"{ECC_7S_1K5_INIT_0E}",
INIT_0F => X"{ECC_7S_1K5_INIT_0F}",
INIT_10 => X"{ECC_7S_1K5_INIT_10}",
INIT_11 => X"{ECC_7S_1K5_INIT_11}",
INIT_12 => X"{ECC_7S_1K5_INIT_12}",
INIT_13 => X"{ECC_7S_1K5_INIT_13}",
INIT_14 => X"{ECC_7S_1K5_INIT_14}",
INIT_15 => X"{ECC_7S_1K5_INIT_15}",
INIT_16 => X"{ECC_7S_1K5_INIT_16}",
INIT_17 => X"{ECC_7S_1K5_INIT_17}",
INIT_18 => X"{ECC_7S_1K5_INIT_18}",
INIT_19 => X"{ECC_7S_1K5_INIT_19}",
INIT_1A => X"{ECC_7S_1K5_INIT_1A}",
INIT_1B => X"{ECC_7S_1K5_INIT_1B}",
INIT_1C => X"{ECC_7S_1K5_INIT_1C}",
INIT_1D => X"{ECC_7S_1K5_INIT_1D}",
INIT_1E => X"{ECC_7S_1K5_INIT_1E}",
INIT_1F => X"{ECC_7S_1K5_INIT_1F}",
INIT_20 => X"{ECC_7S_1K5_INIT_20}",
INIT_21 => X"{ECC_7S_1K5_INIT_21}",
INIT_22 => X"{ECC_7S_1K5_INIT_22}",
INIT_23 => X"{ECC_7S_1K5_INIT_23}",
INIT_24 => X"{ECC_7S_1K5_INIT_24}",
INIT_25 => X"{ECC_7S_1K5_INIT_25}",
INIT_26 => X"{ECC_7S_1K5_INIT_26}",
INIT_27 => X"{ECC_7S_1K5_INIT_27}",
INIT_28 => X"{ECC_7S_1K5_INIT_28}",
INIT_29 => X"{ECC_7S_1K5_INIT_29}",
INIT_2A => X"{ECC_7S_1K5_INIT_2A}",
INIT_2B => X"{ECC_7S_1K5_INIT_2B}",
INIT_2C => X"{ECC_7S_1K5_INIT_2C}",
INIT_2D => X"{ECC_7S_1K5_INIT_2D}",
INIT_2E => X"{ECC_7S_1K5_INIT_2E}",
INIT_2F => X"{ECC_7S_1K5_INIT_2F}",
INIT_30 => X"{ECC_7S_1K5_INIT_30}",
INIT_31 => X"{ECC_7S_1K5_INIT_31}",
INIT_32 => X"{ECC_7S_1K5_INIT_32}",
INIT_33 => X"{ECC_7S_1K5_INIT_33}",
INIT_34 => X"{ECC_7S_1K5_INIT_34}",
INIT_35 => X"{ECC_7S_1K5_INIT_35}",
INIT_36 => X"{ECC_7S_1K5_INIT_36}",
INIT_37 => X"{ECC_7S_1K5_INIT_37}",
INIT_38 => X"{ECC_7S_1K5_INIT_38}",
INIT_39 => X"{ECC_7S_1K5_INIT_39}",
INIT_3A => X"{ECC_7S_1K5_INIT_3A}",
INIT_3B => X"{ECC_7S_1K5_INIT_3B}",
INIT_3C => X"{ECC_7S_1K5_INIT_3C}",
INIT_3D => X"{ECC_7S_1K5_INIT_3D}",
INIT_3E => X"{ECC_7S_1K5_INIT_3E}",
INIT_3F => X"{ECC_7S_1K5_INIT_3F}",
INIT_40 => X"{ECC_7S_1K5_INIT_40}",
INIT_41 => X"{ECC_7S_1K5_INIT_41}",
INIT_42 => X"{ECC_7S_1K5_INIT_42}",
INIT_43 => X"{ECC_7S_1K5_INIT_43}",
INIT_44 => X"{ECC_7S_1K5_INIT_44}",
INIT_45 => X"{ECC_7S_1K5_INIT_45}",
INIT_46 => X"{ECC_7S_1K5_INIT_46}",
INIT_47 => X"{ECC_7S_1K5_INIT_47}",
INIT_48 => X"{ECC_7S_1K5_INIT_48}",
INIT_49 => X"{ECC_7S_1K5_INIT_49}",
INIT_4A => X"{ECC_7S_1K5_INIT_4A}",
INIT_4B => X"{ECC_7S_1K5_INIT_4B}",
INIT_4C => X"{ECC_7S_1K5_INIT_4C}",
INIT_4D => X"{ECC_7S_1K5_INIT_4D}",
INIT_4E => X"{ECC_7S_1K5_INIT_4E}",
INIT_4F => X"{ECC_7S_1K5_INIT_4F}",
INIT_50 => X"{ECC_7S_1K5_INIT_50}",
INIT_51 => X"{ECC_7S_1K5_INIT_51}",
INIT_52 => X"{ECC_7S_1K5_INIT_52}",
INIT_53 => X"{ECC_7S_1K5_INIT_53}",
INIT_54 => X"{ECC_7S_1K5_INIT_54}",
INIT_55 => X"{ECC_7S_1K5_INIT_55}",
INIT_56 => X"{ECC_7S_1K5_INIT_56}",
INIT_57 => X"{ECC_7S_1K5_INIT_57}",
INIT_58 => X"{ECC_7S_1K5_INIT_58}",
INIT_59 => X"{ECC_7S_1K5_INIT_59}",
INIT_5A => X"{ECC_7S_1K5_INIT_5A}",
INIT_5B => X"{ECC_7S_1K5_INIT_5B}",
INIT_5C => X"{ECC_7S_1K5_INIT_5C}",
INIT_5D => X"{ECC_7S_1K5_INIT_5D}",
INIT_5E => X"{ECC_7S_1K5_INIT_5E}",
INIT_5F => X"{ECC_7S_1K5_INIT_5F}",
INIT_60 => X"{ECC_7S_1K5_INIT_60}",
INIT_61 => X"{ECC_7S_1K5_INIT_61}",
INIT_62 => X"{ECC_7S_1K5_INIT_62}",
INIT_63 => X"{ECC_7S_1K5_INIT_63}",
INIT_64 => X"{ECC_7S_1K5_INIT_64}",
INIT_65 => X"{ECC_7S_1K5_INIT_65}",
INIT_66 => X"{ECC_7S_1K5_INIT_66}",
INIT_67 => X"{ECC_7S_1K5_INIT_67}",
INIT_68 => X"{ECC_7S_1K5_INIT_68}",
INIT_69 => X"{ECC_7S_1K5_INIT_69}",
INIT_6A => X"{ECC_7S_1K5_INIT_6A}",
INIT_6B => X"{ECC_7S_1K5_INIT_6B}",
INIT_6C => X"{ECC_7S_1K5_INIT_6C}",
INIT_6D => X"{ECC_7S_1K5_INIT_6D}",
INIT_6E => X"{ECC_7S_1K5_INIT_6E}",
INIT_6F => X"{ECC_7S_1K5_INIT_6F}",
INIT_70 => X"{ECC_7S_1K5_INIT_70}",
INIT_71 => X"{ECC_7S_1K5_INIT_71}",
INIT_72 => X"{ECC_7S_1K5_INIT_72}",
INIT_73 => X"{ECC_7S_1K5_INIT_73}",
INIT_74 => X"{ECC_7S_1K5_INIT_74}",
INIT_75 => X"{ECC_7S_1K5_INIT_75}",
INIT_76 => X"{ECC_7S_1K5_INIT_76}",
INIT_77 => X"{ECC_7S_1K5_INIT_77}",
INIT_78 => X"{ECC_7S_1K5_INIT_78}",
INIT_79 => X"{ECC_7S_1K5_INIT_79}",
INIT_7A => X"{ECC_7S_1K5_INIT_7A}",
INIT_7B => X"{ECC_7S_1K5_INIT_7B}",
INIT_7C => X"{ECC_7S_1K5_INIT_7C}",
INIT_7D => X"{ECC_7S_1K5_INIT_7D}",
INIT_7E => X"{ECC_7S_1K5_INIT_7E}",
INIT_7F => X"{ECC_7S_1K5_INIT_7F}",
INITP_00 => X"{ECC_7S_1K5_INITP_00}",
INITP_01 => X"{ECC_7S_1K5_INITP_01}",
INITP_02 => X"{ECC_7S_1K5_INITP_02}",
INITP_03 => X"{ECC_7S_1K5_INITP_03}",
INITP_04 => X"{ECC_7S_1K5_INITP_04}",
INITP_05 => X"{ECC_7S_1K5_INITP_05}",
INITP_06 => X"{ECC_7S_1K5_INITP_06}",
INITP_07 => X"{ECC_7S_1K5_INITP_07}",
INITP_08 => X"{ECC_7S_1K5_INITP_08}",
INITP_09 => X"{ECC_7S_1K5_INITP_09}",
INITP_0A => X"{ECC_7S_1K5_INITP_0A}",
INITP_0B => X"{ECC_7S_1K5_INITP_0B}",
INITP_0C => X"{ECC_7S_1K5_INITP_0C}",
INITP_0D => X"{ECC_7S_1K5_INITP_0D}",
INITP_0E => X"{ECC_7S_1K5_INITP_0E}",
INITP_0F => X"{ECC_7S_1K5_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out(31 downto 0),
DIADI => data_in(31 downto 0),
DIPADIP => data_in_p(3 downto 0),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '0',
CLKBWRCLK => '0',
DOBDO => data_out(63 downto 32),
DIBDI => data_in(63 downto 32),
DIPBDIP => data_in_p(7 downto 4),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
SBITERR => SBITERR,
DBITERR => DBITERR,
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
pipe_address_loop: for i in 9 to 11 generate
begin
--
kcpsm6_rom_flop: FDE
port map ( D => address(i),
Q => pipe_address(i),
CE => enable,
C => clk);
--
end generate pipe_address_loop;
--
instruction_width_loop: for i in 0 to 17 generate
begin
--
force_low: if default_jump(i)='0' generate
begin
--
kcpsm6_rom_lut: LUT6
generic map (INIT => X"0000000000F0CCAA")
port map( I0 => data_out(i),
I1 => data_out(i+20),
I2 => data_out(i+40),
I3 => pipe_address(9),
I4 => pipe_address(10),
I5 => pipe_address(11),
O => instruction(i));
--
end generate force_low;
--
force_high: if default_jump(i)='1' generate
begin
--
kcpsm6_rom_lut: LUT6
generic map (INIT => X"FFFFFFFFFFF0CCAA")
port map( I0 => data_out(i),
I1 => data_out(i+20),
I2 => data_out(i+40),
I3 => pipe_address(9),
I4 => pipe_address(10),
I5 => pipe_address(11),
O => instruction(i));
--
end generate force_high;
--
end generate instruction_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
mit
|
Main-Project-MEC/Systolic-Processor-On-FPGA
|
Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/bin_to_7segment.vhd
|
1
|
3865
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bin_to_7segment is
Port( CLK_I : in std_logic;
T2 : in std_logic;
PC : in std_logic_vector(15 downto 0);
SEG1 : out std_logic_vector(7 downto 1);
SEG2 : out std_logic_vector(7 downto 0));
end bin_to_7segment;
architecture Behavioral of bin_to_7segment is
-- +------- middle upper
-- |+------- right upper
-- ||+------ right lower
-- |||+----- middle lower
-- ||||+---- left lower
-- |||||+--- left upper
-- ||||||+-- middle middle
-- |||||||
constant LEDV_0 : std_logic_vector(6 downto 0):= "1111110";-- 0
constant LEDV_1 : std_logic_vector(6 downto 0):= "0110000";-- 1
constant LEDV_2 : std_logic_vector(6 downto 0):= "1101101";-- 2
constant LEDV_3 : std_logic_vector(6 downto 0):= "1111001";-- 3
constant LEDV_4 : std_logic_vector(6 downto 0):= "0110011";-- 4
constant LEDV_5 : std_logic_vector(6 downto 0):= "1011011";-- 5
constant LEDV_6 : std_logic_vector(6 downto 0):= "1011111";-- 6
constant LEDV_7 : std_logic_vector(6 downto 0):= "1110000";-- 7
constant LEDV_8 : std_logic_vector(6 downto 0):= "1111111";-- 8
constant LEDV_9 : std_logic_vector(6 downto 0):= "1111011";-- 9
constant LEDV_A : std_logic_vector(6 downto 0):= "1110111";-- A
constant LEDV_b : std_logic_vector(6 downto 0):= "0011111";-- b
constant LEDV_C : std_logic_vector(6 downto 0):= "1001110";-- C
constant LEDV_d : std_logic_vector(6 downto 0):= "0111101";-- d
constant LEDV_E : std_logic_vector(6 downto 0):= "1001111";-- E
constant LEDV_F : std_logic_vector(6 downto 0):= "1000111";-- F
signal LED_CNT : std_logic_vector(24 downto 0);
signal LED_VAL : std_logic_vector(15 downto 0);
begin
process(CLK_I)
variable LED4H, LED4L : std_logic_vector(3 downto 0);
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (LED_CNT(24) = '0') then
LED4H := LED_VAL( 7 downto 4);
LED4L := LED_VAL( 3 downto 0);
else
LED4H := LED_VAL(15 downto 12);
LED4L := LED_VAL(11 downto 8);
end if;
if (LED_CNT = 0) then LED_VAL <= PC; end if;
LED_CNT <= LED_CNT + 1;
case LED4H is
when X"0" => SEG1 <= LEDV_0;
when X"1" => SEG1 <= LEDV_1;
when X"2" => SEG1 <= LEDV_2;
when X"3" => SEG1 <= LEDV_3;
when X"4" => SEG1 <= LEDV_4;
when X"5" => SEG1 <= LEDV_5;
when X"6" => SEG1 <= LEDV_6;
when X"7" => SEG1 <= LEDV_7;
when X"8" => SEG1 <= LEDV_8;
when X"9" => SEG1 <= LEDV_9;
when X"A" => SEG1 <= LEDV_A;
when X"B" => SEG1 <= LEDV_b;
when X"C" => SEG1 <= LEDV_c;
when X"D" => SEG1 <= LEDV_d;
when X"E" => SEG1 <= LEDV_E;
when others => SEG1 <= LEDV_F;
end case;
case LED4L is
when X"0" => SEG2(7 downto 1) <= LEDV_0;
when X"1" => SEG2(7 downto 1) <= LEDV_1;
when X"2" => SEG2(7 downto 1) <= LEDV_2;
when X"3" => SEG2(7 downto 1) <= LEDV_3;
when X"4" => SEG2(7 downto 1) <= LEDV_4;
when X"5" => SEG2(7 downto 1) <= LEDV_5;
when X"6" => SEG2(7 downto 1) <= LEDV_6;
when X"7" => SEG2(7 downto 1) <= LEDV_7;
when X"8" => SEG2(7 downto 1) <= LEDV_8;
when X"9" => SEG2(7 downto 1) <= LEDV_9;
when X"A" => SEG2(7 downto 1) <= LEDV_A;
when X"B" => SEG2(7 downto 1) <= LEDV_b;
when X"C" => SEG2(7 downto 1) <= LEDV_c;
when X"D" => SEG2(7 downto 1) <= LEDV_d;
when X"E" => SEG2(7 downto 1) <= LEDV_E;
when others => SEG2(7 downto 1) <= LEDV_F;
end case;
SEG2(0) <= LED_CNT(24);
end if;
end if;
end process;
end Behavioral;
|
mit
|
Main-Project-MEC/Systolic-Processor-On-FPGA
|
Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/uart_tx.vhd
|
3
|
1725
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : in std_logic; -- toggle to send data
SER_OUT : out std_logic; -- Serial output line
DATA_FLAGQ : out std_logic -- Transmitting Flag
);
end UART_TX;
architecture TX_UART_arch of UART_TX is
signal BUF : std_logic_vector(7 downto 0);
signal TODO : integer range 0 to 9; -- bits to send
signal FLAGQ : std_logic;
signal CE_1 : std_logic;
signal C16 : std_logic_vector(3 downto 0);
begin
DATA_FLAGQ <= FLAGQ;
-- generate a CE_1 every 16 CE_16...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_1 <= '0';
if (RST_I = '1') then
C16 <= "0000";
elsif (CE_16 = '1') then
if (C16 = "1111") then
CE_1 <= '1';
end if;
C16 <= C16 + "0001";
end if;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
SER_OUT <= '1';
BUF <= "11111111";
TODO <= 0;
FLAGQ <= DATA_FLAG; -- idle
elsif (CE_1 = '1') then
if (TODO > 0) then -- transmitting
SER_OUT <= BUF(0); -- next bit
BUF <= '1' & BUF(7 downto 1);
if (TODO = 1) then
FLAGQ <= DATA_FLAG;
end if;
TODO <= TODO - 1;
elsif (FLAGQ /= DATA_FLAG) then -- new byte
SER_OUT <= '0'; -- start bit
TODO <= 9;
BUF <= DATA;
end if;
end if;
end if;
end process;
end TX_UART_arch;
|
mit
|
timtian090/Playground
|
UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_range_rtl.vhd
|
1
|
6299
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_range is
constant assert_name : string := "OVL_RANGE";
constant path : string := "";
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY);
constant cover_corner : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_CORNER);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
signal prev_test_expr : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif (not ovl_is_x(test_expr_x01)) then
if((unsigned(test_expr_x01) < min) or (unsigned(test_expr_x01) > max)) then
fire(0) <= '1';
ovl_error_proc("Test expression evaluates to a value outside the range specified by parameters min and max", severity_level,
property_type, assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif (ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_sanity or cover_corner)) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
prev_test_expr <= test_expr_x01;
if (reset_n = '0') then
fire(2) <= '0';
else
fire(2) <= '0';
if (cover_sanity and (test_expr_x01 /= prev_test_expr) and
not ovl_is_x(test_expr_x01) and not ovl_is_x(prev_test_expr)) then
ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
if (cover_corner and (unsigned(test_expr_x01) = min) and not ovl_is_x(test_expr_x01)) then
ovl_cover_proc("test_expr_at_min covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
if (cover_corner and (unsigned(test_expr_x01) = max) and not ovl_is_x(test_expr_x01)) then
ovl_cover_proc("test_expr_at_max covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not(cover_sanity) and not(cover_corner))) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
|
mit
|
scarter93/RSA-Encryption
|
testpy/me_tb_template.vhd
|
1
|
1960
|
-- Entity name: modular_exponentiation_tb
-- Author: Luis Gallet, Jacob Barnett
-- Contact: [email protected], [email protected]
-- Date: ${DATE}
-- Description:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
entity modular_exponentiation_tb is
end entity;
architecture test of modular_exponentiation_tb is
-- define the ALU compontent to be tested
component modular_exponentiation is
generic(
WIDTH_IN : integer := ${DATA_WIDTH}
);
port( N : in unsigned(WIDTH_IN-1 downto 0); --Number
Exp : in unsigned(WIDTH_IN-1 downto 0); --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
--latch_in: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0) --Output
--C : out std_logic
);
end component;
CONSTANT WIDTH_IN : integer := ${DATA_WIDTH};
CONSTANT clk_period : time := 1 ns;
Signal M_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal N_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal Exp_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal latch_in : std_logic := '0';
Signal clk : std_logic := '0';
Signal reset_t : std_logic := '0';
Signal C_out : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
--signal c_out : std_logic;
Begin
-- device under test
dut: modular_exponentiation
generic map(WIDTH_IN => WIDTH_IN)
PORT MAP( N => N_in,
Exp => Exp_in,
M => M_in,
--latch_in => latch_in,
clk => clk,
reset => reset_t,
C => C_out
);
-- process for clock
clk_process : Process
Begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_process: process
Begin
reset_t <= '1';
wait for 1 * clk_period;
reset_t <= '0';
wait for 1 * clk_period;
${TEST_BODY}
wait;
end process;
end;
|
mit
|
timtian090/Playground
|
UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_never_unknown_async.vhd
|
1
|
1153
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown_async is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown_async;
|
mit
|
Main-Project-MEC/Systolic-Processor-On-FPGA
|
ISE Design Files/FA10/FA10_tb.vhd
|
1
|
2943
|
library ieee;
use ieee.std_logic_1164.all;
entity FA10_tb is
end FA10_tb;
architecture tb of FA10_tb is
component FA10
port(
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0);
Sout : out std_logic_vector(9 downto 0);
Cout : out std_logic
);
end component;
signal A : std_logic_vector(9 downto 0);
signal B : std_logic_vector(9 downto 0);
signal Sout : std_logic_vector(9 downto 0);
signal Cout : std_logic;
begin
mapping: FA10 port map(A,B,Sout,Cout);
-- A(0)<='0';
-- A(1)<='0';
-- A(2)<='0';
-- A(3)<='0';
-- A(4)<='0';
-- A(5)<='0';
-- A(6)<='0';
-- A(7)<='0';
-- A(8)<='0';
-- A(9)<='0';
-- B(0)<='0';
-- B(1)<='0';
-- B(2)<='0';
-- B(3)<='0';
-- B(4)<='0';
-- B(5)<='0';
-- B(6)<='0';
-- B(7)<='0';
-- B(8)<='0';
-- B(9)<='0';
process
begin
A(0)<='0'; wait for 1 ns;
A(0)<='1'; wait for 1 ns;
end process;
process
begin
A(1)<='0'; wait for 2 ns;
A(1)<='1'; wait for 2 ns;
end process;
process
begin
A(2)<='0'; wait for 4 ns;
A(2)<='1'; wait for 4 ns;
end process;
process
begin
A(3)<='0'; wait for 8 ns;
A(3)<='1'; wait for 8 ns;
end process;
process
begin
A(4)<='0'; wait for 16 ns;
A(4)<='1'; wait for 16 ns;
end process;
process
begin
A(5)<='0'; wait for 32 ns;
A(5)<='1'; wait for 32 ns;
end process;
process
begin
A(6)<='0'; wait for 64 ns;
A(6)<='1'; wait for 64 ns;
end process;
process
begin
A(7)<='0'; wait for 128 ns;
A(7)<='1'; wait for 128 ns;
end process;
process
begin
A(8)<='0'; wait for 256 ns;
A(8)<='1'; wait for 256 ns;
end process;
process
begin
A(9)<='0'; wait for 512 ns;
A(9)<='1'; wait for 512 ns;
end process;
process
begin
B(0)<='0'; wait for 1024 ns;
B(0)<='1'; wait for 1024 ns;
end process;
process
begin
B(1)<='0'; wait for 2048 ns;
B(1)<='1'; wait for 2048 ns;
end process;
process
begin
B(2)<='0'; wait for 4096 ns;
B(2)<='1'; wait for 4096 ns;
end process;
process
begin
B(3)<='0'; wait for 8192 ns;
B(3)<='1'; wait for 8192 ns;
end process;
process
begin
B(4)<='0'; wait for 16384 ns;
B(4)<='1'; wait for 16384 ns;
end process;
process
begin
B(5)<='0'; wait for 32768 ns;
B(5)<='1'; wait for 32768 ns;
end process;
process
begin
B(6)<='0'; wait for 65536 ns;
B(6)<='1'; wait for 65536 ns;
end process;
process
begin
B(7)<='0'; wait for 131072 ns;
B(7)<='1'; wait for 131072 ns;
end process;
process
begin
B(8)<='0'; wait for 262144 ns;
B(8)<='1'; wait for 262144 ns;
end process;
process
begin
B(9)<='0'; wait for 524288 ns;
B(9)<='1'; wait for 524288 ns;
end process;
end tb;
configuration cfg_tb of FA10_tb is
for tb
end for;
end cfg_tb;
|
mit
|
Main-Project-MEC/Systolic-Processor-On-FPGA
|
Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/mem_content.vhd
|
1
|
26582
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mem_content is
-- content of m_0_0
constant m_0_0_0 : BIT_VECTOR := X"E2BF124C93051303CFCCAC2652AEC692651B64AB6F4B926C081C0804080004D8";
constant m_0_0_1 : BIT_VECTOR := X"3FECF52100000231E7622B29268922F7931543E3664B3853387CEE7E65615B26";
constant m_0_0_2 : BIT_VECTOR := X"A3DF7793B9EFA732AAA25225224A0504A18029D278325DA4C200000709A03C38";
constant m_0_0_3 : BIT_VECTOR := X"16FB6E31C79C5674A32FF38CBCDDCC3AC9249D44A8BC952CC48B890935196A2A";
constant m_0_0_4 : BIT_VECTOR := X"9747FF77CA23FDFFD5BFFD5AA5FFEAD447FFAB5019BBED52FFDD5F2099A8D485";
constant m_0_0_5 : BIT_VECTOR := X"BEBDD5F1A999ABDED9BDB7E3C3C87F7FECF6FFECF7BDB97FF67BDED8BFFB3DEF";
constant m_0_0_6 : BIT_VECTOR := X"F5795E5795A769DE72DEF5AFDAA92E593BEBF001E1A9DD5E15659B6EFA4B6B57";
constant m_0_0_7 : BIT_VECTOR := X"C979FFA375642725E137AB37725E7FE8DD5909287E2725E7FECDD49094D55FD7";
constant m_0_0_8 : BIT_VECTOR := X"CC29BD98577B30A6F6615DECC5056F6418B3E6AF158EE4EE2725E7FE8DD49096";
constant m_0_0_9 : BIT_VECTOR := X"A9468AB07F9A8DD52A43627DAB64EFEB6142615DECC29BD98577B30A6F6615DE";
constant m_0_0_A : BIT_VECTOR := X"C37F407497FFC07C6F39FD9ABA7747C65D0AB43A1468556A56BA4AF04870D26E";
constant m_0_0_B : BIT_VECTOR := X"D5A1521A956A49666EFB555B43EA964B4EA54B4A2940E47252C115963FB6E0D3";
constant m_0_0_C : BIT_VECTOR := X"D914D4D3FF4DEE6A66D4D4B6A6A514D4AA6A5352B4F696CACD252979E92D4A92";
constant m_0_0_D : BIT_VECTOR := X"FB783C1E0F07825B7DA5A8B56DFEB66D412888104BF52A4192884BC2D115A6FD";
constant m_0_0_E : BIT_VECTOR := X"D949482400AE5242865241948065201242A2A48250A884F290DF6942A59554A6";
constant m_0_0_F : BIT_VECTOR := X"E37FFEB6A42ADBBBB776EDDCABFC921BF5B5247F1241E46A40934A52921525BE";
-- content of m_0_1
constant m_0_1_0 : BIT_VECTOR := X"80710228CA648A1C4AC88A359072F4E3512A2443C653894400000400080005F8";
constant m_0_1_1 : BIT_VECTOR := X"2CDA76114000020319D9E2815261D81190833D5B640CA648A1C4A25E44519435";
constant m_0_1_2 : BIT_VECTOR := X"584711D108232251871523DA353AE97B250035ADC4767BADF1000005A216E21B";
constant m_0_1_3 : BIT_VECTOR := X"227805D04096659DA10D7682C82A834F48844968961CC087A661488CA5A921C7";
constant m_0_1_4 : BIT_VECTOR := X"9050A52548A93452D3052D320429699010A5A64449CAD232525737A0D57AFD47";
constant m_0_1_5 : BIT_VECTOR := X"AF3C7AC2F0A8C7203045C2290F304D14A6AA14A6AB2A8B0A535594448529AACA";
constant m_0_1_6 : BIT_VECTOR := X"EF694EF694EF295EF2F7FDAFA41022C42AF0C8000EF6C7AD2F13A802BD1890E0";
constant m_0_1_7 : BIT_VECTOR := X"6156F7D6D11BD9855C9BA46D1855BDF1B446F6279219855BDF1B4C4E486CF694";
constant m_0_1_8 : BIT_VECTOR := X"633522C66E458CDC8B19A9163426C8B0464D9A22FF7BB0ABD9855BDF1B4C4E4A";
constant m_0_1_9 : BIT_VECTOR := X"A4EE4A88CA560B349EA159FA54B0ABB499BD99A91633522C66E458CDC8B19A91";
constant m_0_1_A : BIT_VECTOR := X"88093E5F9081BE5F9F2CA1A53F15F2360FDF1F9FBF3F1F3E7EEF2788D45AB659";
constant m_0_1_B : BIT_VECTOR := X"0F9B3A81D327503B7334ADACDE1FC8E55E10E44B0CAE7331395EC7A39F805D7E";
constant m_0_1_C : BIT_VECTOR := X"6BAC675508C62DA3AACC670263384C676633B79DCE03B9D45321990CBD7C99D6";
constant m_0_1_D : BIT_VECTOR := X"26F47A3D1E8F472B1372BDCC034A00E323915631F0E65688A40DF5FF3BCE6466";
constant m_0_1_E : BIT_VECTOR := X"A944E733BE62199C6A39D88E746399D9984833392E4E6BE9CEC4DCAAB2230E56";
constant m_0_1_F : BIT_VECTOR := X"F49B5E4973A800AD5564D56C292E39D350019D254333583B3249792C4E1F9989";
-- content of m_0_2
constant m_0_2_0 : BIT_VECTOR := X"094339A22811E831226222911943600815C01222E322D910000000040FFFFAD8";
constant m_0_2_1 : BIT_VECTOR := X"8021119540000264311108A4D1D45A49D84AB11170E2851E8712291311144691";
constant m_0_2_2 : BIT_VECTOR := X"3D374DDCCE9BB99CF4C89A01A01246517C0028D20D0300221940000404400681";
constant m_0_2_3 : BIT_VECTOR := X"810CD0934E45111006D2F323B23B637CA7D346F226C3D1A0516CA6A28BC21314";
constant m_0_2_4 : BIT_VECTOR := X"0B8A117245658508C3508C357284618A8A1186AA2C85C8D8882CD34A228540D4";
constant m_0_2_5 : BIT_VECTOR := X"5943E85C8A2008F70B2E687C38E7E1422E41422E41905CA11720C92F508B9064";
constant m_0_2_6 : BIT_VECTOR := X"4212908421480090004B1283B5B966C925DE97FFF9D83E8540F220416447DC3C";
constant m_0_2_7 : BIT_VECTOR := X"49BDDA54D2B72126FB52A54D126F769534ADC8973A9126F769134BFDA8488400";
constant m_0_2_8 : BIT_VECTOR := X"309790612B20C2564184AC830C52E418E1E3061C321924972126F769134BFDAA";
constant m_0_2_9 : BIT_VECTOR := X"2216631A98006004406B91BB5124972684B204AC8309590612F20C25E4184BC8";
constant m_0_2_A : BIT_VECTOR := X"4A211611561106100323C842E00B1C5E1C78C138718250A30EB8101A0D440300";
constant m_0_2_B : BIT_VECTOR := X"19B762E317AC5477A1F22570D9185A2D04342D13D5AE2699AB1EEC0149842C44";
constant m_0_2_C : BIT_VECTOR := X"E95497EE4949856BF25497E524BF1497EA4BD61A5CFE0BD8A6A5B53D914DFB17";
constant m_0_2_D : BIT_VECTOR := X"F60D068341A0D168FB16349044226A2428B156294B113F4AD29C4BB17B62F753";
constant m_0_2_E : BIT_VECTOR := X"A54C2D563E732B5A730B5EC2C770B12B1A5A56396D4562385A3EC58AD6ABA2C1";
constant m_0_2_F : BIT_VECTOR := X"C36DEC041630105D0BAD42EE59AC8B5B4022B535156365F16B6D129184F0B07D";
-- content of m_0_3
constant m_0_3_0 : BIT_VECTOR := X"0006843D0F080F409E1D1E5F1004CFC4F5074E20000011F80C0C0C0C000000C9";
constant m_0_3_1 : BIT_VECTOR := X"0CD2700740000109524077C210821021C00020405E10F080F40BE4F0E8F23C5F";
constant m_0_3_2 : BIT_VECTOR := X"28A7A1C00043800020044044044B6099BF800892559008B04060000106602AD8";
constant m_0_3_3 : BIT_VECTOR := X"10204088A13C8F26D0807802802A03721D084001040001020840909080000200";
constant m_0_3_4 : BIT_VECTOR := X"6121110490004488BB088BB000445DA10111768402088800884442241140C459";
constant m_0_3_5 : BIT_VECTOR := X"88054C008C465A2200603120BA379122209C22209C270A11104E128008882709";
constant m_0_3_6 : BIT_VECTOR := X"31CC731CE67B8EF399A5215935B92A5BC88137FFF96054C00111404232488000";
constant m_0_3_7 : BIT_VECTOR := X"9ED7DB6CD5166A7B5112AECD67B5F6DB35459A569D0A7B5F6DB35559AD99B9CF";
constant m_0_3_8 : BIT_VECTOR := X"9654272CA84E59509CB2A13965CA89CB2DF9F2E990C84F226A7B5F6DF35559AD";
constant m_0_3_9 : BIT_VECTOR := X"B4E7828B938683369A2EF4934B4F2246B2A6B2B139656272CA84E59509CB2A13";
constant m_0_3_A : BIT_VECTOR := X"DA1165E7451175E613AC8806CE11212710C91321932642644FC4A6AB45983619";
constant m_0_3_B : BIT_VECTOR := X"4C1833C98346713183A231309912AD57EC2057C00AD8443015F089D098044A1D";
constant m_0_3_C : BIT_VECTOR := X"7D86076808605923B246072030398607230396D8EFFC9DB80231919C39E0819C";
constant m_0_3_D : BIT_VECTOR := X"BF75BA5D6EB74AB55FABCC984223222E0D5F7475424B76C8F74D4663BF076C07";
constant m_0_3_E : BIT_VECTOR := X"E0A856ABE24015F06015B0056C015B15F0606B65887252C8AF57EAFD2BEF357A";
constant m_0_3_F : BIT_VECTOR := X"64891C042B60108F9124647C0C8C95E840215B9192B645CEBE498A5292E55EAF";
-- content of m_0_4
constant m_0_4_0 : BIT_VECTOR := X"00848018060306401898780C00840DC0C0461C20800010CC180C080C07FFF811";
constant m_0_4_1 : BIT_VECTOR := X"4C814146000001000211460000800600E08000014C006430600180C4C3C0F00C";
constant m_0_4_2 : BIT_VECTOR := X"200380E09001C120298C92C92C9B24480300000001B2990284600000064000D8";
constant m_0_4_3 : BIT_VECTOR := X"10014208A0303C2200A07A48A08A5800B9000500618231604018800014010200";
constant m_0_4_4 : BIT_VECTOR := X"210050F1B09000282082820A2814105100504145000028448C00406132050118";
constant m_0_4_5 : BIT_VECTOR := X"04202449CC440810612531088000000A1E340A1E358D00050F1AC68002878D63";
constant m_0_4_6 : BIT_VECTOR := X"6B58C6B5AD210A42918D695B74CB6ECBC0419000000802449809414010404994";
constant m_0_4_7 : BIT_VECTOR := X"5E00493A0C40E97805060BA05780124E83103A12B409780124E83103A50A158C";
constant m_0_4_8 : BIT_VECTOR := X"82018D04031A080634100C682F406341048B568CB65B2F00E9780124A83103A7";
constant m_0_4_9 : BIT_VECTOR := X"2297422300865324508C8437492F0127900E900C682018D04031A080634100C6";
constant m_0_4_A : BIT_VECTOR := X"530050C04050D0C003A20C20020010971C48913811227160C722142311843099";
constant m_0_4_B : BIT_VECTOR := X"0D983381B3467A19018A30320D402513802C13A80270241004A0001003142001";
constant m_0_4_C : BIT_VECTOR := X"1D86076828601003B246073030394607230396DC470008B21231918419ECC19C";
constant m_0_4_D : BIT_VECTOR := X"19008040603018940489C60060A0A00A8C4A224CB18000080111B03117022E43";
constant m_0_4_E : BIT_VECTOR := X"44A81289C00404A60404A90128404E84A60609C0002000002501225509492128";
constant m_0_4_F : BIT_VECTOR := X"2008011409545002000400100A8084EE08A04E50909C040094009294A6004A06";
-- content of m_0_5
constant m_0_5_0 : BIT_VECTOR := X"528E81485241520A28282814528C94914452148AA94A42540400000407FFF855";
constant m_0_5_1 : BIT_VECTOR := X"220104224000010146514A28A2A8A28ACA944A531405201520A2814141405114";
constant m_0_5_2 : BIT_VECTOR := X"8A2B8ACA8515950A28AA90A90A9344953900089251A055269260000141092840";
constant m_0_5_3 : BIT_VECTOR := X"04A32A28A050146680A93A4225200232A822955428A29428428A8505155148A8";
constant m_0_5_4 : BIT_VECTOR := X"64344AF1D2AA082504225040A5128204144A08145028250425414244AA0D1419";
constant m_0_5_5 : BIT_VECTOR := X"82151128A1112288108484AA728F82095E34895E358D2944AF1AC791A2578D63";
constant m_0_5_6 : BIT_VECTOR := X"635AC6B1AD6B58C6B18C63084A201800282247FFF52151120504532A0A082042";
constant m_0_5_7 : BIT_VECTOR := X"014124892D04940506E11892C05049224B41250A4D2405049224B4125108B18D";
constant m_0_5_8 : BIT_VECTOR := X"880B8D10171A202E34405C68830163441020C1AA010080A09405049264B41251";
constant m_0_5_9 : BIT_VECTOR := X"020748A13210088042065284A000A0894049405C6880B8D10171A202E34405C6";
constant m_0_5_A : BIT_VECTOR := X"3142D144544A41442B0A250AC85042864552A51A840A3448970210A140908044";
constant m_0_5_B : BIT_VECTOR := X"D5A1530AB56A6B480A89415095128141808541AAA832A15250651944A0328295";
constant m_0_5_C : BIT_VECTOR := X"3410910A6509024890109114848810910848828481FC902A8524493229A55A9A";
constant m_0_5_D : BIT_VECTOR := X"9951A8D46A151A054CA04A212894952A4D0223450400101C01FF00520D141A15";
constant m_0_5_E : BIT_VECTOR := X"456140A0CAA15062815068541A1502102282A0CA52829482835328332040040A";
constant m_0_5_F : BIT_VECTOR := X"204110B2A042CA8610468435A2501062A595064A820CA1CA0492108424E502A6";
-- content of m_0_6
constant m_0_6_0 : BIT_VECTOR := X"516CAA4E935593534C4EADA6516C66DA641B46AA4E4A9A600000000407FFF859";
constant m_0_6_1 : BIT_VECTOR := X"0CEB6412000001484604134D284D2AD2D21B521366A935593534DA62756D59A6";
constant m_0_6_2 : BIT_VECTOR := X"B34BD2D289A5A51296ACC0CC0CDB709981800A52109A0892512000001660085C";
constant m_0_6_3 : BIT_VECTOR := X"16AA4A2AAA9B5662240D7A10800A00800DB49466AAA8D5AA54AA296941946B36";
constant m_0_6_4 : BIT_VECTOR := X"742692719A82AB496434964281A4B2140692C85412A049402901093011A49008";
constant m_0_6_5 : BIT_VECTOR := X"021015A82DDDA88A14B0B68340882AD24E36D24E378DA869271BC7D534938DE3";
constant m_0_6_6 : BIT_VECTOR := X"214A5210A5294A5231AC6B1D92ADAB61A02040000109015A84441A4808622042";
constant m_0_6_7 : BIT_VECTOR := X"0D012499244524340921499243404926491149A95514340492649114930A94A4";
constant m_0_6_8 : BIT_VECTOR := X"E8A98DD1531BA2A637454C6E8515637450A142A2110886812434049264911493";
constant m_0_6_9 : BIT_VECTOR := X"B6C74A2120974336D8040299200680824552454C6E8A98DD1531BA2A637454C6";
constant m_0_6_A : BIT_VECTOR := X"126A52611692D261232029A8004042065D52A52AA54A550A1700B6010080B819";
constant m_0_6_B : BIT_VECTOR := X"90A2431215086840A81250400000211184B511A32234A6514469501722A48484";
constant m_0_6_C : BIT_VECTOR := X"1016D423496DB24A1356D426B6A156D42B6A1A1023000468D5254922018D1218";
constant m_0_6_D : BIT_VECTOR := X"0B0080402010088C058842A14D25241A24426644FBFC0F03C1DCF8108D111810";
constant m_0_6_E : BIT_VECTOR := X"D16D1088D4A2446AA2446091182446046A8A885294ACA4022101623308CC3118";
constant m_0_6_F : BIT_VECTOR := X"2248842488C092028054A0102C94C42AA12442929884A60084921AD6B7004202";
-- content of m_0_7
constant m_0_7_0 : BIT_VECTOR := X"0080010842414248282829141080148141020400210040400000000400000241";
constant m_0_7_1 : BIT_VECTOR := X"0A8340020000000800150A208A208208C8840800140420142082914141485014";
constant m_0_7_2 : BIT_VECTOR := X"082388C804119008888210210203148401000240008804020020000015400054";
constant m_0_7_3 : BIT_VECTOR := X"0021220000521400008038400402400088020010208010200208044440400088";
constant m_0_7_4 : BIT_VECTOR := X"6020484010800224000240002012000100480000000024000400091008040108";
constant m_0_7_5 : BIT_VECTOR := X"0000000800000082041400200080008908040908040100048402008002420100";
constant m_0_7_6 : BIT_VECTOR := X"214A52948421084210A521084804892800081000040000000000012000200000";
constant m_0_7_7 : BIT_VECTOR := X"4010000804409100448048805004000201102400040100400020100241421084";
constant m_0_7_8 : BIT_VECTOR := X"8202010404020808041010082140004104085080804020009100400020100241";
constant m_0_7_9 : BIT_VECTOR := X"06874021008542A0D08410048920002910091010082020104040208080410100";
constant m_0_7_A : BIT_VECTOR := X"11005141004851410B0000020200109604000008000010000700342110802815";
constant m_0_7_B : BIT_VECTOR := X"04881340900260000009000000000300A0040080801201000024000080120204";
constant m_0_7_C : BIT_VECTOR := X"1480010024000000810001000008000100008A00030000680120090009A4409A";
constant m_0_7_D : BIT_VECTOR := X"090080402010080C0480C208209091100406664C00000000000000100D001A00";
constant m_0_7_E : BIT_VECTOR := X"406001804A210022210028400A10028022220048420210000101203300C82018";
constant m_0_7_F : BIT_VECTOR := X"2248801200D04802801020140244406200900648080C22000C00000001000602";
-- content of m_1_0
constant m_1_0_0 : BIT_VECTOR := X"E5E0924F05AD3BEC52829CFDAFFF7EFFAF2B5FD201E0900D20B7B41DE0924832";
constant m_1_0_1 : BIT_VECTOR := X"04A24A04964929EFCFD28E74A2E9673A5934F4A39D2CABA4B16D65E03F249241";
constant m_1_0_2 : BIT_VECTOR := X"8A412056D752A9E02F7BD752A9E02F73D09E0F04824124920C0E9E0944555535";
constant m_1_0_3 : BIT_VECTOR := X"000001E3C3777EAB7773F56EEC7BADDDCA9078241EA78249549176D5B5AA48A4";
constant m_1_0_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_8 : BIT_VECTOR := X"880140807C6807C6803A2C000000000000000000000000000000000000000000";
constant m_1_0_9 : BIT_VECTOR := X"801CE4B9C536A49F2B8E0029E91F562502C2982B550056AA53E19B235C46394F";
constant m_1_0_A : BIT_VECTOR := X"4895717C7129B6C4810133C1085B924C90C9A388000A2E3310AE4EA0AE239675";
constant m_1_0_B : BIT_VECTOR := X"5F47CD474F6ABF32B73D539E882248FB762D558A32E44D0BC944CC72B4B9571C";
constant m_1_0_C : BIT_VECTOR := X"E31C831C849DC891DC85115F2D5048D56322B9195BD5AB46ADECC8F355D5C2EE";
constant m_1_0_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000724AC77C";
constant m_1_0_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_1
constant m_1_1_0 : BIT_VECTOR := X"931179D88A1ECA9082DEDFAD29DAD2BDE73BDB351F10CCEB5038631311CCD440";
constant m_1_1_1 : BIT_VECTOR := X"8E75677ACCF79C1D7439D3AE751CEDD732FB0E74EB98965E76CA305BF95E76A3";
constant m_1_1_2 : BIT_VECTOR := X"B6A351492202815BFC9F2AA6D35BFC972F31188E46A04135100EF11CCB2AAA84";
constant m_1_1_3 : BIT_VECTOR := X"0000017E215953EA557A7D4AAD4AA955A9A8C46A22DC432A0654255320A32A32";
constant m_1_1_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000100000";
constant m_1_1_8 : BIT_VECTOR := X"A8012080330804A680330E000000000000000000000000000000000000000000";
constant m_1_1_9 : BIT_VECTOR := X"4002C943DB0B492E3096001832E8624B8480A04C660098CC30608537586EB0C1";
constant m_1_1_A : BIT_VECTOR := X"1C296235629D20280E24574421100489948022940017300000309420C2110A65";
constant m_1_1_B : BIT_VECTOR := X"281B8D0AC168C81056346B1A310501494C08881022608086110808A034380628";
constant m_1_1_C : BIT_VECTOR := X"C12009200829420294112FA852B801220084980466090502130081034601826C";
constant m_1_1_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000601988A0";
constant m_1_1_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_2
constant m_1_2_0 : BIT_VECTOR := X"78348B01A5C785C90F250000520425210042148348355AE034FD8E38345A0D3F";
constant m_1_2_1 : BIT_VECTOR := X"A2C2AD5558A8B4611C4B48E2D2258471691E12C238B1CBAAD4E48139EF22C068";
constant m_1_2_2 : BIT_VECTOR := X"B06834A086360939E3B0E6360939E3B0E08341A2E06B64834FFC8345A5575508";
constant m_1_2_3 : BIT_VECTOR := X"0000011068B0B9220B0204416040882C481A0D069F20D57ACAF4720392157357";
constant m_1_2_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_2_8 : BIT_VECTOR := X"88016000664807C6001F28000000000000000000000000000000000000000000";
constant m_1_2_9 : BIT_VECTOR := X"001A14B8F744A490B4BC0028C9FA6B2F864E18707800E0F051ABA26E02DC0546";
constant m_1_2_A : BIT_VECTOR := X"0DCC09C009E81544850F2E8F7BC35245A859C118001F167733964B40D2B69009";
constant m_1_2_B : BIT_VECTOR := X"53442C5546623A5A208110408863F0A6376165CA01424E83C8E42256899DF194";
constant m_1_2_C : BIT_VECTOR := X"159D859D871619E1618B9F9329D988D9752A50A913CBAAECA9E22AEB117C6141";
constant m_1_2_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000000B8DDF4C";
constant m_1_2_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_3
constant m_1_3_0 : BIT_VECTOR := X"155615EA90AC88E810208563085694842148C6112952AF9D12B0BB5152AD44CF";
constant m_1_3_1 : BIT_VECTOR := X"357856D0ADA15F117515ABA5788AF5D2B432456AE95EA2056C89515CA9057A2D";
constant m_1_3_2 : BIT_VECTOR := X"E22516808E995E5CA8922E995E5CA89220956A956A252D9133F2152AD1061028";
constant m_1_3_3 : BIT_VECTOR := X"00000052A51D1C621102AC42225188444A8955A2E5A54AB7456C44EA2542B62B";
constant m_1_3_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_8 : BIT_VECTOR := X"D00141002E3800D3806552000000000000000000000000000000000000000000";
constant m_1_3_9 : BIT_VECTOR := X"800A8DE26151EDB41A14000C9BE3336B86001201800403001930A86610CC2064";
constant m_1_3_A : BIT_VECTOR := X"0848432C4388860C94346614A50986C198404010001704004004D80068500C41";
constant m_1_3_B : BIT_VECTOR := X"014D064C6432631AE42D3216995715940004011D1484C20B582CA4C098388834";
constant m_1_3_C : BIT_VECTOR := X"81B009B00AB2822B28193EC17C14AB80402721013B55AE209DAA49B193A21488";
constant m_1_3_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000414BCA04";
constant m_1_3_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_4
constant m_1_4_0 : BIT_VECTOR := X"044304E218A00029326DEE399EF398C73BDE72047046251847B8885046251180";
constant m_1_4_1 : BIT_VECTOR := X"312C128827104A801084A8813C4270409E00213A204AB1412863C18208412884";
constant m_1_4_2 : BIT_VECTOR := X"408C438287188C82000007188C82000008842231288D2484200104627820823A";
constant m_1_4_3 : BIT_VECTOR := X"000000308C0407620022EC40045988008E23108840611895413871918D209409";
constant m_1_4_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_5 : BIT_VECTOR := X"0000000000000000000000000000000040000000000000000000000000000000";
constant m_1_4_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000180000";
constant m_1_4_8 : BIT_VECTOR := X"F0016180757807C5005F56000000000000000000000000000000000000000000";
constant m_1_4_9 : BIT_VECTOR := X"600050138A0A000A84A80012200000002484E301FF8603FF247B05184A309491";
constant m_1_4_A : BIT_VECTOR := X"D0012801281122201A3A105AD69070080082278C000038226138076012C18A0C";
constant m_1_4_B : BIT_VECTOR := X"3802A9129148800012804940218020684808EA45A168048C01009830A0044209";
constant m_1_4_C : BIT_VECTOR := X"50000800080882408812803802A1003A90885A044C10010A0609800A40108165";
constant m_1_4_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000281410E0";
constant m_1_4_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_5
constant m_1_5_0 : BIT_VECTOR := X"0D46902A346828214480842958C6B18C6B1A525069468129063221C54681418F";
constant m_1_5_1 : BIT_VECTOR := X"340A419481290282409022041A4835020D20A4188106682409635490A1241A0D";
constant m_1_5_2 : BIT_VECTOR := X"CA0D06B652422190A81202422190A81204146A341A0C001063F2146814924929";
constant m_1_5_3 : BIT_VECTOR := X"000000428D0505495041812A0A112541068351A0C4A51A0CD40931858F0A04A0";
constant m_1_5_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_5_8 : BIT_VECTOR := X"6804000029280090802228000000000000000000000000000000000000000000";
constant m_1_5_9 : BIT_VECTOR := X"DFFFE01FFEFC000FFF7DFFFFC0FFFE0FAFDFFB7FFF8203FF7FDBFF7FFEFFFDFF";
constant m_1_5_A : BIT_VECTOR := X"FFFFF0FFF0FFF001CFAF1FEF7BFFE01FC1FC0821FFFF7EFFBFFE07DFFFEF7DFB";
constant m_1_5_B : BIT_VECTOR := X"FFF3FFE3FFFF1FFF1FFFCFFFE7E1F87EFFFFFF83FFF01F5F8301FC3FE3FFFF8F";
constant m_1_5_C : BIT_VECTOR := X"EF0FFF8FFF8FFFF8FFFF8FFE07FE1C7FFFF9FC7FCFFFF91FE7FFFE7FFCFFFFFF";
constant m_1_5_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000779F9FF9";
constant m_1_5_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_6
constant m_1_6_0 : BIT_VECTOR := X"4C02046010E2202954818C6B5AC6B5AC694843402002234C02B289D4022300A0";
constant m_1_6_1 : BIT_VECTOR := X"910811802300462A02046811080210088408810A0442E0010963650208811804";
constant m_1_6_2 : BIT_VECTOR := X"480402A4965AAD020248965AAD02024894C020110805B6C02800002210000828";
constant m_1_6_3 : BIT_VECTOR := X"000000100404044A40538948087029010A0100805000088DD11971958FA88C88";
constant m_1_6_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_8 : BIT_VECTOR := X"E80000802820008000020A000000000000000000000000000000000000000000";
constant m_1_6_9 : BIT_VECTOR := X"E01EF011FF7E000FBFBE003FE01F7F078088827E0004FC007FFBBF7F1EFE3DFF";
constant m_1_6_A : BIT_VECTOR := X"1DFC78FC787DA3E010101FD0841BF009BCD3E79C000F2044422007E0FEF79E7D";
constant m_1_6_B : BIT_VECTOR := X"7F13EF13FF789F7887BC03DE00F0FC7F7F4DFFC537EE0F8FC1E0FE343D3DFF8C";
constant m_1_6_C : BIT_VECTOR := X"F7810781078FD1F8FD0F81FF03F9E27FF789FBBC4FDF89EE27EFE27BC47FE7EF";
constant m_1_6_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000007BDFDFFC";
constant m_1_6_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_7
constant m_1_7_0 : BIT_VECTOR := X"4442006210200021100084294A521084294A52042042032842300940420310A0";
constant m_1_7_1 : BIT_VECTOR := X"1018008001000280128020900840104804002008240220000800500008801884";
constant m_1_7_2 : BIT_VECTOR := X"C084420242000000024892000000024894442210188492442800042030020008";
constant m_1_7_3 : BIT_VECTOR := X"00000000840405010010A02002140400422110885001080C4018000001000C00";
constant m_1_7_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_8 : BIT_VECTOR := X"0805808008080000802228000000000000000000000000000000000000000000";
constant m_1_7_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
end mem_content;
package body mem_content is
end mem_content;
|
mit
|
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II
|
MaterialDeAuxilo/MIPS-MC_SingleEdge/mult_div.vhd
|
2
|
5816
|
-----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity multiplica is
generic(N: integer := 32);
port( Mcando: in std_logic_vector((N-1) downto 0);
Mcador: in std_logic_vector((N-1) downto 0);
clock,start: in std_logic;
endop: out std_logic;
produto: out std_logic_vector(2*N-1 downto 0));
end;
architecture multiplica of multiplica is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal cont: integer;
begin
--
-- registradores regP, regB, produto, endop e contador de execução
--
process(start, clock)
begin
if start='1'then
regP( N*2 downto N) <= (others=>'0');
regP( N-1 downto 0) <= Mcador;
regB <= '0' & Mcando;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=calc and regP(0)='1' then
regP(N*2 downto N) <= regP(N*2 downto N) + regB;
elsif EA=desloca then
regP <= '0' & regP(N*2 downto 1);
cont <= cont + 1;
elsif EA=termina then
produto <= regP( N*2-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a multiplicação
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= calc;
when calc => EA <= desloca;
when desloca => if cont=N then
EA <= termina;
else
EA <= calc;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end multiplica;
-----------------------------------------------------------------------
-- DIVISÃO
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity divide is
generic(N: integer := 16);
port( divisor: in std_logic_vector( (N-1) downto 0);
dividendo: in std_logic_vector( (N-1) downto 0);
clock,start : in std_logic;
endop : out std_logic;
quociente : out std_logic_vector( N-1 downto 0);
resto : out std_logic_vector( N-1 downto 0));
end;
architecture divide of divide is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal diferenca : std_logic_vector( N downto 0);
signal cont: integer;
begin
diferenca <= regP( N*2 downto N) - regB( N downto 0);
process(start, clock)
begin
if start='1'then
regP(N*2 downto N) <= (others=>'0');
regP(N-1 downto 0) <= dividendo;
regB <= '0' & divisor;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=desloca then
regP <= regP( N*2-1 downto 0) & regP(N*2);
elsif EA=calc then
if diferenca(N)='1' then
regP(0)<='0';
else
regP(0)<='1';
regP(N*2 downto N) <= diferenca;
end if;
cont <= cont + 1;
elsif EA=termina then
resto <= regP( N*2-1 downto N);
quociente <= regP( N-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a DIVISAO
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= desloca;
when desloca => EA <= calc;
when calc => if cont=N then
EA <= termina;
else
EA <= desloca;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end divide;
|
mit
|
timtian090/Playground
|
UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_implication.vhd
|
1
|
1343
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_implication is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
antecedent_expr : in std_logic;
consequent_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_implication;
|
mit
|
bluemurder/chaotic-rngs
|
rng01-vhdl/variable_Caos.vhd
|
1
|
2024
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0';
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
return res;
end function;
end variable_Caos;
|
mit
|
bluemurder/chaotic-rngs
|
rng06-vhdl/chaoticMap.vhd
|
2
|
1546
|
-- This block describes the chaotic map used for the random generator --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end chaoticMap;
architecture Behavioral of chaoticMap is
-- Supposing 2 integer bits and two's complement, the constants
-- correspond to zero, one and minus one values
constant zero : signed(N_BIT-1 downto 0) := (others => '0');
constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => '1', others => '0');
constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => '1', N_BIT-2 => '1', others => '0');
-- Stores the current state
signal reg : signed(N_BIT-1 downto 0);
begin
-- update map
proc_map: process(clk,reset)
begin
if reset = '0' then
if rising_edge(clk) then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(N_BIT-2 downto 0) & '0' ) - ( "111" & reg(N_BIT-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(N_BIT-2 downto 0)&'0' ) - ( "000" & reg(N_BIT-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= X0;
end if;
end process;
output <= reg(N_BIT-1);
end Behavioral;
|
mit
|
bluemurder/chaotic-rngs
|
rng08-vhdl/variable_Caos.vhd
|
1
|
3082
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0' ;
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
--if (k(scalamento)= '1') then
-- sott := conv_signed(2**((scalamento)+1),numBit)- k;
-- res := ((2**(scalamento+1)) * conv_integer(x))/(2**(scalamento));
--else
-- sott := conv_signed(2**((scalamento)),numBit)- k;
-- res := ((2**(scalamento)) * conv_integer(x))/(2**(scalamento));
--
--end if;
-- for i in 1 to scalamento loop
-- if(sott((scalamento)-i) = '1')then
-- res := res - ((2**(scalamento-i)) * conv_integer(x))/(2**(scalamento));
-- end if;
-- end loop;
--return res;
--res := (conv_integer(x)/(2**(numBit/2)))*(conv_integer(k)/(2**(numBit/2)));
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
--res := (((2**numBit-1)/(2**(numBit/2))) * (conv_integer(x)/(2**(numBit/2))))-(((conv_integer(1/8 * 2**(numBit-1))/(2**(numBit/2))))*(conv_integer(x)/(2**(numBit/2))));
--res := (2**Nint) * res;
--res := res/4;
--res :=(conv_integer(x)*conv_integer(k))/(2**(scalamento));
return res;
end function;
end variable_Caos;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.srcs/sources_1/ip/dbg_ila/dbg_ila_stub.vhdl
|
1
|
2795
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Oct 31 12:11:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top dbg_ila -prefix
-- dbg_ila_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dbg_ila is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end dbg_ila;
architecture stub of dbg_ila is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
palbicoc/AUX_Bus
|
AUX_bus.srcs/sim_1/new/vme64x_top_tb.vhd
|
1
|
34606
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.01.2016 14:56:57
-- Design Name:
-- Module Name: vme64x_top_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- librerie per simulazione vme64x ...
library work;
use work.VME64xSim.all;
use work.VME64x.all;
-- vme64x che non servono per la simulazione
-- use work.VME_CR_pack.all;
-- use work.VME_CSR_pack.all;
-- use work.wishbone_pkg.all;
-- use work.vme64x_pack.all;
library std;
use std.textio.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity vme64x_top_tb is
end vme64x_top_tb;
architecture AUX_Behavioral of vme64x_top_tb is
-- Component Declaration of UUT
COMPONENT VME64x_top
PORT (
clk_p : in STD_LOGIC;
clk_n : in STD_LOGIC;
-- Segnali Bus VME
VME_sysres_n : in STD_LOGIC;
VME_data : inout STD_LOGIC_VECTOR (31 downto 0); -- ALSO AUX
VME_dataOE : out STD_LOGIC;
VME_data_DIR : out STD_LOGIC;
VME_DSy : in STD_LOGIC_VECTOR (1 downto 0);
VME_addr : inout STD_LOGIC_VECTOR (31 downto 1);
VME_addrOE : out STD_LOGIC;
VME_addr_DIR : out STD_LOGIC;
VME_WRITEy : in STD_LOGIC;
VME_LWordy : inout STD_LOGIC;
VME_oeabBERR : out STD_LOGIC;
VME_oeabDTACK : out STD_LOGIC;
VME_DTACKa : out STD_LOGIC;
VME_ASy : in STD_LOGIC;
VME_IACKy : in STD_LOGIC;
VME_IACKINy : in std_logic;
VME_IACKOUTa : out std_logic;
VME_oeabRETRY : out STD_LOGIC;
VME_RETRYa : out STD_LOGIC;
VME_am : in STD_LOGIC_VECTOR (5 downto 0);
VME_switch : in STD_LOGIC_VECTOR (7 downto 0);
VME_irq : out STD_LOGIC_VECTOR (7 downto 1);
VME_ga_n : in STD_LOGIC_VECTOR (4 downto 0);
VME_gap_n : in STD_LOGIC;
VME_sysclk : in STD_LOGIC;
VME_statrd_n : out STD_LOGIC;
-- Segnali Bus AUX
AUX_xsel_n : out STD_LOGIC;
AUX_xsds_n : out STD_LOGIC;
AUX_xeob_n : out STD_LOGIC;
AUX_xdk_n : out STD_LOGIC;
AUX_xbusy : out STD_LOGIC;
AUX_xbk_n : out STD_LOGIC;
AUX_xberr : out STD_LOGIC;
AUX_xds_n : in STD_LOGIC;
AUX_on_n : out STD_LOGIC;
AUX_xtrig : in STD_LOGIC_VECTOR (3 downto 0);
AUX_xas_n : in STD_LOGIC;
AUX_xtrgv_n : in STD_LOGIC;
AUX_xsyncrd_n : in STD_LOGIC;
AUX_xa_sel : in STD_LOGIC;
Led_red : out STD_LOGIC_VECTOR (2 downto 0);
Led_yellow : out STD_LOGIC_VECTOR (2 downto 0)
);
END COMPONENT;
-- Generic
-- Constant xxx
-- UUT BiDirs
signal VME_data : STD_LOGIC_VECTOR (31 downto 0);
signal VME_addr : STD_LOGIC_VECTOR (31 downto 0);
-- UUT Inputs ( := )
signal clk_p : STD_LOGIC := '0';
signal clk_n : STD_LOGIC := '1';
signal VME_sysres_n : STD_LOGIC;
signal VME_DSy : STD_LOGIC_VECTOR (1 downto 0);
signal VME_WRITEy : STD_LOGIC;
-- alias VME_LWordy : STD_LOGIC IS VME_addr(0);
signal VME_ASy : STD_LOGIC;
signal VME_IACKy : STD_LOGIC;
signal VME_am : STD_LOGIC_VECTOR (5 downto 0);
signal VME_switch : STD_LOGIC_VECTOR (7 downto 0) := BA;
signal VME_ga_n : STD_LOGIC_VECTOR (4 downto 0) := "11111"; -- simulo old vme bus := VME_GA(4 downto 0);
signal VME_gap_n : STD_LOGIC := '1'; -- simulo old vme bus := VME_GA(5);
signal VME_sysclk : STD_LOGIC;
signal AUX_xds_n : STD_LOGIC;
signal AUX_xtrig : STD_LOGIC_VECTOR (3 downto 0);
signal AUX_xas_n : STD_LOGIC;
signal AUX_xtrgv_n : STD_LOGIC;
signal AUX_xsyncrd_n : STD_LOGIC;
signal AUX_xa_sel : STD_LOGIC;
-- UUT Outputs
signal VME_dataOE : STD_LOGIC;
signal VME_data_DIR : STD_LOGIC;
signal VME_addrOE : STD_LOGIC;
signal VME_addr_DIR : STD_LOGIC;
signal VME_oeabBERR : STD_LOGIC;
signal VME_oeabDTACK : STD_LOGIC;
signal VME_DTACKa : STD_LOGIC;
signal VME_oeabRETRY : STD_LOGIC;
signal VME_RETRYa : STD_LOGIC;
signal VME_irq : STD_LOGIC_VECTOR (7 downto 1);
signal VME_statrd_n : STD_LOGIC;
signal AUX_xsel_n : STD_LOGIC;
signal AUX_xsds_n : STD_LOGIC;
signal AUX_xeob_n : STD_LOGIC;
signal AUX_xdk_n : STD_LOGIC;
signal AUX_xbusy : STD_LOGIC;
signal AUX_xbk_n : STD_LOGIC;
signal AUX_xberr : STD_LOGIC;
signal AUX_on_n : STD_LOGIC;
signal Led_red : STD_LOGIC_VECTOR (2 downto 0);
signal Led_yellow : STD_LOGIC_VECTOR (2 downto 0);
-- Others signal
signal VME_IACKINy : STD_LOGIC;
signal VME_IACKOUTa : STD_LOGIC;
-- Flags
signal ReadInProgress : std_logic := '0';
signal WriteInProgress : std_logic := '0';
-- Buffer and type
signal s_Buffer_BLT : t_Buffer_BLT;
signal s_Buffer_MBLT : t_Buffer_MBLT;
signal s_dataTransferType : t_dataTransferType;
signal s_AddressingType : t_Addressing_Type;
-- Control signals
signal s_dataToSend : std_logic_vector(31 downto 0) := (others => '0');
signal s_dataToReceive : std_logic_vector(31 downto 0) := (others => '0');
signal s_address : std_logic_vector(63 downto 0) := (others => '0');
signal csr_address : std_logic_vector(19 downto 0) := (others => '0');
signal s_num : std_logic_vector( 8 downto 0) := (others => '0');
-- Records
signal VME64xBus_out : VME64xBusOut_Record := VME64xBusOut_Default;
signal VME64xBus_in : VME64xBusIn_Record;
-- BUS VME testbench signal
signal BUS_DATA : STD_LOGIC_VECTOR (31 downto 0) :=(others => '1');
signal BUS_ADDR : STD_LOGIC_VECTOR (31 downto 0) :=(others => '1');
-- alias BUS_LWORD_n : STD_LOGIC IS BUS_ADDR(0);
signal BUS_DS_n : STD_LOGIC_VECTOR ( 1 downto 0) :=(others => '1');
signal BUS_AM : STD_LOGIC_VECTOR ( 5 downto 0) :=(others => '1');
signal BUS_SYSRES_n : STD_LOGIC := '1';
signal BUS_SYSCLK : STD_LOGIC := '1';
signal BUS_AS_n : STD_LOGIC := '1';
signal BUS_IACK_n : STD_LOGIC := '1';
signal BUS_IACKIN_n : STD_LOGIC := '1';
signal BUS_IACKOUT_n : STD_LOGIC; --out
signal BUS_DTACK_n : STD_LOGIC; --out
signal BUS_WRITE_n : STD_LOGIC := '1';
signal BUS_RETRY_n : STD_LOGIC; --out
signal BUS_BERR_n : STD_LOGIC; --out
signal BUS_IRQ : STD_LOGIC_VECTOR ( 7 downto 1); --out
-- BUS AUX testbench signal
signal BUS_XD : STD_LOGIC_VECTOR (19 downto 0); -- out
signal BUS_XT : STD_LOGIC_VECTOR (11 downto 0) :=(others => '1');
signal BUS_XSDS_n : STD_LOGIC; --out
signal BUS_XAS_n : STD_LOGIC := '1';
signal BUS_XTRGV_n : STD_LOGIC := '1';
signal BUS_XDS_n : STD_LOGIC := '1';
signal BUS_XSYNCRD_n : STD_LOGIC := '1';
signal BUS_XDK_n : STD_LOGIC := '1';
signal BUS_XEOB_n : STD_LOGIC := '1';
signal BUS_XA_SEL : STD_LOGIC := '1';
signal BUS_XBK : STD_LOGIC; --out
signal BUS_XBUSY_n : STD_LOGIC; --out
signal BUS_XBERR_n : STD_LOGIC; --out
signal BUS_XT1 : STD_LOGIC := '0';
signal BUS_XT2 : STD_LOGIC := '0';
signal BUS_XRES : STD_LOGIC := '0';
signal BUS_XCLK : STD_LOGIC := '0';
signal STAT_REG : STD_LOGIC_VECTOR (7 downto 0);
-- Other Components
COMPONENT sn74vme
GENERIC ( NUMOFBIT : integer);
PORT(
I1OEAB : in STD_LOGIC;
I1A : in STD_LOGIC;
I1Y : out STD_LOGIC;
O1B : inout STD_LOGIC;
I2OEAB : in STD_LOGIC;
I2A : in STD_LOGIC;
I2Y : out STD_LOGIC;
O2B : inout STD_LOGIC;
OEn : in STD_LOGIC;
DIR : in STD_LOGIC;
I3A : inout STD_LOGIC_VECTOR (NUMOFBIT - 1 downto 0);
O3B : inout STD_LOGIC_VECTOR (NUMOFBIT - 1 downto 0)
);
END COMPONENT;
-- ram block ...
-- Clock period definitions
constant CLK_period : time := 5 ns; -- 200 MHz
-- constant definition
-- procedure declaration
--------------------
-- PRBS_ANY
--------------------
component PRBS_ANY
generic (
-- out alp:
--CHK_MODE: boolean := false;
INV_PATTERN : boolean := false;
POLY_LENGHT : natural range 0 to 63 := 31;
POLY_TAP : natural range 0 to 63 := 3;
NBITS : natural range 0 to 512 := 22
);
port (
-- in alp:
CHK_MODE : in std_logic;
RST : in std_logic; -- sync reset active high
CLK : in std_logic; -- system clock
DATA_IN : in std_logic_vector(NBITS - 1 downto 0); -- inject error/data to be checked
EN : in std_logic; -- enable/pause pattern generation
DATA_OUT : out std_logic_vector(NBITS - 1 downto 0) -- generated prbs pattern/errors found
);
end component;
--------------------
-- PRBS_ANY
--------------------
-- PRBS-15 Settings
constant A_INV_PATTERN : boolean := true;
constant B_INV_PATTERN : boolean := false;
constant POLY_LENGHT : natural range 0 to 63 := 15;
constant POLY_TAP : natural range 0 to 63 := 14;
--------------------
-- CHECK RX DATA
--------------------
signal a_data : std_logic_vector(11 downto 0) := (others => '0');
signal a_valid : std_logic := '0';
signal a_data_check : std_logic_vector(11 downto 0) := (others => '0');
signal a_clk : std_logic := '1';
signal b_data : std_logic_vector(11 downto 0) := (others => '0');
signal b_valid : std_logic := '0';
signal b_data_check : std_logic_vector(11 downto 0) := (others => '0');
signal b_clk : std_logic := '1';
--------------------
-- AUXBUS STIMULI
--------------------
signal rst : std_logic := '1';
signal trigger : std_logic := '0';
signal trig_num : integer := 0;
signal founddata : std_logic := '0';
signal rx_data : std_logic_vector(19 downto 0) := (others => '0');
begin
-- Instantiate the Unit Under Test (UUT)
uut: VME64x_top
PORT MAP (
clk_p => clk_p,
clk_n => clk_n,
VME_sysres_n => VME_sysres_n,
VME_data => VME_data,
VME_dataOE => VME_dataOE,
VME_data_DIR => VME_data_DIR,
VME_DSy => VME_DSy,
VME_addr => VME_addr(31 downto 1),
VME_addrOE => VME_addrOE,
VME_addr_DIR => VME_addr_DIR,
VME_WRITEy => VME_WRITEy,
VME_LWordy => VME_addr(0),
VME_oeabBERR => VME_oeabBERR,
VME_oeabDTACK => VME_oeabDTACK,
VME_DTACKa => VME_DTACKa,
VME_ASy => VME_ASy,
VME_IACKy => VME_IACKy,
VME_IACKINy => VME_IACKINy,
VME_IACKOUTa => VME_IACKOUTa,
VME_oeabRETRY => VME_oeabRETRY,
VME_RETRYa => VME_RETRYa,
VME_am => VME_am,
VME_switch => VME_switch,
VME_irq => VME_irq,
VME_ga_n => VME_ga_n,
VME_gap_n => VME_gap_n,
VME_sysclk => VME_sysclk,
VME_statrd_n => VME_statrd_n,
AUX_xsel_n => AUX_xsel_n,
AUX_xsds_n => AUX_xsds_n,
AUX_xeob_n => AUX_xeob_n,
AUX_xdk_n => AUX_xdk_n,
AUX_xbusy => AUX_xbusy,
AUX_xbk_n => AUX_xbk_n,
AUX_xberr => AUX_xberr,
AUX_xds_n => AUX_xds_n,
AUX_on_n => AUX_on_n,
AUX_xtrig => AUX_xtrig,
AUX_xas_n => AUX_xas_n,
AUX_xtrgv_n => AUX_xtrgv_n,
AUX_xsyncrd_n => AUX_xsyncrd_n,
AUX_xa_sel => AUX_xa_sel,
Led_red => Led_red,
Led_yellow => Led_yellow
);
U15_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(7 downto 0),
O3B => BUS_DATA(7 downto 0)
);
U16_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_Dsy(1),
O1B => BUS_DS_n(1),
I2OEAB => '0',
I2A => '0',
I2Y => VME_Dsy(0),
O2B => BUS_DS_n(0),
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(15 downto 8),
O3B => BUS_DATA(15 downto 8)
);
U17_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(23 downto 16),
O3B => BUS_DATA(23 downto 16)
);
U18_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(31 downto 24),
O3B => BUS_DATA(31 downto 24)
);
U21_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_ASy,
O1B => BUS_AS_n,
I2OEAB => '0',
I2A => '0',
I2Y => VME_IACKy,
O2B => BUS_IACK_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(7 downto 0),
O3B => BUS_ADDR(7 downto 0)
);
U22_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_IACKINy,
O1B => BUS_IACKIN_n,
I2OEAB => '1',
I2A => VME_IACKOUTa,
I2Y => open,
O2B => BUS_IACKOUT_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(15 downto 8),
O3B => BUS_ADDR(15 downto 8)
);
U23_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => VME_oeabDTACK,
I1A => VME_DTACKa,
I1Y => open,
O1B => BUS_DTACK_n,
I2OEAB => '0',
I2A => '0',
I2Y => VME_WRITEy,
O2B => BUS_WRITE_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(23 downto 16),
O3B => BUS_ADDR(23 downto 16)
);
U24_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => VME_oeabRETRY,
I1A => VME_RETRYa,
I1Y => open,
O1B => BUS_RETRY_n,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(31 downto 24),
O3B => BUS_ADDR(31 downto 24)
);
U19_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 6 )
PORT MAP(
I1OEAB => VME_oeabBERR,
I1A => '0',
I1Y => open,
O1B => BUS_BERR_n,
I2OEAB => VME_IRQ(1),
I2A => '0',
I2Y => open,
O2B => BUS_IRQ(1),
OEn => '0',
DIR => '0',
I3A => VME_am(5 downto 0),
O3B => BUS_AM(5 downto 0)
);
--in realta' sono su U19 ...
VME_sysclk <= BUS_SYSCLK;
VME_sysres_n <= BUS_SYSRES_n;
U51_LCV07A:
for i in 2 to 7 generate
BUS_IRQ(i) <= '0' when (VME_IRQ(i) = '1') else 'Z';
end generate;
-- AUX BUS
BUS_XT2 <= trigger;
-- in realta arrivano differenziali su U31 ...
AUX_xtrig <= BUS_XCLK & BUS_XRES & BUS_XT2 & BUS_XT1;
U25_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '1',
I2A => AUX_xsds_n,
I2Y => open,
O2B => BUS_XSDS_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(7 downto 0),
O3B => BUS_XD(7 downto 0)
);
U26_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xas_n,
O1B => BUS_XAS_n,
I2OEAB => '0',
I2A => '0',
I2Y => AUX_xtrgv_n,
O2B => BUS_XTRGV_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(15 downto 8),
O3B => BUS_XD(15 downto 8)
);
U27_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 4 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xds_n,
O1B => BUS_XDS_n,
I2OEAB => '0',
I2A => '0',
I2Y => AUX_xsyncrd_n,
O2B => BUS_XSYNCRD_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(19 downto 16),
O3B => BUS_XD(19 downto 16)
);
-- in realta sono su U27 ...
-- out alp:
-- AUX_xdk_n <= BUS_XDK_n when AUX_xsel_n = '0' else 'Z';
-- AUX_xeob_n <= BUS_XEOB_n when AUX_xsel_n = '0' else 'Z';
-- in alp:
BUS_xdk_n <= AUX_XDK_n when AUX_xsel_n = '0' else 'Z';
BUS_xeob_n <= AUX_XEOB_n when AUX_xsel_n = '0' else 'Z';
U28_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xa_sel,
O1B => BUS_XA_SEL,
I2OEAB => AUX_xbk_n,
I2A => '0',
I2Y => BUS_XBK,
O2B => open,
OEn => AUX_on_n,
DIR => '0',
I3A => VME_data(27 downto 20),
O3B => BUS_XT(7 downto 0)
);
U20_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 4 )
PORT MAP(
I1OEAB => AUX_xbusy,
I1A => '0',
I1Y => open,
O1B => BUS_XBUSY_n,
I2OEAB => AUX_xberr,
I2A => '0',
I2Y => open,
O2B => BUS_XBERR_n,
OEn => AUX_on_n,
DIR => '0',
I3A => VME_data(31 downto 28),
O3B => BUS_XT(11 downto 8)
);
U52_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_statrd_n,
DIR => '1',
I3A => STAT_REG(7 downto 0),
O3B => BUS_DATA(7 downto 0)
);
STAT_REG <= "00" & AUX_xbk_n & AUX_xeob_n & AUX_xsds_n & AUX_xbusy & AUX_xberr & AUX_on_n;
-- VME BUS SIGNAL from vme64x simulation
BUS_IACKIN_n <= VME64xBus_out.Vme64xIACKIN;
BUS_IACK_n <= VME64xBus_out.Vme64xIACK;
BUS_AS_n <= VME64xBus_out.Vme64xAsN;
BUS_WRITE_n <= VME64xBus_out.Vme64xWRITEN;
BUS_AM <= VME64xBus_out.Vme64xAM;
BUS_DS_n(1) <= VME64xBus_out.Vme64xDs1N;
BUS_DS_n(0) <= VME64xBus_out.Vme64xDs0N;
BUS_ADDR(0) <= VME64xBus_out.Vme64xLWORDN;
BUS_ADDR(31 downto 1) <= VME64xBus_out.Vme64xADDR;
BUS_DATA <= VME64xBus_out.Vme64xDATA;
VME64xBus_in.Vme64xLWORDN <= to_UX01(BUS_ADDR(0));
VME64xBus_in.Vme64xADDR <= to_UX01(BUS_ADDR(31 downto 1));
VME64xBus_in.Vme64xDATA <= to_UX01(BUS_DATA);
VME64xBus_in.Vme64xDtackN <= to_UX01(BUS_DTACK_n);
VME64xBus_in.Vme64xBerrN <= to_UX01(BUS_BERR_n);
VME64xBus_in.Vme64xRetryN <= to_UX01(BUS_RETRY_n);
VME64xBus_in.Vme64xIRQ <= BUS_IRQ; -- era _n perche'?
VME64xBus_in.Vme64xIACKOUT <= BUS_IACKOUT_n;
PULLUP_DTACK_n : PULLUP
port map (
O => BUS_DTACK_n -- Pullup output (connect directly to top-level port)
);
PULLUP_BERR_n : PULLUP
port map (
O => BUS_BERR_n -- Pullup output (connect directly to top-level port)
);
PULLUP_RETRY_n : PULLUP
port map (
O => BUS_RETRY_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBUSY_n : PULLUP
port map (
O => BUS_XBUSY_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBERR_n : PULLUP
port map (
O => BUS_XBERR_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBK : PULLUP
port map (
O => BUS_XBK -- Pullup output (connect directly to top-level port)
);
BUS_PULL_UP:
for i in 0 to 31 generate
data_pull_up : PULLUP
port map (
O => BUS_DATA(i)
);
addr_pull_up : PULLUP
port map (
O => BUS_ADDR(i)
);
end generate;
-- Clock process definitions
CLK_process :process
begin
clk_p <= '0';
clk_n <= '1';
wait for CLK_period/2;
clk_p <= '1';
clk_n <= '0';
wait for CLK_period/2;
end process;
-- Stimuli process
VME_stimuli_proc: process
--variable s : line;
---------- in alp: -----------
procedure W_CSR( address : in integer; data : in integer range 0 to 2**08-1 ) is
begin s_AddressingType <= CR_CSR; s_dataTransferType <= D08Byte3; s_dataToSend <= std_logic_vector(to_unsigned(data,32)); wait for 1 ns;
WriteCSR(c_address => std_logic_vector(to_unsigned(address, 20)), s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
end procedure;
procedure W_CSR( address : in std_logic_vector(19 downto 0); data : in std_logic_vector(7 downto 0) ) is
begin s_AddressingType <= CR_CSR; s_dataTransferType <= D08Byte3; s_dataToSend <= x"000000" & data; wait for 1 ns;
WriteCSR(c_address => address, s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
end procedure;
procedure axi_write( address : in integer; data : in integer ) is
begin s_AddressingType <= A32; s_dataTransferType <= D32; s_dataToSend <= std_logic_vector(to_unsigned(data,32)); wait for 1 ns;
S_Write(v_address => x"00000000" & x"0800" & std_logic_vector(to_unsigned(address, 14)) & "00" , s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 100 ns;
end procedure;
procedure axi_write( address : in std_logic_vector(13 downto 0); data : in std_logic_vector(31 downto 0) ) is
begin s_AddressingType <= A32; s_dataTransferType <= D32; s_dataToSend <= data; wait for 1 ns;
S_Write(v_address => x"00000000" & x"0800" & address & "00" , s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 100 ns;
end procedure;
procedure axi_read( address : in integer; data : in integer range 0 to 2**8-1 ) is begin
-- create the procedure in pack
end procedure;
----------------------
begin
BUS_SYSRES_n <= '0'; -- hold reset state for 100 ns.
wait for 102 ns;
wait for 1 us;
BUS_SYSRES_n <= '1';
VME64xBus_Out.Vme64xIACK <= '1';
VME64xBus_Out.Vme64xIACKIN <= '1';
wait for 10 us; -- wait until the initialization finish (wait more than 8705 ns)
------------------------------------------------------------------------------
-- Configure window to access WB bus (ADER)
------------------------------------------------------------------------------
wait for 50 ns;
report "START WRITE ADER";
--W_CSR(x"FFF63", x"08"); -- 0x0FFF63: "00001000"
W_CSR(c_FUNC0_ADER_3, ADER0_A32(31 downto 24)); -- 0x07FF63: BA(7 downto 3) & "000"
W_CSR(c_FUNC0_ADER_2, ADER0_A32(23 downto 16)); -- 0x07FF67: "00000000"
W_CSR(c_FUNC0_ADER_1, ADER0_A32(15 downto 8)); -- 0x07FF6B: "00000000"
W_CSR(c_FUNC0_ADER_0, ADER0_A32( 7 downto 0)); -- 0x07FF6F: Addr Modifier & "00" : 0x24 per AM = 0x09
report "THE MASTER HAS WRITTEN CORRECTLY ALL THE ADERs";
------------------------------------------------------------------------------
-- Enables the VME64x core
------------------------------------------------------------------------------
-- Module Enabled:
W_CSR(c_BIT_SET_REG, x"10"); -- 0x07FF6B: "00010000"
report "THE MASTER HAS ENABLED THE BOARD";
------------------------------------------------------------------------------
-- Access to AXI registers
------------------------------------------------------------------------------
-- Reset AUX BUS
axi_write(0,1);
-- Enable AUX BUS Test Mode
axi_write(1,3);
-- Run AUX BUS
axi_write(0,0);
report "THE MASTER HAS SET THE AUX IN BUILT_IN TEST MODE";
-- Enable AUX BUS
W_CSR(c_USR_BIT_SET_REG, "00000000");
report "THE MASTER HAS ENABLED THE AUX";
-- wait for 1 us;
-- -- Enable AUX BUS
-- W_CSR(c_USR_BIT_CLR_REG, "00000000");
-- report "THE MASTER HAS DISENABLED THE AUX";
wait;
end process;
--------------------
-- CHECK RX DATA
--------------------
process
variable inc : integer := 0;
variable van : integer := 0;
variable vbn : integer := 0;
variable vai : integer := 0;
variable vbi : integer := 0;
begin
wait until rising_edge(BUS_xtrgv_n);
if BUS_xsyncrd_n = '0' then
wait until rising_edge(BUS_xsyncrd_n);
else
-- TEST MODE
wait until falling_edge(BUS_xdk_n);
if to_integer(unsigned(BUS_xd(BUS_xd'high downto BUS_xd'high-6))) < 48 then
a_data <= BUS_xd(BUS_xd'high-8 downto 0);
a_valid <= '1';
a_clk <= '0';
else
b_data <= BUS_xd(BUS_xd'high-8 downto 0);
b_valid <= '1';
b_clk <= '0';
end if;
while BUS_xeob_n/='0' loop
wait until BUS_xdk_n'event and BUS_xdk_n='1';--rising_edge(BUS_xdk_n);
a_valid <= '1';
a_clk <= '1';
b_valid <= '1';
b_clk <= '1';
wait until falling_edge(BUS_xdk_n);
if to_integer(unsigned(BUS_xd(BUS_xd'high downto BUS_xd'high-6))) < 48 then
a_data <= BUS_xd(BUS_xd'high-8 downto 0);
a_valid <= '1';
a_clk <= '0';
else
b_data <= BUS_xd(BUS_xd'high-8 downto 0);
b_valid <= '1';
b_clk <= '0';
end if;
end loop;
wait until BUS_xdk_n'event and BUS_xdk_n='1';--rising_edge(BUS_xdk_n);
a_valid <= '1';
a_clk <= '1';
b_valid <= '1';
b_clk <= '1';
inc := inc+1;
end if;
end process;
--------------------
-- PRBS_ANY: A DATA CHECK
--------------------
a_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => A_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => a_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => a_clk,
DATA_IN => a_data,
EN => a_valid,
DATA_OUT => a_data_check
);
--------------------
-- PRBS_ANY: B DATA CHECK
--------------------
b_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => B_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => b_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => b_clk,
DATA_IN => b_data,
EN => b_valid,
DATA_OUT => b_data_check
);
--------------------
-- AUXBUS STIMULI
--------------------
process
--------------------
-- Sync Cycle
--------------------
procedure sync_cycle is
constant tn : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(trig_num,12));
begin
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others=> '0');
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '0';
wait for 50 ns;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '0';
wait until BUS_xbk = '1' for 1 us;
-- if BUS_xbk = '0' then
-- report "No response during Trigger Cycle with Trigger Number " & integer'image(trig_num) & "." severity WARNING;
-- end if;
founddata <= not BUS_xsds_n;
wait for 5 ns;
assert not(BUS_xbk='0') report "ERROR: xbk asserted to '0' before xtrgv_n is released during trigger cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
end sync_cycle;
--------------------
-- Sync Readout Cycle
--------------------
procedure sync_readout (founddata : std_logic) is
begin
if founddata = '0' then
report "Error: xsds not asserted low during sync cycle." severity FAILURE;
return;
end if;
-- Address Bus
BUS_xa_sel <= '1';
wait for 40 ns;
-- Address Bus is Valid
BUS_xas_n <= '0';
wait for 1 ns;
RO_loop: loop
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '0';
wait until BUS_xdk_n = '0' for 1 us;
if BUS_xdk_n /= '0' then
report "No response from target " & "during Sync Readout Cycle " & "." severity FAILURE;
exit RO_loop;
end if;
rx_data <= BUS_xd;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '1';
wait for 15 ns;
exit RO_loop when BUS_xeob_n = '0';
report "xeob_n not asserted low during Sync Readout" & "." severity FAILURE;
end loop;
wait for 5 ns;
-- Address Bus is Valid
BUS_xas_n <= '1';
wait for 50 ns;
-- Address Bus
BUS_xa_sel <= '0';
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '1';
end sync_readout;
--------------------
-- Set in Idle
--------------------
procedure idle is
begin
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Address Bus
BUS_xa_sel <= '0';
-- Address Bus is Valid
BUS_xas_n <= '1';
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '1';
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '1';
-- ROCK send a system HALT due to Error,
--xsyshalt <= '1';
-- ROCK produces a create level AUX reset
--xsysreset <= '1';
-- Other Signals
founddata <= '0';
rx_data <= (others => '0');
end idle;
--------------------
-- Trigger Cycle
--------------------
procedure trigger_cycle (trig_num :integer) is
constant tn : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(trig_num,12));
begin
-- Trigger Bus, first valid trigger is 000
BUS_xt <= tn;
wait for 40 ns;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '0';
wait until BUS_xbk = '1' for 1 us;
-- if xbk = '0' then
-- report "No response during Trigger Cycle with Trigger Number " & integer'image(trig_num) & "." severity WARNING;
-- else
founddata <= not BUS_xsds_n;
wait for 5 ns;
assert not(BUS_xbk='0') report "ERROR: xbk asserted to '0' before xtrgv_n is released during trigger cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
-- end if;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
end trigger_cycle;
--------------------
-- Trigger Readout Cycle
--------------------
procedure trigger_readout (trig_num : integer; founddata : std_logic) is
begin
if founddata = '0' then
--report "No found data, exiting from readout cycle." severity note;
return;
end if;
-- Address Bus
BUS_xa_sel <= '1';
wait for 40 ns;
-- Address Bus is Valid
BUS_xas_n <= '0';
wait for 1 ns;
RO_loop: loop
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '0';
wait until BUS_xdk_n = '0' for 1 us;
if BUS_xdk_n /= '0' then
report "No response from target " & "during Readout Cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
exit RO_loop;
end if;
rx_data <= BUS_xd;
wait for 4 ns;
BUS_xds_n <= '1';
wait for 1 ns;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
exit RO_loop when BUS_xeob_n = '0';
wait for 15 ns;
end loop;
wait for 10 ns;
-- Address Bus is Valid
BUS_xas_n <= '1';
wait for 40 ns;
-- Address Bus
BUS_xa_sel <= '0';
end trigger_readout;
variable tst : time := 300 ps;
begin
tst := (tst + 300 ps);
-- idle
idle;
wait for 100 ns;
if AUX_on_n='1' then
wait until AUX_on_n = '0';
wait for 100 ns;
end if;
trig_num <= trig_num + 1;
wait for tst;
--report "Start AUX Trigger Cycle..." severity NOTE;
trigger_cycle(trig_num);
--report "Done." severity NOTE;
wait for 150 ns;
wait for tst;
--report "Start AUX Trigger Readout Cycle..." severity NOTE;
trigger_readout(trig_num, founddata);
--report "Done." severity NOTE;
--wait for 100 ns;
--trig_num <= trig_num + 1;
wait for 10 ns;
wait for tst;
idle;
wait for 1 us;
wait for tst;
sync_cycle;
wait for 150 ns;
wait for tst;
sync_readout(founddata);
wait for 10 ns;
--wait;
end process;
--------------------
-- TIMING REPORT
--------------------
-- trigger (35 ns)
process
variable time_diff : time;
variable curr_time : time;
begin
wait until falling_edge(BUS_xtrgv_n);
wait until BUS_xsds_n = '0';
curr_time := now;
wait until BUS_xbk = '1'; --'Z'
time_diff := now - curr_time;
--report "--------- - - 35ns -> " & time'image(time_diff) severity NOTE;
assert time_diff >= 35 ns report "TRIGGER TIMING ERROR:35ns -> " & time'image(time_diff) severity FAILURE;
end process;
-- readout (15 ns)
process
variable time_diff : time;
variable curr_time : time;
variable xd_temp : std_logic_vector(19 DOWNTO 0);
begin
wait until rising_edge(BUS_xds_n);
wait until BUS_xd'event;
xd_temp := BUS_xd;
curr_time := now;
loop ---------- Note: There could be a second event in xd.
wait until falling_edge(BUS_xdk_n) or BUS_xd'event;
if xd_temp = BUS_xd then
exit;
end if;
xd_temp := BUS_xd;
curr_time := now;
end loop;
time_diff := now - curr_time;
--report "--------- - - 15ns -> " & time'image(time_diff) severity NOTE;
assert time_diff >= 15 ns report "READOUT TIMING ERROR: 15ns -> " & time'image(time_diff) severity FAILURE;
end process;
rst <= not BUS_SYSRES_n;
--------------------
-- TRIGGER PROCESS
--------------------
tr_pr: process
begin
trigger <= '0';
wait for clk_period*1;
if rst = '1' then
wait until rst='0';
end if;
wait for clk_period*50;
wait until clk_p'event and clk_p='1';
wait for clk_period/5;
if BUS_xsyncrd_n='1'and AUX_xbusy='0' then
trigger <= '1';
end if;
wait for clk_period*10;
end process;
end AUX_Behavioral;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/7328ecd7be110fa2/fifo_generator_rx_inst_sim_netlist.vhdl
|
1
|
199238
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 09:34:25 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
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WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => Q(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => din(31 downto 0),
DIBDI(31 downto 0) => din(63 downto 32),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => dout(31 downto 0),
DOBDO(31 downto 0) => dout(63 downto 32),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => \out\(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => WEBWE(0),
WEBWE(6) => WEBWE(0),
WEBWE(5) => WEBWE(0),
WEBWE(4) => WEBWE(0),
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => ram_empty_fb_i_reg(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
\gc0.count_d1_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \^gc0.count_d1_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair1";
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\gc0.count_d1_reg[7]_0\(7 downto 0) <= \^gc0.count_d1_reg[7]_0\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
I1 => \^gc0.count_d1_reg[7]_0\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
I1 => \^gc0.count_d1_reg[7]_0\(1),
I2 => \^gc0.count_d1_reg[7]_0\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(1),
I1 => \^gc0.count_d1_reg[7]_0\(0),
I2 => \^gc0.count_d1_reg[7]_0\(2),
I3 => \^gc0.count_d1_reg[7]_0\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(2),
I1 => \^gc0.count_d1_reg[7]_0\(0),
I2 => \^gc0.count_d1_reg[7]_0\(1),
I3 => \^gc0.count_d1_reg[7]_0\(3),
I4 => \^gc0.count_d1_reg[7]_0\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(3),
I1 => \^gc0.count_d1_reg[7]_0\(1),
I2 => \^gc0.count_d1_reg[7]_0\(0),
I3 => \^gc0.count_d1_reg[7]_0\(2),
I4 => \^gc0.count_d1_reg[7]_0\(4),
I5 => \^gc0.count_d1_reg[7]_0\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[7]_0\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[7]_0\(6),
I2 => \^gc0.count_d1_reg[7]_0\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(6),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[7]_0\(7),
I3 => rd_pntr_plus1(8),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(5),
I1 => \^gc0.count_d1_reg[7]_0\(3),
I2 => \^gc0.count_d1_reg[7]_0\(1),
I3 => \^gc0.count_d1_reg[7]_0\(0),
I4 => \^gc0.count_d1_reg[7]_0\(2),
I5 => \^gc0.count_d1_reg[7]_0\(4),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(0),
Q => \^q\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(1),
Q => \^q\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(2),
Q => \^q\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(3),
Q => \^q\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(4),
Q => \^q\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(5),
Q => \^q\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(6),
Q => \^q\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(7),
Q => \^q\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(8),
Q => \^q\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^gc0.count_d1_reg[7]_0\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^gc0.count_d1_reg[7]_0\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^gc0.count_d1_reg[7]_0\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^gc0.count_d1_reg[7]_0\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^gc0.count_d1_reg[7]_0\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^gc0.count_d1_reg[7]_0\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => \^gc0.count_d1_reg[7]_0\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => \^gc0.count_d1_reg[7]_0\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_full_i_reg
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_i_reg
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_reg[8]\(0),
O => ram_full_i_reg_0
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(0) <= \^q\(0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => p_12_out(7),
I3 => \^q\(0),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_reg[7]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_reg[7]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_reg[7]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_reg[7]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => ram_empty_i_reg_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
ram_full_comb => ram_full_comb,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]_0\,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg_0 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal rpntr_n_10 : STD_LOGIC;
signal rpntr_n_12 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[8]\ => rpntr_n_12,
\gc0.count_reg[8]\ => rpntr_n_10,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8 downto 0) => Q(8 downto 0),
clk => clk,
\gc0.count_d1_reg[7]_0\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[8]\(0) => \gcc0.gc0.count_reg[8]\(0),
ram_empty_i_reg => rpntr_n_10,
ram_empty_i_reg_0 => rpntr_n_12,
ram_full_i_reg => ram_full_i_reg,
ram_full_i_reg_0 => ram_full_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
WEBWE(0) <= \^webwe\(0);
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^webwe\(0),
clk => clk,
full => full,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\gc0.count_d1_reg[8]_0\ => \gc0.count_d1_reg[8]_0\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
ram_empty_fb_i_reg(0) => E(0),
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \c1/v1_reg\(3 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^webwe\(0),
Q(0) => Q(0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_1(3 downto 0) => \c1/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_17\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(8 downto 0) => p_0_out(8 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_17\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[8]\(0) => p_11_out(8),
\gcc0.gc0.count_reg[8]\(0) => p_12_out(8),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_3\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_21\,
rd_en => rd_en,
v1_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_11_out(8 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(0) => p_12_out(8),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gc0.count_d1_reg[8]_0\ => \gntv_or_sync_fifo.gl0.rd_n_21\,
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_17\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_20\,
v1_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(8 downto 0) => p_0_out(8 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\out\(0) => rd_rst_i(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 510;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 509;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 510;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 509;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => '0',
rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/3ff1695805bf427f/dbg_ila_stub.vhdl
|
1
|
3217
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Oct 31 09:19:48 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe27 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe29 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe30 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0],probe26[3:0],probe27[7:0],probe28[0:0],probe29[3:0],probe30[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
superboy0712/MIPS
|
HostComm.vhd
|
1
|
4426
|
-- Part of TDT4255 Computer Design laboratory exercises
-- Group for Computer Architecture and Design
-- Department of Computer and Information Science
-- Norwegian University of Science and Technology
-- HostComm.vhd
-- A module which wraps some registers, address mapping logic and
-- a UART-to-register control interface to control TDT4255 exercises.
-- This particular variant is to be used for exercises 1 and 2, and
-- contains the following registers:
-- * Magic word (for identification) at address 0x4000. Always returns 0xCAFEC0DE.
-- * Processor enable register (1-bit) at address 0x0000
-- * Processor reset register (1-bit) at address 0x0001
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity HostComm is
port (
clk, reset : in std_logic;
-- interface towards the UART ports
UART_Rx : in std_logic;
UART_Tx : out std_logic;
-- interface towards the processor
proc_en, proc_rst : out std_logic;
-- interface towards the instruction memory
imem_data_in : in std_logic_vector(7 downto 0);
imem_data_out : out std_logic_vector(7 downto 0);
imem_addr : out std_logic_vector(9 downto 0);
imem_wr_en : out std_logic;
-- interface towards the data memory
dmem_data_in : in std_logic_vector(7 downto 0);
dmem_data_out : out std_logic_vector(7 downto 0);
dmem_addr : out std_logic_vector(9 downto 0);
dmem_wr_en : out std_logic
);
end HostComm;
architecture Behavioral of HostComm is
constant TDT4255_EX1_MAGIC : std_logic_vector(31 downto 0) := x"CAFEC0DE";
-- addresses for status/control registers
constant REG_ADDR_PROC_EN : std_logic_vector(15 downto 0) := x"0000";
constant REG_ADDR_PROC_RESET : std_logic_vector(15 downto 0) := x"0001";
-- addresses for the magic ID register
constant REG_ADDR_MAGIC0 : std_logic_vector(15 downto 0) := x"4000";
constant REG_ADDR_MAGIC1 : std_logic_vector(15 downto 0) := x"4001";
constant REG_ADDR_MAGIC2 : std_logic_vector(15 downto 0) := x"4002";
constant REG_ADDR_MAGIC3 : std_logic_vector(15 downto 0) := x"4003";
-- UART register control interface signals
signal regReadData, regWriteData : std_logic_vector(7 downto 0);
signal regAddress : std_logic_vector(15 downto 0);
signal regReadEnable, regWriteEnable : std_logic;
-- control/status registers
signal procResetSignal, procEnableSignal : std_logic;
begin
-- instantiate the UART register controller
UARTHandlerInst: entity work.uart2BusTop
-- 16 bits address width (for register addressing over UART)
generic map (AW => 16)
port map (
clr => reset, clk => clk, serIn => UART_Rx, serOut => UART_Tx,
intAccessGnt => '1', intRdData => regReadData, intWrData => regWriteData,
intAddress => regAddress, intWrite => regWriteEnable, intRead => regReadEnable
);
-- register read mux
regReadData <= dmem_data_in when regAddress(15 downto 14) = "10" else
imem_data_in when regAddress(15 downto 14) = "11" else
"0000000" & procEnableSignal when regAddress = REG_ADDR_PROC_EN else
"0000000" & procResetSignal when regAddress = REG_ADDR_PROC_RESET else
TDT4255_EX1_MAGIC(31 downto 24) when regAddress = REG_ADDR_MAGIC0 else
TDT4255_EX1_MAGIC(23 downto 16) when regAddress = REG_ADDR_MAGIC1 else
TDT4255_EX1_MAGIC(15 downto 8) when regAddress = REG_ADDR_MAGIC2 else
TDT4255_EX1_MAGIC(7 downto 0) when regAddress = REG_ADDR_MAGIC3 else
x"00";
-- instruction memory connections
imem_wr_en <= regWriteEnable and (regAddress(15) and regAddress(14)) and (not procEnableSignal);
imem_addr <= regAddress(9 downto 0);
imem_data_out <= regWriteData;
-- data memory connections
dmem_wr_en <= regWriteEnable and (regAddress(15) and (not regAddress(14))) and (not procEnableSignal);
dmem_addr <= regAddress(9 downto 0);
dmem_data_out <= regWriteData;
ControlRegs: process(clk, reset)
begin
if reset = '1' then
procResetSignal <= '0';
procEnableSignal <= '0';
elsif rising_edge(clk) then
-- implement the enable signal ctrl register
if regWriteEnable = '1' and regAddress = REG_ADDR_PROC_EN then
procEnableSignal <= regWriteData(0);
end if;
-- implement the reset signal ctrl register
if regWriteEnable = '1' and regAddress = REG_ADDR_PROC_RESET then
procResetSignal <= regWriteData(0);
end if;
end if;
end process;
proc_rst <= procResetSignal;
proc_en <= procEnableSignal;
end Behavioral;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_sim_netlist.vhdl
|
1
|
336266
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:22 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_rx_inst_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare : entity is "compare";
end fifo_generator_rx_inst_compare;
architecture STRUCTURE of fifo_generator_rx_inst_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => E(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_3 : entity is "compare";
end fifo_generator_rx_inst_compare_3;
architecture STRUCTURE of fifo_generator_rx_inst_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_4 : entity is "compare";
end fifo_generator_rx_inst_compare_4;
architecture STRUCTURE of fifo_generator_rx_inst_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_5 : entity is "compare";
end fifo_generator_rx_inst_compare_5;
architecture STRUCTURE of fifo_generator_rx_inst_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_rx_inst_rd_bin_cntr;
architecture STRUCTURE of fifo_generator_rx_inst_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(0),
Q => Q(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(10),
Q => Q(10)
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(11),
Q => Q(11)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(1),
Q => Q(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(2),
Q => Q(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(3),
Q => Q(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(4),
Q => Q(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(5),
Q => Q(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(6),
Q => Q(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(7),
Q => Q(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(8),
Q => Q(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(9),
Q => Q(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
D => \gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^d\(0)
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10)
);
\gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4)
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8)
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_0;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_1;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_2;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_rx_inst_wr_bin_cntr;
architecture STRUCTURE of fifo_generator_rx_inst_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(10),
Q => \^q\(10)
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(11),
Q => \^q\(11)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \^q\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(9),
Q => \^q\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10)
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8)
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_rx_inst_blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_rx_inst_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
\gc0.count_d1_reg[11]\ : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_status_flags_ss : entity is "rd_status_flags_ss";
end fifo_generator_rx_inst_rd_status_flags_ss;
architecture STRUCTURE of fifo_generator_rx_inst_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.fifo_generator_rx_inst_compare_4
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.fifo_generator_rx_inst_compare_5
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => \gc0.count_d1_reg[11]\
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_rx_inst_reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_rx_inst_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[0]\(1) <= rd_rst_reg(2);
\gc0.count_reg[0]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_status_flags_ss : entity is "wr_status_flags_ss";
end fifo_generator_rx_inst_wr_status_flags_ss;
architecture STRUCTURE of fifo_generator_rx_inst_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.fifo_generator_rx_inst_compare
port map (
E(0) => E(0),
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_comb => ram_full_comb,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.fifo_generator_rx_inst_compare_3
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_rx_inst_blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_rx_inst_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_logic : entity is "rd_logic";
end fifo_generator_rx_inst_rd_logic;
architecture STRUCTURE of fifo_generator_rx_inst_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.fifo_generator_rx_inst_rd_status_flags_ss
port map (
clk => clk,
empty => empty,
\gc0.count_d1_reg[11]\ => \^e\(0),
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.fifo_generator_rx_inst_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
ram_empty_fb_i_reg => \^e\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_logic : entity is "wr_logic";
end fifo_generator_rx_inst_wr_logic;
architecture STRUCTURE of fifo_generator_rx_inst_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.fifo_generator_rx_inst_wr_status_flags_ss
port map (
E(0) => E(0),
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.fifo_generator_rx_inst_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_rx_inst_blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_rx_inst_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth : entity is "blk_mem_gen_v8_3_4_synth";
end fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_rx_inst_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_v8_3_4 : entity is "blk_mem_gen_v8_3_4";
end fifo_generator_rx_inst_blk_mem_gen_v8_3_4;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_memory : entity is "memory";
end fifo_generator_rx_inst_memory;
architecture STRUCTURE of fifo_generator_rx_inst_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo_generator_rx_inst_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_rx_inst_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_rx_inst_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(2),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_rx_inst_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => wr_rst_i(1),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_rx_inst_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\out\(0) => rd_rst_i(0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.fifo_generator_rx_inst_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[0]\(1) => rd_rst_i(2),
\gc0.count_reg[0]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_rx_inst_fifo_generator_top;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_rx_inst_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2_synth : entity is "fifo_generator_v13_1_2_synth";
end fifo_generator_rx_inst_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_rx_inst_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "fifo_generator_v13_1_2";
end fifo_generator_rx_inst_fifo_generator_v13_1_2;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_rx_inst_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_rx_inst : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_rx_inst : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_rx_inst : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_rx_inst : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end fifo_generator_rx_inst;
architecture STRUCTURE of fifo_generator_rx_inst is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_generator_rx_inst_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
dumpram/zedboard-ofdm
|
vhdl/xillydemo.vhd
|
1
|
27692
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
-- For Vivado, delete the port declarations for PS_CLK, PS_PORB and
-- PS_SRSTB, and uncomment their declarations as signals further below.
--PS_CLK : IN std_logic;
--PS_PORB : IN std_logic;
--PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component cyclic_prefix_fsm
port (
reset : in std_logic;
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
fd_out : out std_logic;
rffd : in std_logic;
dft_data_valid : in std_logic
);
end component;
component dft_in_fsm
port (
reset : in std_logic;
clk : in std_logic;
fifo_data : in std_logic_vector(31 downto 0);
fifo_rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dft_data : out std_logic_vector(31 downto 0);
dft_fd_in : out std_logic;
dft_rffd : in std_logic;
dft_data_valid : in std_logic;
fifo_watchdog_reset : out std_logic
);
end component;
component dft_out_fsm
port (
reset : in std_logic;
clk : in std_logic;
dft_ce : out std_logic;
dft_dout : in std_logic_vector(31 downto 0);
dft_fd_out : in std_logic;
fifo_data : out std_logic_vector(31 downto 0);
fifo_wr_en : out std_logic;
fifo_wr_count : in std_logic_vector(9 downto 0);
fifo_watchdog_reset : out std_logic
);
end component;
COMPONENT dft_16
PORT (
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
XN_RE : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
XN_IM : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FD_IN : IN STD_LOGIC;
FWD_INV : IN STD_LOGIC;
SIZE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RFFD : OUT STD_LOGIC;
XK_RE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
XK_IM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
BLK_EXP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FD_OUT : OUT STD_LOGIC;
DATA_VALID : OUT STD_LOGIC
);
END COMPONENT;
component reset_controller
port (
clk : in std_logic;
input_fsm_wd_reset : in std_logic;
output_fsm_wd_reset : in std_logic;
reset : out std_logic
);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
COMPONENT fifo_32x1024
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
-- Note that none of the ARM processor's direct connections to pads is
-- defined as I/O on this module. Normally, they should be connected
-- as toplevel ports here, but that confuses Vivado 2013.4 to think that
-- some of these ports are real I/Os, causing an implementation failure.
-- This detachment results in a lot of warnings during synthesis and
-- implementation, but has no practical significance, as these pads are
-- completely unrelated to the FPGA bitstream.
signal PS_CLK : std_logic;
signal PS_PORB : std_logic;
signal PS_SRSTB : std_logic;
signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
signal DDR_CAS_n : std_logic;
signal DDR_CKE : std_logic;
signal DDR_CS_n : std_logic;
signal DDR_Clk : std_logic;
signal DDR_Clk_n : std_logic;
signal DDR_DM : std_logic_vector(3 DOWNTO 0);
signal DDR_DQ : std_logic_vector(31 DOWNTO 0);
signal DDR_DQS : std_logic_vector(3 DOWNTO 0);
signal DDR_DQS_n : std_logic_vector(3 DOWNTO 0);
signal DDR_DRSTB : std_logic;
signal DDR_ODT : std_logic;
signal DDR_RAS_n : std_logic;
signal DDR_VRN : std_logic;
signal DDR_VRP : std_logic;
signal MIO : std_logic_vector(53 DOWNTO 0);
signal DDR_WEB : std_logic;
-- Signali za input FSM
signal input_fsm_reset : std_logic;
-- Signali za output FSM
signal output_fsm_reset : std_logic;
signal output_fsm_dft_ce : std_logic;
-- Signali za ulazni FIFO
signal fifo_read_data : std_logic_vector(31 downto 0);
signal fifo_read_rd_en : std_logic;
signal fifo_in_reset : std_logic;
signal fifo_in_empty : std_logic;
signal fifo_read_count : std_logic_vector(9 downto 0);
-- Signali za izlazni FIFO
signal fifo_write_data : std_logic_vector(31 downto 0);
signal fifo_write_wr_en : std_logic;
signal fifo_out_reset : std_logic;
signal fifo_out_full : std_logic;
signal fifo_write_count : std_logic_vector(9 downto 0);
-- Signali za DFT IP core
-- DFT-960 => size_const = 29 = 0x1d = 0b011101
constant dft_size_const : std_logic_vector(5 downto 0) := "011101";
signal dft_data_in : std_logic_vector(31 downto 0);
signal dft_out_I : std_logic_vector(15 downto 0);
signal dft_out_Q : std_logic_vector(15 downto 0);
signal dft_out_blk_exp : std_logic_vector(3 downto 0);
signal dft_fd_in : std_logic;
signal dft_fd_out : std_logic;
signal dft_data_valid : std_logic;
signal dft_rffd : std_logic;
signal dft_sclr : std_logic;
signal dft_out : std_logic_vector(31 downto 0);
-- Reset controller signals
signal controller_reset : std_logic;
signal input_fsm_wd_reset : std_logic;
signal output_fsm_wd_reset : std_logic;
-- DEBUG
signal led_sig : std_logic;
signal led_cnt : std_logic_vector(7 downto 0);
signal dft_fd_out_prev : std_logic := dft_fd_out;
signal PS_GPIO_xillybus : std_logic_vector(55 downto 0);
signal heartbeat_led_cnt : std_logic_vector(23 downto 0);
signal led_heartbeat : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO_xillybus,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
---- 32-bit loopback
-- fifo_32 : fifo_32x512
-- port map(
-- clk => bus_clk,
-- srst => reset_32,
-- din => user_w_write_32_data,
-- wr_en => user_w_write_32_wren,
-- rd_en => user_r_read_32_rden,
-- dout => user_r_read_32_data,
-- full => user_w_write_32_full,
-- empty => user_r_read_32_empty
-- );
-- reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
-- user_r_read_32_eof <= '0';
-- INPUT FIFO
fifo_in : fifo_32x1024
port map(
clk => bus_clk,
srst => fifo_in_reset,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => fifo_read_rd_en,
dout => fifo_read_data,
full => user_w_write_32_full,
empty => fifo_in_empty,
data_count => fifo_read_count
);
fifo_in_reset <= controller_reset;
-- OUTPUT FIFO
fifo_out : fifo_32x1024
port map(
clk => bus_clk,
srst => fifo_out_reset,
din => fifo_write_data,
wr_en => fifo_write_wr_en,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => fifo_out_full,
empty => user_r_read_32_empty,
data_count => fifo_write_count
);
fifo_out_reset <= controller_reset;
input_fsm : dft_in_fsm
port map (
reset => input_fsm_reset,
clk => bus_clk,
fifo_data => fifo_read_data,
fifo_rd_en => fifo_read_rd_en,
fifo_rd_count => fifo_read_count,
dft_data => dft_data_in,
dft_fd_in => dft_fd_in,
dft_rffd => dft_rffd,
dft_data_valid => dft_data_valid,
fifo_watchdog_reset => input_fsm_wd_reset
);
input_fsm_reset <= controller_reset;
output_fsm : dft_out_fsm
port map (
reset => output_fsm_reset,
clk => bus_clk,
dft_ce => output_fsm_dft_ce,
dft_dout => dft_out,
dft_fd_out => dft_fd_out,
fifo_data => fifo_write_data,
fifo_wr_en => fifo_write_wr_en,
fifo_wr_count => fifo_write_count,
fifo_watchdog_reset => output_fsm_wd_reset
);
output_fsm_reset <= controller_reset;
dft_out_I <= dft_out(31 downto 16);
dft_out_Q <= dft_out(15 downto 0);
dft_16_I : dft_16
PORT MAP (
CLK => bus_clk,
SCLR => dft_sclr,
CE => output_fsm_dft_ce,
SIZE => dft_size_const,
FWD_INV => '1',
-- Vremenska domena
XN_RE => dft_data_in(31 downto 16),
XN_IM => dft_data_in(15 downto 0),
FD_IN => dft_fd_in,
RFFD => dft_rffd,
-- Frekvencijska domena
XK_RE => dft_out_I,
XK_IM => dft_out_Q,
BLK_EXP => dft_out_blk_exp,
FD_OUT => dft_fd_out,
DATA_VALID => dft_data_valid
);
dft_sclr <= controller_reset;
-- Reset controller
reset_controller_I : reset_controller
port map (
clk => bus_clk,
input_fsm_wd_reset => input_fsm_wd_reset,
output_fsm_wd_reset => output_fsm_wd_reset,
reset => controller_reset
);
PS_GPIO <= PS_GPIO_xillybus(55 downto 11) & led_sig & led_heartbeat & PS_GPIO_xillybus(8 downto 0);
process(bus_clk)
begin
if rising_edge(bus_clk) then
if (dft_fd_out /= dft_fd_out_prev) then
dft_fd_out_prev <= dft_fd_out;
if led_cnt /= (led_cnt'range => '0') then
led_cnt <= x"ff";
led_sig <= not led_sig;
else
led_cnt <= led_cnt - '1';
led_sig <= led_sig;
end if;
end if;
end if;
end process;
process(bus_clk)
begin
if rising_edge(bus_clk) then
if heartbeat_led_cnt /= (heartbeat_led_cnt'range => '0') then
heartbeat_led_cnt <= x"ffffff";
led_heartbeat <= not led_heartbeat;
else
heartbeat_led_cnt <= heartbeat_led_cnt - '1';
led_heartbeat <= led_heartbeat;
end if;
end if;
end process;
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/6f42175531c6f264/dbg_ila_stub.vhdl
|
1
|
3029
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Oct 19 10:57:11 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe27 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0],probe26[3:0],probe27[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_inv_core.vhd
|
10
|
9935
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - CORE ***
--*** ***
--*** DP_INV_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublepeed ***
--*** SIII Latency = 18 + doublespeed ***
--***************************************************
ENTITY dp_inv_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
END dp_inv_core;
ARCHITECTURE rtl OF dp_inv_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaleden : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal twonode, subscaleden : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessone : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteval : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal absolutevalff, absoluteff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal abscarryff : STD_LOGIC;
signal iteratenumnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal iteratenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteerror : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal mulabsguessff : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal mulabsguess : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(54 DOWNTO 36),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8+speed
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(54 DOWNTO 1);
gta: FOR k IN 1 TO 54 GENERATE
subscaleden(k) <= NOT(scaleden(k));
END GENERATE;
subscaleden(55) <= '1';
-- in level 8+doublespeed, outlevel 9+2*doublespeed
addtwoone: dp_fxadd
GENERIC MAP (width=>55,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>twonode,bb=>subscaleden,carryin=>'1',
cc=>guessone);
guessonevec <= guessone(54 DOWNTO 1);
-- absolute value of guess lower 36 bits
-- this is still correct, because (for positive), value will be 1.(17 zeros)error
-- can also be calculated from guessonevec (code below)
-- gabs: FOR k IN 1 TO 36 GENERATE
-- absoluteval(k) <= guessonevec(k) XOR NOT(guessonevec(54));
-- END GENERATE;
gabs: FOR k IN 1 TO 36 GENERATE
absoluteval(k) <= scaleden(k) XOR NOT(scaleden(54));
END GENERATE;
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
absolutevalff(k) <= '0';
absoluteff(k) <= '0';
END LOOP;
abscarryff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absolutevalff <= absoluteval; -- out level 9+speed
abscarryff <= NOT(scaleden(54));
absoluteff <= absolutevalff + (zerovec(35 DOWNTO 1) & abscarryff); -- out level 10+speed
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>18,pipes=>4+2*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invdivisor,
cc=>delinvdivisor);
-- in level 9+2*doublespeed, out level 12+3*doublespeed
muloneone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>delinvdivisor,
result=>iteratenumnode);
-- in level 10+doublespeed, out level 13+doublespeed
mulonetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>absoluteff,databb=>absoluteff,
result=>absoluteerror);
-- if speed = 0, delay absoluteerror 1 clock, else 2
-- this guess always positive (check??)
-- change here, error can be [19:1], not [18:1] - this is because (1.[17 zeros].error)^2
-- gives 1.[34 zeros].error
pgaa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 19 LOOP
mulabsguessff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulabsguessff <= absoluteerror(72 DOWNTO 54) +
(zerovec(18 DOWNTO 1) & absoluteerror(53));
END IF;
END IF;
END PROCESS;
mulabsguess(19 DOWNTO 1) <= mulabsguessff;
gmga: FOR k IN 20 TO 53 GENERATE
mulabsguess(k) <= '0';
END GENERATE;
mulabsguess(54) <= '1';
-- mulabsguess at 14+doublespeed depth
-- iteratenum at 12+3*doublespeed depth
-- mulabsguess 5 (5)clocks from absolutevalff
-- iteratenum 3+2doublespeed (3/5)clocks from abssolutevalff
-- delay iterate num
gdoa: IF (doublespeed = 0) GENERATE
delonetwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>iteratenumnode,
cc=>iteratenum);
END GENERATE;
gdob: IF (doublespeed = 1) GENERATE
iteratenum <= iteratenumnode;
END GENERATE;
--*********************
--*** OUTPUT SCALE ***
--*********************
-- in level 14+doublespeed
-- SII out level 19+2*doublespeed
-- SIII/IV out level 18+doublespeed
mulout: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>iteratenum,databb=>mulabsguess,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 17);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_explut7.vhd
|
10
|
16883
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT7.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut7 IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END fp_explut7;
ARCHITECTURE rtl OF fp_explut7 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "0000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= '0';
WHEN "0000001" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= '0';
WHEN "0000010" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= '0';
WHEN "0000011" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= '0';
WHEN "0000100" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= '0';
WHEN "0000101" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= '0';
WHEN "0000110" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= '0';
WHEN "0000111" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= '0';
WHEN "0001000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= '0';
WHEN "0001001" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= '0';
WHEN "0001010" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= '0';
WHEN "0001011" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= '0';
WHEN "0001100" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= '0';
WHEN "0001101" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= '0';
WHEN "0001110" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= '0';
WHEN "0001111" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= '0';
WHEN "0010000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= '0';
WHEN "0010001" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= '0';
WHEN "0010010" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= '0';
WHEN "0010011" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= '0';
WHEN "0010100" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= '0';
WHEN "0010101" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= '0';
WHEN "0010110" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= '0';
WHEN "0010111" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= '0';
WHEN "0011000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= '0';
WHEN "0011001" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= '0';
WHEN "0011010" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= '0';
WHEN "0011011" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= '0';
WHEN "0011100" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= '0';
WHEN "0011101" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= '0';
WHEN "0011110" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= '0';
WHEN "0011111" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= '0';
WHEN "0100000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= '0';
WHEN "0100001" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= '0';
WHEN "0100010" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= '0';
WHEN "0100011" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= '0';
WHEN "0100100" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= '0';
WHEN "0100101" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= '0';
WHEN "0100110" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= '0';
WHEN "0100111" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= '0';
WHEN "0101000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= '0';
WHEN "0101001" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= '0';
WHEN "0101010" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= '0';
WHEN "0101011" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= '0';
WHEN "0101100" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= '0';
WHEN "0101101" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= '0';
WHEN "0101110" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= '0';
WHEN "0101111" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= '0';
WHEN "0110000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= '0';
WHEN "0110001" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= '0';
WHEN "0110010" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= '0';
WHEN "0110011" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= '0';
WHEN "0110100" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= '0';
WHEN "0110101" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= '0';
WHEN "0110110" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= '0';
WHEN "0110111" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= '0';
WHEN "0111000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= '0';
WHEN "0111001" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= '0';
WHEN "0111010" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= '0';
WHEN "0111011" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= '0';
WHEN "0111100" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= '0';
WHEN "0111101" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= '0';
WHEN "0111110" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= '0';
WHEN "0111111" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= '0';
WHEN "1000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= '0';
WHEN "1000001" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= '0';
WHEN "1000010" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= '0';
WHEN "1000011" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= '0';
WHEN "1000100" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= '0';
WHEN "1000101" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= '0';
WHEN "1000110" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= '0';
WHEN "1000111" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= '0';
WHEN "1001000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= '0';
WHEN "1001001" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= '0';
WHEN "1001010" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= '0';
WHEN "1001011" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= '0';
WHEN "1001100" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= '0';
WHEN "1001101" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= '0';
WHEN "1001110" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= '0';
WHEN "1001111" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= '0';
WHEN "1010000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= '0';
WHEN "1010001" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= '0';
WHEN "1010010" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= '0';
WHEN "1010011" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= '0';
WHEN "1010100" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= '0';
WHEN "1010101" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= '0';
WHEN "1010110" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= '0';
WHEN "1010111" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= '0';
WHEN "1011000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= '0';
WHEN "1011001" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= '1';
WHEN "1011010" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= '1';
WHEN "1011011" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= '1';
WHEN "1011100" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= '1';
WHEN "1011101" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= '1';
WHEN "1011110" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= '1';
WHEN "1011111" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= '1';
WHEN "1100000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= '1';
WHEN "1100001" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= '1';
WHEN "1100010" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= '1';
WHEN "1100011" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= '1';
WHEN "1100100" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= '1';
WHEN "1100101" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= '1';
WHEN "1100110" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= '1';
WHEN "1100111" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= '1';
WHEN "1101000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= '1';
WHEN "1101001" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= '1';
WHEN "1101010" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= '1';
WHEN "1101011" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= '1';
WHEN "1101100" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= '1';
WHEN "1101101" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= '1';
WHEN "1101110" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= '1';
WHEN "1101111" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= '1';
WHEN "1110000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= '1';
WHEN "1110001" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= '1';
WHEN "1110010" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= '1';
WHEN "1110011" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= '1';
WHEN "1110100" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= '1';
WHEN "1110101" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= '1';
WHEN "1110110" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= '1';
WHEN "1110111" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= '1';
WHEN "1111000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= '1';
WHEN "1111001" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= '1';
WHEN "1111010" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= '1';
WHEN "1111011" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= '1';
WHEN "1111100" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= '1';
WHEN "1111101" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= '1';
WHEN "1111110" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= '1';
WHEN "1111111" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= '1';
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_mulfp3236.vhd
|
10
|
5397
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00";
cczipff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc<= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_tan.vhd
|
10
|
24604
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TAN1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Tangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** 1. for very top of range (last 256 mantissa lsbs before pi/2), use seperate ROM, not
--*** calculation
--*** 2. if round up starting when X.49999, errors reduce about 25%, need to tweak this, still getting
--*** all -1 errors with bX.111111111. less errors with less tail bits for smaller exponents (like 122)
--*** more for exponent = 126
ENTITY fp_tan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
signout : OUT STD_LOGIC;
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_tan;
ARCHITECTURE rtl of fp_tan IS
-- input section
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal argumentff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topargumentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal middleargumentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanhighmantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmiddleff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanlowsumff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal shiftin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal shiftinbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal argumentbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanmiddle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal deltwo_tailnode : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal tantailnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowsumnode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal tanlowmantissabus : STD_LOGIC_VECTOR (56 DOWNTO 1);
-- numerator section
signal tanlowff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsumff : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal tanlowshift : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal numeratormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delone_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delthr_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowbus : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsum : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal numeratorlead, numeratorleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
-- denominator section
signal lowleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inverseexponentff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lowleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_tanlowsum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal lowmantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delthr_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal delfor_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_lowlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
-- divider section
signal tanexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanmantissanormff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundbitff : STD_LOGIC;
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overff : STD_LOGIC;
signal denominatorinverse : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multiplier_tan : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal tanmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmantissanorm : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal tanmantissatail : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal overcheck : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal del_inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal del_numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanexponent, tanexponentnorm : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutnode : STD_LOGIC_VECTOR (23 DOWNTO 1);
-- small inputs
signal signff : STD_LOGIC_VECTOR (30 DOWNTO 1);
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (28 DOWNTO 1);
signal mantissabase : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (8 DOWNTO 1);
component fp_tanlut1
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_tanlut2
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_clz36x6
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft56x20
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
end component;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- convert to fixed point
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
argumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
topargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
middleargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
tanhighmantissaff(k) <= '0';
tanmiddleff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanhighexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanlowsumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain;
exponentinff <= exponentin;
argumentff <= argumentbus;
topargumentff <= argumentff(36 DOWNTO 28);
middleargumentff <= argumentff(27 DOWNTO 20);
tanhighmantissaff <= tanhighmantissa;
tanhighexponentff <= tanhighexponent;
tanmiddleff <= tanmiddle;
tanlowsumff <= tanlowsumnode;
END IF;
END IF;
END PROCESS;
shiftin <= 127 - exponentinff;
shiftinbus <= '1' & mantissainff & zerovec(12 DOWNTO 1);
csftin: fp_rsft36
PORT MAP (inbus=>shiftinbus,shift=>shiftin(6 DOWNTO 1),
outbus=>argumentbus);
chtt: fp_tanlut1
PORT MAP (add=>topargumentff,
mantissa=>tanhighmantissa,
exponent=>tanhighexponent);
cltt: fp_tanlut2
PORT MAP (add=>middleargumentff,
tanfraction=>tanmiddle);
-- in level 2, out level 4
dtail: fp_del
GENERIC MAP (width=>19,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>argumentff(19 DOWNTO 1),
cc=>deltwo_tailnode);
tantailnode <= zerovec(8 DOWNTO 1) & deltwo_tailnode & zerovec(9 DOWNTO 1);
tanlowsumnode <= ('0' & tanmiddleff(36 DOWNTO 1)) + ('0' & tantailnode);
tanlowmantissabus <= tanlowsumff & zerovec(19 DOWNTO 1);
--*********************************************
--*** Align two tangent values for addition ***
--*********************************************
padd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 56 LOOP
tanlowff(k) <= '0';
END LOOP;
FOR k IN 1 TO 57 LOOP
numeratorsumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numeratormantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
numeratorexponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanlowff <= tanlowbus;
numeratorsumff <= numeratorsum;
numeratormantissaff <= numeratormantissa;
numeratorexponentff <= numeratorexponent;
END IF;
END IF;
END PROCESS;
-- in level 4, out level 5
dhxa: fp_del
GENERIC MAP (width=>5,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighexponentff,
cc=>delone_tanhighexponent);
-- in level 5, out level 7
dhxb: fp_del
GENERIC MAP (width=>5,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delthr_tanhighexponent);
-- in level 4, out level 6
dhm: fp_del
GENERIC MAP (width=>36,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighmantissaff,
cc=>deltwo_tanhighmantissa);
-- tan high mantissa format 1.XXX, tan low mantissa format 0.XXXXX
-- tan high exponent base is 119 (top of middle range)
tanlowshift <= delone_tanhighexponent;
crsadd: fp_rsft56x20
PORT MAP (inbus=>tanlowmantissabus,
shift=>tanlowshift,
outbus=>tanlowbus);
numeratorsum <= ('0' & deltwo_tanhighmantissa & zerovec(20 DOWNTO 1)) + ('0' & tanlowff);
-- level 8
-- no pipe between clz and shift as only 6 bit shift
-- middle exponent is 119, and 2 overflow bits in numerator sum, so this will
-- cover downto (119+2-6) = 115 exponent
-- below 115 exponent, output mantissa = input mantissa
clznuma: fp_clz36x6
PORT MAP (mantissa=>numeratorsumff(57 DOWNTO 22),
leading=>numeratorlead);
numeratorleadnode <= "000" & numeratorlead(3 DOWNTO 1); -- force [6:4] to 0 to optimize away logic in LSFT
clsnuma: fp_lsft36
PORT MAP (inbus=>numeratorsumff(57 DOWNTO 22),shift=>numeratorleadnode,
outbus=>numeratormantissa);
numeratorexponent <= delthr_tanhighexponent - numeratorlead(5 DOWNTO 1) + 1;
--gnnadd: FOR k IN 1 TO 36 GENERATE
-- numeratormantissa(k) <= (numeratorsumff(k+20) AND NOT(numeratorsumff(57))) OR
-- (numeratorsumff(k+21) AND numeratorsumff(57));
--END GENERATE;
--numeratorexponent <= delthr_tanhighexponent + ("0000" & numeratorsumff(57));
--***************************************************
--*** Align two tangent values for multiplication ***
--***************************************************
pmul: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 6 LOOP
lowleadff(k) <= '0';
denominatorleadff(k) <= '0';
inverseexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
multshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
denominatorproductff(k) <= '0';
denominatorff(k) <= '0';
denominatormantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowleadff <= lowleadnode;
multshiftff <= multshiftnode;
denominatorproductff <= denominatorproductbus;
denominatorff <= denominator;
denominatorleadff <= denominatorlead;
denominatormantissaff <= denominatormantissa;
inverseexponentff <= inverseexponent;
END IF;
END IF;
END PROCESS;
clzmula: fp_clz36
PORT MAP (mantissa=>tanlowsumff(37 DOWNTO 2),
leading=>lowleadnode);
-- in level 5, out level 6
dlm: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanlowsumff(37 DOWNTO 2),
cc=>delone_tanlowsum);
clsmula: fp_lsft36
PORT MAP (inbus=>delone_tanlowsum,shift=>lowleadff,
outbus=>lowmantissabus);
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>deltwo_tanhighmantissa,
databb=>lowmantissabus,
result=>multipliernode);
-- in level 5, out level 8
dhxc: fp_del
GENERIC MAP (width=>5,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delfor_tanhighexponent);
-- in level 6, out level 8
dlla: fp_del
GENERIC MAP (width=>6,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>lowleadff,
cc=>deltwo_lowlead);
-- msb of lowmantissa(37) is at exponent 0 for highmantissa
multexponent <= ('0' & delfor_tanhighexponent);
--multshiftnode <= "001000" - multexponent + 8 - 1 + lowlead;
multshiftnode <= "001111" - multexponent + deltwo_lowlead;
-- '1.0' is at exponent 8 compared to highmantissa
crsmul: fp_rsft36
PORT MAP (inbus=>multipliernode(72 DOWNTO 37),shift=>multshiftff,
outbus=>denominatorproductbus);
denominator <= ('1' & zerovec(35 DOWNTO 1)) - denominatorproductff;
-- in level 11, out level 12
dda: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>denominatorff,
cc=>delone_denominator);
clzmulb: fp_clz36
PORT MAP (mantissa=>denominatorff,
leading=>denominatorlead);
-- denominatormantissa level 12, (denominatormantissaff level 13)
clsmulb: fp_lsft36
PORT MAP (inbus=>delone_denominator,shift=>denominatorleadff,
outbus=>denominatormantissa);
denominatorexponent <= denominatorleadff; -- actually inverse of exponent i.e. 4 => -4, so sign does not have to change after inverting
-- inverseexponentff level 13
inverseexponent <= denominatorexponent - 1;
--****************************
--*** main divider section ***
--****************************
pdiv: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
tanexponentff(k) <= '0';
tanexponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 24 LOOP
tanmantissanormff(k) <= '0';
END LOOP;
roundbitff <= '0';
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
overff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanexponentff <= tanexponent;
tanmantissanormff <= tanmantissanorm; -- level 29
tanexponentnormff <= tanexponentnorm; -- level 29
overff <= overcheck(24);
-- round up if 0.4999
roundbitff <= tanmantissanorm(1) OR
(tanmantissatail(9) AND
tanmantissatail(8) AND tanmantissatail(7) AND
tanmantissatail(6) AND tanmantissatail(5) AND
tanmantissatail(4) AND tanmantissatail(3) AND
tanmantissatail(2) AND tanmantissatail(1));
mantissaoutff <= mantissaoutnode; -- level 30
exponentoutff <= exponentoutnode; -- level 30
END IF;
END IF;
END PROCESS;
-- latency 12
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
-- level 13 in, level 25 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>denominatormantissaff,
quotient=>denominatorinverse);
-- level 8 in, level 25 out
dnuma: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratormantissaff,
cc=>del_numeratormantissa);
-- level 25 in, level 28 out
cmt: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numeratormantissa,
databb=>denominatorinverse,
result=>multiplier_tan);
tanmantissa <= multiplier_tan(72 DOWNTO 37);
gmna: FOR k IN 1 TO 24 GENERATE
tanmantissanorm(k) <= (tanmantissa(k+9) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+10) AND tanmantissa(35));
END GENERATE;
gmnb: FOR k IN 1 TO 9 GENERATE
tanmantissatail(k) <= (tanmantissa(k) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+1) AND tanmantissa(35));
END GENERATE;
overcheck(1) <= tanmantissanorm(1);
gova: FOR k IN 2 TO 24 GENERATE
overcheck(k) <= overcheck(k-1) AND tanmantissanorm(k);
END GENERATE;
-- level 13 in, level 27 out
ddena: fp_del
GENERIC MAP (width=>6,pipes=>14)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>inverseexponentff,
cc=>del_inverseexponent);
-- level 8 in, level 27 out
dnumb: fp_del
GENERIC MAP (width=>5,pipes=>19)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratorexponentff,
cc=>del_numeratorexponent);
tanexponent <= "01110111" +
(del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent) +
(del_inverseexponent(6) & del_inverseexponent(6) & del_inverseexponent); -- 119 + exponent
tanexponentnorm <= tanexponentff + tanmantissa(35);
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 30 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 28 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 30 LOOP
signff(k) <= signff(k-1);
END LOOP;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 28 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--mantissabase(1) <= (tanmantissanormff(1) AND NOT(small_inputff(28)));
mantissabase(1) <= (roundbitff AND NOT(small_inputff(28)));
gmba: FOR k IN 2 TO 24 GENERATE
mantissabase(k) <= (small_mantissa(k-1) AND small_inputff(28)) OR
(tanmantissanormff(k) AND NOT(small_inputff(28)));
END GENERATE;
gxba: FOR k IN 1 TO 8 GENERATE
exponentbase(k) <= (small_exponent(k) AND small_inputff(28)) OR
(tanexponentnormff(k) AND NOT(small_inputff(28)));
END GENERATE;
mantissaoutnode <= mantissabase(24 DOWNTO 2) + mantissabase(1);
exponentoutnode <= exponentbase + (overff AND NOT(small_inputff(28)));
--***************
--*** OUTPUTS ***
--***************
signout <= signff(30);
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fpc_library_package_sv.vhd
|
10
|
48066
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package;
PACKAGE BODY fpc_library_package is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_clz36x6.vhd
|
10
|
2148
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36X6.VHD ***
--*** ***
--*** Function: 6 bit Count Leading Zeros in a ***
--*** 36 bit number ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36x6 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36x6;
ARCHITECTURE rtl of fp_clz36x6 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerogroup : STD_LOGIC;
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(k) <= position(k) AND zerogroup;
END GENERATE;
leading <= positionmux;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_lnlutpow.vhd
|
10
|
230947
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlutpow;
ARCHITECTURE rtl OF dp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "0000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "0000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1023,11);
WHEN "0000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN others =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_div_est.vhd
|
10
|
6558
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse ***
--*** ***
--*** Used by both single and double dividers ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_div_est;
ARCHITECTURE rtl OF fp_div_est IS
type twodelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type ziplutdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (17 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal twodelff : twodelfftype;
signal ziplutdelff : ziplutdelfftype;
signal invdivisorff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 17 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= divisor(18 DOWNTO 10);
two <= divisor(9 DOWNTO 1);
-- these register seperate to make the LUTs into memories
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
onelutff <= onelut;
ziplutff <= ziplut;
END IF;
END IF;
END PROCESS;
upper: fp_div_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_div_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 20 LOOP
invdivisorff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invdivisorff <= ziplutdelff(2)(20 DOWNTO 1) -
(zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
invdivisor <= invdivisorff(20 DOWNTO 3);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dotProduct64_safe_path_sv.vhd
|
10
|
410
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
mit
|
kucherenko/basta
|
fixtures/vhdl/file2.vhd
|
12226531
|
0
|
mit
|
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_tanpi_s5.vhd
|
10
|
707279
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_tanpi_s5
-- VHDL created on Wed Feb 27 15:22:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_tanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_tanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWE_uid8_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwSMo_uid22_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal piwFP1_uid29_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal xpi_uid30_fpTanPiTest_a : std_logic_vector (23 downto 0);
signal xpi_uid30_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal xpi_uid30_fpTanPiTest_s1 : std_logic_vector (47 downto 0);
signal xpi_uid30_fpTanPiTest_pr : UNSIGNED (47 downto 0);
signal xpi_uid30_fpTanPiTest_q : std_logic_vector (47 downto 0);
signal roundAndExpUpdateCst_uid38_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal cstAllOWE_uid52_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid53_spix_uid43_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid54_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid55_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid74_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid76_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid81_spix_uid43_fpTanPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid88_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid91_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal p_uid102_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal p_uid102_spix_uid43_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid108_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid108_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid114_spix_uid43_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid115_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid115_spix_uid43_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid116_spix_uid43_fpTanPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid116_spix_uid43_fpTanPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid116_spix_uid43_fpTanPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q : std_logic_vector (48 downto 0);
signal excRZero_uid134_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid134_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid134_spix_uid43_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid134_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid136_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid142_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid142_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal signComp_uid148_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid148_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid148_spix_uid43_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid148_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid149_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid149_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid151_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid151_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid151_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid239_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid247_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid247_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid247_cpix_uid44_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid247_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid249_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid249_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid249_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid294_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid294_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid294_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expXmY_uid295_tpix_uid45_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal expXmY_uid295_tpix_uid45_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal expXmY_uid295_tpix_uid45_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal expXmY_uid295_tpix_uid45_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal expR_uid296_tpix_uid45_fpTanPiTest_a : std_logic_vector(10 downto 0);
signal expR_uid296_tpix_uid45_fpTanPiTest_b : std_logic_vector(10 downto 0);
signal expR_uid296_tpix_uid45_fpTanPiTest_o : std_logic_vector (10 downto 0);
signal expR_uid296_tpix_uid45_fpTanPiTest_q : std_logic_vector (9 downto 0);
signal fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal fracYPostZ_uid303_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal z_uid306_tpix_uid45_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal zeroOverReg_uid326_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal zeroOverReg_uid326_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xRegOrZero_uid328_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xRegOrZero_uid328_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xRegOrZero_uid328_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid360_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid389_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid458_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal memoryC2_uid577_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_a : std_logic_vector (25 downto 0);
signal prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_pr : UNSIGNED (49 downto 0);
signal prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_q : std_logic_vector (49 downto 0);
signal prodXY_uid613_pT1_uid460_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid613_pT1_uid460_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid613_pT1_uid460_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid613_pT1_uid460_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid613_pT1_uid460_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid616_pT2_uid466_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid616_pT2_uid466_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid616_pT2_uid466_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid616_pT2_uid466_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid616_pT2_uid466_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid619_pT1_uid579_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid619_pT1_uid579_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid619_pT1_uid579_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid619_pT1_uid579_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid619_pT1_uid579_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid622_pT2_uid585_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid622_pT2_uid585_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid622_pT2_uid585_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid622_pT2_uid585_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid622_pT2_uid585_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid625_pT1_uid598_invPE_a : std_logic_vector (11 downto 0);
signal prodXY_uid625_pT1_uid598_invPE_b : std_logic_vector (11 downto 0);
signal prodXY_uid625_pT1_uid598_invPE_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid625_pT1_uid598_invPE_pr : SIGNED (24 downto 0);
signal prodXY_uid625_pT1_uid598_invPE_q : std_logic_vector (23 downto 0);
signal prodXY_uid628_pT2_uid604_invPE_a : std_logic_vector (13 downto 0);
signal prodXY_uid628_pT2_uid604_invPE_b : std_logic_vector (22 downto 0);
signal prodXY_uid628_pT2_uid604_invPE_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid628_pT2_uid604_invPE_pr : SIGNED (37 downto 0);
signal prodXY_uid628_pT2_uid604_invPE_q : std_logic_vector (36 downto 0);
signal memoryC0_uid594_invTab_lutmem_reset0 : std_logic;
signal memoryC0_uid594_invTab_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid594_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid594_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid594_invTab_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid594_invTab_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid595_invTab_lutmem_reset0 : std_logic;
signal memoryC1_uid595_invTab_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid595_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid595_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid595_invTab_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid595_invTab_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid596_invTab_lutmem_reset0 : std_logic;
signal memoryC2_uid596_invTab_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid596_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid596_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid596_invTab_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid596_invTab_lutmem_q : std_logic_vector (11 downto 0);
signal reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1_q : std_logic_vector (11 downto 0);
signal reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q : std_logic_vector (13 downto 0);
signal reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1_q : std_logic_vector (22 downto 0);
signal reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3_q : std_logic_vector (25 downto 0);
signal reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q : std_logic_vector (10 downto 0);
signal reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q : std_logic_vector (31 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expRSmallpix_uid36_fpTanPiTest_a_q : std_logic_vector (7 downto 0);
signal ld_signX_uid26_fpTanPiTest_b_to_join_uid41_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q_to_exc_R_uid72_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_y_uid86_spix_uid43_fpTanPiTest_b_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_multRightOp_uid115_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid135_spix_uid43_fpTanPiTest_q_to_fracRPostExc1_uid136_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid139_spix_uid43_fpTanPiTest_q_to_expRPostExc1_uid142_spix_uid43_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid75_spix_uid43_fpTanPiTest_n_to_InvXFrac_uid146_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid85_spix_uid43_fpTanPiTest_b_to_signComp_uid148_spix_uid43_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid26_fpTanPiTest_b_to_signR_uid151_spix_uid43_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid151_spix_uid43_fpTanPiTest_q_to_R_uid152_spix_uid43_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_y_uid86_spix_uid43_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid233_cpix_uid44_fpTanPiTest_q_to_fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid231_cpix_uid44_fpTanPiTest_q_to_expRPostExc1_uid239_cpix_uid44_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q_to_signRComp_uid247_cpix_uid44_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q_to_signR_uid249_cpix_uid44_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid249_cpix_uid44_fpTanPiTest_q_to_R_uid250_cpix_uid44_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracYZero_uid261_tpix_uid45_fpTanPiTest_q_to_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_lOAdded_uid304_tpix_uid45_fpTanPiTest_q_to_oFracXExt_uid307_tpix_uid45_fpTanPiTest_b_q : std_logic_vector (23 downto 0);
signal ld_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRYZ_uid331_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIYZ_uid333_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIYR_uid334_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q_to_concExc_uid339_tpix_uid45_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_sRPostExc_uid350_tpix_uid45_fpTanPiTest_q_to_divR_uid351_tpix_uid45_fpTanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q_to_prodXY_uid625_pT1_uid598_invPE_a_q : std_logic_vector (11 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC1_uid595_invTab_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_z_uid96_spix_uid43_fpTanPiTest_q_to_reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_yT1_uid459_sinPiZPolyEval_b_to_reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0);
signal ld_excRNaN_uid232_cpix_uid44_fpTanPiTest_q_to_reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid277_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid293_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_a_q : std_logic_vector (0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q : signal is true;
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q : signal is true;
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_mem_top_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q : signal is true;
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_outputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q : signal is true;
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q : signal is true;
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q : signal is true;
signal yIsZero_uid87_spix_uid43_fpTanPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid87_spix_uid43_fpTanPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid87_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_c : std_logic_vector (0 downto 0);
signal xHalfRZI_uid135_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid135_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid135_spix_uid43_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid135_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid233_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expUdf_uid322_tpix_uid45_fpTanPiTest_a : std_logic_vector(13 downto 0);
signal expUdf_uid322_tpix_uid45_fpTanPiTest_b : std_logic_vector(13 downto 0);
signal expUdf_uid322_tpix_uid45_fpTanPiTest_o : std_logic_vector (13 downto 0);
signal expUdf_uid322_tpix_uid45_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid322_tpix_uid45_fpTanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid325_tpix_uid45_fpTanPiTest_a : std_logic_vector(13 downto 0);
signal expOvf_uid325_tpix_uid45_fpTanPiTest_b : std_logic_vector(13 downto 0);
signal expOvf_uid325_tpix_uid45_fpTanPiTest_o : std_logic_vector (13 downto 0);
signal expOvf_uid325_tpix_uid45_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid325_tpix_uid45_fpTanPiTest_n : std_logic_vector (0 downto 0);
signal InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expXP1_uid105_spix_uid43_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid105_spix_uid43_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid105_spix_uid43_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid105_spix_uid43_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid131_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid131_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid146_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid146_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal lOAdded_uid304_tpix_uid45_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal join_uid89_spix_uid43_fpTanPiTest_q : std_logic_vector (35 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid25_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid25_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid26_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid26_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid10_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal tanXIsX_uid28_fpTanPiTest_a : std_logic_vector(10 downto 0);
signal tanXIsX_uid28_fpTanPiTest_b : std_logic_vector(10 downto 0);
signal tanXIsX_uid28_fpTanPiTest_o : std_logic_vector (10 downto 0);
signal tanXIsX_uid28_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal tanXIsX_uid28_fpTanPiTest_c : std_logic_vector (0 downto 0);
signal expRSmallpix2_uid39_fpTanPiTest_a : std_logic_vector(33 downto 0);
signal expRSmallpix2_uid39_fpTanPiTest_b : std_logic_vector(33 downto 0);
signal expRSmallpix2_uid39_fpTanPiTest_o : std_logic_vector (33 downto 0);
signal expRSmallpix2_uid39_fpTanPiTest_q : std_logic_vector (33 downto 0);
signal expXIsMax_uid63_spix_uid43_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid63_spix_uid43_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid63_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid65_spix_uid43_fpTanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid65_spix_uid43_fpTanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid65_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid66_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid66_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid66_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid68_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid68_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid68_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid73_spix_uid43_fpTanPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid73_spix_uid43_fpTanPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid73_spix_uid43_fpTanPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid73_spix_uid43_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid73_spix_uid43_fpTanPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid75_spix_uid43_fpTanPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid75_spix_uid43_fpTanPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid75_spix_uid43_fpTanPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid75_spix_uid43_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid75_spix_uid43_fpTanPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid77_spix_uid43_fpTanPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid77_spix_uid43_fpTanPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid77_spix_uid43_fpTanPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid77_spix_uid43_fpTanPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid77_spix_uid43_fpTanPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid80_spix_uid43_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid80_spix_uid43_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid80_spix_uid43_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid80_spix_uid43_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid90_spix_uid43_fpTanPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid90_spix_uid43_fpTanPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid90_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid92_spix_uid43_fpTanPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid92_spix_uid43_fpTanPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid92_spix_uid43_fpTanPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid92_spix_uid43_fpTanPiTest_q : std_logic_vector (37 downto 0);
signal z_uid96_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal z_uid96_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid104_spix_uid43_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid104_spix_uid43_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid104_spix_uid43_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid104_spix_uid43_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid128_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid128_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid128_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid129_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid129_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid129_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid138_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid138_spix_uid43_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid139_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid139_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid139_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid143_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid143_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid143_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid145_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid145_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid150_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid150_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid150_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid207_cpix_uid44_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid207_cpix_uid44_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid207_cpix_uid44_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid207_cpix_uid44_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid232_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid232_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid232_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid236_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid236_cpix_uid44_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid243_cpix_uid44_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid243_cpix_uid44_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid330_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid330_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid330_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid330_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXRYROvf_uid332_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXRYROvf_uid332_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal excXRYROvf_uid332_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid335_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid335_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid335_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid335_tpix_uid45_fpTanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid335_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid340_tpix_uid45_fpTanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid344_tpix_uid45_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid348_tpix_uid45_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid348_tpix_uid45_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal sRPostExc_uid350_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal sRPostExc_uid350_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal sRPostExc_uid350_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid456_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid457_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid575_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid576_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fsel_uid31_fpTanPiTest_in : std_logic_vector (47 downto 0);
signal fsel_uid31_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal fracRSmallPiXH_uid32_fpTanPiTest_in : std_logic_vector (46 downto 0);
signal fracRSmallPiXH_uid32_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal fracRSmallPiXL_uid33_fpTanPiTest_in : std_logic_vector (45 downto 0);
signal fracRSmallPiXL_uid33_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal normBit_uid117_spix_uid43_fpTanPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid117_spix_uid43_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid118_spix_uid43_fpTanPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid118_spix_uid43_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid119_spix_uid43_fpTanPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid119_spix_uid43_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal oFracXExt_uid307_tpix_uid45_fpTanPiTest_q : std_logic_vector (25 downto 0);
signal leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid626_pT1_uid598_invPE_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid626_pT1_uid598_invPE_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid629_pT2_uid604_invPE_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid629_pT2_uid604_invPE_b : std_logic_vector (23 downto 0);
signal divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q : std_logic_vector (25 downto 0);
signal expRSmallpix_uid36_fpTanPiTest_a : std_logic_vector(8 downto 0);
signal expRSmallpix_uid36_fpTanPiTest_b : std_logic_vector(8 downto 0);
signal expRSmallpix_uid36_fpTanPiTest_o : std_logic_vector (8 downto 0);
signal expRSmallpix_uid36_fpTanPiTest_q : std_logic_vector (8 downto 0);
signal R_uid152_spix_uid43_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal R_uid250_cpix_uid44_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal concExc_uid339_tpix_uid45_fpTanPiTest_q : std_logic_vector (2 downto 0);
signal divR_uid351_tpix_uid45_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal tanPiXOutMux_uid47_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal tanPiXOutMux_uid47_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_a : std_logic_vector(5 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_b : std_logic_vector(5 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_a : std_logic_vector(3 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_b : std_logic_vector(3 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal expXP1R_uid106_spix_uid43_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid106_spix_uid43_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal oFracX_uid27_uid27_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRSmallPiXR_uid40_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal expFracRSmallPiXR_uid40_fpTanPiTest_b : std_logic_vector (30 downto 0);
signal InvExc_I_uid70_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid70_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid69_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid69_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid83_spix_uid43_fpTanPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid83_spix_uid43_fpTanPiTest_b : std_logic_vector (5 downto 0);
signal InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid94_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid94_spix_uid43_fpTanPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid110_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid110_spix_uid43_fpTanPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid111_spix_uid43_fpTanPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid111_spix_uid43_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid107_spix_uid43_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid107_spix_uid43_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_b : std_logic_vector (35 downto 0);
signal z_uid202_cpix_uid44_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal z_uid202_cpix_uid44_fpTanPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid208_cpix_uid44_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid208_cpix_uid44_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (31 downto 0);
signal rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (31 downto 0);
signal fracRSmallPiXNorm_uid34_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRSmallPiXNorm_uid34_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid122_uid123_spix_uid43_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal normBit_uid215_cpix_uid44_fpTanPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid215_cpix_uid44_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid216_cpix_uid44_fpTanPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid216_cpix_uid44_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid217_cpix_uid44_fpTanPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid217_cpix_uid44_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid461_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid462_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid467_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid580_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid580_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid581_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid581_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid586_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid586_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid587_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid587_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid599_invPE_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid599_invPE_b : std_logic_vector (0 downto 0);
signal highBBits_uid600_invPE_in : std_logic_vector (12 downto 0);
signal highBBits_uid600_invPE_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid605_invPE_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid605_invPE_b : std_logic_vector (1 downto 0);
signal highBBits_uid606_invPE_in : std_logic_vector (23 downto 0);
signal highBBits_uid606_invPE_b : std_logic_vector (21 downto 0);
signal norm_uid310_tpix_uid45_fpTanPiTest_in : std_logic_vector (25 downto 0);
signal norm_uid310_tpix_uid45_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_in : std_logic_vector (24 downto 0);
signal divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_in : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal expFracRSmallpixConc_uid37_fpTanPiTest_q : std_logic_vector (32 downto 0);
signal expX_uid255_tpix_uid45_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid255_tpix_uid45_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid256_tpix_uid45_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid256_tpix_uid45_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid257_tpix_uid45_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid257_tpix_uid45_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal expY_uid258_tpix_uid45_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid258_tpix_uid45_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal fracY_uid259_tpix_uid45_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid259_tpix_uid45_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal signY_uid260_tpix_uid45_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid260_tpix_uid45_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal fracYAddr_uid298_tpix_uid45_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal fracYAddr_uid298_tpix_uid45_fpTanPiTest_b : std_logic_vector (8 downto 0);
signal yPE_uid299_tpix_uid45_fpTanPiTest_in : std_logic_vector (13 downto 0);
signal yPE_uid299_tpix_uid45_fpTanPiTest_b : std_logic_vector (13 downto 0);
signal extendedFracX_uid82_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal join_uid41_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal exc_R_uid72_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid72_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid72_spix_uid43_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid72_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid459_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal zAddr_uid210_cpix_uid44_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid210_cpix_uid44_fpTanPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid211_cpix_uid44_fpTanPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid211_cpix_uid44_fpTanPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid376_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid379_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid382_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid446_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid449_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid452_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid565_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid568_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid571_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid124_spix_uid43_fpTanPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid124_spix_uid43_fpTanPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid124_spix_uid43_fpTanPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid124_spix_uid43_fpTanPiTest_q : std_logic_vector (32 downto 0);
signal fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid220_uid221_cpix_uid44_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid463_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal sumAHighB_uid582_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid582_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid582_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid582_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid588_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid588_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid588_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid588_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal sumAHighB_uid601_invPE_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid601_invPE_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid601_invPE_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid601_invPE_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid607_invPE_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid607_invPE_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid607_invPE_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid607_invPE_q : std_logic_vector (31 downto 0);
signal normFracRnd_uid313_tpix_uid45_fpTanPiTest_s : std_logic_vector (0 downto 0);
signal normFracRnd_uid313_tpix_uid45_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid316_tpix_uid45_fpTanPiTest_q : std_logic_vector (24 downto 0);
signal expXIsZero_uid266_tpix_uid45_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid266_tpix_uid45_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid266_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid268_tpix_uid45_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid268_tpix_uid45_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid268_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid270_tpix_uid45_fpTanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid270_tpix_uid45_fpTanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid270_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid282_tpix_uid45_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid282_tpix_uid45_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid282_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid284_tpix_uid45_fpTanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid284_tpix_uid45_fpTanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid284_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracYZero_uid261_tpix_uid45_fpTanPiTest_a : std_logic_vector(22 downto 0);
signal fracYZero_uid261_tpix_uid45_fpTanPiTest_b : std_logic_vector(22 downto 0);
signal fracYZero_uid261_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid286_tpix_uid45_fpTanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid286_tpix_uid45_fpTanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid286_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid597_invPE_in : std_logic_vector (13 downto 0);
signal yT1_uid597_invPE_b : std_logic_vector (11 downto 0);
signal X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (4 downto 0);
signal xIsInt_uid130_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid130_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid130_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid133_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid133_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid133_spix_uid43_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid133_spix_uid43_fpTanPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid133_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid228_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid228_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid228_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid231_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid231_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid231_cpix_uid44_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid231_cpix_uid44_fpTanPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid231_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid578_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid578_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal fracRComp_uid125_spix_uid43_fpTanPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid125_spix_uid43_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid126_spix_uid43_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid126_spix_uid43_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid222_cpix_uid44_fpTanPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid222_cpix_uid44_fpTanPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid222_cpix_uid44_fpTanPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid222_cpix_uid44_fpTanPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal s1_uid580_uid583_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid586_uid589_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal s1_uid599_uid602_invPE_q : std_logic_vector (22 downto 0);
signal s2_uid605_uid608_invPE_q : std_logic_vector (33 downto 0);
signal expFracRnd_uid314_tpix_uid45_fpTanPiTest_q : std_logic_vector (33 downto 0);
signal expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_a : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_b : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_o : std_logic_vector (35 downto 0);
signal expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excXZYZ_uid336_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXZYZ_uid336_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXZYZ_uid336_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid271_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid271_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid271_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excXIYZ_uid333_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXIYZ_uid333_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXIYZ_uid333_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid287_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid287_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid287_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid356_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid359_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal InvXIsInt_uid147_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid147_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal join_uid144_spix_uid43_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal intXParity_uid85_spix_uid43_fpTanPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid85_spix_uid43_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal y_uid86_spix_uid43_fpTanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid86_spix_uid43_fpTanPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid100_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid100_spix_uid43_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid206_cpix_uid44_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid206_cpix_uid44_fpTanPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid223_cpix_uid44_fpTanPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid223_cpix_uid44_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid224_cpix_uid44_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid224_cpix_uid44_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid113_spix_uid43_fpTanPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid113_spix_uid43_fpTanPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid213_cpix_uid44_fpTanPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid213_cpix_uid44_fpTanPiTest_b : std_logic_vector (24 downto 0);
signal invY_uid301_tpix_uid45_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal invY_uid301_tpix_uid45_fpTanPiTest_b : std_logic_vector (25 downto 0);
signal invYO_uid302_tpix_uid45_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal invYO_uid302_tpix_uid45_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPreExc_uid319_tpix_uid45_fpTanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid319_tpix_uid45_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal excRPreExc_uid320_tpix_uid45_fpTanPiTest_in : std_logic_vector (31 downto 0);
signal excRPreExc_uid320_tpix_uid45_fpTanPiTest_b : std_logic_vector (7 downto 0);
signal expRExt_uid321_tpix_uid45_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal expRExt_uid321_tpix_uid45_fpTanPiTest_b : std_logic_vector (10 downto 0);
signal InvExc_I_uid275_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid275_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excXIYI_uid337_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXIYI_uid337_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXIYI_uid337_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid273_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid273_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid273_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid291_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid291_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid289_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid289_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid289_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal join_uid242_cpix_uid44_fpTanPiTest_q : std_logic_vector (1 downto 0);
signal yBottom_uid95_spix_uid43_fpTanPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid95_spix_uid43_fpTanPiTest_b : std_logic_vector (34 downto 0);
signal FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b : std_logic_vector (0 downto 0);
signal r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q : std_logic_vector (5 downto 0);
signal pHardCase_uid101_spix_uid43_fpTanPiTest_q : std_logic_vector (23 downto 0);
signal r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid338_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid338_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid338_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid338_tpix_uid45_fpTanPiTest_d : std_logic_vector(0 downto 0);
signal excRNaN_uid338_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid274_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid274_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid290_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid290_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (1 downto 0);
signal exc_R_uid277_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid277_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid277_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid277_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid293_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid293_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid293_tpix_uid45_fpTanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid293_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal excXRYZ_uid331_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXRYZ_uid331_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXRYZ_uid331_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal excXIYR_uid334_tpix_uid45_fpTanPiTest_a : std_logic_vector(0 downto 0);
signal excXIYR_uid334_tpix_uid45_fpTanPiTest_b : std_logic_vector(0 downto 0);
signal excXIYR_uid334_tpix_uid45_fpTanPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_q : std_logic_vector (34 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable(LOGICAL,1446)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_a <= en;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q <= not ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_a;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor(LOGICAL,1471)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_b <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_q <= not (ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_a or ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_b);
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_mem_top(CONSTANT,1467)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_mem_top_q <= "011111";
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp(LOGICAL,1468)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_a <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_mem_top_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q);
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_q <= "1" when ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_a = ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_b else "0";
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg(REG,1469)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena(REG,1472)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_nor_q = "1") THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd(LOGICAL,1473)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_a <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_sticky_ena_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_b <= en;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_a and ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_b;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt(COUNTER,1463)
-- every=1, low=0, high=31, step=1, init=1
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_i <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_i,5));
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg(REG,1464)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux(MUX,1465)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_s <= en;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux: PROCESS (ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_s, ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q, ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem(DUALMEM,1462)
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_reset0 <= areset;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ia <= a;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_aa <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdreg_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ab <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_rdmux_q;
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 5,
numwords_a => 32,
width_b => 32,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_iq,
address_a => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_aa,
data_a => ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_ia
);
ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_iq(31 downto 0);
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor(LOGICAL,1459)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_b <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_q <= not (ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_a or ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_b);
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_mem_top(CONSTANT,1455)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_mem_top_q <= "011010";
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp(LOGICAL,1456)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_a <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_mem_top_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q);
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_q <= "1" when ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_a = ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_b else "0";
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg(REG,1457)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena(REG,1460)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_nor_q = "1") THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd(LOGICAL,1461)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_a <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_sticky_ena_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_b <= en;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_a and ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_b;
--signX_uid26_fpTanPiTest(BITSELECT,25)@0
signX_uid26_fpTanPiTest_in <= a;
signX_uid26_fpTanPiTest_b <= signX_uid26_fpTanPiTest_in(31 downto 31);
--ld_signX_uid26_fpTanPiTest_b_to_join_uid41_fpTanPiTest_b(DELAY,792)@0
ld_signX_uid26_fpTanPiTest_b_to_join_uid41_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => signX_uid26_fpTanPiTest_b, xout => ld_signX_uid26_fpTanPiTest_b_to_join_uid41_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--roundAndExpUpdateCst_uid38_fpTanPiTest(CONSTANT,37)
roundAndExpUpdateCst_uid38_fpTanPiTest_q <= "1000000000000000000000001";
--piwFP1_uid29_fpTanPiTest(CONSTANT,28)
piwFP1_uid29_fpTanPiTest_q <= "110010010000111111011011";
--fracX_uid25_fpTanPiTest(BITSELECT,24)@0
fracX_uid25_fpTanPiTest_in <= a(22 downto 0);
fracX_uid25_fpTanPiTest_b <= fracX_uid25_fpTanPiTest_in(22 downto 0);
--oFracX_uid27_uid27_fpTanPiTest(BITJOIN,26)@0
oFracX_uid27_uid27_fpTanPiTest_q <= VCC_q & fracX_uid25_fpTanPiTest_b;
--xpi_uid30_fpTanPiTest(MULT,29)@0
xpi_uid30_fpTanPiTest_pr <= UNSIGNED(xpi_uid30_fpTanPiTest_a) * UNSIGNED(xpi_uid30_fpTanPiTest_b);
xpi_uid30_fpTanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xpi_uid30_fpTanPiTest_a <= (others => '0');
xpi_uid30_fpTanPiTest_b <= (others => '0');
xpi_uid30_fpTanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xpi_uid30_fpTanPiTest_a <= oFracX_uid27_uid27_fpTanPiTest_q;
xpi_uid30_fpTanPiTest_b <= piwFP1_uid29_fpTanPiTest_q;
xpi_uid30_fpTanPiTest_s1 <= STD_LOGIC_VECTOR(xpi_uid30_fpTanPiTest_pr);
END IF;
END IF;
END PROCESS;
xpi_uid30_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xpi_uid30_fpTanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xpi_uid30_fpTanPiTest_q <= xpi_uid30_fpTanPiTest_s1;
END IF;
END IF;
END PROCESS;
--fsel_uid31_fpTanPiTest(BITSELECT,30)@3
fsel_uid31_fpTanPiTest_in <= xpi_uid30_fpTanPiTest_q;
fsel_uid31_fpTanPiTest_b <= fsel_uid31_fpTanPiTest_in(47 downto 47);
--exp_uid9_fpTanPiTest(BITSELECT,8)@0
exp_uid9_fpTanPiTest_in <= a(30 downto 0);
exp_uid9_fpTanPiTest_b <= exp_uid9_fpTanPiTest_in(30 downto 23);
--ld_exp_uid9_fpTanPiTest_b_to_expRSmallpix_uid36_fpTanPiTest_a(DELAY,785)@0
ld_exp_uid9_fpTanPiTest_b_to_expRSmallpix_uid36_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => exp_uid9_fpTanPiTest_b, xout => ld_exp_uid9_fpTanPiTest_b_to_expRSmallpix_uid36_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expRSmallpix_uid36_fpTanPiTest(ADD,35)@3
expRSmallpix_uid36_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_exp_uid9_fpTanPiTest_b_to_expRSmallpix_uid36_fpTanPiTest_a_q);
expRSmallpix_uid36_fpTanPiTest_b <= STD_LOGIC_VECTOR("00000000" & fsel_uid31_fpTanPiTest_b);
expRSmallpix_uid36_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRSmallpix_uid36_fpTanPiTest_a) + UNSIGNED(expRSmallpix_uid36_fpTanPiTest_b));
expRSmallpix_uid36_fpTanPiTest_q <= expRSmallpix_uid36_fpTanPiTest_o(8 downto 0);
--fracRSmallPiXH_uid32_fpTanPiTest(BITSELECT,31)@3
fracRSmallPiXH_uid32_fpTanPiTest_in <= xpi_uid30_fpTanPiTest_q(46 downto 0);
fracRSmallPiXH_uid32_fpTanPiTest_b <= fracRSmallPiXH_uid32_fpTanPiTest_in(46 downto 23);
--fracRSmallPiXL_uid33_fpTanPiTest(BITSELECT,32)@3
fracRSmallPiXL_uid33_fpTanPiTest_in <= xpi_uid30_fpTanPiTest_q(45 downto 0);
fracRSmallPiXL_uid33_fpTanPiTest_b <= fracRSmallPiXL_uid33_fpTanPiTest_in(45 downto 22);
--fracRSmallPiXNorm_uid34_fpTanPiTest(MUX,33)@3
fracRSmallPiXNorm_uid34_fpTanPiTest_s <= fsel_uid31_fpTanPiTest_b;
fracRSmallPiXNorm_uid34_fpTanPiTest: PROCESS (fracRSmallPiXNorm_uid34_fpTanPiTest_s, en, fracRSmallPiXL_uid33_fpTanPiTest_b, fracRSmallPiXH_uid32_fpTanPiTest_b)
BEGIN
CASE fracRSmallPiXNorm_uid34_fpTanPiTest_s IS
WHEN "0" => fracRSmallPiXNorm_uid34_fpTanPiTest_q <= fracRSmallPiXL_uid33_fpTanPiTest_b;
WHEN "1" => fracRSmallPiXNorm_uid34_fpTanPiTest_q <= fracRSmallPiXH_uid32_fpTanPiTest_b;
WHEN OTHERS => fracRSmallPiXNorm_uid34_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSmallpixConc_uid37_fpTanPiTest(BITJOIN,36)@3
expFracRSmallpixConc_uid37_fpTanPiTest_q <= expRSmallpix_uid36_fpTanPiTest_q & fracRSmallPiXNorm_uid34_fpTanPiTest_q;
--reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0(REG,769)@3
reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0_q <= expFracRSmallpixConc_uid37_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--expRSmallpix2_uid39_fpTanPiTest(ADD,38)@4
expRSmallpix2_uid39_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracRSmallpixConc_uid37_fpTanPiTest_0_to_expRSmallpix2_uid39_fpTanPiTest_0_q);
expRSmallpix2_uid39_fpTanPiTest_b <= STD_LOGIC_VECTOR("000000000" & roundAndExpUpdateCst_uid38_fpTanPiTest_q);
expRSmallpix2_uid39_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRSmallpix2_uid39_fpTanPiTest_a) + UNSIGNED(expRSmallpix2_uid39_fpTanPiTest_b));
expRSmallpix2_uid39_fpTanPiTest_q <= expRSmallpix2_uid39_fpTanPiTest_o(33 downto 0);
--expFracRSmallPiXR_uid40_fpTanPiTest(BITSELECT,39)@4
expFracRSmallPiXR_uid40_fpTanPiTest_in <= expRSmallpix2_uid39_fpTanPiTest_q(31 downto 0);
expFracRSmallPiXR_uid40_fpTanPiTest_b <= expFracRSmallPiXR_uid40_fpTanPiTest_in(31 downto 1);
--join_uid41_fpTanPiTest(BITJOIN,40)@4
join_uid41_fpTanPiTest_q <= ld_signX_uid26_fpTanPiTest_b_to_join_uid41_fpTanPiTest_b_q & expFracRSmallPiXR_uid40_fpTanPiTest_b;
--reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3(REG,770)@4
reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q <= join_uid41_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=26, step=1, init=1
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i = 25 THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i - 26;
ELSE
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_i,5));
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg(REG,1452)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux(MUX,1453)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_s <= en;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux: PROCESS (ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_s, ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q, ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem(DUALMEM,1450)
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_reset0 <= areset;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ia <= reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_aa <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdreg_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ab <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_rdmux_q;
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 5,
numwords_a => 27,
width_b => 32,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_iq,
address_a => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_aa,
data_a => ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_ia
);
ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_iq(31 downto 0);
--cstAllZWF_uid53_spix_uid43_fpTanPiTest(CONSTANT,52)
cstAllZWF_uid53_spix_uid43_fpTanPiTest_q <= "00000000000000000000000";
--LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,380)@1
LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,379)
leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "000";
--leftShiftStage2Idx3_uid382_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,381)@1
leftShiftStage2Idx3_uid382_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage133dto0_uid381_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,377)@1
LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(34 downto 0);
--z_uid306_tpix_uid45_fpTanPiTest(CONSTANT,305)
z_uid306_tpix_uid45_fpTanPiTest_q <= "00";
--leftShiftStage2Idx2_uid379_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,378)@1
leftShiftStage2Idx2_uid379_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage134dto0_uid378_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & z_uid306_tpix_uid45_fpTanPiTest_q;
--LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,374)@1
LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid376_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,375)@1
leftShiftStage2Idx1_uid376_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage135dto0_uid375_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & GND_q;
--leftShiftStage0Idx3_uid360_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,359)
leftShiftStage0Idx3_uid360_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,357)@0
X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= extendedFracX_uid82_spix_uid43_fpTanPiTest_q(4 downto 0);
X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,356)
leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid359_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,358)@0
leftShiftStage0Idx2_uid359_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= X4dto0_uid358_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,354)@0
X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= extendedFracX_uid82_spix_uid43_fpTanPiTest_q(20 downto 0);
X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,353)
leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid356_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,355)@0
leftShiftStage0Idx1_uid356_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= X20dto0_uid355_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--cst01pWShift_uid81_spix_uid43_fpTanPiTest(CONSTANT,80)
cst01pWShift_uid81_spix_uid43_fpTanPiTest_q <= "0000000000000";
--extendedFracX_uid82_spix_uid43_fpTanPiTest(BITJOIN,81)@0
extendedFracX_uid82_spix_uid43_fpTanPiTest_q <= cst01pWShift_uid81_spix_uid43_fpTanPiTest_q & oFracX_uid27_uid27_fpTanPiTest_q;
--cstBiasMwSMo_uid22_fpTanPiTest(CONSTANT,21)
cstBiasMwSMo_uid22_fpTanPiTest_q <= "01110010";
--shiftValue_uid80_spix_uid43_fpTanPiTest(SUB,79)@0
shiftValue_uid80_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & exp_uid9_fpTanPiTest_b);
shiftValue_uid80_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwSMo_uid22_fpTanPiTest_q);
shiftValue_uid80_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid80_spix_uid43_fpTanPiTest_a) - UNSIGNED(shiftValue_uid80_spix_uid43_fpTanPiTest_b));
shiftValue_uid80_spix_uid43_fpTanPiTest_q <= shiftValue_uid80_spix_uid43_fpTanPiTest_o(8 downto 0);
--fxpShifterBits_uid83_spix_uid43_fpTanPiTest(BITSELECT,82)@0
fxpShifterBits_uid83_spix_uid43_fpTanPiTest_in <= shiftValue_uid80_spix_uid43_fpTanPiTest_q(5 downto 0);
fxpShifterBits_uid83_spix_uid43_fpTanPiTest_b <= fxpShifterBits_uid83_spix_uid43_fpTanPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,360)@0
leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= fxpShifterBits_uid83_spix_uid43_fpTanPiTest_b;
leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(5 downto 4);
--leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest(MUX,361)@0
leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_s <= leftShiftStageSel5Dto4_uid361_fixedPointX_uid84_spix_uid43_fpTanPiTest_b;
leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_s, en, extendedFracX_uid82_spix_uid43_fpTanPiTest_q, leftShiftStage0Idx1_uid356_fixedPointX_uid84_spix_uid43_fpTanPiTest_q, leftShiftStage0Idx2_uid359_fixedPointX_uid84_spix_uid43_fpTanPiTest_q, leftShiftStage0Idx3_uid360_fixedPointX_uid84_spix_uid43_fpTanPiTest_q)
BEGIN
CASE leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= extendedFracX_uid82_spix_uid43_fpTanPiTest_q;
WHEN "01" => leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage0Idx1_uid356_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN "10" => leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage0Idx2_uid359_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN "11" => leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage0Idx3_uid360_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,369)@0
LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,368)
leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,370)@0
leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage024dto0_uid370_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5(REG,679)@0
reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5_q <= leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,366)@0
LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(28 downto 0);
--cstAllZWE_uid8_fpTanPiTest(CONSTANT,7)
cstAllZWE_uid8_fpTanPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,367)@0
leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage028dto0_uid367_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & cstAllZWE_uid8_fpTanPiTest_q;
--reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4(REG,678)@0
reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4_q <= leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,363)@0
LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest(CONSTANT,362)
leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= "0000";
--leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITJOIN,364)@0
leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= LeftShiftStage032dto0_uid364_fixedPointX_uid84_spix_uid43_fpTanPiTest_b & leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3(REG,677)@0
reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3_q <= leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2(REG,676)@0
reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2_q <= leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,371)@0
leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= fxpShifterBits_uid83_spix_uid43_fpTanPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1(REG,675)@0
reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q <= leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest(MUX,372)@1
leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_s <= reg_leftShiftStageSel3Dto2_uid372_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q;
leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_s, en, reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2_q, reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3_q, reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4_q, reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage0_uid362_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx1_uid365_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_3_q;
WHEN "10" => leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx2_uid368_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_4_q;
WHEN "11" => leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx3_uid371_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest(BITSELECT,382)@0
leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_in <= fxpShifterBits_uid83_spix_uid43_fpTanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_b <= leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1(REG,680)@0
reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q <= leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest(MUX,383)@1
leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_s <= reg_leftShiftStageSel1Dto0_uid383_fixedPointX_uid84_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_1_q;
leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_s, en, leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx1_uid376_fixedPointX_uid84_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx2_uid379_fixedPointX_uid84_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx3_uid382_fixedPointX_uid84_spix_uid43_fpTanPiTest_q)
BEGIN
CASE leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage1_uid373_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN "01" => leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx1_uid376_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN "10" => leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx2_uid379_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN "11" => leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx3_uid382_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid86_spix_uid43_fpTanPiTest(BITSELECT,85)@1
y_uid86_spix_uid43_fpTanPiTest_in <= leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q(35 downto 0);
y_uid86_spix_uid43_fpTanPiTest_b <= y_uid86_spix_uid43_fpTanPiTest_in(35 downto 0);
--FxpXFrac35_uid192_cpix_uid44_fpTanPiTest(BITSELECT,191)@1
FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_in <= y_uid86_spix_uid43_fpTanPiTest_b;
FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b <= FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_in(35 downto 35);
--intXParity_uid85_spix_uid43_fpTanPiTest(BITSELECT,84)@1
intXParity_uid85_spix_uid43_fpTanPiTest_in <= leftShiftStage2_uid384_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
intXParity_uid85_spix_uid43_fpTanPiTest_b <= intXParity_uid85_spix_uid43_fpTanPiTest_in(36 downto 36);
--xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest(LOGICAL,243)@1
xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_a <= intXParity_uid85_spix_uid43_fpTanPiTest_b;
xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_b <= FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b;
xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q <= xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_a xor xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_b;
--ld_xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q_to_signRComp_uid247_cpix_uid44_fpTanPiTest_c(DELAY,973)@1
ld_xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q_to_signRComp_uid247_cpix_uid44_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q, xout => ld_xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q_to_signRComp_uid247_cpix_uid44_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid55_spix_uid43_fpTanPiTest(CONSTANT,54)
cstBiasPwF_uid55_spix_uid43_fpTanPiTest_q <= "10010110";
--xIntExp_uid73_spix_uid43_fpTanPiTest(COMPARE,72)@0
xIntExp_uid73_spix_uid43_fpTanPiTest_cin <= GND_q;
xIntExp_uid73_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid55_spix_uid43_fpTanPiTest_q) & '0';
xIntExp_uid73_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpTanPiTest_b) & xIntExp_uid73_spix_uid43_fpTanPiTest_cin(0);
xIntExp_uid73_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid73_spix_uid43_fpTanPiTest_a) - UNSIGNED(xIntExp_uid73_spix_uid43_fpTanPiTest_b));
xIntExp_uid73_spix_uid43_fpTanPiTest_c(0) <= xIntExp_uid73_spix_uid43_fpTanPiTest_o(10);
--ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a(DELAY,867)@0
ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xIntExp_uid73_spix_uid43_fpTanPiTest_c, xout => ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXIntExp_uid131_spix_uid43_fpTanPiTest(LOGICAL,130)@2
InvXIntExp_uid131_spix_uid43_fpTanPiTest_a <= ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a_q;
InvXIntExp_uid131_spix_uid43_fpTanPiTest_q <= not InvXIntExp_uid131_spix_uid43_fpTanPiTest_a;
--tanXIsX_uid28_fpTanPiTest(COMPARE,27)@0
tanXIsX_uid28_fpTanPiTest_cin <= GND_q;
tanXIsX_uid28_fpTanPiTest_a <= STD_LOGIC_VECTOR("00" & exp_uid9_fpTanPiTest_b) & '0';
tanXIsX_uid28_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMwSMo_uid22_fpTanPiTest_q) & tanXIsX_uid28_fpTanPiTest_cin(0);
tanXIsX_uid28_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(tanXIsX_uid28_fpTanPiTest_a) - UNSIGNED(tanXIsX_uid28_fpTanPiTest_b));
tanXIsX_uid28_fpTanPiTest_c(0) <= tanXIsX_uid28_fpTanPiTest_o(10);
--ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a(DELAY,937)@0
ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => tanXIsX_uid28_fpTanPiTest_c, xout => ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest(LOGICAL,224)@2
InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a <= ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a_q;
InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_q <= not InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a;
--signRComp_uid247_cpix_uid44_fpTanPiTest(LOGICAL,246)@2
signRComp_uid247_cpix_uid44_fpTanPiTest_a <= InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_q;
signRComp_uid247_cpix_uid44_fpTanPiTest_b <= InvXIntExp_uid131_spix_uid43_fpTanPiTest_q;
signRComp_uid247_cpix_uid44_fpTanPiTest_c <= ld_xParityXorHalfParity_uid244_cpix_uid44_fpTanPiTest_q_to_signRComp_uid247_cpix_uid44_fpTanPiTest_c_q;
signRComp_uid247_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid247_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid247_cpix_uid44_fpTanPiTest_q <= signRComp_uid247_cpix_uid44_fpTanPiTest_a and signRComp_uid247_cpix_uid44_fpTanPiTest_b and signRComp_uid247_cpix_uid44_fpTanPiTest_c;
END IF;
END PROCESS;
--ozz_uid88_spix_uid43_fpTanPiTest(CONSTANT,87)
ozz_uid88_spix_uid43_fpTanPiTest_q <= "00000000000000000000000000000000000";
--join_uid89_spix_uid43_fpTanPiTest(BITJOIN,88)@2
join_uid89_spix_uid43_fpTanPiTest_q <= VCC_q & ozz_uid88_spix_uid43_fpTanPiTest_q;
--reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1(REG,681)@1
reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q <= y_uid86_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid90_spix_uid43_fpTanPiTest(LOGICAL,89)@2
yIsZero_uid90_spix_uid43_fpTanPiTest_a <= reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q;
yIsZero_uid90_spix_uid43_fpTanPiTest_b <= join_uid89_spix_uid43_fpTanPiTest_q;
yIsZero_uid90_spix_uid43_fpTanPiTest_q <= "1" when yIsZero_uid90_spix_uid43_fpTanPiTest_a = yIsZero_uid90_spix_uid43_fpTanPiTest_b else "0";
--InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest(LOGICAL,247)@2
InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_a <= yIsZero_uid90_spix_uid43_fpTanPiTest_q;
InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q <= not InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_a;
--ld_InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q_to_signR_uid249_cpix_uid44_fpTanPiTest_a(DELAY,975)@2
ld_InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q_to_signR_uid249_cpix_uid44_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q, xout => ld_InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q_to_signR_uid249_cpix_uid44_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid249_cpix_uid44_fpTanPiTest(LOGICAL,248)@3
signR_uid249_cpix_uid44_fpTanPiTest_a <= ld_InvFxpXFracHalf_uid248_cpix_uid44_fpTanPiTest_q_to_signR_uid249_cpix_uid44_fpTanPiTest_a_q;
signR_uid249_cpix_uid44_fpTanPiTest_b <= signRComp_uid247_cpix_uid44_fpTanPiTest_q;
signR_uid249_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid249_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid249_cpix_uid44_fpTanPiTest_q <= signR_uid249_cpix_uid44_fpTanPiTest_a and signR_uid249_cpix_uid44_fpTanPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid249_cpix_uid44_fpTanPiTest_q_to_R_uid250_cpix_uid44_fpTanPiTest_c(DELAY,979)@4
ld_signR_uid249_cpix_uid44_fpTanPiTest_q_to_R_uid250_cpix_uid44_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid249_cpix_uid44_fpTanPiTest_q, xout => ld_signR_uid249_cpix_uid44_fpTanPiTest_q_to_R_uid250_cpix_uid44_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid54_spix_uid43_fpTanPiTest(CONSTANT,53)
cstBias_uid54_spix_uid43_fpTanPiTest_q <= "01111111";
--cstAllOWE_uid52_spix_uid43_fpTanPiTest(CONSTANT,51)
cstAllOWE_uid52_spix_uid43_fpTanPiTest_q <= "11111111";
--pad_o_uid164_uid195_cpix_uid44_fpTanPiTest(BITJOIN,194)@1
pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0(REG,721)@1
reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0_q <= pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest(SUB,195)@2
oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid164_uid195_cpix_uid44_fpTanPiTest_0_to_oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_0_q);
oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q);
oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_a) - UNSIGNED(oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_b));
oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_q <= oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_o(37 downto 0);
--oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest(BITSELECT,196)@2
oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_in <= oMFxpXFrac_uid195_cpix_uid44_fpTanPiTest_q(35 downto 0);
oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_b <= oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_in(35 downto 0);
--ld_y_uid86_spix_uid43_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_c(DELAY,913)@1
ld_y_uid86_spix_uid43_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => y_uid86_spix_uid43_fpTanPiTest_b, xout => ld_y_uid86_spix_uid43_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_b(DELAY,912)@1
ld_FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b, xout => ld_FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest(MUX,198)@2
rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_s <= ld_FxpXFrac35_uid192_cpix_uid44_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_b_q;
rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q <= ld_y_uid86_spix_uid43_fpTanPiTest_b_to_rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q <= oMFxpXFrac_uid197_cpix_uid44_fpTanPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid165_uid200_cpix_uid44_fpTanPiTest(BITJOIN,199)@2
pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0(REG,723)@2
reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0_q <= pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest(SUB,200)@3
z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid165_uid200_cpix_uid44_fpTanPiTest_0_to_z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_0_q);
z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid199_cpix_uid44_fpTanPiTest_q);
z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_b));
z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_q <= z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_o(36 downto 0);
--z_uid202_cpix_uid44_fpTanPiTest(BITSELECT,201)@3
z_uid202_cpix_uid44_fpTanPiTest_in <= z_halfMRRFxPXE_uid200_cpix_uid44_fpTanPiTest_q(34 downto 0);
z_uid202_cpix_uid44_fpTanPiTest_b <= z_uid202_cpix_uid44_fpTanPiTest_in(34 downto 0);
--zAddr_uid210_cpix_uid44_fpTanPiTest(BITSELECT,209)@3
zAddr_uid210_cpix_uid44_fpTanPiTest_in <= z_uid202_cpix_uid44_fpTanPiTest_b;
zAddr_uid210_cpix_uid44_fpTanPiTest_b <= zAddr_uid210_cpix_uid44_fpTanPiTest_in(34 downto 28);
--reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0(REG,740)@3
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0_q <= zAddr_uid210_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid577_sinPiZTableGenerator(LOOKUP,576)@4
memoryC2_uid577_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid577_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid577_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid577_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid577_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid577_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid577_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid577_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid211_cpix_uid44_fpTanPiTest(BITSELECT,210)@3
zPPolyEval_uid211_cpix_uid44_fpTanPiTest_in <= z_uid202_cpix_uid44_fpTanPiTest_b(27 downto 0);
zPPolyEval_uid211_cpix_uid44_fpTanPiTest_b <= zPPolyEval_uid211_cpix_uid44_fpTanPiTest_in(27 downto 12);
--yT1_uid578_sinPiZPolyEval(BITSELECT,577)@3
yT1_uid578_sinPiZPolyEval_in <= zPPolyEval_uid211_cpix_uid44_fpTanPiTest_b;
yT1_uid578_sinPiZPolyEval_b <= yT1_uid578_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0(REG,741)@3
reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q <= yT1_uid578_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_a(DELAY,1326)@4
ld_reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid619_pT1_uid579_sinPiZPolyEval(MULT,618)@5
prodXY_uid619_pT1_uid579_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid619_pT1_uid579_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid619_pT1_uid579_sinPiZPolyEval_b);
prodXY_uid619_pT1_uid579_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid619_pT1_uid579_sinPiZPolyEval_a <= (others => '0');
prodXY_uid619_pT1_uid579_sinPiZPolyEval_b <= (others => '0');
prodXY_uid619_pT1_uid579_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid619_pT1_uid579_sinPiZPolyEval_a <= ld_reg_yT1_uid578_sinPiZPolyEval_0_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_0_q_to_prodXY_uid619_pT1_uid579_sinPiZPolyEval_a_q;
prodXY_uid619_pT1_uid579_sinPiZPolyEval_b <= memoryC2_uid577_sinPiZTableGenerator_q;
prodXY_uid619_pT1_uid579_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid619_pT1_uid579_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid619_pT1_uid579_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid619_pT1_uid579_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid619_pT1_uid579_sinPiZPolyEval_q <= prodXY_uid619_pT1_uid579_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval(BITSELECT,619)@8
prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_in <= prodXY_uid619_pT1_uid579_sinPiZPolyEval_q;
prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_b <= prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid581_sinPiZPolyEval(BITSELECT,580)@8
highBBits_uid581_sinPiZPolyEval_in <= prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_b;
highBBits_uid581_sinPiZPolyEval_b <= highBBits_uid581_sinPiZPolyEval_in(14 downto 1);
--ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_inputreg(DELAY,1661)
ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => zAddr_uid210_cpix_uid44_fpTanPiTest_b, xout => ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a(DELAY,1408)@3
ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_inputreg_q, xout => ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0(REG,742)@7
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_q <= ld_zAddr_uid210_cpix_uid44_fpTanPiTest_b_to_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid576_sinPiZTableGenerator(LOOKUP,575)@8
memoryC1_uid576_sinPiZTableGenerator: PROCESS (reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC1_uid576_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC1_uid576_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid576_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid576_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid576_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid576_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid576_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid576_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid576_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid576_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid576_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid576_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid576_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid576_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid576_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid576_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid576_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid576_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid576_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid576_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid576_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid576_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid576_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid576_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid576_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid576_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid576_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid576_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid576_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid576_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid576_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid576_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid576_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid576_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid576_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid576_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid576_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid576_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid576_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid576_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid576_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid576_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid576_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid576_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid576_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid576_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid576_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid576_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid576_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid576_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid576_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid576_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid576_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid576_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid576_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid576_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid576_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid576_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid576_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid576_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid576_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid576_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid576_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid576_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid576_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid576_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid576_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid576_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid576_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid576_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid576_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid576_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid576_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid576_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid576_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid576_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid576_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid576_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid576_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid576_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid576_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid576_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid576_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid576_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid576_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid576_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid576_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid576_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid576_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid576_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid576_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid576_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid576_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid576_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid582_sinPiZPolyEval(ADD,581)@8
sumAHighB_uid582_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid576_sinPiZTableGenerator_q(20)) & memoryC1_uid576_sinPiZTableGenerator_q);
sumAHighB_uid582_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid581_sinPiZPolyEval_b(13)) & highBBits_uid581_sinPiZPolyEval_b);
sumAHighB_uid582_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid582_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid582_sinPiZPolyEval_b));
sumAHighB_uid582_sinPiZPolyEval_q <= sumAHighB_uid582_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid580_sinPiZPolyEval(BITSELECT,579)@8
lowRangeB_uid580_sinPiZPolyEval_in <= prodXYTruncFR_uid620_pT1_uid579_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid580_sinPiZPolyEval_b <= lowRangeB_uid580_sinPiZPolyEval_in(0 downto 0);
--s1_uid580_uid583_sinPiZPolyEval(BITJOIN,582)@8
s1_uid580_uid583_sinPiZPolyEval_q <= sumAHighB_uid582_sinPiZPolyEval_q & lowRangeB_uid580_sinPiZPolyEval_b;
--reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1(REG,744)@8
reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1_q <= s1_uid580_uid583_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor(LOGICAL,1631)
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_b);
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_mem_top(CONSTANT,1503)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_mem_top_q <= "011";
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp(LOGICAL,1504)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_a <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_mem_top_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q);
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_q <= "1" when ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_a = ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_b else "0";
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg(REG,1505)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena(REG,1632)
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd(LOGICAL,1633)
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0(REG,743)@3
reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q <= zPPolyEval_uid211_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt(COUNTER,1499)
-- every=1, low=0, high=3, step=1, init=1
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_i <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_i,2));
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg(REG,1500)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux(MUX,1501)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_s <= en;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux: PROCESS (ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_s, ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q, ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem(DUALMEM,1622)
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ia <= reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_aa <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ab <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 4,
width_b => 16,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid622_pT2_uid585_sinPiZPolyEval(MULT,621)@9
prodXY_uid622_pT2_uid585_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid622_pT2_uid585_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid622_pT2_uid585_sinPiZPolyEval_b);
prodXY_uid622_pT2_uid585_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid622_pT2_uid585_sinPiZPolyEval_a <= (others => '0');
prodXY_uid622_pT2_uid585_sinPiZPolyEval_b <= (others => '0');
prodXY_uid622_pT2_uid585_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid622_pT2_uid585_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid211_cpix_uid44_fpTanPiTest_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_0_q_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid622_pT2_uid585_sinPiZPolyEval_b <= reg_s1_uid580_uid583_sinPiZPolyEval_0_to_prodXY_uid622_pT2_uid585_sinPiZPolyEval_1_q;
prodXY_uid622_pT2_uid585_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid622_pT2_uid585_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid622_pT2_uid585_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid622_pT2_uid585_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid622_pT2_uid585_sinPiZPolyEval_q <= prodXY_uid622_pT2_uid585_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval(BITSELECT,622)@12
prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_in <= prodXY_uid622_pT2_uid585_sinPiZPolyEval_q;
prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_b <= prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid587_sinPiZPolyEval(BITSELECT,586)@12
highBBits_uid587_sinPiZPolyEval_in <= prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_b;
highBBits_uid587_sinPiZPolyEval_b <= highBBits_uid587_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor(LOGICAL,1607)
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_mem_top(CONSTANT,1540)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp(LOGICAL,1541)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_a <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_mem_top_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q);
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_q <= "1" when ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_a = ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_b else "0";
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg(REG,1542)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena(REG,1608)
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd(LOGICAL,1609)
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt(COUNTER,1536)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg(REG,1537)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux(MUX,1538)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_s, ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q, ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem(DUALMEM,1598)
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC2_uid577_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid575_sinPiZTableGenerator(LOOKUP,574)@12
memoryC0_uid575_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid210_cpix_uid44_fpTanPiTest_0_to_memoryC0_uid575_sinPiZTableGenerator_0_q_to_memoryC0_uid575_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid575_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid575_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid588_sinPiZPolyEval(ADD,587)@12
sumAHighB_uid588_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid575_sinPiZTableGenerator_q(28)) & memoryC0_uid575_sinPiZTableGenerator_q);
sumAHighB_uid588_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid587_sinPiZPolyEval_b(21)) & highBBits_uid587_sinPiZPolyEval_b);
sumAHighB_uid588_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid588_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid588_sinPiZPolyEval_b));
sumAHighB_uid588_sinPiZPolyEval_q <= sumAHighB_uid588_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid586_sinPiZPolyEval(BITSELECT,585)@12
lowRangeB_uid586_sinPiZPolyEval_in <= prodXYTruncFR_uid623_pT2_uid585_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid586_sinPiZPolyEval_b <= lowRangeB_uid586_sinPiZPolyEval_in(1 downto 0);
--s2_uid586_uid589_sinPiZPolyEval(BITJOIN,588)@12
s2_uid586_uid589_sinPiZPolyEval_q <= sumAHighB_uid588_sinPiZPolyEval_q & lowRangeB_uid586_sinPiZPolyEval_b;
--fxpSinRes_uid213_cpix_uid44_fpTanPiTest(BITSELECT,212)@12
fxpSinRes_uid213_cpix_uid44_fpTanPiTest_in <= s2_uid586_uid589_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid213_cpix_uid44_fpTanPiTest_b <= fxpSinRes_uid213_cpix_uid44_fpTanPiTest_in(29 downto 5);
--reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1(REG,747)@12
reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1_q <= fxpSinRes_uid213_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor(LOGICAL,1672)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_b <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_q <= not (ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_a or ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_b);
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_mem_top(CONSTANT,1668)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_mem_top_q <= "010";
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp(LOGICAL,1669)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_a <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_mem_top_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q);
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_q <= "1" when ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_a = ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_b else "0";
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg(REG,1670)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena(REG,1673)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd(LOGICAL,1674)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_a and ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,569)@7
LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid571_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,570)@7
leftShiftStage2Idx3_uid571_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage131dto0_uid570_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,566)@7
LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid568_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,567)@7
leftShiftStage2Idx2_uid568_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage132dto0_uid567_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & z_uid306_tpix_uid45_fpTanPiTest_q;
--LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,563)@7
LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid565_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,564)@7
leftShiftStage2Idx1_uid565_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage133dto0_uid564_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & GND_q;
--vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,508)@3
vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= z_uid202_cpix_uid44_fpTanPiTest_b(2 downto 0);
vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(2 downto 0);
--ld_vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_b(DELAY,1255)@3
ld_vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b, xout => ld_vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,547)@6
leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= ld_vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q & leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,543)@3
X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= z_uid202_cpix_uid44_fpTanPiTest_b(18 downto 0);
X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(18 downto 0);
--ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_inputreg(DELAY,1596)
ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b, xout => ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b(DELAY,1254)@3
ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_inputreg_q, xout => ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,544)@6
leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= ld_X18dto0_uid544_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_b_q & leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_inputreg(DELAY,1597)
ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid202_cpix_uid44_fpTanPiTest_b, xout => ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c(DELAY,1258)@3
ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_inputreg_q, xout => ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,505)@3
rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= z_uid202_cpix_uid44_fpTanPiTest_b;
rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(34 downto 3);
--reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1(REG,724)@3
reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,506)@4
vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--ld_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_f(DELAY,1252)@4
ld_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q, xout => ld_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid389_lzcZ_uid98_spix_uid43_fpTanPiTest(CONSTANT,388)
mO_uid389_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "11111111111111111111111111111";
--cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITJOIN,509)@3
cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= vStage_uid509_lzcZ_uid204_cpix_uid44_fpTanPiTest_b & mO_uid389_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
--reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3(REG,726)@3
reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest(MUX,511)@4
vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_s <= vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest: PROCESS (vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_s, en, reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q, reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_rVStage_uid506_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_cStage_uid510_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,513)@4
rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(31 downto 16);
--reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1(REG,727)@4
reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,514)@5
vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--ld_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_e(DELAY,1251)@5
ld_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q, xout => ld_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,515)@4
vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid512_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(15 downto 0);
vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(15 downto 0);
--reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3(REG,729)@4
reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest(MUX,517)@5
vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_s <= vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest: PROCESS (vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_s, en, reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q, reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_rVStage_uid514_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_vStage_uid516_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,519)@5
rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(15 downto 8);
--vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,520)@5
vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= cstAllZWE_uid8_fpTanPiTest_q;
vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3(REG,733)@5
reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,521)@5
vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid518_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(7 downto 0);
vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(7 downto 0);
--vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest(MUX,523)@5
vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_s <= vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest: PROCESS (vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_s, en, rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_b, vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_b)
BEGIN
CASE vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= rVStage_uid520_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
WHEN "1" => vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= vStage_uid522_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
WHEN OTHERS => vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,525)@5
rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(7 downto 4);
--reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1(REG,730)@5
reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q <= rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,526)@6
vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,527)@5
vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid524_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(3 downto 0);
vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(3 downto 0);
--reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3(REG,732)@5
reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q <= vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest(MUX,529)@6
vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_s <= vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest: PROCESS (vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_s, en, reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q, reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_rVStage_uid526_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= reg_vStage_uid528_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,531)@6
rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(3 downto 2);
--vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,532)@6
vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= z_uid306_tpix_uid45_fpTanPiTest_q;
vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,533)@6
vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid530_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(1 downto 0);
vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(1 downto 0);
--vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest(MUX,535)@6
vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_s <= vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest: PROCESS (vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_s, en, rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_b, vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_b)
BEGIN
CASE vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= rVStage_uid532_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
WHEN "1" => vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= vStage_uid534_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
WHEN OTHERS => vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITSELECT,537)@6
rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_in <= vStagei_uid536_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_in(1 downto 1);
--vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest(LOGICAL,538)@6
vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_a <= rVStage_uid538_lzcZ_uid204_cpix_uid44_fpTanPiTest_b;
vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_b <= GND_q;
vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= "1" when vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_a = vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_b else "0";
--r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest(BITJOIN,539)@6
r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q <= ld_vCount_uid507_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_f_q & ld_vCount_uid515_lzcZ_uid204_cpix_uid44_fpTanPiTest_q_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_e_q & reg_vCount_uid521_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_3_q & vCount_uid527_lzcZ_uid204_cpix_uid44_fpTanPiTest_q & vCount_uid533_lzcZ_uid204_cpix_uid44_fpTanPiTest_q & vCount_uid539_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
--leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,549)@6
leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(5 downto 4);
--leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest(MUX,550)@6
leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_s <= leftShiftStageSel5Dto4_uid550_alignedZ_uid205_cpix_uid44_fpTanPiTest_b;
leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest: PROCESS (leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_s, en, ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_q, leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_q, leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_q, ozz_uid88_spix_uid43_fpTanPiTest_q)
BEGIN
CASE leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_s IS
WHEN "00" => leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= ld_z_uid202_cpix_uid44_fpTanPiTest_b_to_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_c_q;
WHEN "01" => leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage0Idx1_uid545_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN "10" => leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage0Idx2_uid548_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN "11" => leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= ozz_uid88_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,558)@6
LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,559)@6
leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage022dto0_uid559_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5(REG,738)@6
reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5_q <= leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,555)@6
LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,556)@6
leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage026dto0_uid556_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & cstAllZWE_uid8_fpTanPiTest_q;
--reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4(REG,737)@6
reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4_q <= leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,552)@6
LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITJOIN,553)@6
leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= LeftShiftStage030dto0_uid553_alignedZ_uid205_cpix_uid44_fpTanPiTest_b & leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3(REG,736)@6
reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3_q <= leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2(REG,735)@6
reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2_q <= leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,560)@6
leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1(REG,734)@6
reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q <= leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest(MUX,561)@7
leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_s <= reg_leftShiftStageSel3Dto2_uid561_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q;
leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest: PROCESS (leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_s, en, reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2_q, reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3_q, reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4_q, reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_s IS
WHEN "00" => leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= reg_leftShiftStage0_uid551_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= reg_leftShiftStage1Idx1_uid554_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_3_q;
WHEN "10" => leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= reg_leftShiftStage1Idx2_uid557_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_4_q;
WHEN "11" => leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= reg_leftShiftStage1Idx3_uid560_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest(BITSELECT,571)@6
leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_in <= r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_b <= leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1(REG,739)@6
reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q <= leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest(MUX,572)@7
leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_s <= reg_leftShiftStageSel1Dto0_uid572_alignedZ_uid205_cpix_uid44_fpTanPiTest_0_to_leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_1_q;
leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest: PROCESS (leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_s, en, leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q, leftShiftStage2Idx1_uid565_alignedZ_uid205_cpix_uid44_fpTanPiTest_q, leftShiftStage2Idx2_uid568_alignedZ_uid205_cpix_uid44_fpTanPiTest_q, leftShiftStage2Idx3_uid571_alignedZ_uid205_cpix_uid44_fpTanPiTest_q)
BEGIN
CASE leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_s IS
WHEN "00" => leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage1_uid562_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN "01" => leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage2Idx1_uid565_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN "10" => leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage2Idx2_uid568_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN "11" => leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= leftShiftStage2Idx3_uid571_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid206_cpix_uid44_fpTanPiTest(BITSELECT,205)@7
alignedZLow_uid206_cpix_uid44_fpTanPiTest_in <= leftShiftStage2_uid573_alignedZ_uid205_cpix_uid44_fpTanPiTest_q;
alignedZLow_uid206_cpix_uid44_fpTanPiTest_b <= alignedZLow_uid206_cpix_uid44_fpTanPiTest_in(34 downto 11);
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_inputreg(DELAY,1662)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid206_cpix_uid44_fpTanPiTest_b, xout => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt(COUNTER,1664)
-- every=1, low=0, high=2, step=1, init=1
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_i,2));
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg(REG,1665)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux(MUX,1666)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_s <= en;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux: PROCESS (ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_s, ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q, ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem(DUALMEM,1663)
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_inputreg_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_aa <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdreg_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ab <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_rdmux_q;
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0(REG,746)@12
reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_q <= ld_alignedZLow_uid206_cpix_uid44_fpTanPiTest_b_to_reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest(MULT,590)@13
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_pr <= UNSIGNED(prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_a) * UNSIGNED(prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b);
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_a <= (others => '0');
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b <= (others => '0');
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_a <= reg_alignedZLow_uid206_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_0_q;
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b <= reg_fxpSinRes_uid213_cpix_uid44_fpTanPiTest_0_to_prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_1_q;
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_q <= prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest(BITSELECT,591)@16
prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_in <= prodXY_uid591_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_q;
prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b <= prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_in(48 downto 23);
--normBit_uid215_cpix_uid44_fpTanPiTest(BITSELECT,214)@16
normBit_uid215_cpix_uid44_fpTanPiTest_in <= prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b;
normBit_uid215_cpix_uid44_fpTanPiTest_b <= normBit_uid215_cpix_uid44_fpTanPiTest_in(25 downto 25);
--rndExpUpdate_uid220_uid221_cpix_uid44_fpTanPiTest(BITJOIN,220)@16
rndExpUpdate_uid220_uid221_cpix_uid44_fpTanPiTest_q <= normBit_uid215_cpix_uid44_fpTanPiTest_b & cstAllZWF_uid53_spix_uid43_fpTanPiTest_q & VCC_q;
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor(LOGICAL,1544)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_b <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_q <= not (ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_a or ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_b);
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena(REG,1545)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_nor_q = "1") THEN
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd(LOGICAL,1546)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_a <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_sticky_ena_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_b <= en;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_a and ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_b;
--reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1(REG,748)@6
reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q <= r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem(DUALMEM,1535)
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ia <= reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_aa <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ab <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q;
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_ia
);
ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_iq(5 downto 0);
--biasM1_uid74_spix_uid43_fpTanPiTest(CONSTANT,73)
biasM1_uid74_spix_uid43_fpTanPiTest_q <= "01111110";
--expHardCase_uid207_cpix_uid44_fpTanPiTest(SUB,206)@15
expHardCase_uid207_cpix_uid44_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid74_spix_uid43_fpTanPiTest_q);
expHardCase_uid207_cpix_uid44_fpTanPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_mem_q);
expHardCase_uid207_cpix_uid44_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid207_cpix_uid44_fpTanPiTest_a) - UNSIGNED(expHardCase_uid207_cpix_uid44_fpTanPiTest_b));
expHardCase_uid207_cpix_uid44_fpTanPiTest_q <= expHardCase_uid207_cpix_uid44_fpTanPiTest_o(8 downto 0);
--expP_uid208_cpix_uid44_fpTanPiTest(BITSELECT,207)@15
expP_uid208_cpix_uid44_fpTanPiTest_in <= expHardCase_uid207_cpix_uid44_fpTanPiTest_q(7 downto 0);
expP_uid208_cpix_uid44_fpTanPiTest_b <= expP_uid208_cpix_uid44_fpTanPiTest_in(7 downto 0);
--reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1(REG,749)@15
reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1_q <= expP_uid208_cpix_uid44_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid216_cpix_uid44_fpTanPiTest(BITSELECT,215)@16
highRes_uid216_cpix_uid44_fpTanPiTest_in <= prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b(24 downto 0);
highRes_uid216_cpix_uid44_fpTanPiTest_b <= highRes_uid216_cpix_uid44_fpTanPiTest_in(24 downto 1);
--lowRes_uid217_cpix_uid44_fpTanPiTest(BITSELECT,216)@16
lowRes_uid217_cpix_uid44_fpTanPiTest_in <= prodXYTruncFR_uid592_mul2xSinRes_uid214_cpix_uid44_fpTanPiTest_b(23 downto 0);
lowRes_uid217_cpix_uid44_fpTanPiTest_b <= lowRes_uid217_cpix_uid44_fpTanPiTest_in(23 downto 0);
--fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest(MUX,217)@16
fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_s <= normBit_uid215_cpix_uid44_fpTanPiTest_b;
fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest: PROCESS (fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_s, en, lowRes_uid217_cpix_uid44_fpTanPiTest_b, highRes_uid216_cpix_uid44_fpTanPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_q <= lowRes_uid217_cpix_uid44_fpTanPiTest_b;
WHEN "1" => fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_q <= highRes_uid216_cpix_uid44_fpTanPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest(BITJOIN,218)@16
expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_q <= reg_expP_uid208_cpix_uid44_fpTanPiTest_0_to_expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_1_q & fracRCompPreRnd_uid218_cpix_uid44_fpTanPiTest_q;
--expFracComp_uid222_cpix_uid44_fpTanPiTest(ADD,221)@16
expFracComp_uid222_cpix_uid44_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid219_uid219_cpix_uid44_fpTanPiTest_q);
expFracComp_uid222_cpix_uid44_fpTanPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid220_uid221_cpix_uid44_fpTanPiTest_q);
expFracComp_uid222_cpix_uid44_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid222_cpix_uid44_fpTanPiTest_a) + UNSIGNED(expFracComp_uid222_cpix_uid44_fpTanPiTest_b));
expFracComp_uid222_cpix_uid44_fpTanPiTest_q <= expFracComp_uid222_cpix_uid44_fpTanPiTest_o(32 downto 0);
--expRComp_uid224_cpix_uid44_fpTanPiTest(BITSELECT,223)@16
expRComp_uid224_cpix_uid44_fpTanPiTest_in <= expFracComp_uid222_cpix_uid44_fpTanPiTest_q(31 downto 0);
expRComp_uid224_cpix_uid44_fpTanPiTest_b <= expRComp_uid224_cpix_uid44_fpTanPiTest_in(31 downto 24);
--fracXIsZero_uid65_spix_uid43_fpTanPiTest(LOGICAL,64)@0
fracXIsZero_uid65_spix_uid43_fpTanPiTest_a <= fracX_uid25_fpTanPiTest_b;
fracXIsZero_uid65_spix_uid43_fpTanPiTest_b <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
fracXIsZero_uid65_spix_uid43_fpTanPiTest_q <= "1" when fracXIsZero_uid65_spix_uid43_fpTanPiTest_a = fracXIsZero_uid65_spix_uid43_fpTanPiTest_b else "0";
--ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b(DELAY,803)@0
ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => fracXIsZero_uid65_spix_uid43_fpTanPiTest_q, xout => ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid67_spix_uid43_fpTanPiTest(LOGICAL,66)@2
InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_a <= ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b_q;
InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_q <= not InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_a;
--expXIsMax_uid63_spix_uid43_fpTanPiTest(LOGICAL,62)@0
expXIsMax_uid63_spix_uid43_fpTanPiTest_a <= exp_uid9_fpTanPiTest_b;
expXIsMax_uid63_spix_uid43_fpTanPiTest_b <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
expXIsMax_uid63_spix_uid43_fpTanPiTest_q <= "1" when expXIsMax_uid63_spix_uid43_fpTanPiTest_a = expXIsMax_uid63_spix_uid43_fpTanPiTest_b else "0";
--ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a(DELAY,802)@0
ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsMax_uid63_spix_uid43_fpTanPiTest_q, xout => ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_N_uid68_spix_uid43_fpTanPiTest(LOGICAL,67)@2
exc_N_uid68_spix_uid43_fpTanPiTest_a <= ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a_q;
exc_N_uid68_spix_uid43_fpTanPiTest_b <= InvFracXIsZero_uid67_spix_uid43_fpTanPiTest_q;
exc_N_uid68_spix_uid43_fpTanPiTest_q <= exc_N_uid68_spix_uid43_fpTanPiTest_a and exc_N_uid68_spix_uid43_fpTanPiTest_b;
--InvExc_N_uid69_spix_uid43_fpTanPiTest(LOGICAL,68)@2
InvExc_N_uid69_spix_uid43_fpTanPiTest_a <= exc_N_uid68_spix_uid43_fpTanPiTest_q;
InvExc_N_uid69_spix_uid43_fpTanPiTest_q <= not InvExc_N_uid69_spix_uid43_fpTanPiTest_a;
--exc_I_uid66_spix_uid43_fpTanPiTest(LOGICAL,65)@2
exc_I_uid66_spix_uid43_fpTanPiTest_a <= ld_expXIsMax_uid63_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_a_q;
exc_I_uid66_spix_uid43_fpTanPiTest_b <= ld_fracXIsZero_uid65_spix_uid43_fpTanPiTest_q_to_exc_I_uid66_spix_uid43_fpTanPiTest_b_q;
exc_I_uid66_spix_uid43_fpTanPiTest_q <= exc_I_uid66_spix_uid43_fpTanPiTest_a and exc_I_uid66_spix_uid43_fpTanPiTest_b;
--InvExc_I_uid70_spix_uid43_fpTanPiTest(LOGICAL,69)@2
InvExc_I_uid70_spix_uid43_fpTanPiTest_a <= exc_I_uid66_spix_uid43_fpTanPiTest_q;
InvExc_I_uid70_spix_uid43_fpTanPiTest_q <= not InvExc_I_uid70_spix_uid43_fpTanPiTest_a;
--expXIsZero_uid10_fpTanPiTest(LOGICAL,9)@0
expXIsZero_uid10_fpTanPiTest_a <= exp_uid9_fpTanPiTest_b;
expXIsZero_uid10_fpTanPiTest_b <= cstAllZWE_uid8_fpTanPiTest_q;
expXIsZero_uid10_fpTanPiTest_q <= "1" when expXIsZero_uid10_fpTanPiTest_a = expXIsZero_uid10_fpTanPiTest_b else "0";
--InvExpXIsZero_uid71_spix_uid43_fpTanPiTest(LOGICAL,70)@0
InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_a <= expXIsZero_uid10_fpTanPiTest_q;
InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q <= not InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_a;
--ld_InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q_to_exc_R_uid72_spix_uid43_fpTanPiTest_a(DELAY,810)@0
ld_InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q_to_exc_R_uid72_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q, xout => ld_InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q_to_exc_R_uid72_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_R_uid72_spix_uid43_fpTanPiTest(LOGICAL,71)@2
exc_R_uid72_spix_uid43_fpTanPiTest_a <= ld_InvExpXIsZero_uid71_spix_uid43_fpTanPiTest_q_to_exc_R_uid72_spix_uid43_fpTanPiTest_a_q;
exc_R_uid72_spix_uid43_fpTanPiTest_b <= InvExc_I_uid70_spix_uid43_fpTanPiTest_q;
exc_R_uid72_spix_uid43_fpTanPiTest_c <= InvExc_N_uid69_spix_uid43_fpTanPiTest_q;
exc_R_uid72_spix_uid43_fpTanPiTest_q <= exc_R_uid72_spix_uid43_fpTanPiTest_a and exc_R_uid72_spix_uid43_fpTanPiTest_b and exc_R_uid72_spix_uid43_fpTanPiTest_c;
--xIsHalf_uid231_cpix_uid44_fpTanPiTest(LOGICAL,230)@2
xIsHalf_uid231_cpix_uid44_fpTanPiTest_a <= exc_R_uid72_spix_uid43_fpTanPiTest_q;
xIsHalf_uid231_cpix_uid44_fpTanPiTest_b <= yIsZero_uid90_spix_uid43_fpTanPiTest_q;
xIsHalf_uid231_cpix_uid44_fpTanPiTest_c <= InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_q;
xIsHalf_uid231_cpix_uid44_fpTanPiTest_d <= InvXIntExp_uid131_spix_uid43_fpTanPiTest_q;
xIsHalf_uid231_cpix_uid44_fpTanPiTest_q <= xIsHalf_uid231_cpix_uid44_fpTanPiTest_a and xIsHalf_uid231_cpix_uid44_fpTanPiTest_b and xIsHalf_uid231_cpix_uid44_fpTanPiTest_c and xIsHalf_uid231_cpix_uid44_fpTanPiTest_d;
--ld_xIsHalf_uid231_cpix_uid44_fpTanPiTest_q_to_expRPostExc1_uid239_cpix_uid44_fpTanPiTest_b(DELAY,959)@2
ld_xIsHalf_uid231_cpix_uid44_fpTanPiTest_q_to_expRPostExc1_uid239_cpix_uid44_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid231_cpix_uid44_fpTanPiTest_q, xout => ld_xIsHalf_uid231_cpix_uid44_fpTanPiTest_q_to_expRPostExc1_uid239_cpix_uid44_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid239_cpix_uid44_fpTanPiTest(MUX,238)@16
expRPostExc1_uid239_cpix_uid44_fpTanPiTest_s <= ld_xIsHalf_uid231_cpix_uid44_fpTanPiTest_q_to_expRPostExc1_uid239_cpix_uid44_fpTanPiTest_b_q;
expRPostExc1_uid239_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid239_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q <= expRComp_uid224_cpix_uid44_fpTanPiTest_b;
WHEN "1" => expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q <= cstAllZWE_uid8_fpTanPiTest_q;
WHEN OTHERS => expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor(LOGICAL,1556)
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_b <= ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_q <= not (ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_a or ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_b);
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_mem_top(CONSTANT,1528)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp(LOGICAL,1529)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_a <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_mem_top_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q);
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_q <= "1" when ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_a = ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_b else "0";
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg(REG,1530)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena(REG,1557)
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_nor_q = "1") THEN
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd(LOGICAL,1558)
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_a <= ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_sticky_ena_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_b <= en;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_q <= ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_a and ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_b;
--ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b(DELAY,877)@0
ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid10_fpTanPiTest_q, xout => ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid193_cpix_uid44_fpTanPiTest(LOGICAL,192)@2
fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_a <= reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q;
fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_b <= STD_LOGIC_VECTOR("0" & ozz_uid88_spix_uid43_fpTanPiTest_q);
fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_q <= "1" when fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_a = fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_b else "0";
--fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest(LOGICAL,225)@2
fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_a <= fxpXFracZero_uid193_cpix_uid44_fpTanPiTest_q;
fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_b <= InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_q;
fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_q <= fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_a and fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_b;
--evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest(LOGICAL,226)@2
evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_a <= ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a_q;
evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_b <= fracZCosNotOne_uid226_cpix_uid44_fpTanPiTest_q;
evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_q <= evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_a or evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_b;
--xIsInt_uid228_cpix_uid44_fpTanPiTest(LOGICAL,227)@2
xIsInt_uid228_cpix_uid44_fpTanPiTest_a <= exc_R_uid72_spix_uid43_fpTanPiTest_q;
xIsInt_uid228_cpix_uid44_fpTanPiTest_b <= evenIntCosNotOneFZ_uid227_cpix_uid44_fpTanPiTest_q;
xIsInt_uid228_cpix_uid44_fpTanPiTest_q <= xIsInt_uid228_cpix_uid44_fpTanPiTest_a and xIsInt_uid228_cpix_uid44_fpTanPiTest_b;
--xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest(LOGICAL,240)@2
xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_a <= xIsInt_uid228_cpix_uid44_fpTanPiTest_q;
xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_b <= ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b_q;
xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_c <= ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a_q;
xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_q <= xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_a or xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_b or xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_c;
--excRNaN_uid232_cpix_uid44_fpTanPiTest(LOGICAL,231)@2
excRNaN_uid232_cpix_uid44_fpTanPiTest_a <= exc_N_uid68_spix_uid43_fpTanPiTest_q;
excRNaN_uid232_cpix_uid44_fpTanPiTest_b <= exc_I_uid66_spix_uid43_fpTanPiTest_q;
excRNaN_uid232_cpix_uid44_fpTanPiTest_q <= excRNaN_uid232_cpix_uid44_fpTanPiTest_a or excRNaN_uid232_cpix_uid44_fpTanPiTest_b;
--rInfOrNaN_uid240_cpix_uid44_fpTanPiTest(LOGICAL,239)@2
rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_a <= GND_q;
rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_b <= excRNaN_uid232_cpix_uid44_fpTanPiTest_q;
rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_q <= rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_a or rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_b;
--join_uid242_cpix_uid44_fpTanPiTest(BITJOIN,241)@2
join_uid242_cpix_uid44_fpTanPiTest_q <= xIntOrXZOrCosOne_uid241_cpix_uid44_fpTanPiTest_q & rInfOrNaN_uid240_cpix_uid44_fpTanPiTest_q;
--reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1(REG,751)@2
reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q <= join_uid242_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt(COUNTER,1524)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg(REG,1525)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux(MUX,1526)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_s, ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q, ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem(DUALMEM,1547)
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ia <= reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_aa <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ab <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q;
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_ia
);
ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_q <= ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid243_cpix_uid44_fpTanPiTest(MUX,242)@17
expRPostExc_uid243_cpix_uid44_fpTanPiTest_s <= ld_reg_join_uid242_cpix_uid44_fpTanPiTest_0_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_1_q_to_expRPostExc_uid243_cpix_uid44_fpTanPiTest_b_replace_mem_q;
expRPostExc_uid243_cpix_uid44_fpTanPiTest: PROCESS (expRPostExc_uid243_cpix_uid44_fpTanPiTest_s, en, expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q, cstAllOWE_uid52_spix_uid43_fpTanPiTest_q, cstBias_uid54_spix_uid43_fpTanPiTest_q, cstBias_uid54_spix_uid43_fpTanPiTest_q)
BEGIN
CASE expRPostExc_uid243_cpix_uid44_fpTanPiTest_s IS
WHEN "00" => expRPostExc_uid243_cpix_uid44_fpTanPiTest_q <= expRPostExc1_uid239_cpix_uid44_fpTanPiTest_q;
WHEN "01" => expRPostExc_uid243_cpix_uid44_fpTanPiTest_q <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
WHEN "10" => expRPostExc_uid243_cpix_uid44_fpTanPiTest_q <= cstBias_uid54_spix_uid43_fpTanPiTest_q;
WHEN "11" => expRPostExc_uid243_cpix_uid44_fpTanPiTest_q <= cstBias_uid54_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => expRPostExc_uid243_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest(CONSTANT,136)
oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q <= "00000000000000000000001";
--fracRComp_uid223_cpix_uid44_fpTanPiTest(BITSELECT,222)@16
fracRComp_uid223_cpix_uid44_fpTanPiTest_in <= expFracComp_uid222_cpix_uid44_fpTanPiTest_q(23 downto 0);
fracRComp_uid223_cpix_uid44_fpTanPiTest_b <= fracRComp_uid223_cpix_uid44_fpTanPiTest_in(23 downto 1);
--reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5(REG,720)@2
reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5_q <= xIsHalf_uid231_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4(REG,719)@2
reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4_q <= ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3(REG,718)@2
reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3_q <= yIsZero_uid90_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2(REG,717)@2
reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2_q <= xIsInt_uid228_cpix_uid44_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1(REG,716)@2
reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1_q <= ld_tanXIsX_uid28_fpTanPiTest_c_to_InvCosXIsOne_uid225_cpix_uid44_fpTanPiTest_a_q;
END IF;
END IF;
END PROCESS;
--bigCond_uid233_cpix_uid44_fpTanPiTest(LOGICAL,232)@3
bigCond_uid233_cpix_uid44_fpTanPiTest_a <= reg_tanXIsX_uid28_fpTanPiTest_1_to_bigCond_uid233_cpix_uid44_fpTanPiTest_1_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_b <= reg_xIsInt_uid228_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_2_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_c <= reg_yIsZero_uid90_spix_uid43_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_3_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_d <= reg_expXIsZero_uid10_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_4_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_f <= reg_xIsHalf_uid231_cpix_uid44_fpTanPiTest_0_to_bigCond_uid233_cpix_uid44_fpTanPiTest_5_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_g <= GND_q;
bigCond_uid233_cpix_uid44_fpTanPiTest_q <= bigCond_uid233_cpix_uid44_fpTanPiTest_a or bigCond_uid233_cpix_uid44_fpTanPiTest_b or bigCond_uid233_cpix_uid44_fpTanPiTest_c or bigCond_uid233_cpix_uid44_fpTanPiTest_d or bigCond_uid233_cpix_uid44_fpTanPiTest_f or bigCond_uid233_cpix_uid44_fpTanPiTest_g;
--ld_bigCond_uid233_cpix_uid44_fpTanPiTest_q_to_fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_b(DELAY,955)@3
ld_bigCond_uid233_cpix_uid44_fpTanPiTest_q_to_fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid233_cpix_uid44_fpTanPiTest_q, xout => ld_bigCond_uid233_cpix_uid44_fpTanPiTest_q_to_fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid234_cpix_uid44_fpTanPiTest(MUX,233)@16
fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_s <= ld_bigCond_uid233_cpix_uid44_fpTanPiTest_q_to_fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_b_q;
fracRPostExc1_uid234_cpix_uid44_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q <= fracRComp_uid223_cpix_uid44_fpTanPiTest_b;
WHEN "1" => fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid232_cpix_uid44_fpTanPiTest_q_to_reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_a(DELAY,1416)@2
ld_excRNaN_uid232_cpix_uid44_fpTanPiTest_q_to_reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => excRNaN_uid232_cpix_uid44_fpTanPiTest_q, xout => ld_excRNaN_uid232_cpix_uid44_fpTanPiTest_q_to_reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1(REG,750)@16
reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_q <= ld_excRNaN_uid232_cpix_uid44_fpTanPiTest_q_to_reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid236_cpix_uid44_fpTanPiTest(MUX,235)@17
fracRPostExc_uid236_cpix_uid44_fpTanPiTest_s <= reg_excRNaN_uid232_cpix_uid44_fpTanPiTest_0_to_fracRPostExc_uid236_cpix_uid44_fpTanPiTest_1_q;
fracRPostExc_uid236_cpix_uid44_fpTanPiTest: PROCESS (fracRPostExc_uid236_cpix_uid44_fpTanPiTest_s, en, fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q, oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q)
BEGIN
CASE fracRPostExc_uid236_cpix_uid44_fpTanPiTest_s IS
WHEN "0" => fracRPostExc_uid236_cpix_uid44_fpTanPiTest_q <= fracRPostExc1_uid234_cpix_uid44_fpTanPiTest_q;
WHEN "1" => fracRPostExc_uid236_cpix_uid44_fpTanPiTest_q <= oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => fracRPostExc_uid236_cpix_uid44_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid250_cpix_uid44_fpTanPiTest(BITJOIN,249)@17
R_uid250_cpix_uid44_fpTanPiTest_q <= ld_signR_uid249_cpix_uid44_fpTanPiTest_q_to_R_uid250_cpix_uid44_fpTanPiTest_c_q & expRPostExc_uid243_cpix_uid44_fpTanPiTest_q & fracRPostExc_uid236_cpix_uid44_fpTanPiTest_q;
--fracY_uid259_tpix_uid45_fpTanPiTest(BITSELECT,258)@17
fracY_uid259_tpix_uid45_fpTanPiTest_in <= R_uid250_cpix_uid44_fpTanPiTest_q(22 downto 0);
fracY_uid259_tpix_uid45_fpTanPiTest_b <= fracY_uid259_tpix_uid45_fpTanPiTest_in(22 downto 0);
--fracXIsZero_uid286_tpix_uid45_fpTanPiTest(LOGICAL,285)@17
fracXIsZero_uid286_tpix_uid45_fpTanPiTest_a <= fracY_uid259_tpix_uid45_fpTanPiTest_b;
fracXIsZero_uid286_tpix_uid45_fpTanPiTest_b <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
fracXIsZero_uid286_tpix_uid45_fpTanPiTest_q <= "1" when fracXIsZero_uid286_tpix_uid45_fpTanPiTest_a = fracXIsZero_uid286_tpix_uid45_fpTanPiTest_b else "0";
--expY_uid258_tpix_uid45_fpTanPiTest(BITSELECT,257)@17
expY_uid258_tpix_uid45_fpTanPiTest_in <= R_uid250_cpix_uid44_fpTanPiTest_q(30 downto 0);
expY_uid258_tpix_uid45_fpTanPiTest_b <= expY_uid258_tpix_uid45_fpTanPiTest_in(30 downto 23);
--expXIsMax_uid284_tpix_uid45_fpTanPiTest(LOGICAL,283)@17
expXIsMax_uid284_tpix_uid45_fpTanPiTest_a <= expY_uid258_tpix_uid45_fpTanPiTest_b;
expXIsMax_uid284_tpix_uid45_fpTanPiTest_b <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
expXIsMax_uid284_tpix_uid45_fpTanPiTest_q <= "1" when expXIsMax_uid284_tpix_uid45_fpTanPiTest_a = expXIsMax_uid284_tpix_uid45_fpTanPiTest_b else "0";
--exc_I_uid287_tpix_uid45_fpTanPiTest(LOGICAL,286)@17
exc_I_uid287_tpix_uid45_fpTanPiTest_a <= expXIsMax_uid284_tpix_uid45_fpTanPiTest_q;
exc_I_uid287_tpix_uid45_fpTanPiTest_b <= fracXIsZero_uid286_tpix_uid45_fpTanPiTest_q;
exc_I_uid287_tpix_uid45_fpTanPiTest_q <= exc_I_uid287_tpix_uid45_fpTanPiTest_a and exc_I_uid287_tpix_uid45_fpTanPiTest_b;
--ld_intXParity_uid85_spix_uid43_fpTanPiTest_b_to_signComp_uid148_spix_uid43_fpTanPiTest_c(DELAY,898)@1
ld_intXParity_uid85_spix_uid43_fpTanPiTest_b_to_signComp_uid148_spix_uid43_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid85_spix_uid43_fpTanPiTest_b, xout => ld_intXParity_uid85_spix_uid43_fpTanPiTest_b_to_signComp_uid148_spix_uid43_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--xFrac_uid75_spix_uid43_fpTanPiTest(COMPARE,74)@0
xFrac_uid75_spix_uid43_fpTanPiTest_cin <= GND_q;
xFrac_uid75_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid74_spix_uid43_fpTanPiTest_q) & '0';
xFrac_uid75_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpTanPiTest_b) & xFrac_uid75_spix_uid43_fpTanPiTest_cin(0);
xFrac_uid75_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid75_spix_uid43_fpTanPiTest_a) - UNSIGNED(xFrac_uid75_spix_uid43_fpTanPiTest_b));
xFrac_uid75_spix_uid43_fpTanPiTest_n(0) <= not xFrac_uid75_spix_uid43_fpTanPiTest_o(10);
--ld_xFrac_uid75_spix_uid43_fpTanPiTest_n_to_InvXFrac_uid146_spix_uid43_fpTanPiTest_a(DELAY,894)@0
ld_xFrac_uid75_spix_uid43_fpTanPiTest_n_to_InvXFrac_uid146_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xFrac_uid75_spix_uid43_fpTanPiTest_n, xout => ld_xFrac_uid75_spix_uid43_fpTanPiTest_n_to_InvXFrac_uid146_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid146_spix_uid43_fpTanPiTest(LOGICAL,145)@2
InvXFrac_uid146_spix_uid43_fpTanPiTest_a <= ld_xFrac_uid75_spix_uid43_fpTanPiTest_n_to_InvXFrac_uid146_spix_uid43_fpTanPiTest_a_q;
InvXFrac_uid146_spix_uid43_fpTanPiTest_q <= not InvXFrac_uid146_spix_uid43_fpTanPiTest_a;
--biasMwShift_uid76_spix_uid43_fpTanPiTest(CONSTANT,75)
biasMwShift_uid76_spix_uid43_fpTanPiTest_q <= "01110011";
--sinXIsX_uid77_spix_uid43_fpTanPiTest(COMPARE,76)@0
sinXIsX_uid77_spix_uid43_fpTanPiTest_cin <= GND_q;
sinXIsX_uid77_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("00" & exp_uid9_fpTanPiTest_b) & '0';
sinXIsX_uid77_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid76_spix_uid43_fpTanPiTest_q) & sinXIsX_uid77_spix_uid43_fpTanPiTest_cin(0);
sinXIsX_uid77_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid77_spix_uid43_fpTanPiTest_a) - UNSIGNED(sinXIsX_uid77_spix_uid43_fpTanPiTest_b));
sinXIsX_uid77_spix_uid43_fpTanPiTest_c(0) <= sinXIsX_uid77_spix_uid43_fpTanPiTest_o(10);
--ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a(DELAY,864)@0
ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsX_uid77_spix_uid43_fpTanPiTest_c, xout => ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_spix_uid43_fpTanPiTest(LOGICAL,126)@2
InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a <= ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a_q;
InvSinXIsX_uid127_spix_uid43_fpTanPiTest_q <= not InvSinXIsX_uid127_spix_uid43_fpTanPiTest_a;
--yIsZero_uid87_spix_uid43_fpTanPiTest(LOGICAL,86)@2
yIsZero_uid87_spix_uid43_fpTanPiTest_a <= reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q;
yIsZero_uid87_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid87_spix_uid43_fpTanPiTest_q <= "1" when yIsZero_uid87_spix_uid43_fpTanPiTest_a = yIsZero_uid87_spix_uid43_fpTanPiTest_b else "0";
--yZSinXNX_uid128_spix_uid43_fpTanPiTest(LOGICAL,127)@2
yZSinXNX_uid128_spix_uid43_fpTanPiTest_a <= yIsZero_uid87_spix_uid43_fpTanPiTest_q;
yZSinXNX_uid128_spix_uid43_fpTanPiTest_b <= InvSinXIsX_uid127_spix_uid43_fpTanPiTest_q;
yZSinXNX_uid128_spix_uid43_fpTanPiTest_q <= yZSinXNX_uid128_spix_uid43_fpTanPiTest_a and yZSinXNX_uid128_spix_uid43_fpTanPiTest_b;
--xIntYz_uid129_spix_uid43_fpTanPiTest(LOGICAL,128)@2
xIntYz_uid129_spix_uid43_fpTanPiTest_a <= ld_xIntExp_uid73_spix_uid43_fpTanPiTest_c_to_xIntYz_uid129_spix_uid43_fpTanPiTest_a_q;
xIntYz_uid129_spix_uid43_fpTanPiTest_b <= yZSinXNX_uid128_spix_uid43_fpTanPiTest_q;
xIntYz_uid129_spix_uid43_fpTanPiTest_q <= xIntYz_uid129_spix_uid43_fpTanPiTest_a or xIntYz_uid129_spix_uid43_fpTanPiTest_b;
--xIsInt_uid130_spix_uid43_fpTanPiTest(LOGICAL,129)@2
xIsInt_uid130_spix_uid43_fpTanPiTest_a <= exc_R_uid72_spix_uid43_fpTanPiTest_q;
xIsInt_uid130_spix_uid43_fpTanPiTest_b <= xIntYz_uid129_spix_uid43_fpTanPiTest_q;
xIsInt_uid130_spix_uid43_fpTanPiTest_q <= xIsInt_uid130_spix_uid43_fpTanPiTest_a and xIsInt_uid130_spix_uid43_fpTanPiTest_b;
--InvXIsInt_uid147_spix_uid43_fpTanPiTest(LOGICAL,146)@2
InvXIsInt_uid147_spix_uid43_fpTanPiTest_a <= xIsInt_uid130_spix_uid43_fpTanPiTest_q;
InvXIsInt_uid147_spix_uid43_fpTanPiTest_q <= not InvXIsInt_uid147_spix_uid43_fpTanPiTest_a;
--signComp_uid148_spix_uid43_fpTanPiTest(LOGICAL,147)@2
signComp_uid148_spix_uid43_fpTanPiTest_a <= InvXIsInt_uid147_spix_uid43_fpTanPiTest_q;
signComp_uid148_spix_uid43_fpTanPiTest_b <= InvXFrac_uid146_spix_uid43_fpTanPiTest_q;
signComp_uid148_spix_uid43_fpTanPiTest_c <= ld_intXParity_uid85_spix_uid43_fpTanPiTest_b_to_signComp_uid148_spix_uid43_fpTanPiTest_c_q;
signComp_uid148_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid148_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signComp_uid148_spix_uid43_fpTanPiTest_q <= signComp_uid148_spix_uid43_fpTanPiTest_a and signComp_uid148_spix_uid43_fpTanPiTest_b and signComp_uid148_spix_uid43_fpTanPiTest_c;
END IF;
END PROCESS;
--InvYIsZero_uid149_spix_uid43_fpTanPiTest(LOGICAL,148)@2
InvYIsZero_uid149_spix_uid43_fpTanPiTest_a <= yIsZero_uid87_spix_uid43_fpTanPiTest_q;
InvYIsZero_uid149_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid149_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvYIsZero_uid149_spix_uid43_fpTanPiTest_q <= not InvYIsZero_uid149_spix_uid43_fpTanPiTest_a;
END IF;
END PROCESS;
--yZSC_uid150_spix_uid43_fpTanPiTest(LOGICAL,149)@3
yZSC_uid150_spix_uid43_fpTanPiTest_a <= InvYIsZero_uid149_spix_uid43_fpTanPiTest_q;
yZSC_uid150_spix_uid43_fpTanPiTest_b <= signComp_uid148_spix_uid43_fpTanPiTest_q;
yZSC_uid150_spix_uid43_fpTanPiTest_q <= yZSC_uid150_spix_uid43_fpTanPiTest_a and yZSC_uid150_spix_uid43_fpTanPiTest_b;
--ld_signX_uid26_fpTanPiTest_b_to_signR_uid151_spix_uid43_fpTanPiTest_a(DELAY,902)@0
ld_signX_uid26_fpTanPiTest_b_to_signR_uid151_spix_uid43_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => signX_uid26_fpTanPiTest_b, xout => ld_signX_uid26_fpTanPiTest_b_to_signR_uid151_spix_uid43_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid151_spix_uid43_fpTanPiTest(LOGICAL,150)@3
signR_uid151_spix_uid43_fpTanPiTest_a <= ld_signX_uid26_fpTanPiTest_b_to_signR_uid151_spix_uid43_fpTanPiTest_a_q;
signR_uid151_spix_uid43_fpTanPiTest_b <= yZSC_uid150_spix_uid43_fpTanPiTest_q;
signR_uid151_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid151_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid151_spix_uid43_fpTanPiTest_q <= signR_uid151_spix_uid43_fpTanPiTest_a xor signR_uid151_spix_uid43_fpTanPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid151_spix_uid43_fpTanPiTest_q_to_R_uid152_spix_uid43_fpTanPiTest_c(DELAY,906)@4
ld_signR_uid151_spix_uid43_fpTanPiTest_q_to_R_uid152_spix_uid43_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid151_spix_uid43_fpTanPiTest_q, xout => ld_signR_uid151_spix_uid43_fpTanPiTest_q_to_R_uid152_spix_uid43_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--piwFP2_uid114_spix_uid43_fpTanPiTest(CONSTANT,113)
piwFP2_uid114_spix_uid43_fpTanPiTest_q <= "1100100100001111110110101";
--cOne_uid91_spix_uid43_fpTanPiTest(CONSTANT,90)
cOne_uid91_spix_uid43_fpTanPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid92_spix_uid43_fpTanPiTest(SUB,91)@2
oneMinusY_uid92_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid91_spix_uid43_fpTanPiTest_q);
oneMinusY_uid92_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid86_spix_uid43_fpTanPiTest_0_to_yIsZero_uid90_spix_uid43_fpTanPiTest_1_q);
oneMinusY_uid92_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid92_spix_uid43_fpTanPiTest_a) - UNSIGNED(oneMinusY_uid92_spix_uid43_fpTanPiTest_b));
oneMinusY_uid92_spix_uid43_fpTanPiTest_q <= oneMinusY_uid92_spix_uid43_fpTanPiTest_o(37 downto 0);
--oMyBottom_uid94_spix_uid43_fpTanPiTest(BITSELECT,93)@2
oMyBottom_uid94_spix_uid43_fpTanPiTest_in <= oneMinusY_uid92_spix_uid43_fpTanPiTest_q(34 downto 0);
oMyBottom_uid94_spix_uid43_fpTanPiTest_b <= oMyBottom_uid94_spix_uid43_fpTanPiTest_in(34 downto 0);
--ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d(DELAY,831)@2
ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => oMyBottom_uid94_spix_uid43_fpTanPiTest_b, xout => ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid95_spix_uid43_fpTanPiTest(BITSELECT,94)@1
yBottom_uid95_spix_uid43_fpTanPiTest_in <= y_uid86_spix_uid43_fpTanPiTest_b(34 downto 0);
yBottom_uid95_spix_uid43_fpTanPiTest_b <= yBottom_uid95_spix_uid43_fpTanPiTest_in(34 downto 0);
--ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c(DELAY,830)@1
ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid95_spix_uid43_fpTanPiTest_b, xout => ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid86_spix_uid43_fpTanPiTest_b_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b(DELAY,826)@1
ld_y_uid86_spix_uid43_fpTanPiTest_b_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid86_spix_uid43_fpTanPiTest_b, xout => ld_y_uid86_spix_uid43_fpTanPiTest_b_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0(REG,685)@2
reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0_q <= oneMinusY_uid92_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest(COMPARE,92)@3
cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_cin <= GND_q;
cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid92_spix_uid43_fpTanPiTest_0_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_0_q) & '0';
cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid86_spix_uid43_fpTanPiTest_b_to_cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b_q) & cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_cin(0);
cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_b));
cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_c(0) <= cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_o(40);
--z_uid96_spix_uid43_fpTanPiTest(MUX,95)@3
z_uid96_spix_uid43_fpTanPiTest_s <= cmpYToOneMinusY_uid93_spix_uid43_fpTanPiTest_c;
z_uid96_spix_uid43_fpTanPiTest: PROCESS (z_uid96_spix_uid43_fpTanPiTest_s, en, ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c_q, ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d_q)
BEGIN
CASE z_uid96_spix_uid43_fpTanPiTest_s IS
WHEN "0" => z_uid96_spix_uid43_fpTanPiTest_q <= ld_yBottom_uid95_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_c_q;
WHEN "1" => z_uid96_spix_uid43_fpTanPiTest_q <= ld_oMyBottom_uid94_spix_uid43_fpTanPiTest_b_to_z_uid96_spix_uid43_fpTanPiTest_d_q;
WHEN OTHERS => z_uid96_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid110_spix_uid43_fpTanPiTest(BITSELECT,109)@3
zAddr_uid110_spix_uid43_fpTanPiTest_in <= z_uid96_spix_uid43_fpTanPiTest_q;
zAddr_uid110_spix_uid43_fpTanPiTest_b <= zAddr_uid110_spix_uid43_fpTanPiTest_in(34 downto 28);
--reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0(REG,705)@3
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0_q <= zAddr_uid110_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sinPiZTableGenerator(LOOKUP,457)@4
memoryC2_uid458_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid458_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid458_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid458_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid458_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid458_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid458_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid458_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid111_spix_uid43_fpTanPiTest(BITSELECT,110)@3
zPPolyEval_uid111_spix_uid43_fpTanPiTest_in <= z_uid96_spix_uid43_fpTanPiTest_q(27 downto 0);
zPPolyEval_uid111_spix_uid43_fpTanPiTest_b <= zPPolyEval_uid111_spix_uid43_fpTanPiTest_in(27 downto 12);
--yT1_uid459_sinPiZPolyEval(BITSELECT,458)@3
yT1_uid459_sinPiZPolyEval_in <= zPPolyEval_uid111_spix_uid43_fpTanPiTest_b;
yT1_uid459_sinPiZPolyEval_b <= yT1_uid459_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid459_sinPiZPolyEval_b_to_reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_a(DELAY,1372)@3
ld_yT1_uid459_sinPiZPolyEval_b_to_reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid459_sinPiZPolyEval_b, xout => ld_yT1_uid459_sinPiZPolyEval_b_to_reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0(REG,706)@4
reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_q <= ld_yT1_uid459_sinPiZPolyEval_b_to_reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid613_pT1_uid460_sinPiZPolyEval(MULT,612)@5
prodXY_uid613_pT1_uid460_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid613_pT1_uid460_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid613_pT1_uid460_sinPiZPolyEval_b);
prodXY_uid613_pT1_uid460_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid613_pT1_uid460_sinPiZPolyEval_a <= (others => '0');
prodXY_uid613_pT1_uid460_sinPiZPolyEval_b <= (others => '0');
prodXY_uid613_pT1_uid460_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid613_pT1_uid460_sinPiZPolyEval_a <= reg_yT1_uid459_sinPiZPolyEval_0_to_prodXY_uid613_pT1_uid460_sinPiZPolyEval_0_q;
prodXY_uid613_pT1_uid460_sinPiZPolyEval_b <= memoryC2_uid458_sinPiZTableGenerator_q;
prodXY_uid613_pT1_uid460_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid613_pT1_uid460_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid613_pT1_uid460_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid613_pT1_uid460_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid613_pT1_uid460_sinPiZPolyEval_q <= prodXY_uid613_pT1_uid460_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval(BITSELECT,613)@8
prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_in <= prodXY_uid613_pT1_uid460_sinPiZPolyEval_q;
prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_b <= prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid462_sinPiZPolyEval(BITSELECT,461)@8
highBBits_uid462_sinPiZPolyEval_in <= prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_b;
highBBits_uid462_sinPiZPolyEval_b <= highBBits_uid462_sinPiZPolyEval_in(14 downto 1);
--ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_inputreg(DELAY,1660)
ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => zAddr_uid110_spix_uid43_fpTanPiTest_b, xout => ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a(DELAY,1373)@3
ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_inputreg_q, xout => ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0(REG,707)@7
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_q <= ld_zAddr_uid110_spix_uid43_fpTanPiTest_b_to_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sinPiZTableGenerator(LOOKUP,456)@8
memoryC1_uid457_sinPiZTableGenerator: PROCESS (reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC1_uid457_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC1_uid457_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid457_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid457_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid457_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid457_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid457_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid457_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid457_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid457_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid457_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid457_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid457_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid457_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid457_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid457_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid457_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid457_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid457_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid457_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid457_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid457_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid457_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid457_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid457_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid457_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid457_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid457_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid457_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid457_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid457_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid457_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid457_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid457_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid457_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid457_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid457_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid457_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid457_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid457_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid457_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid457_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid457_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid457_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid457_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid457_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid457_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid457_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid457_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid457_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid457_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid457_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid457_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid457_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid457_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid457_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid457_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid457_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid457_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid457_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid457_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid457_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid457_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid457_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid457_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid457_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid457_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid457_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid457_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid457_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid457_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid457_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid457_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid457_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid457_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid457_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid457_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid457_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid457_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid457_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid457_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid457_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid457_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid457_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid457_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid457_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid457_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid457_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid457_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid457_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid457_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid457_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid457_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid457_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid463_sinPiZPolyEval(ADD,462)@8
sumAHighB_uid463_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sinPiZTableGenerator_q(20)) & memoryC1_uid457_sinPiZTableGenerator_q);
sumAHighB_uid463_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid462_sinPiZPolyEval_b(13)) & highBBits_uid462_sinPiZPolyEval_b);
sumAHighB_uid463_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid463_sinPiZPolyEval_b));
sumAHighB_uid463_sinPiZPolyEval_q <= sumAHighB_uid463_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid461_sinPiZPolyEval(BITSELECT,460)@8
lowRangeB_uid461_sinPiZPolyEval_in <= prodXYTruncFR_uid614_pT1_uid460_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid461_sinPiZPolyEval_b <= lowRangeB_uid461_sinPiZPolyEval_in(0 downto 0);
--s1_uid461_uid464_sinPiZPolyEval(BITJOIN,463)@8
s1_uid461_uid464_sinPiZPolyEval_q <= sumAHighB_uid463_sinPiZPolyEval_q & lowRangeB_uid461_sinPiZPolyEval_b;
--reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1(REG,709)@8
reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1_q <= s1_uid461_uid464_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor(LOGICAL,1619)
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena(REG,1620)
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd(LOGICAL,1621)
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0(REG,708)@3
reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q <= zPPolyEval_uid111_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem(DUALMEM,1610)
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ia <= reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_aa <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ab <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 4,
width_b => 16,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid616_pT2_uid466_sinPiZPolyEval(MULT,615)@9
prodXY_uid616_pT2_uid466_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid616_pT2_uid466_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid616_pT2_uid466_sinPiZPolyEval_b);
prodXY_uid616_pT2_uid466_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid616_pT2_uid466_sinPiZPolyEval_a <= (others => '0');
prodXY_uid616_pT2_uid466_sinPiZPolyEval_b <= (others => '0');
prodXY_uid616_pT2_uid466_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid616_pT2_uid466_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid111_spix_uid43_fpTanPiTest_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_0_q_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid616_pT2_uid466_sinPiZPolyEval_b <= reg_s1_uid461_uid464_sinPiZPolyEval_0_to_prodXY_uid616_pT2_uid466_sinPiZPolyEval_1_q;
prodXY_uid616_pT2_uid466_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid616_pT2_uid466_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid616_pT2_uid466_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid616_pT2_uid466_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid616_pT2_uid466_sinPiZPolyEval_q <= prodXY_uid616_pT2_uid466_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval(BITSELECT,616)@12
prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_in <= prodXY_uid616_pT2_uid466_sinPiZPolyEval_q;
prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_b <= prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid468_sinPiZPolyEval(BITSELECT,467)@12
highBBits_uid468_sinPiZPolyEval_in <= prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_b;
highBBits_uid468_sinPiZPolyEval_b <= highBBits_uid468_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor(LOGICAL,1593)
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena(REG,1594)
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd(LOGICAL,1595)
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem(DUALMEM,1584)
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC2_uid458_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid540_lzcZ_uid204_cpix_uid44_fpTanPiTest_0_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_1_q_to_expHardCase_uid207_cpix_uid44_fpTanPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid456_sinPiZTableGenerator(LOOKUP,455)@12
memoryC0_uid456_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid110_spix_uid43_fpTanPiTest_0_to_memoryC0_uid456_sinPiZTableGenerator_0_q_to_memoryC0_uid456_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid456_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid456_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid469_sinPiZPolyEval(ADD,468)@12
sumAHighB_uid469_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sinPiZTableGenerator_q(28)) & memoryC0_uid456_sinPiZTableGenerator_q);
sumAHighB_uid469_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sinPiZPolyEval_b(21)) & highBBits_uid468_sinPiZPolyEval_b);
sumAHighB_uid469_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid469_sinPiZPolyEval_b));
sumAHighB_uid469_sinPiZPolyEval_q <= sumAHighB_uid469_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid467_sinPiZPolyEval(BITSELECT,466)@12
lowRangeB_uid467_sinPiZPolyEval_in <= prodXYTruncFR_uid617_pT2_uid466_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid467_sinPiZPolyEval_b <= lowRangeB_uid467_sinPiZPolyEval_in(1 downto 0);
--s2_uid467_uid470_sinPiZPolyEval(BITJOIN,469)@12
s2_uid467_uid470_sinPiZPolyEval_q <= sumAHighB_uid469_sinPiZPolyEval_q & lowRangeB_uid467_sinPiZPolyEval_b;
--fxpSinRes_uid113_spix_uid43_fpTanPiTest(BITSELECT,112)@12
fxpSinRes_uid113_spix_uid43_fpTanPiTest_in <= s2_uid467_uid470_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid113_spix_uid43_fpTanPiTest_b <= fxpSinRes_uid113_spix_uid43_fpTanPiTest_in(29 downto 5);
--ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_multRightOp_uid115_spix_uid43_fpTanPiTest_b(DELAY,847)@0
ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_multRightOp_uid115_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid77_spix_uid43_fpTanPiTest_c, xout => ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_multRightOp_uid115_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid115_spix_uid43_fpTanPiTest(MUX,114)@12
multRightOp_uid115_spix_uid43_fpTanPiTest_s <= ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_multRightOp_uid115_spix_uid43_fpTanPiTest_b_q;
multRightOp_uid115_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid115_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid115_spix_uid43_fpTanPiTest_s IS
WHEN "0" => multRightOp_uid115_spix_uid43_fpTanPiTest_q <= fxpSinRes_uid113_spix_uid43_fpTanPiTest_b;
WHEN "1" => multRightOp_uid115_spix_uid43_fpTanPiTest_q <= piwFP2_uid114_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => multRightOp_uid115_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor(LOGICAL,1507)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_b <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_q <= not (ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_a or ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_b);
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena(REG,1508)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_nor_q = "1") THEN
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd(LOGICAL,1509)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_a <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_sticky_ena_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_b <= en;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_a and ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_b;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor(LOGICAL,1483)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_b <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_q <= not (ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_a or ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_b);
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_mem_top(CONSTANT,1479)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_mem_top_q <= "0101";
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp(LOGICAL,1480)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_a <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_mem_top_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q);
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_q <= "1" when ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_a = ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_b else "0";
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg(REG,1481)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena(REG,1484)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_nor_q = "1") THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd(LOGICAL,1485)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_a <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_sticky_ena_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_b <= en;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_a and ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_b;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt(COUNTER,1475)
-- every=1, low=0, high=5, step=1, init=1
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i = 4 THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i - 5;
ELSE
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_i,3));
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg(REG,1476)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux(MUX,1477)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_s, ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q, ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem(DUALMEM,1474)
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ia <= oFracX_uid27_uid27_fpTanPiTest_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_aa <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ab <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q;
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 3,
numwords_a => 6,
width_b => 24,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_ia
);
ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_iq(23 downto 0);
--LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,450)@7
LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid452_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,451)@7
leftShiftStage2Idx3_uid452_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage131dto0_uid451_alignedZ_uid99_spix_uid43_fpTanPiTest_b & leftShiftStage2Idx3Pad3_uid380_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,447)@7
LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid449_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,448)@7
leftShiftStage2Idx2_uid449_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage132dto0_uid448_alignedZ_uid99_spix_uid43_fpTanPiTest_b & z_uid306_tpix_uid45_fpTanPiTest_q;
--LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,444)@7
LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid446_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,445)@7
leftShiftStage2Idx1_uid446_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage133dto0_uid445_alignedZ_uid99_spix_uid43_fpTanPiTest_b & GND_q;
--vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,389)@3
vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= z_uid96_spix_uid43_fpTanPiTest_q(2 downto 0);
vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_in(2 downto 0);
--ld_vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_b(DELAY,1168)@3
ld_vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 2 )
PORT MAP ( xin => vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b, xout => ld_vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,428)@5
leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= ld_vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q & leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4(REG,698)@5
reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q <= leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,424)@3
X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= z_uid96_spix_uid43_fpTanPiTest_q(18 downto 0);
X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_in(18 downto 0);
--ld_X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_b(DELAY,1167)@3
ld_X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b, xout => ld_X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,425)@5
leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= ld_X18dto0_uid425_alignedZ_uid99_spix_uid43_fpTanPiTest_b_to_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_b_q & leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3(REG,697)@5
reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q <= leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid96_spix_uid43_fpTanPiTest_q_to_reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_a(DELAY,1362)@3
ld_z_uid96_spix_uid43_fpTanPiTest_q_to_reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => z_uid96_spix_uid43_fpTanPiTest_q, xout => ld_z_uid96_spix_uid43_fpTanPiTest_q_to_reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2(REG,696)@5
reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q <= ld_z_uid96_spix_uid43_fpTanPiTest_q_to_reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,386)@3
rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= z_uid96_spix_uid43_fpTanPiTest_q;
rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_in(34 downto 3);
--reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1(REG,686)@3
reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,387)@4
vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= leftShiftStage0Idx2Pad32_uid357_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--ld_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_f(DELAY,1165)@4
ld_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q, xout => ld_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest(BITJOIN,390)@3
cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= vStage_uid390_lzcZ_uid98_spix_uid43_fpTanPiTest_b & mO_uid389_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
--reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3(REG,688)@3
reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest(MUX,392)@4
vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_s <= vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest: PROCESS (vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_s, en, reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q, reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_s IS
WHEN "0" => vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_rVStage_uid387_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_cStage_uid391_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,394)@4
rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_in(31 downto 16);
--reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1(REG,689)@4
reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,395)@5
vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= leftShiftStage0Idx1Pad16_uid354_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--ld_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_e(DELAY,1164)@5
ld_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q, xout => ld_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,396)@4
vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid393_lzcZ_uid98_spix_uid43_fpTanPiTest_q(15 downto 0);
vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_in(15 downto 0);
--reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3(REG,691)@4
reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest(MUX,398)@5
vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_s <= vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest: PROCESS (vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_s, en, reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q, reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_s IS
WHEN "0" => vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_rVStage_uid395_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_vStage_uid397_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,400)@5
rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_in(15 downto 8);
--vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,401)@5
vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= cstAllZWE_uid8_fpTanPiTest_q;
vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3(REG,695)@5
reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,402)@5
vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid399_lzcZ_uid98_spix_uid43_fpTanPiTest_q(7 downto 0);
vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_in(7 downto 0);
--vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest(MUX,404)@5
vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_s <= vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest: PROCESS (vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_s, en, rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_b, vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_b)
BEGIN
CASE vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_s IS
WHEN "0" => vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= rVStage_uid401_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
WHEN "1" => vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= vStage_uid403_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
WHEN OTHERS => vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,406)@5
rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_in(7 downto 4);
--reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1(REG,692)@5
reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q <= rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,407)@6
vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,408)@5
vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid405_lzcZ_uid98_spix_uid43_fpTanPiTest_q(3 downto 0);
vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_in(3 downto 0);
--reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3(REG,694)@5
reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q <= vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest(MUX,410)@6
vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_s <= vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest: PROCESS (vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_s, en, reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q, reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q)
BEGIN
CASE vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_s IS
WHEN "0" => vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_rVStage_uid407_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_1_q;
WHEN "1" => vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= reg_vStage_uid409_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q;
WHEN OTHERS => vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,412)@6
rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_in(3 downto 2);
--vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,413)@6
vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= z_uid306_tpix_uid45_fpTanPiTest_q;
vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,414)@6
vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid411_lzcZ_uid98_spix_uid43_fpTanPiTest_q(1 downto 0);
vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_in(1 downto 0);
--vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest(MUX,416)@6
vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_s <= vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest: PROCESS (vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_s, en, rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_b, vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_b)
BEGIN
CASE vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_s IS
WHEN "0" => vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= rVStage_uid413_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
WHEN "1" => vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= vStage_uid415_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
WHEN OTHERS => vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest(BITSELECT,418)@6
rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_in <= vStagei_uid417_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_in(1 downto 1);
--vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest(LOGICAL,419)@6
vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_a <= rVStage_uid419_lzcZ_uid98_spix_uid43_fpTanPiTest_b;
vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_b <= GND_q;
vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= "1" when vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_a = vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_b else "0";
--r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest(BITJOIN,420)@6
r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q <= ld_vCount_uid388_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_f_q & ld_vCount_uid396_lzcZ_uid98_spix_uid43_fpTanPiTest_q_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_e_q & reg_vCount_uid402_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_3_q & vCount_uid408_lzcZ_uid98_spix_uid43_fpTanPiTest_q & vCount_uid414_lzcZ_uid98_spix_uid43_fpTanPiTest_q & vCount_uid420_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
--leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,430)@6
leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_in(5 downto 4);
--leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest(MUX,431)@6
leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_s <= leftShiftStageSel5Dto4_uid431_alignedZ_uid99_spix_uid43_fpTanPiTest_b;
leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_s, en, reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q, reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q, reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q, ozz_uid88_spix_uid43_fpTanPiTest_q)
BEGIN
CASE leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_z_uid96_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage0Idx1_uid426_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage0Idx2_uid429_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= ozz_uid88_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,439)@6
LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,440)@6
leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage022dto0_uid440_alignedZ_uid99_spix_uid43_fpTanPiTest_b & leftShiftStage1Idx3Pad12_uid369_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5(REG,703)@6
reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5_q <= leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,436)@6
LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,437)@6
leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage026dto0_uid437_alignedZ_uid99_spix_uid43_fpTanPiTest_b & cstAllZWE_uid8_fpTanPiTest_q;
--reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4(REG,702)@6
reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q <= leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,433)@6
LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest(BITJOIN,434)@6
leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= LeftShiftStage030dto0_uid434_alignedZ_uid99_spix_uid43_fpTanPiTest_b & leftShiftStage1Idx1Pad4_uid363_fixedPointX_uid84_spix_uid43_fpTanPiTest_q;
--reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3(REG,701)@6
reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q <= leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2(REG,700)@6
reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q <= leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,441)@6
leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1(REG,699)@6
reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q <= leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest(MUX,442)@7
leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_s <= reg_leftShiftStageSel3Dto2_uid442_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q;
leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_s, en, reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q, reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q, reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q, reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage0_uid432_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx1_uid435_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_3_q;
WHEN "10" => leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx2_uid438_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_4_q;
WHEN "11" => leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= reg_leftShiftStage1Idx3_uid441_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest(BITSELECT,452)@6
leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_in <= r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_b <= leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1(REG,704)@6
reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q <= leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest(MUX,453)@7
leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_s <= reg_leftShiftStageSel1Dto0_uid453_alignedZ_uid99_spix_uid43_fpTanPiTest_0_to_leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_1_q;
leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest: PROCESS (leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_s, en, leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx1_uid446_alignedZ_uid99_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx2_uid449_alignedZ_uid99_spix_uid43_fpTanPiTest_q, leftShiftStage2Idx3_uid452_alignedZ_uid99_spix_uid43_fpTanPiTest_q)
BEGIN
CASE leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_s IS
WHEN "00" => leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= leftShiftStage1_uid443_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
WHEN "01" => leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx1_uid446_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
WHEN "10" => leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx2_uid449_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
WHEN "11" => leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= leftShiftStage2Idx3_uid452_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid100_spix_uid43_fpTanPiTest(BITSELECT,99)@7
alignedZLow_uid100_spix_uid43_fpTanPiTest_in <= leftShiftStage2_uid454_alignedZ_uid99_spix_uid43_fpTanPiTest_q;
alignedZLow_uid100_spix_uid43_fpTanPiTest_b <= alignedZLow_uid100_spix_uid43_fpTanPiTest_in(34 downto 12);
--pHardCase_uid101_spix_uid43_fpTanPiTest(BITJOIN,100)@7
pHardCase_uid101_spix_uid43_fpTanPiTest_q <= alignedZLow_uid100_spix_uid43_fpTanPiTest_b & GND_q;
--ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b(DELAY,834)@0
ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => sinXIsX_uid77_spix_uid43_fpTanPiTest_c, xout => ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid102_spix_uid43_fpTanPiTest(MUX,101)@7
p_uid102_spix_uid43_fpTanPiTest_s <= ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b_q;
p_uid102_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid102_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid102_spix_uid43_fpTanPiTest_s IS
WHEN "0" => p_uid102_spix_uid43_fpTanPiTest_q <= pHardCase_uid101_spix_uid43_fpTanPiTest_q;
WHEN "1" => p_uid102_spix_uid43_fpTanPiTest_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid102_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem(DUALMEM,1498)
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_reset0 <= areset;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ia <= p_uid102_spix_uid43_fpTanPiTest_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_aa <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdreg_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ab <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_rdmux_q;
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 4,
width_b => 24,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_iq,
address_a => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_aa,
data_a => ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_ia
);
ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_q <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_iq(23 downto 0);
--mul2xSinRes_uid116_spix_uid43_fpTanPiTest(MULT,115)@13
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_pr <= UNSIGNED(mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a) * UNSIGNED(mul2xSinRes_uid116_spix_uid43_fpTanPiTest_b);
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a <= (others => '0');
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_b <= (others => '0');
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a <= ld_p_uid102_spix_uid43_fpTanPiTest_q_to_mul2xSinRes_uid116_spix_uid43_fpTanPiTest_a_replace_mem_q;
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_b <= multRightOp_uid115_spix_uid43_fpTanPiTest_q;
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid116_spix_uid43_fpTanPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid116_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q <= mul2xSinRes_uid116_spix_uid43_fpTanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid117_spix_uid43_fpTanPiTest(BITSELECT,116)@16
normBit_uid117_spix_uid43_fpTanPiTest_in <= mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q;
normBit_uid117_spix_uid43_fpTanPiTest_b <= normBit_uid117_spix_uid43_fpTanPiTest_in(48 downto 48);
--rndExpUpdate_uid122_uid123_spix_uid43_fpTanPiTest(BITJOIN,122)@16
rndExpUpdate_uid122_uid123_spix_uid43_fpTanPiTest_q <= normBit_uid117_spix_uid43_fpTanPiTest_b & cstAllZWF_uid53_spix_uid43_fpTanPiTest_q & VCC_q;
--ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor(LOGICAL,1520)
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_b <= ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_q <= not (ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_a or ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_b);
--ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena(REG,1521)
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_nor_q = "1") THEN
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd(LOGICAL,1522)
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_a <= ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_sticky_ena_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_b <= en;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_q <= ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_a and ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_b;
--ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor(LOGICAL,1495)
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_b <= ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_q <= not (ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_a or ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_b);
--ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena(REG,1496)
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_nor_q = "1") THEN
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd(LOGICAL,1497)
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_a <= ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_sticky_ena_q;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_b <= en;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_q <= ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_a and ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_b;
--ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem(DUALMEM,1486)
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_reset0 <= areset;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ia <= exp_uid9_fpTanPiTest_b;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_aa <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ab <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q;
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_iq,
address_a => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_aa,
data_a => ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_ia
);
ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_q <= ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid105_spix_uid43_fpTanPiTest(ADD,104)@7
expXP1_uid105_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_exp_uid9_fpTanPiTest_b_to_expXP1_uid105_spix_uid43_fpTanPiTest_a_replace_mem_q);
expXP1_uid105_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid105_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid105_spix_uid43_fpTanPiTest_a) + UNSIGNED(expXP1_uid105_spix_uid43_fpTanPiTest_b));
expXP1_uid105_spix_uid43_fpTanPiTest_q <= expXP1_uid105_spix_uid43_fpTanPiTest_o(8 downto 0);
--expXP1R_uid106_spix_uid43_fpTanPiTest(BITSELECT,105)@7
expXP1R_uid106_spix_uid43_fpTanPiTest_in <= expXP1_uid105_spix_uid43_fpTanPiTest_q(7 downto 0);
expXP1R_uid106_spix_uid43_fpTanPiTest_b <= expXP1R_uid106_spix_uid43_fpTanPiTest_in(7 downto 0);
--reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1(REG,711)@6
reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1_q <= r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid104_spix_uid43_fpTanPiTest(SUB,103)@7
expHardCase_uid104_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid74_spix_uid43_fpTanPiTest_q);
expHardCase_uid104_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid421_lzcZ_uid98_spix_uid43_fpTanPiTest_0_to_expHardCase_uid104_spix_uid43_fpTanPiTest_1_q);
expHardCase_uid104_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid104_spix_uid43_fpTanPiTest_a) - UNSIGNED(expHardCase_uid104_spix_uid43_fpTanPiTest_b));
expHardCase_uid104_spix_uid43_fpTanPiTest_q <= expHardCase_uid104_spix_uid43_fpTanPiTest_o(8 downto 0);
--expHardCaseR_uid107_spix_uid43_fpTanPiTest(BITSELECT,106)@7
expHardCaseR_uid107_spix_uid43_fpTanPiTest_in <= expHardCase_uid104_spix_uid43_fpTanPiTest_q(7 downto 0);
expHardCaseR_uid107_spix_uid43_fpTanPiTest_b <= expHardCaseR_uid107_spix_uid43_fpTanPiTest_in(7 downto 0);
--expP_uid108_spix_uid43_fpTanPiTest(MUX,107)@7
expP_uid108_spix_uid43_fpTanPiTest_s <= ld_sinXIsX_uid77_spix_uid43_fpTanPiTest_c_to_p_uid102_spix_uid43_fpTanPiTest_b_q;
expP_uid108_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid108_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid108_spix_uid43_fpTanPiTest_s IS
WHEN "0" => expP_uid108_spix_uid43_fpTanPiTest_q <= expHardCaseR_uid107_spix_uid43_fpTanPiTest_b;
WHEN "1" => expP_uid108_spix_uid43_fpTanPiTest_q <= expXP1R_uid106_spix_uid43_fpTanPiTest_b;
WHEN OTHERS => expP_uid108_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem(DUALMEM,1511)
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ia <= expP_uid108_spix_uid43_fpTanPiTest_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_aa <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ab <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q;
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_iq,
address_a => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_aa,
data_a => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_ia
);
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_q <= ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_iq(7 downto 0);
--ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_outputreg(DELAY,1510)
ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_replace_mem_q, xout => ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--highRes_uid118_spix_uid43_fpTanPiTest(BITSELECT,117)@16
highRes_uid118_spix_uid43_fpTanPiTest_in <= mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q(47 downto 0);
highRes_uid118_spix_uid43_fpTanPiTest_b <= highRes_uid118_spix_uid43_fpTanPiTest_in(47 downto 24);
--lowRes_uid119_spix_uid43_fpTanPiTest(BITSELECT,118)@16
lowRes_uid119_spix_uid43_fpTanPiTest_in <= mul2xSinRes_uid116_spix_uid43_fpTanPiTest_q(46 downto 0);
lowRes_uid119_spix_uid43_fpTanPiTest_b <= lowRes_uid119_spix_uid43_fpTanPiTest_in(46 downto 23);
--fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest(MUX,119)@16
fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_s <= normBit_uid117_spix_uid43_fpTanPiTest_b;
fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest: PROCESS (fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_s, en, lowRes_uid119_spix_uid43_fpTanPiTest_b, highRes_uid118_spix_uid43_fpTanPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_q <= lowRes_uid119_spix_uid43_fpTanPiTest_b;
WHEN "1" => fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_q <= highRes_uid118_spix_uid43_fpTanPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest(BITJOIN,120)@16
expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_q <= ld_expP_uid108_spix_uid43_fpTanPiTest_q_to_expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_b_outputreg_q & fracRCompPreRnd_uid120_spix_uid43_fpTanPiTest_q;
--expFracComp_uid124_spix_uid43_fpTanPiTest(ADD,123)@16
expFracComp_uid124_spix_uid43_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid121_uid121_spix_uid43_fpTanPiTest_q);
expFracComp_uid124_spix_uid43_fpTanPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid122_uid123_spix_uid43_fpTanPiTest_q);
expFracComp_uid124_spix_uid43_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid124_spix_uid43_fpTanPiTest_a) + UNSIGNED(expFracComp_uid124_spix_uid43_fpTanPiTest_b));
expFracComp_uid124_spix_uid43_fpTanPiTest_q <= expFracComp_uid124_spix_uid43_fpTanPiTest_o(32 downto 0);
--expRComp_uid126_spix_uid43_fpTanPiTest(BITSELECT,125)@16
expRComp_uid126_spix_uid43_fpTanPiTest_in <= expFracComp_uid124_spix_uid43_fpTanPiTest_q(31 downto 0);
expRComp_uid126_spix_uid43_fpTanPiTest_b <= expRComp_uid126_spix_uid43_fpTanPiTest_in(31 downto 24);
--reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2(REG,713)@2
reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2_q <= xIsInt_uid130_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--excRZero_uid134_spix_uid43_fpTanPiTest(LOGICAL,133)@2
excRZero_uid134_spix_uid43_fpTanPiTest_a <= xIsInt_uid130_spix_uid43_fpTanPiTest_q;
excRZero_uid134_spix_uid43_fpTanPiTest_b <= ld_expXIsZero_uid10_fpTanPiTest_q_to_excRZero_uid134_spix_uid43_fpTanPiTest_b_q;
excRZero_uid134_spix_uid43_fpTanPiTest_c <= exc_I_uid66_spix_uid43_fpTanPiTest_q;
excRZero_uid134_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excRZero_uid134_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
excRZero_uid134_spix_uid43_fpTanPiTest_q <= excRZero_uid134_spix_uid43_fpTanPiTest_a or excRZero_uid134_spix_uid43_fpTanPiTest_b or excRZero_uid134_spix_uid43_fpTanPiTest_c;
END IF;
END PROCESS;
--rZOrXInt_uid139_spix_uid43_fpTanPiTest(LOGICAL,138)@3
rZOrXInt_uid139_spix_uid43_fpTanPiTest_a <= excRZero_uid134_spix_uid43_fpTanPiTest_q;
rZOrXInt_uid139_spix_uid43_fpTanPiTest_b <= reg_xIsInt_uid130_spix_uid43_fpTanPiTest_0_to_rZOrXInt_uid139_spix_uid43_fpTanPiTest_2_q;
rZOrXInt_uid139_spix_uid43_fpTanPiTest_q <= rZOrXInt_uid139_spix_uid43_fpTanPiTest_a or rZOrXInt_uid139_spix_uid43_fpTanPiTest_b;
--ld_rZOrXInt_uid139_spix_uid43_fpTanPiTest_q_to_expRPostExc1_uid142_spix_uid43_fpTanPiTest_b(DELAY,887)@3
ld_rZOrXInt_uid139_spix_uid43_fpTanPiTest_q_to_expRPostExc1_uid142_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => rZOrXInt_uid139_spix_uid43_fpTanPiTest_q, xout => ld_rZOrXInt_uid139_spix_uid43_fpTanPiTest_q_to_expRPostExc1_uid142_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid142_spix_uid43_fpTanPiTest(MUX,141)@16
expRPostExc1_uid142_spix_uid43_fpTanPiTest_s <= ld_rZOrXInt_uid139_spix_uid43_fpTanPiTest_q_to_expRPostExc1_uid142_spix_uid43_fpTanPiTest_b_q;
expRPostExc1_uid142_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid142_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid142_spix_uid43_fpTanPiTest_s IS
WHEN "0" => expRPostExc1_uid142_spix_uid43_fpTanPiTest_q <= expRComp_uid126_spix_uid43_fpTanPiTest_b;
WHEN "1" => expRPostExc1_uid142_spix_uid43_fpTanPiTest_q <= cstAllZWE_uid8_fpTanPiTest_q;
WHEN OTHERS => expRPostExc1_uid142_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor(LOGICAL,1532)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_b <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_q <= not (ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_a or ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_b);
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena(REG,1533)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_nor_q = "1") THEN
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd(LOGICAL,1534)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_a <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_sticky_ena_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_b <= en;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_a and ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_b;
--xRyHalf_uid133_spix_uid43_fpTanPiTest(LOGICAL,132)@2
xRyHalf_uid133_spix_uid43_fpTanPiTest_a <= exc_R_uid72_spix_uid43_fpTanPiTest_q;
xRyHalf_uid133_spix_uid43_fpTanPiTest_b <= yIsZero_uid90_spix_uid43_fpTanPiTest_q;
xRyHalf_uid133_spix_uid43_fpTanPiTest_c <= InvSinXIsX_uid127_spix_uid43_fpTanPiTest_q;
xRyHalf_uid133_spix_uid43_fpTanPiTest_d <= InvXIntExp_uid131_spix_uid43_fpTanPiTest_q;
xRyHalf_uid133_spix_uid43_fpTanPiTest_q <= xRyHalf_uid133_spix_uid43_fpTanPiTest_a and xRyHalf_uid133_spix_uid43_fpTanPiTest_b and xRyHalf_uid133_spix_uid43_fpTanPiTest_c and xRyHalf_uid133_spix_uid43_fpTanPiTest_d;
--excRIoN_uid143_spix_uid43_fpTanPiTest(LOGICAL,142)@2
excRIoN_uid143_spix_uid43_fpTanPiTest_a <= GND_q;
excRIoN_uid143_spix_uid43_fpTanPiTest_b <= exc_N_uid68_spix_uid43_fpTanPiTest_q;
excRIoN_uid143_spix_uid43_fpTanPiTest_q <= excRIoN_uid143_spix_uid43_fpTanPiTest_a or excRIoN_uid143_spix_uid43_fpTanPiTest_b;
--join_uid144_spix_uid43_fpTanPiTest(BITJOIN,143)@2
join_uid144_spix_uid43_fpTanPiTest_q <= xRyHalf_uid133_spix_uid43_fpTanPiTest_q & excRIoN_uid143_spix_uid43_fpTanPiTest_q;
--reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1(REG,714)@2
reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q <= join_uid144_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem(DUALMEM,1523)
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ia <= reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_aa <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdreg_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ab <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_rdmux_q;
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_ia
);
ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_q <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid145_spix_uid43_fpTanPiTest(MUX,144)@17
expRPostExc_uid145_spix_uid43_fpTanPiTest_s <= ld_reg_join_uid144_spix_uid43_fpTanPiTest_0_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_1_q_to_expRPostExc_uid145_spix_uid43_fpTanPiTest_b_replace_mem_q;
expRPostExc_uid145_spix_uid43_fpTanPiTest: PROCESS (expRPostExc_uid145_spix_uid43_fpTanPiTest_s, en, expRPostExc1_uid142_spix_uid43_fpTanPiTest_q, cstAllOWE_uid52_spix_uid43_fpTanPiTest_q, cstBias_uid54_spix_uid43_fpTanPiTest_q, cstBias_uid54_spix_uid43_fpTanPiTest_q)
BEGIN
CASE expRPostExc_uid145_spix_uid43_fpTanPiTest_s IS
WHEN "00" => expRPostExc_uid145_spix_uid43_fpTanPiTest_q <= expRPostExc1_uid142_spix_uid43_fpTanPiTest_q;
WHEN "01" => expRPostExc_uid145_spix_uid43_fpTanPiTest_q <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
WHEN "10" => expRPostExc_uid145_spix_uid43_fpTanPiTest_q <= cstBias_uid54_spix_uid43_fpTanPiTest_q;
WHEN "11" => expRPostExc_uid145_spix_uid43_fpTanPiTest_q <= cstBias_uid54_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => expRPostExc_uid145_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRComp_uid125_spix_uid43_fpTanPiTest(BITSELECT,124)@16
fracRComp_uid125_spix_uid43_fpTanPiTest_in <= expFracComp_uid124_spix_uid43_fpTanPiTest_q(23 downto 0);
fracRComp_uid125_spix_uid43_fpTanPiTest_b <= fracRComp_uid125_spix_uid43_fpTanPiTest_in(23 downto 1);
--reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1(REG,683)@2
reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1_q <= xRyHalf_uid133_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid135_spix_uid43_fpTanPiTest(LOGICAL,134)@3
xHalfRZI_uid135_spix_uid43_fpTanPiTest_a <= reg_xRyHalf_uid133_spix_uid43_fpTanPiTest_0_to_xHalfRZI_uid135_spix_uid43_fpTanPiTest_1_q;
xHalfRZI_uid135_spix_uid43_fpTanPiTest_b <= excRZero_uid134_spix_uid43_fpTanPiTest_q;
xHalfRZI_uid135_spix_uid43_fpTanPiTest_c <= GND_q;
xHalfRZI_uid135_spix_uid43_fpTanPiTest_q <= xHalfRZI_uid135_spix_uid43_fpTanPiTest_a or xHalfRZI_uid135_spix_uid43_fpTanPiTest_b or xHalfRZI_uid135_spix_uid43_fpTanPiTest_c;
--ld_xHalfRZI_uid135_spix_uid43_fpTanPiTest_q_to_fracRPostExc1_uid136_spix_uid43_fpTanPiTest_b(DELAY,881)@3
ld_xHalfRZI_uid135_spix_uid43_fpTanPiTest_q_to_fracRPostExc1_uid136_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xHalfRZI_uid135_spix_uid43_fpTanPiTest_q, xout => ld_xHalfRZI_uid135_spix_uid43_fpTanPiTest_q_to_fracRPostExc1_uid136_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid136_spix_uid43_fpTanPiTest(MUX,135)@16
fracRPostExc1_uid136_spix_uid43_fpTanPiTest_s <= ld_xHalfRZI_uid135_spix_uid43_fpTanPiTest_q_to_fracRPostExc1_uid136_spix_uid43_fpTanPiTest_b_q;
fracRPostExc1_uid136_spix_uid43_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid136_spix_uid43_fpTanPiTest_s IS
WHEN "0" => fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q <= fracRComp_uid125_spix_uid43_fpTanPiTest_b;
WHEN "1" => fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1(REG,712)@2
reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q <= exc_N_uid68_spix_uid43_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_b(DELAY,883)@3
ld_reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q, xout => ld_reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid138_spix_uid43_fpTanPiTest(MUX,137)@17
fracRPostExc_uid138_spix_uid43_fpTanPiTest_s <= ld_reg_exc_N_uid68_spix_uid43_fpTanPiTest_0_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_1_q_to_fracRPostExc_uid138_spix_uid43_fpTanPiTest_b_q;
fracRPostExc_uid138_spix_uid43_fpTanPiTest: PROCESS (fracRPostExc_uid138_spix_uid43_fpTanPiTest_s, en, fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q, oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q)
BEGIN
CASE fracRPostExc_uid138_spix_uid43_fpTanPiTest_s IS
WHEN "0" => fracRPostExc_uid138_spix_uid43_fpTanPiTest_q <= fracRPostExc1_uid136_spix_uid43_fpTanPiTest_q;
WHEN "1" => fracRPostExc_uid138_spix_uid43_fpTanPiTest_q <= oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => fracRPostExc_uid138_spix_uid43_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid152_spix_uid43_fpTanPiTest(BITJOIN,151)@17
R_uid152_spix_uid43_fpTanPiTest_q <= ld_signR_uid151_spix_uid43_fpTanPiTest_q_to_R_uid152_spix_uid43_fpTanPiTest_c_q & expRPostExc_uid145_spix_uid43_fpTanPiTest_q & fracRPostExc_uid138_spix_uid43_fpTanPiTest_q;
--fracX_uid256_tpix_uid45_fpTanPiTest(BITSELECT,255)@17
fracX_uid256_tpix_uid45_fpTanPiTest_in <= R_uid152_spix_uid43_fpTanPiTest_q(22 downto 0);
fracX_uid256_tpix_uid45_fpTanPiTest_b <= fracX_uid256_tpix_uid45_fpTanPiTest_in(22 downto 0);
--fracXIsZero_uid270_tpix_uid45_fpTanPiTest(LOGICAL,269)@17
fracXIsZero_uid270_tpix_uid45_fpTanPiTest_a <= fracX_uid256_tpix_uid45_fpTanPiTest_b;
fracXIsZero_uid270_tpix_uid45_fpTanPiTest_b <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
fracXIsZero_uid270_tpix_uid45_fpTanPiTest_q <= "1" when fracXIsZero_uid270_tpix_uid45_fpTanPiTest_a = fracXIsZero_uid270_tpix_uid45_fpTanPiTest_b else "0";
--expX_uid255_tpix_uid45_fpTanPiTest(BITSELECT,254)@17
expX_uid255_tpix_uid45_fpTanPiTest_in <= R_uid152_spix_uid43_fpTanPiTest_q(30 downto 0);
expX_uid255_tpix_uid45_fpTanPiTest_b <= expX_uid255_tpix_uid45_fpTanPiTest_in(30 downto 23);
--expXIsMax_uid268_tpix_uid45_fpTanPiTest(LOGICAL,267)@17
expXIsMax_uid268_tpix_uid45_fpTanPiTest_a <= expX_uid255_tpix_uid45_fpTanPiTest_b;
expXIsMax_uid268_tpix_uid45_fpTanPiTest_b <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
expXIsMax_uid268_tpix_uid45_fpTanPiTest_q <= "1" when expXIsMax_uid268_tpix_uid45_fpTanPiTest_a = expXIsMax_uid268_tpix_uid45_fpTanPiTest_b else "0";
--exc_I_uid271_tpix_uid45_fpTanPiTest(LOGICAL,270)@17
exc_I_uid271_tpix_uid45_fpTanPiTest_a <= expXIsMax_uid268_tpix_uid45_fpTanPiTest_q;
exc_I_uid271_tpix_uid45_fpTanPiTest_b <= fracXIsZero_uid270_tpix_uid45_fpTanPiTest_q;
exc_I_uid271_tpix_uid45_fpTanPiTest_q <= exc_I_uid271_tpix_uid45_fpTanPiTest_a and exc_I_uid271_tpix_uid45_fpTanPiTest_b;
--excXIYI_uid337_tpix_uid45_fpTanPiTest(LOGICAL,336)@17
excXIYI_uid337_tpix_uid45_fpTanPiTest_a <= exc_I_uid271_tpix_uid45_fpTanPiTest_q;
excXIYI_uid337_tpix_uid45_fpTanPiTest_b <= exc_I_uid287_tpix_uid45_fpTanPiTest_q;
excXIYI_uid337_tpix_uid45_fpTanPiTest_q <= excXIYI_uid337_tpix_uid45_fpTanPiTest_a and excXIYI_uid337_tpix_uid45_fpTanPiTest_b;
--InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest(LOGICAL,287)@17
InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_a <= fracXIsZero_uid286_tpix_uid45_fpTanPiTest_q;
InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_q <= not InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_a;
--exc_N_uid289_tpix_uid45_fpTanPiTest(LOGICAL,288)@17
exc_N_uid289_tpix_uid45_fpTanPiTest_a <= expXIsMax_uid284_tpix_uid45_fpTanPiTest_q;
exc_N_uid289_tpix_uid45_fpTanPiTest_b <= InvFracXIsZero_uid288_tpix_uid45_fpTanPiTest_q;
exc_N_uid289_tpix_uid45_fpTanPiTest_q <= exc_N_uid289_tpix_uid45_fpTanPiTest_a and exc_N_uid289_tpix_uid45_fpTanPiTest_b;
--InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest(LOGICAL,271)@17
InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_a <= fracXIsZero_uid270_tpix_uid45_fpTanPiTest_q;
InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_q <= not InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_a;
--exc_N_uid273_tpix_uid45_fpTanPiTest(LOGICAL,272)@17
exc_N_uid273_tpix_uid45_fpTanPiTest_a <= expXIsMax_uid268_tpix_uid45_fpTanPiTest_q;
exc_N_uid273_tpix_uid45_fpTanPiTest_b <= InvFracXIsZero_uid272_tpix_uid45_fpTanPiTest_q;
exc_N_uid273_tpix_uid45_fpTanPiTest_q <= exc_N_uid273_tpix_uid45_fpTanPiTest_a and exc_N_uid273_tpix_uid45_fpTanPiTest_b;
--expXIsZero_uid282_tpix_uid45_fpTanPiTest(LOGICAL,281)@17
expXIsZero_uid282_tpix_uid45_fpTanPiTest_a <= expY_uid258_tpix_uid45_fpTanPiTest_b;
expXIsZero_uid282_tpix_uid45_fpTanPiTest_b <= cstAllZWE_uid8_fpTanPiTest_q;
expXIsZero_uid282_tpix_uid45_fpTanPiTest_q <= "1" when expXIsZero_uid282_tpix_uid45_fpTanPiTest_a = expXIsZero_uid282_tpix_uid45_fpTanPiTest_b else "0";
--expXIsZero_uid266_tpix_uid45_fpTanPiTest(LOGICAL,265)@17
expXIsZero_uid266_tpix_uid45_fpTanPiTest_a <= expX_uid255_tpix_uid45_fpTanPiTest_b;
expXIsZero_uid266_tpix_uid45_fpTanPiTest_b <= cstAllZWE_uid8_fpTanPiTest_q;
expXIsZero_uid266_tpix_uid45_fpTanPiTest_q <= "1" when expXIsZero_uid266_tpix_uid45_fpTanPiTest_a = expXIsZero_uid266_tpix_uid45_fpTanPiTest_b else "0";
--excXZYZ_uid336_tpix_uid45_fpTanPiTest(LOGICAL,335)@17
excXZYZ_uid336_tpix_uid45_fpTanPiTest_a <= expXIsZero_uid266_tpix_uid45_fpTanPiTest_q;
excXZYZ_uid336_tpix_uid45_fpTanPiTest_b <= expXIsZero_uid282_tpix_uid45_fpTanPiTest_q;
excXZYZ_uid336_tpix_uid45_fpTanPiTest_q <= excXZYZ_uid336_tpix_uid45_fpTanPiTest_a and excXZYZ_uid336_tpix_uid45_fpTanPiTest_b;
--excRNaN_uid338_tpix_uid45_fpTanPiTest(LOGICAL,337)@17
excRNaN_uid338_tpix_uid45_fpTanPiTest_a <= excXZYZ_uid336_tpix_uid45_fpTanPiTest_q;
excRNaN_uid338_tpix_uid45_fpTanPiTest_b <= exc_N_uid273_tpix_uid45_fpTanPiTest_q;
excRNaN_uid338_tpix_uid45_fpTanPiTest_c <= exc_N_uid289_tpix_uid45_fpTanPiTest_q;
excRNaN_uid338_tpix_uid45_fpTanPiTest_d <= excXIYI_uid337_tpix_uid45_fpTanPiTest_q;
excRNaN_uid338_tpix_uid45_fpTanPiTest_q <= excRNaN_uid338_tpix_uid45_fpTanPiTest_a or excRNaN_uid338_tpix_uid45_fpTanPiTest_b or excRNaN_uid338_tpix_uid45_fpTanPiTest_c or excRNaN_uid338_tpix_uid45_fpTanPiTest_d;
--InvExcRNaN_uid349_tpix_uid45_fpTanPiTest(LOGICAL,348)@17
InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_a <= excRNaN_uid338_tpix_uid45_fpTanPiTest_q;
InvExcRNaN_uid349_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_q <= not InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_a;
END IF;
END PROCESS;
--signY_uid260_tpix_uid45_fpTanPiTest(BITSELECT,259)@17
signY_uid260_tpix_uid45_fpTanPiTest_in <= R_uid250_cpix_uid44_fpTanPiTest_q;
signY_uid260_tpix_uid45_fpTanPiTest_b <= signY_uid260_tpix_uid45_fpTanPiTest_in(31 downto 31);
--signX_uid257_tpix_uid45_fpTanPiTest(BITSELECT,256)@17
signX_uid257_tpix_uid45_fpTanPiTest_in <= R_uid152_spix_uid43_fpTanPiTest_q;
signX_uid257_tpix_uid45_fpTanPiTest_b <= signX_uid257_tpix_uid45_fpTanPiTest_in(31 downto 31);
--signR_uid294_tpix_uid45_fpTanPiTest(LOGICAL,293)@17
signR_uid294_tpix_uid45_fpTanPiTest_a <= signX_uid257_tpix_uid45_fpTanPiTest_b;
signR_uid294_tpix_uid45_fpTanPiTest_b <= signY_uid260_tpix_uid45_fpTanPiTest_b;
signR_uid294_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid294_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid294_tpix_uid45_fpTanPiTest_q <= signR_uid294_tpix_uid45_fpTanPiTest_a xor signR_uid294_tpix_uid45_fpTanPiTest_b;
END IF;
END PROCESS;
--sRPostExc_uid350_tpix_uid45_fpTanPiTest(LOGICAL,349)@18
sRPostExc_uid350_tpix_uid45_fpTanPiTest_a <= signR_uid294_tpix_uid45_fpTanPiTest_q;
sRPostExc_uid350_tpix_uid45_fpTanPiTest_b <= InvExcRNaN_uid349_tpix_uid45_fpTanPiTest_q;
sRPostExc_uid350_tpix_uid45_fpTanPiTest_q <= sRPostExc_uid350_tpix_uid45_fpTanPiTest_a and sRPostExc_uid350_tpix_uid45_fpTanPiTest_b;
--ld_sRPostExc_uid350_tpix_uid45_fpTanPiTest_q_to_divR_uid351_tpix_uid45_fpTanPiTest_c(DELAY,1093)@18
ld_sRPostExc_uid350_tpix_uid45_fpTanPiTest_q_to_divR_uid351_tpix_uid45_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sRPostExc_uid350_tpix_uid45_fpTanPiTest_q, xout => ld_sRPostExc_uid350_tpix_uid45_fpTanPiTest_q_to_divR_uid351_tpix_uid45_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor(LOGICAL,1581)
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_b <= ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_q <= not (ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_a or ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_b);
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_mem_top(CONSTANT,1565)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_mem_top_q <= "01001";
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp(LOGICAL,1566)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_a <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_mem_top_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q);
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_q <= "1" when ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_a = ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_b else "0";
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg(REG,1567)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena(REG,1582)
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_nor_q = "1") THEN
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd(LOGICAL,1583)
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_a <= ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_sticky_ena_q;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_b <= en;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_q <= ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_a and ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_b;
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt(COUNTER,1561)
-- every=1, low=0, high=9, step=1, init=1
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i = 8 THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i - 9;
ELSE
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_i,4));
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg(REG,1562)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux(MUX,1563)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_s <= en;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux: PROCESS (ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_s, ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q, ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem(DUALMEM,1572)
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_reset0 <= areset;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ia <= fracX_uid256_tpix_uid45_fpTanPiTest_b;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_aa <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ab <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q;
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 10,
width_b => 23,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_iq,
address_a => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_aa,
data_a => ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_ia
);
ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_q <= ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_iq(22 downto 0);
--lOAdded_uid304_tpix_uid45_fpTanPiTest(BITJOIN,303)@28
lOAdded_uid304_tpix_uid45_fpTanPiTest_q <= VCC_q & ld_fracX_uid256_tpix_uid45_fpTanPiTest_b_to_lOAdded_uid304_tpix_uid45_fpTanPiTest_a_replace_mem_q;
--ld_lOAdded_uid304_tpix_uid45_fpTanPiTest_q_to_oFracXExt_uid307_tpix_uid45_fpTanPiTest_b(DELAY,1027)@28
ld_lOAdded_uid304_tpix_uid45_fpTanPiTest_q_to_oFracXExt_uid307_tpix_uid45_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => lOAdded_uid304_tpix_uid45_fpTanPiTest_q, xout => ld_lOAdded_uid304_tpix_uid45_fpTanPiTest_q_to_oFracXExt_uid307_tpix_uid45_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--oFracXExt_uid307_tpix_uid45_fpTanPiTest(BITJOIN,306)@30
oFracXExt_uid307_tpix_uid45_fpTanPiTest_q <= ld_lOAdded_uid304_tpix_uid45_fpTanPiTest_q_to_oFracXExt_uid307_tpix_uid45_fpTanPiTest_b_q & z_uid306_tpix_uid45_fpTanPiTest_q;
--reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3(REG,757)@30
reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3_q <= oFracXExt_uid307_tpix_uid45_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--fracYAddr_uid298_tpix_uid45_fpTanPiTest(BITSELECT,297)@17
fracYAddr_uid298_tpix_uid45_fpTanPiTest_in <= R_uid250_cpix_uid44_fpTanPiTest_q(22 downto 0);
fracYAddr_uid298_tpix_uid45_fpTanPiTest_b <= fracYAddr_uid298_tpix_uid45_fpTanPiTest_in(22 downto 14);
--memoryC2_uid596_invTab_lutmem(DUALMEM,646)@17
memoryC2_uid596_invTab_lutmem_reset0 <= areset;
memoryC2_uid596_invTab_lutmem_ia <= (others => '0');
memoryC2_uid596_invTab_lutmem_aa <= (others => '0');
memoryC2_uid596_invTab_lutmem_ab <= fracYAddr_uid298_tpix_uid45_fpTanPiTest_b;
memoryC2_uid596_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tanpi_s5_memoryC2_uid596_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid596_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid596_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid596_invTab_lutmem_iq,
address_a => memoryC2_uid596_invTab_lutmem_aa,
data_a => memoryC2_uid596_invTab_lutmem_ia
);
memoryC2_uid596_invTab_lutmem_q <= memoryC2_uid596_invTab_lutmem_iq(11 downto 0);
--reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1(REG,753)@19
reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1_q <= memoryC2_uid596_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPE_uid299_tpix_uid45_fpTanPiTest(BITSELECT,298)@17
yPE_uid299_tpix_uid45_fpTanPiTest_in <= R_uid250_cpix_uid44_fpTanPiTest_q(13 downto 0);
yPE_uid299_tpix_uid45_fpTanPiTest_b <= yPE_uid299_tpix_uid45_fpTanPiTest_in(13 downto 0);
--yT1_uid597_invPE(BITSELECT,596)@17
yT1_uid597_invPE_in <= yPE_uid299_tpix_uid45_fpTanPiTest_b;
yT1_uid597_invPE_b <= yT1_uid597_invPE_in(13 downto 2);
--reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0(REG,752)@17
reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q <= yT1_uid597_invPE_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q_to_prodXY_uid625_pT1_uid598_invPE_a(DELAY,1332)@18
ld_reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q_to_prodXY_uid625_pT1_uid598_invPE_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q, xout => ld_reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q_to_prodXY_uid625_pT1_uid598_invPE_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid625_pT1_uid598_invPE(MULT,624)@20
prodXY_uid625_pT1_uid598_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid625_pT1_uid598_invPE_a),13)) * SIGNED(prodXY_uid625_pT1_uid598_invPE_b);
prodXY_uid625_pT1_uid598_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid625_pT1_uid598_invPE_a <= (others => '0');
prodXY_uid625_pT1_uid598_invPE_b <= (others => '0');
prodXY_uid625_pT1_uid598_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid625_pT1_uid598_invPE_a <= ld_reg_yT1_uid597_invPE_0_to_prodXY_uid625_pT1_uid598_invPE_0_q_to_prodXY_uid625_pT1_uid598_invPE_a_q;
prodXY_uid625_pT1_uid598_invPE_b <= reg_memoryC2_uid596_invTab_lutmem_0_to_prodXY_uid625_pT1_uid598_invPE_1_q;
prodXY_uid625_pT1_uid598_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid625_pT1_uid598_invPE_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid625_pT1_uid598_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid625_pT1_uid598_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid625_pT1_uid598_invPE_q <= prodXY_uid625_pT1_uid598_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid626_pT1_uid598_invPE(BITSELECT,625)@23
prodXYTruncFR_uid626_pT1_uid598_invPE_in <= prodXY_uid625_pT1_uid598_invPE_q;
prodXYTruncFR_uid626_pT1_uid598_invPE_b <= prodXYTruncFR_uid626_pT1_uid598_invPE_in(23 downto 11);
--highBBits_uid600_invPE(BITSELECT,599)@23
highBBits_uid600_invPE_in <= prodXYTruncFR_uid626_pT1_uid598_invPE_b;
highBBits_uid600_invPE_b <= highBBits_uid600_invPE_in(12 downto 1);
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg(DELAY,1646)
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => fracYAddr_uid298_tpix_uid45_fpTanPiTest_b, xout => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC1_uid595_invTab_lutmem_a(DELAY,1339)@17
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC1_uid595_invTab_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg_q, xout => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC1_uid595_invTab_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid595_invTab_lutmem(DUALMEM,645)@21
memoryC1_uid595_invTab_lutmem_reset0 <= areset;
memoryC1_uid595_invTab_lutmem_ia <= (others => '0');
memoryC1_uid595_invTab_lutmem_aa <= (others => '0');
memoryC1_uid595_invTab_lutmem_ab <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC1_uid595_invTab_lutmem_a_q;
memoryC1_uid595_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tanpi_s5_memoryC1_uid595_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid595_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid595_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid595_invTab_lutmem_iq,
address_a => memoryC1_uid595_invTab_lutmem_aa,
data_a => memoryC1_uid595_invTab_lutmem_ia
);
memoryC1_uid595_invTab_lutmem_q <= memoryC1_uid595_invTab_lutmem_iq(20 downto 0);
--sumAHighB_uid601_invPE(ADD,600)@23
sumAHighB_uid601_invPE_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid595_invTab_lutmem_q(20)) & memoryC1_uid595_invTab_lutmem_q);
sumAHighB_uid601_invPE_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid600_invPE_b(11)) & highBBits_uid600_invPE_b);
sumAHighB_uid601_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid601_invPE_a) + SIGNED(sumAHighB_uid601_invPE_b));
sumAHighB_uid601_invPE_q <= sumAHighB_uid601_invPE_o(21 downto 0);
--lowRangeB_uid599_invPE(BITSELECT,598)@23
lowRangeB_uid599_invPE_in <= prodXYTruncFR_uid626_pT1_uid598_invPE_b(0 downto 0);
lowRangeB_uid599_invPE_b <= lowRangeB_uid599_invPE_in(0 downto 0);
--s1_uid599_uid602_invPE(BITJOIN,601)@23
s1_uid599_uid602_invPE_q <= sumAHighB_uid601_invPE_q & lowRangeB_uid599_invPE_b;
--reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1(REG,755)@23
reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1_q <= s1_uid599_uid602_invPE_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor(LOGICAL,1643)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_b <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_q <= not (ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_a or ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_b);
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_mem_top(CONSTANT,1639)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_mem_top_q <= "0100";
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp(LOGICAL,1640)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_a <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_mem_top_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q);
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_q <= "1" when ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_a = ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_b else "0";
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg(REG,1641)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena(REG,1644)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_nor_q = "1") THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd(LOGICAL,1645)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_a <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_sticky_ena_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_b <= en;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_a and ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_b;
--reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0(REG,754)@17
reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q <= yPE_uid299_tpix_uid45_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt(COUNTER,1635)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i = 3 THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_i,3));
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg(REG,1636)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux(MUX,1637)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_s <= en;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux: PROCESS (ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_s, ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q, ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem(DUALMEM,1634)
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_reset0 <= areset;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ia <= reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_aa <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdreg_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ab <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_rdmux_q;
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 3,
numwords_a => 5,
width_b => 14,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_iq,
address_a => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_aa,
data_a => ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_ia
);
ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_q <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_iq(13 downto 0);
--prodXY_uid628_pT2_uid604_invPE(MULT,627)@24
prodXY_uid628_pT2_uid604_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid628_pT2_uid604_invPE_a),15)) * SIGNED(prodXY_uid628_pT2_uid604_invPE_b);
prodXY_uid628_pT2_uid604_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid628_pT2_uid604_invPE_a <= (others => '0');
prodXY_uid628_pT2_uid604_invPE_b <= (others => '0');
prodXY_uid628_pT2_uid604_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid628_pT2_uid604_invPE_a <= ld_reg_yPE_uid299_tpix_uid45_fpTanPiTest_0_to_prodXY_uid628_pT2_uid604_invPE_0_q_to_prodXY_uid628_pT2_uid604_invPE_a_replace_mem_q;
prodXY_uid628_pT2_uid604_invPE_b <= reg_s1_uid599_uid602_invPE_0_to_prodXY_uid628_pT2_uid604_invPE_1_q;
prodXY_uid628_pT2_uid604_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid628_pT2_uid604_invPE_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid628_pT2_uid604_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid628_pT2_uid604_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid628_pT2_uid604_invPE_q <= prodXY_uid628_pT2_uid604_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid629_pT2_uid604_invPE(BITSELECT,628)@27
prodXYTruncFR_uid629_pT2_uid604_invPE_in <= prodXY_uid628_pT2_uid604_invPE_q;
prodXYTruncFR_uid629_pT2_uid604_invPE_b <= prodXYTruncFR_uid629_pT2_uid604_invPE_in(36 downto 13);
--highBBits_uid606_invPE(BITSELECT,605)@27
highBBits_uid606_invPE_in <= prodXYTruncFR_uid629_pT2_uid604_invPE_b;
highBBits_uid606_invPE_b <= highBBits_uid606_invPE_in(23 downto 2);
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor(LOGICAL,1656)
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_b <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_q <= not (ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_a or ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_b);
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena(REG,1657)
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_nor_q = "1") THEN
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd(LOGICAL,1658)
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_a <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_sticky_ena_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_b <= en;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_q <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_a and ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_b;
--ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem(DUALMEM,1647)
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_reset0 <= areset;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ia <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_inputreg_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_aa <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdreg_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ab <= ld_oFracX_uid27_uid27_fpTanPiTest_q_to_p_uid102_spix_uid43_fpTanPiTest_d_replace_rdmux_q;
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 6,
width_b => 9,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_iq,
address_a => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_aa,
data_a => ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_ia
);
ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_q <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid594_invTab_lutmem(DUALMEM,644)@25
memoryC0_uid594_invTab_lutmem_reset0 <= areset;
memoryC0_uid594_invTab_lutmem_ia <= (others => '0');
memoryC0_uid594_invTab_lutmem_aa <= (others => '0');
memoryC0_uid594_invTab_lutmem_ab <= ld_fracYAddr_uid298_tpix_uid45_fpTanPiTest_b_to_memoryC0_uid594_invTab_lutmem_a_replace_mem_q;
memoryC0_uid594_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tanpi_s5_memoryC0_uid594_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid594_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid594_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid594_invTab_lutmem_iq,
address_a => memoryC0_uid594_invTab_lutmem_aa,
data_a => memoryC0_uid594_invTab_lutmem_ia
);
memoryC0_uid594_invTab_lutmem_q <= memoryC0_uid594_invTab_lutmem_iq(30 downto 0);
--sumAHighB_uid607_invPE(ADD,606)@27
sumAHighB_uid607_invPE_a <= STD_LOGIC_VECTOR((31 downto 31 => memoryC0_uid594_invTab_lutmem_q(30)) & memoryC0_uid594_invTab_lutmem_q);
sumAHighB_uid607_invPE_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid606_invPE_b(21)) & highBBits_uid606_invPE_b);
sumAHighB_uid607_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid607_invPE_a) + SIGNED(sumAHighB_uid607_invPE_b));
sumAHighB_uid607_invPE_q <= sumAHighB_uid607_invPE_o(31 downto 0);
--lowRangeB_uid605_invPE(BITSELECT,604)@27
lowRangeB_uid605_invPE_in <= prodXYTruncFR_uid629_pT2_uid604_invPE_b(1 downto 0);
lowRangeB_uid605_invPE_b <= lowRangeB_uid605_invPE_in(1 downto 0);
--s2_uid605_uid608_invPE(BITJOIN,607)@27
s2_uid605_uid608_invPE_q <= sumAHighB_uid607_invPE_q & lowRangeB_uid605_invPE_b;
--invY_uid301_tpix_uid45_fpTanPiTest(BITSELECT,300)@27
invY_uid301_tpix_uid45_fpTanPiTest_in <= s2_uid605_uid608_invPE_q(30 downto 0);
invY_uid301_tpix_uid45_fpTanPiTest_b <= invY_uid301_tpix_uid45_fpTanPiTest_in(30 downto 5);
--reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0(REG,756)@27
reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0_q <= invY_uid301_tpix_uid45_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest(MULT,609)@28
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_pr <= UNSIGNED(prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_a) * UNSIGNED(prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b);
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_a <= (others => '0');
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b <= (others => '0');
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_a <= reg_invY_uid301_tpix_uid45_fpTanPiTest_0_to_prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_0_q;
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b <= lOAdded_uid304_tpix_uid45_fpTanPiTest_q;
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_q <= prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest(BITSELECT,610)@31
prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_in <= prodXY_uid610_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_q;
prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b <= prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_in(49 downto 24);
--invYO_uid302_tpix_uid45_fpTanPiTest(BITSELECT,301)@27
invYO_uid302_tpix_uid45_fpTanPiTest_in <= s2_uid605_uid608_invPE_q(31 downto 0);
invYO_uid302_tpix_uid45_fpTanPiTest_b <= invYO_uid302_tpix_uid45_fpTanPiTest_in(31 downto 31);
--fracYZero_uid261_tpix_uid45_fpTanPiTest(LOGICAL,260)@17
fracYZero_uid261_tpix_uid45_fpTanPiTest_a <= fracY_uid259_tpix_uid45_fpTanPiTest_b;
fracYZero_uid261_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracYZero_uid261_tpix_uid45_fpTanPiTest_q <= "1" when fracYZero_uid261_tpix_uid45_fpTanPiTest_a = fracYZero_uid261_tpix_uid45_fpTanPiTest_b else "0";
--ld_fracYZero_uid261_tpix_uid45_fpTanPiTest_q_to_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a(DELAY,1024)@17
ld_fracYZero_uid261_tpix_uid45_fpTanPiTest_q_to_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => fracYZero_uid261_tpix_uid45_fpTanPiTest_q, xout => ld_fracYZero_uid261_tpix_uid45_fpTanPiTest_q_to_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--fracYPostZ_uid303_tpix_uid45_fpTanPiTest(LOGICAL,302)@27
fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a <= ld_fracYZero_uid261_tpix_uid45_fpTanPiTest_q_to_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a_q;
fracYPostZ_uid303_tpix_uid45_fpTanPiTest_b <= invYO_uid302_tpix_uid45_fpTanPiTest_b;
fracYPostZ_uid303_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q <= fracYPostZ_uid303_tpix_uid45_fpTanPiTest_a or fracYPostZ_uid303_tpix_uid45_fpTanPiTest_b;
END IF;
END PROCESS;
--ld_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_b(DELAY,1028)@28
ld_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q, xout => ld_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest(MUX,308)@31
divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_s <= ld_fracYPostZ_uid303_tpix_uid45_fpTanPiTest_q_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_b_q;
divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest: PROCESS (divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_s, en, prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b, reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3_q)
BEGIN
CASE divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_s IS
WHEN "0" => divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q <= prodXYTruncFR_uid611_prodDivPreNormProd_uid305_tpix_uid45_fpTanPiTest_b;
WHEN "1" => divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q <= reg_oFracXExt_uid307_tpix_uid45_fpTanPiTest_0_to_divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_3_q;
WHEN OTHERS => divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--norm_uid310_tpix_uid45_fpTanPiTest(BITSELECT,309)@31
norm_uid310_tpix_uid45_fpTanPiTest_in <= divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q;
norm_uid310_tpix_uid45_fpTanPiTest_b <= norm_uid310_tpix_uid45_fpTanPiTest_in(25 downto 25);
--rndOp_uid316_tpix_uid45_fpTanPiTest(BITJOIN,315)@31
rndOp_uid316_tpix_uid45_fpTanPiTest_q <= norm_uid310_tpix_uid45_fpTanPiTest_b & cstAllZWF_uid53_spix_uid43_fpTanPiTest_q & VCC_q;
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor(LOGICAL,1569)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_b <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_q <= not (ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_a or ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_b);
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena(REG,1570)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_nor_q = "1") THEN
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd(LOGICAL,1571)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_a <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_sticky_ena_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_b <= en;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_a and ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_b;
--expXmY_uid295_tpix_uid45_fpTanPiTest(SUB,294)@17
expXmY_uid295_tpix_uid45_fpTanPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid255_tpix_uid45_fpTanPiTest_b);
expXmY_uid295_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid258_tpix_uid45_fpTanPiTest_b);
expXmY_uid295_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid295_tpix_uid45_fpTanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expXmY_uid295_tpix_uid45_fpTanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid295_tpix_uid45_fpTanPiTest_a) - UNSIGNED(expXmY_uid295_tpix_uid45_fpTanPiTest_b));
END IF;
END IF;
END PROCESS;
expXmY_uid295_tpix_uid45_fpTanPiTest_q <= expXmY_uid295_tpix_uid45_fpTanPiTest_o(8 downto 0);
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_inputreg(DELAY,1559)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expXmY_uid295_tpix_uid45_fpTanPiTest_q, xout => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem(DUALMEM,1560)
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_reset0 <= areset;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ia <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_inputreg_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_aa <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdreg_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ab <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_rdmux_q;
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 4,
numwords_a => 10,
width_b => 9,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_iq,
address_a => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_aa,
data_a => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_ia
);
ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_q <= ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_iq(8 downto 0);
--expR_uid296_tpix_uid45_fpTanPiTest(ADD,295)@30
expR_uid296_tpix_uid45_fpTanPiTest_a <= STD_LOGIC_VECTOR((10 downto 9 => ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_q(8)) & ld_expXmY_uid295_tpix_uid45_fpTanPiTest_q_to_expR_uid296_tpix_uid45_fpTanPiTest_a_replace_mem_q);
expR_uid296_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & biasM1_uid74_spix_uid43_fpTanPiTest_q);
expR_uid296_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expR_uid296_tpix_uid45_fpTanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expR_uid296_tpix_uid45_fpTanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid296_tpix_uid45_fpTanPiTest_a) + SIGNED(expR_uid296_tpix_uid45_fpTanPiTest_b));
END IF;
END IF;
END PROCESS;
expR_uid296_tpix_uid45_fpTanPiTest_q <= expR_uid296_tpix_uid45_fpTanPiTest_o(9 downto 0);
--divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest(BITSELECT,310)@31
divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_in <= divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q(24 downto 0);
divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_b <= divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_in(24 downto 1);
--divValPreNormLow_uid312_tpix_uid45_fpTanPiTest(BITSELECT,311)@31
divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_in <= divValPreNormTrunc_uid309_tpix_uid45_fpTanPiTest_q(23 downto 0);
divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_b <= divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_in(23 downto 0);
--normFracRnd_uid313_tpix_uid45_fpTanPiTest(MUX,312)@31
normFracRnd_uid313_tpix_uid45_fpTanPiTest_s <= norm_uid310_tpix_uid45_fpTanPiTest_b;
normFracRnd_uid313_tpix_uid45_fpTanPiTest: PROCESS (normFracRnd_uid313_tpix_uid45_fpTanPiTest_s, en, divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_b, divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_b)
BEGIN
CASE normFracRnd_uid313_tpix_uid45_fpTanPiTest_s IS
WHEN "0" => normFracRnd_uid313_tpix_uid45_fpTanPiTest_q <= divValPreNormLow_uid312_tpix_uid45_fpTanPiTest_b;
WHEN "1" => normFracRnd_uid313_tpix_uid45_fpTanPiTest_q <= divValPreNormHigh_uid311_tpix_uid45_fpTanPiTest_b;
WHEN OTHERS => normFracRnd_uid313_tpix_uid45_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRnd_uid314_tpix_uid45_fpTanPiTest(BITJOIN,313)@31
expFracRnd_uid314_tpix_uid45_fpTanPiTest_q <= expR_uid296_tpix_uid45_fpTanPiTest_q & normFracRnd_uid313_tpix_uid45_fpTanPiTest_q;
--expFracPostRnd_uid317_tpix_uid45_fpTanPiTest(ADD,316)@31
expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_a <= STD_LOGIC_VECTOR((35 downto 34 => expFracRnd_uid314_tpix_uid45_fpTanPiTest_q(33)) & expFracRnd_uid314_tpix_uid45_fpTanPiTest_q);
expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & rndOp_uid316_tpix_uid45_fpTanPiTest_q);
expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_a) + SIGNED(expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_b));
expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_q <= expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_o(34 downto 0);
--excRPreExc_uid320_tpix_uid45_fpTanPiTest(BITSELECT,319)@31
excRPreExc_uid320_tpix_uid45_fpTanPiTest_in <= expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_q(31 downto 0);
excRPreExc_uid320_tpix_uid45_fpTanPiTest_b <= excRPreExc_uid320_tpix_uid45_fpTanPiTest_in(31 downto 24);
--reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3(REG,768)@31
reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q <= excRPreExc_uid320_tpix_uid45_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d(DELAY,1087)@32
ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q, xout => ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2(REG,765)@17
reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q <= excRNaN_uid338_tpix_uid45_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q_to_concExc_uid339_tpix_uid45_fpTanPiTest_c(DELAY,1082)@18
ld_reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q_to_concExc_uid339_tpix_uid45_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q, xout => ld_reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q_to_concExc_uid339_tpix_uid45_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid290_tpix_uid45_fpTanPiTest(LOGICAL,289)@17
InvExc_N_uid290_tpix_uid45_fpTanPiTest_a <= exc_N_uid289_tpix_uid45_fpTanPiTest_q;
InvExc_N_uid290_tpix_uid45_fpTanPiTest_q <= not InvExc_N_uid290_tpix_uid45_fpTanPiTest_a;
--InvExc_I_uid291_tpix_uid45_fpTanPiTest(LOGICAL,290)@17
InvExc_I_uid291_tpix_uid45_fpTanPiTest_a <= exc_I_uid287_tpix_uid45_fpTanPiTest_q;
InvExc_I_uid291_tpix_uid45_fpTanPiTest_q <= not InvExc_I_uid291_tpix_uid45_fpTanPiTest_a;
--InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest(LOGICAL,291)@17
InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_a <= expXIsZero_uid282_tpix_uid45_fpTanPiTest_q;
InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_q <= not InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_a;
--exc_R_uid293_tpix_uid45_fpTanPiTest(LOGICAL,292)@17
exc_R_uid293_tpix_uid45_fpTanPiTest_a <= InvExpXIsZero_uid292_tpix_uid45_fpTanPiTest_q;
exc_R_uid293_tpix_uid45_fpTanPiTest_b <= InvExc_I_uid291_tpix_uid45_fpTanPiTest_q;
exc_R_uid293_tpix_uid45_fpTanPiTest_c <= InvExc_N_uid290_tpix_uid45_fpTanPiTest_q;
exc_R_uid293_tpix_uid45_fpTanPiTest_q <= exc_R_uid293_tpix_uid45_fpTanPiTest_a and exc_R_uid293_tpix_uid45_fpTanPiTest_b and exc_R_uid293_tpix_uid45_fpTanPiTest_c;
--excXIYR_uid334_tpix_uid45_fpTanPiTest(LOGICAL,333)@17
excXIYR_uid334_tpix_uid45_fpTanPiTest_a <= exc_I_uid271_tpix_uid45_fpTanPiTest_q;
excXIYR_uid334_tpix_uid45_fpTanPiTest_b <= exc_R_uid293_tpix_uid45_fpTanPiTest_q;
excXIYR_uid334_tpix_uid45_fpTanPiTest_q <= excXIYR_uid334_tpix_uid45_fpTanPiTest_a and excXIYR_uid334_tpix_uid45_fpTanPiTest_b;
--ld_excXIYR_uid334_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_d(DELAY,1071)@17
ld_excXIYR_uid334_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => excXIYR_uid334_tpix_uid45_fpTanPiTest_q, xout => ld_excXIYR_uid334_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--excXIYZ_uid333_tpix_uid45_fpTanPiTest(LOGICAL,332)@17
excXIYZ_uid333_tpix_uid45_fpTanPiTest_a <= exc_I_uid271_tpix_uid45_fpTanPiTest_q;
excXIYZ_uid333_tpix_uid45_fpTanPiTest_b <= expXIsZero_uid282_tpix_uid45_fpTanPiTest_q;
excXIYZ_uid333_tpix_uid45_fpTanPiTest_q <= excXIYZ_uid333_tpix_uid45_fpTanPiTest_a and excXIYZ_uid333_tpix_uid45_fpTanPiTest_b;
--ld_excXIYZ_uid333_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_c(DELAY,1070)@17
ld_excXIYZ_uid333_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => excXIYZ_uid333_tpix_uid45_fpTanPiTest_q, xout => ld_excXIYZ_uid333_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid321_tpix_uid45_fpTanPiTest(BITSELECT,320)@31
expRExt_uid321_tpix_uid45_fpTanPiTest_in <= expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_q;
expRExt_uid321_tpix_uid45_fpTanPiTest_b <= expRExt_uid321_tpix_uid45_fpTanPiTest_in(34 downto 24);
--reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1(REG,758)@31
reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q <= expRExt_uid321_tpix_uid45_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid325_tpix_uid45_fpTanPiTest(COMPARE,324)@32
expOvf_uid325_tpix_uid45_fpTanPiTest_cin <= GND_q;
expOvf_uid325_tpix_uid45_fpTanPiTest_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q(10)) & reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q) & '0';
expOvf_uid325_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid52_spix_uid43_fpTanPiTest_q) & expOvf_uid325_tpix_uid45_fpTanPiTest_cin(0);
expOvf_uid325_tpix_uid45_fpTanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid325_tpix_uid45_fpTanPiTest_a) - SIGNED(expOvf_uid325_tpix_uid45_fpTanPiTest_b));
expOvf_uid325_tpix_uid45_fpTanPiTest_n(0) <= not expOvf_uid325_tpix_uid45_fpTanPiTest_o(13);
--ld_exc_R_uid293_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_a(DELAY,1426)@17
ld_exc_R_uid293_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => exc_R_uid293_tpix_uid45_fpTanPiTest_q, xout => ld_exc_R_uid293_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3(REG,760)@31
reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_q <= ld_exc_R_uid293_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid274_tpix_uid45_fpTanPiTest(LOGICAL,273)@17
InvExc_N_uid274_tpix_uid45_fpTanPiTest_a <= exc_N_uid273_tpix_uid45_fpTanPiTest_q;
InvExc_N_uid274_tpix_uid45_fpTanPiTest_q <= not InvExc_N_uid274_tpix_uid45_fpTanPiTest_a;
--InvExc_I_uid275_tpix_uid45_fpTanPiTest(LOGICAL,274)@17
InvExc_I_uid275_tpix_uid45_fpTanPiTest_a <= exc_I_uid271_tpix_uid45_fpTanPiTest_q;
InvExc_I_uid275_tpix_uid45_fpTanPiTest_q <= not InvExc_I_uid275_tpix_uid45_fpTanPiTest_a;
--InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest(LOGICAL,275)@17
InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_a <= expXIsZero_uid266_tpix_uid45_fpTanPiTest_q;
InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_q <= not InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_a;
--exc_R_uid277_tpix_uid45_fpTanPiTest(LOGICAL,276)@17
exc_R_uid277_tpix_uid45_fpTanPiTest_a <= InvExpXIsZero_uid276_tpix_uid45_fpTanPiTest_q;
exc_R_uid277_tpix_uid45_fpTanPiTest_b <= InvExc_I_uid275_tpix_uid45_fpTanPiTest_q;
exc_R_uid277_tpix_uid45_fpTanPiTest_c <= InvExc_N_uid274_tpix_uid45_fpTanPiTest_q;
exc_R_uid277_tpix_uid45_fpTanPiTest_q <= exc_R_uid277_tpix_uid45_fpTanPiTest_a and exc_R_uid277_tpix_uid45_fpTanPiTest_b and exc_R_uid277_tpix_uid45_fpTanPiTest_c;
--reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1(REG,763)@17
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q <= exc_R_uid277_tpix_uid45_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a(DELAY,1061)@18
ld_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q, xout => ld_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXRYROvf_uid332_tpix_uid45_fpTanPiTest(LOGICAL,331)@32
excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a <= ld_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_1_q_to_excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a_q;
excXRYROvf_uid332_tpix_uid45_fpTanPiTest_b <= reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_q;
excXRYROvf_uid332_tpix_uid45_fpTanPiTest_c <= expOvf_uid325_tpix_uid45_fpTanPiTest_n;
excXRYROvf_uid332_tpix_uid45_fpTanPiTest_q <= excXRYROvf_uid332_tpix_uid45_fpTanPiTest_a and excXRYROvf_uid332_tpix_uid45_fpTanPiTest_b and excXRYROvf_uid332_tpix_uid45_fpTanPiTest_c;
--excXRYZ_uid331_tpix_uid45_fpTanPiTest(LOGICAL,330)@17
excXRYZ_uid331_tpix_uid45_fpTanPiTest_a <= exc_R_uid277_tpix_uid45_fpTanPiTest_q;
excXRYZ_uid331_tpix_uid45_fpTanPiTest_b <= expXIsZero_uid282_tpix_uid45_fpTanPiTest_q;
excXRYZ_uid331_tpix_uid45_fpTanPiTest_q <= excXRYZ_uid331_tpix_uid45_fpTanPiTest_a and excXRYZ_uid331_tpix_uid45_fpTanPiTest_b;
--ld_excXRYZ_uid331_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_a(DELAY,1068)@17
ld_excXRYZ_uid331_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => excXRYZ_uid331_tpix_uid45_fpTanPiTest_q, xout => ld_excXRYZ_uid331_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid335_tpix_uid45_fpTanPiTest(LOGICAL,334)@32
excRInf_uid335_tpix_uid45_fpTanPiTest_a <= ld_excXRYZ_uid331_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_a_q;
excRInf_uid335_tpix_uid45_fpTanPiTest_b <= excXRYROvf_uid332_tpix_uid45_fpTanPiTest_q;
excRInf_uid335_tpix_uid45_fpTanPiTest_c <= ld_excXIYZ_uid333_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_c_q;
excRInf_uid335_tpix_uid45_fpTanPiTest_d <= ld_excXIYR_uid334_tpix_uid45_fpTanPiTest_q_to_excRInf_uid335_tpix_uid45_fpTanPiTest_d_q;
excRInf_uid335_tpix_uid45_fpTanPiTest_q <= excRInf_uid335_tpix_uid45_fpTanPiTest_a or excRInf_uid335_tpix_uid45_fpTanPiTest_b or excRInf_uid335_tpix_uid45_fpTanPiTest_c or excRInf_uid335_tpix_uid45_fpTanPiTest_d;
--reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2(REG,761)@17
reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2_q <= exc_I_uid287_tpix_uid45_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--xRegOrZero_uid328_tpix_uid45_fpTanPiTest(LOGICAL,327)@17
xRegOrZero_uid328_tpix_uid45_fpTanPiTest_a <= exc_R_uid277_tpix_uid45_fpTanPiTest_q;
xRegOrZero_uid328_tpix_uid45_fpTanPiTest_b <= expXIsZero_uid266_tpix_uid45_fpTanPiTest_q;
xRegOrZero_uid328_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xRegOrZero_uid328_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
xRegOrZero_uid328_tpix_uid45_fpTanPiTest_q <= xRegOrZero_uid328_tpix_uid45_fpTanPiTest_a or xRegOrZero_uid328_tpix_uid45_fpTanPiTest_b;
END IF;
END PROCESS;
--regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest(LOGICAL,328)@18
regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_a <= xRegOrZero_uid328_tpix_uid45_fpTanPiTest_q;
regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_b <= reg_exc_I_uid287_tpix_uid45_fpTanPiTest_0_to_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_2_q;
regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q <= regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_a and regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_b;
--ld_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_c(DELAY,1058)@18
ld_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q, xout => ld_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid277_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_a(DELAY,1425)@17
ld_exc_R_uid277_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => exc_R_uid277_tpix_uid45_fpTanPiTest_q, xout => ld_exc_R_uid277_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2(REG,759)@31
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_q <= ld_exc_R_uid277_tpix_uid45_fpTanPiTest_q_to_reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--expUdf_uid322_tpix_uid45_fpTanPiTest(COMPARE,321)@32
expUdf_uid322_tpix_uid45_fpTanPiTest_cin <= GND_q;
expUdf_uid322_tpix_uid45_fpTanPiTest_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid322_tpix_uid45_fpTanPiTest_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q(10)) & reg_expRExt_uid321_tpix_uid45_fpTanPiTest_0_to_expUdf_uid322_tpix_uid45_fpTanPiTest_1_q) & expUdf_uid322_tpix_uid45_fpTanPiTest_cin(0);
expUdf_uid322_tpix_uid45_fpTanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid322_tpix_uid45_fpTanPiTest_a) - SIGNED(expUdf_uid322_tpix_uid45_fpTanPiTest_b));
expUdf_uid322_tpix_uid45_fpTanPiTest_n(0) <= not expUdf_uid322_tpix_uid45_fpTanPiTest_o(13);
--regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest(LOGICAL,326)@32
regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_a <= expUdf_uid322_tpix_uid45_fpTanPiTest_n;
regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_b <= reg_exc_R_uid277_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_2_q;
regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_c <= reg_exc_R_uid293_tpix_uid45_fpTanPiTest_0_to_regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_3_q;
regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_q <= regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_a and regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_b and regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_c;
--zeroOverReg_uid326_tpix_uid45_fpTanPiTest(LOGICAL,325)@17
zeroOverReg_uid326_tpix_uid45_fpTanPiTest_a <= expXIsZero_uid266_tpix_uid45_fpTanPiTest_q;
zeroOverReg_uid326_tpix_uid45_fpTanPiTest_b <= exc_R_uid293_tpix_uid45_fpTanPiTest_q;
zeroOverReg_uid326_tpix_uid45_fpTanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q <= zeroOverReg_uid326_tpix_uid45_fpTanPiTest_a and zeroOverReg_uid326_tpix_uid45_fpTanPiTest_b;
END IF;
END PROCESS;
--ld_zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_a(DELAY,1056)@18
ld_zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q, xout => ld_zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid330_tpix_uid45_fpTanPiTest(LOGICAL,329)@32
excRZero_uid330_tpix_uid45_fpTanPiTest_a <= ld_zeroOverReg_uid326_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_a_q;
excRZero_uid330_tpix_uid45_fpTanPiTest_b <= regOverRegWithUf_uid327_tpix_uid45_fpTanPiTest_q;
excRZero_uid330_tpix_uid45_fpTanPiTest_c <= ld_regOrZeroOverInf_uid329_tpix_uid45_fpTanPiTest_q_to_excRZero_uid330_tpix_uid45_fpTanPiTest_c_q;
excRZero_uid330_tpix_uid45_fpTanPiTest_q <= excRZero_uid330_tpix_uid45_fpTanPiTest_a or excRZero_uid330_tpix_uid45_fpTanPiTest_b or excRZero_uid330_tpix_uid45_fpTanPiTest_c;
--concExc_uid339_tpix_uid45_fpTanPiTest(BITJOIN,338)@32
concExc_uid339_tpix_uid45_fpTanPiTest_q <= ld_reg_excRNaN_uid338_tpix_uid45_fpTanPiTest_0_to_concExc_uid339_tpix_uid45_fpTanPiTest_2_q_to_concExc_uid339_tpix_uid45_fpTanPiTest_c_q & excRInf_uid335_tpix_uid45_fpTanPiTest_q & excRZero_uid330_tpix_uid45_fpTanPiTest_q;
--reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0(REG,766)@32
reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0_q <= concExc_uid339_tpix_uid45_fpTanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid340_tpix_uid45_fpTanPiTest(LOOKUP,339)@33
excREnc_uid340_tpix_uid45_fpTanPiTest: PROCESS (reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid339_tpix_uid45_fpTanPiTest_0_to_excREnc_uid340_tpix_uid45_fpTanPiTest_0_q) IS
WHEN "000" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "01";
WHEN "001" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "00";
WHEN "010" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "10";
WHEN "011" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "00";
WHEN "100" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "11";
WHEN "101" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "00";
WHEN "110" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "00";
WHEN "111" => excREnc_uid340_tpix_uid45_fpTanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid340_tpix_uid45_fpTanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid348_tpix_uid45_fpTanPiTest(MUX,347)@33
expRPostExc_uid348_tpix_uid45_fpTanPiTest_s <= excREnc_uid340_tpix_uid45_fpTanPiTest_q;
expRPostExc_uid348_tpix_uid45_fpTanPiTest: PROCESS (expRPostExc_uid348_tpix_uid45_fpTanPiTest_s, en, cstAllZWE_uid8_fpTanPiTest_q, ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d_q, cstAllOWE_uid52_spix_uid43_fpTanPiTest_q, cstAllOWE_uid52_spix_uid43_fpTanPiTest_q)
BEGIN
CASE expRPostExc_uid348_tpix_uid45_fpTanPiTest_s IS
WHEN "00" => expRPostExc_uid348_tpix_uid45_fpTanPiTest_q <= cstAllZWE_uid8_fpTanPiTest_q;
WHEN "01" => expRPostExc_uid348_tpix_uid45_fpTanPiTest_q <= ld_reg_excRPreExc_uid320_tpix_uid45_fpTanPiTest_0_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_3_q_to_expRPostExc_uid348_tpix_uid45_fpTanPiTest_d_q;
WHEN "10" => expRPostExc_uid348_tpix_uid45_fpTanPiTest_q <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
WHEN "11" => expRPostExc_uid348_tpix_uid45_fpTanPiTest_q <= cstAllOWE_uid52_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => expRPostExc_uid348_tpix_uid45_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid319_tpix_uid45_fpTanPiTest(BITSELECT,318)@31
fracRPreExc_uid319_tpix_uid45_fpTanPiTest_in <= expFracPostRnd_uid317_tpix_uid45_fpTanPiTest_q(23 downto 0);
fracRPreExc_uid319_tpix_uid45_fpTanPiTest_b <= fracRPreExc_uid319_tpix_uid45_fpTanPiTest_in(23 downto 1);
--reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3(REG,767)@31
reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q <= fracRPreExc_uid319_tpix_uid45_fpTanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d(DELAY,1085)@32
ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q, xout => ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid344_tpix_uid45_fpTanPiTest(MUX,343)@33
fracRPostExc_uid344_tpix_uid45_fpTanPiTest_s <= excREnc_uid340_tpix_uid45_fpTanPiTest_q;
fracRPostExc_uid344_tpix_uid45_fpTanPiTest: PROCESS (fracRPostExc_uid344_tpix_uid45_fpTanPiTest_s, en, cstAllZWF_uid53_spix_uid43_fpTanPiTest_q, ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d_q, cstAllZWF_uid53_spix_uid43_fpTanPiTest_q, oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q)
BEGIN
CASE fracRPostExc_uid344_tpix_uid45_fpTanPiTest_s IS
WHEN "00" => fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
WHEN "01" => fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q <= ld_reg_fracRPreExc_uid319_tpix_uid45_fpTanPiTest_0_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_3_q_to_fracRPostExc_uid344_tpix_uid45_fpTanPiTest_d_q;
WHEN "10" => fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q <= cstAllZWF_uid53_spix_uid43_fpTanPiTest_q;
WHEN "11" => fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q <= oneFracRPostExc2_uid137_spix_uid43_fpTanPiTest_q;
WHEN OTHERS => fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--divR_uid351_tpix_uid45_fpTanPiTest(BITJOIN,350)@33
divR_uid351_tpix_uid45_fpTanPiTest_q <= ld_sRPostExc_uid350_tpix_uid45_fpTanPiTest_q_to_divR_uid351_tpix_uid45_fpTanPiTest_c_q & expRPostExc_uid348_tpix_uid45_fpTanPiTest_q & fracRPostExc_uid344_tpix_uid45_fpTanPiTest_q;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor(LOGICAL,1447)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_notEnable_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_b <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_q <= not (ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_a or ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_b);
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_mem_top(CONSTANT,1443)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_mem_top_q <= "011110";
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp(LOGICAL,1444)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_mem_top_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q);
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_q <= "1" when ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_a = ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_b else "0";
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg(REG,1445)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena(REG,1448)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_nor_q = "1") THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd(LOGICAL,1449)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_a <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_sticky_ena_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_b <= en;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_a and ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_b;
--join_uid46_fpTanPiTest(BITJOIN,45)@0
join_uid46_fpTanPiTest_q <= expXIsZero_uid10_fpTanPiTest_q & tanXIsX_uid28_fpTanPiTest_c;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_inputreg(DELAY,1437)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid46_fpTanPiTest_q, xout => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt(COUNTER,1439)
-- every=1, low=0, high=30, step=1, init=1
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i = 29 THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_eq = '1') THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i - 30;
ELSE
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_i,5));
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg(REG,1440)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux(MUX,1441)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_s <= en;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux: PROCESS (ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_s, ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q, ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem(DUALMEM,1438)
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_reset0 <= areset;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ia <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_inputreg_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_aa <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdreg_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ab <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_rdmux_q;
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 31,
width_b => 2,
widthad_b => 5,
numwords_b => 31,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_iq,
address_a => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_aa,
data_a => ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_ia
);
ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_q <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_iq(1 downto 0);
--xIn(GPIN,3)@0
--tanPiXOutMux_uid47_fpTanPiTest(MUX,46)@33
tanPiXOutMux_uid47_fpTanPiTest_s <= ld_join_uid46_fpTanPiTest_q_to_tanPiXOutMux_uid47_fpTanPiTest_b_replace_mem_q;
tanPiXOutMux_uid47_fpTanPiTest: PROCESS (tanPiXOutMux_uid47_fpTanPiTest_s, en, divR_uid351_tpix_uid45_fpTanPiTest_q, ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_q, ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q, ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q)
BEGIN
CASE tanPiXOutMux_uid47_fpTanPiTest_s IS
WHEN "00" => tanPiXOutMux_uid47_fpTanPiTest_q <= divR_uid351_tpix_uid45_fpTanPiTest_q;
WHEN "01" => tanPiXOutMux_uid47_fpTanPiTest_q <= ld_reg_join_uid41_fpTanPiTest_0_to_tanPiXOutMux_uid47_fpTanPiTest_3_q_to_tanPiXOutMux_uid47_fpTanPiTest_d_replace_mem_q;
WHEN "10" => tanPiXOutMux_uid47_fpTanPiTest_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q;
WHEN "11" => tanPiXOutMux_uid47_fpTanPiTest_q <= ld_xIn_a_to_tanPiXOutMux_uid47_fpTanPiTest_e_replace_mem_q;
WHEN OTHERS => tanPiXOutMux_uid47_fpTanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--xOut(GPOUT,4)@33
q <= tanPiXOutMux_uid47_fpTanPiTest_q;
end normal;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_invsqr_lut0.vhd
|
10
|
37363
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse Root ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_invsqr_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_invsqr_lut0;
ARCHITECTURE rtl OF fp_invsqr_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1047553,20);
WHEN "000000010" => data <= conv_std_logic_vector(1046534,20);
WHEN "000000011" => data <= conv_std_logic_vector(1045517,20);
WHEN "000000100" => data <= conv_std_logic_vector(1044503,20);
WHEN "000000101" => data <= conv_std_logic_vector(1043493,20);
WHEN "000000110" => data <= conv_std_logic_vector(1042485,20);
WHEN "000000111" => data <= conv_std_logic_vector(1041480,20);
WHEN "000001000" => data <= conv_std_logic_vector(1040478,20);
WHEN "000001001" => data <= conv_std_logic_vector(1039479,20);
WHEN "000001010" => data <= conv_std_logic_vector(1038483,20);
WHEN "000001011" => data <= conv_std_logic_vector(1037490,20);
WHEN "000001100" => data <= conv_std_logic_vector(1036500,20);
WHEN "000001101" => data <= conv_std_logic_vector(1035512,20);
WHEN "000001110" => data <= conv_std_logic_vector(1034527,20);
WHEN "000001111" => data <= conv_std_logic_vector(1033545,20);
WHEN "000010000" => data <= conv_std_logic_vector(1032566,20);
WHEN "000010001" => data <= conv_std_logic_vector(1031589,20);
WHEN "000010010" => data <= conv_std_logic_vector(1030616,20);
WHEN "000010011" => data <= conv_std_logic_vector(1029645,20);
WHEN "000010100" => data <= conv_std_logic_vector(1028677,20);
WHEN "000010101" => data <= conv_std_logic_vector(1027711,20);
WHEN "000010110" => data <= conv_std_logic_vector(1026749,20);
WHEN "000010111" => data <= conv_std_logic_vector(1025789,20);
WHEN "000011000" => data <= conv_std_logic_vector(1024831,20);
WHEN "000011001" => data <= conv_std_logic_vector(1023877,20);
WHEN "000011010" => data <= conv_std_logic_vector(1022925,20);
WHEN "000011011" => data <= conv_std_logic_vector(1021975,20);
WHEN "000011100" => data <= conv_std_logic_vector(1021029,20);
WHEN "000011101" => data <= conv_std_logic_vector(1020084,20);
WHEN "000011110" => data <= conv_std_logic_vector(1019143,20);
WHEN "000011111" => data <= conv_std_logic_vector(1018204,20);
WHEN "000100000" => data <= conv_std_logic_vector(1017268,20);
WHEN "000100001" => data <= conv_std_logic_vector(1016334,20);
WHEN "000100010" => data <= conv_std_logic_vector(1015403,20);
WHEN "000100011" => data <= conv_std_logic_vector(1014474,20);
WHEN "000100100" => data <= conv_std_logic_vector(1013548,20);
WHEN "000100101" => data <= conv_std_logic_vector(1012625,20);
WHEN "000100110" => data <= conv_std_logic_vector(1011704,20);
WHEN "000100111" => data <= conv_std_logic_vector(1010785,20);
WHEN "000101000" => data <= conv_std_logic_vector(1009869,20);
WHEN "000101001" => data <= conv_std_logic_vector(1008956,20);
WHEN "000101010" => data <= conv_std_logic_vector(1008045,20);
WHEN "000101011" => data <= conv_std_logic_vector(1007136,20);
WHEN "000101100" => data <= conv_std_logic_vector(1006230,20);
WHEN "000101101" => data <= conv_std_logic_vector(1005327,20);
WHEN "000101110" => data <= conv_std_logic_vector(1004425,20);
WHEN "000101111" => data <= conv_std_logic_vector(1003527,20);
WHEN "000110000" => data <= conv_std_logic_vector(1002630,20);
WHEN "000110001" => data <= conv_std_logic_vector(1001736,20);
WHEN "000110010" => data <= conv_std_logic_vector(1000845,20);
WHEN "000110011" => data <= conv_std_logic_vector(999955,20);
WHEN "000110100" => data <= conv_std_logic_vector(999068,20);
WHEN "000110101" => data <= conv_std_logic_vector(998184,20);
WHEN "000110110" => data <= conv_std_logic_vector(997302,20);
WHEN "000110111" => data <= conv_std_logic_vector(996422,20);
WHEN "000111000" => data <= conv_std_logic_vector(995544,20);
WHEN "000111001" => data <= conv_std_logic_vector(994669,20);
WHEN "000111010" => data <= conv_std_logic_vector(993796,20);
WHEN "000111011" => data <= conv_std_logic_vector(992926,20);
WHEN "000111100" => data <= conv_std_logic_vector(992057,20);
WHEN "000111101" => data <= conv_std_logic_vector(991191,20);
WHEN "000111110" => data <= conv_std_logic_vector(990327,20);
WHEN "000111111" => data <= conv_std_logic_vector(989466,20);
WHEN "001000000" => data <= conv_std_logic_vector(988607,20);
WHEN "001000001" => data <= conv_std_logic_vector(987750,20);
WHEN "001000010" => data <= conv_std_logic_vector(986895,20);
WHEN "001000011" => data <= conv_std_logic_vector(986042,20);
WHEN "001000100" => data <= conv_std_logic_vector(985192,20);
WHEN "001000101" => data <= conv_std_logic_vector(984344,20);
WHEN "001000110" => data <= conv_std_logic_vector(983498,20);
WHEN "001000111" => data <= conv_std_logic_vector(982654,20);
WHEN "001001000" => data <= conv_std_logic_vector(981812,20);
WHEN "001001001" => data <= conv_std_logic_vector(980973,20);
WHEN "001001010" => data <= conv_std_logic_vector(980135,20);
WHEN "001001011" => data <= conv_std_logic_vector(979300,20);
WHEN "001001100" => data <= conv_std_logic_vector(978467,20);
WHEN "001001101" => data <= conv_std_logic_vector(977636,20);
WHEN "001001110" => data <= conv_std_logic_vector(976807,20);
WHEN "001001111" => data <= conv_std_logic_vector(975980,20);
WHEN "001010000" => data <= conv_std_logic_vector(975156,20);
WHEN "001010001" => data <= conv_std_logic_vector(974333,20);
WHEN "001010010" => data <= conv_std_logic_vector(973513,20);
WHEN "001010011" => data <= conv_std_logic_vector(972694,20);
WHEN "001010100" => data <= conv_std_logic_vector(971878,20);
WHEN "001010101" => data <= conv_std_logic_vector(971063,20);
WHEN "001010110" => data <= conv_std_logic_vector(970251,20);
WHEN "001010111" => data <= conv_std_logic_vector(969441,20);
WHEN "001011000" => data <= conv_std_logic_vector(968633,20);
WHEN "001011001" => data <= conv_std_logic_vector(967827,20);
WHEN "001011010" => data <= conv_std_logic_vector(967022,20);
WHEN "001011011" => data <= conv_std_logic_vector(966220,20);
WHEN "001011100" => data <= conv_std_logic_vector(965420,20);
WHEN "001011101" => data <= conv_std_logic_vector(964622,20);
WHEN "001011110" => data <= conv_std_logic_vector(963826,20);
WHEN "001011111" => data <= conv_std_logic_vector(963031,20);
WHEN "001100000" => data <= conv_std_logic_vector(962239,20);
WHEN "001100001" => data <= conv_std_logic_vector(961449,20);
WHEN "001100010" => data <= conv_std_logic_vector(960660,20);
WHEN "001100011" => data <= conv_std_logic_vector(959874,20);
WHEN "001100100" => data <= conv_std_logic_vector(959089,20);
WHEN "001100101" => data <= conv_std_logic_vector(958307,20);
WHEN "001100110" => data <= conv_std_logic_vector(957526,20);
WHEN "001100111" => data <= conv_std_logic_vector(956747,20);
WHEN "001101000" => data <= conv_std_logic_vector(955970,20);
WHEN "001101001" => data <= conv_std_logic_vector(955195,20);
WHEN "001101010" => data <= conv_std_logic_vector(954422,20);
WHEN "001101011" => data <= conv_std_logic_vector(953651,20);
WHEN "001101100" => data <= conv_std_logic_vector(952882,20);
WHEN "001101101" => data <= conv_std_logic_vector(952114,20);
WHEN "001101110" => data <= conv_std_logic_vector(951348,20);
WHEN "001101111" => data <= conv_std_logic_vector(950585,20);
WHEN "001110000" => data <= conv_std_logic_vector(949823,20);
WHEN "001110001" => data <= conv_std_logic_vector(949062,20);
WHEN "001110010" => data <= conv_std_logic_vector(948304,20);
WHEN "001110011" => data <= conv_std_logic_vector(947548,20);
WHEN "001110100" => data <= conv_std_logic_vector(946793,20);
WHEN "001110101" => data <= conv_std_logic_vector(946040,20);
WHEN "001110110" => data <= conv_std_logic_vector(945289,20);
WHEN "001110111" => data <= conv_std_logic_vector(944539,20);
WHEN "001111000" => data <= conv_std_logic_vector(943792,20);
WHEN "001111001" => data <= conv_std_logic_vector(943046,20);
WHEN "001111010" => data <= conv_std_logic_vector(942302,20);
WHEN "001111011" => data <= conv_std_logic_vector(941560,20);
WHEN "001111100" => data <= conv_std_logic_vector(940819,20);
WHEN "001111101" => data <= conv_std_logic_vector(940081,20);
WHEN "001111110" => data <= conv_std_logic_vector(939344,20);
WHEN "001111111" => data <= conv_std_logic_vector(938608,20);
WHEN "010000000" => data <= conv_std_logic_vector(937875,20);
WHEN "010000001" => data <= conv_std_logic_vector(937143,20);
WHEN "010000010" => data <= conv_std_logic_vector(936413,20);
WHEN "010000011" => data <= conv_std_logic_vector(935684,20);
WHEN "010000100" => data <= conv_std_logic_vector(934957,20);
WHEN "010000101" => data <= conv_std_logic_vector(934232,20);
WHEN "010000110" => data <= conv_std_logic_vector(933509,20);
WHEN "010000111" => data <= conv_std_logic_vector(932787,20);
WHEN "010001000" => data <= conv_std_logic_vector(932067,20);
WHEN "010001001" => data <= conv_std_logic_vector(931349,20);
WHEN "010001010" => data <= conv_std_logic_vector(930632,20);
WHEN "010001011" => data <= conv_std_logic_vector(929917,20);
WHEN "010001100" => data <= conv_std_logic_vector(929204,20);
WHEN "010001101" => data <= conv_std_logic_vector(928492,20);
WHEN "010001110" => data <= conv_std_logic_vector(927782,20);
WHEN "010001111" => data <= conv_std_logic_vector(927073,20);
WHEN "010010000" => data <= conv_std_logic_vector(926367,20);
WHEN "010010001" => data <= conv_std_logic_vector(925661,20);
WHEN "010010010" => data <= conv_std_logic_vector(924958,20);
WHEN "010010011" => data <= conv_std_logic_vector(924256,20);
WHEN "010010100" => data <= conv_std_logic_vector(923555,20);
WHEN "010010101" => data <= conv_std_logic_vector(922856,20);
WHEN "010010110" => data <= conv_std_logic_vector(922159,20);
WHEN "010010111" => data <= conv_std_logic_vector(921463,20);
WHEN "010011000" => data <= conv_std_logic_vector(920769,20);
WHEN "010011001" => data <= conv_std_logic_vector(920077,20);
WHEN "010011010" => data <= conv_std_logic_vector(919386,20);
WHEN "010011011" => data <= conv_std_logic_vector(918696,20);
WHEN "010011100" => data <= conv_std_logic_vector(918008,20);
WHEN "010011101" => data <= conv_std_logic_vector(917322,20);
WHEN "010011110" => data <= conv_std_logic_vector(916637,20);
WHEN "010011111" => data <= conv_std_logic_vector(915954,20);
WHEN "010100000" => data <= conv_std_logic_vector(915272,20);
WHEN "010100001" => data <= conv_std_logic_vector(914592,20);
WHEN "010100010" => data <= conv_std_logic_vector(913913,20);
WHEN "010100011" => data <= conv_std_logic_vector(913236,20);
WHEN "010100100" => data <= conv_std_logic_vector(912560,20);
WHEN "010100101" => data <= conv_std_logic_vector(911886,20);
WHEN "010100110" => data <= conv_std_logic_vector(911213,20);
WHEN "010100111" => data <= conv_std_logic_vector(910542,20);
WHEN "010101000" => data <= conv_std_logic_vector(909872,20);
WHEN "010101001" => data <= conv_std_logic_vector(909204,20);
WHEN "010101010" => data <= conv_std_logic_vector(908537,20);
WHEN "010101011" => data <= conv_std_logic_vector(907872,20);
WHEN "010101100" => data <= conv_std_logic_vector(907208,20);
WHEN "010101101" => data <= conv_std_logic_vector(906545,20);
WHEN "010101110" => data <= conv_std_logic_vector(905884,20);
WHEN "010101111" => data <= conv_std_logic_vector(905225,20);
WHEN "010110000" => data <= conv_std_logic_vector(904567,20);
WHEN "010110001" => data <= conv_std_logic_vector(903910,20);
WHEN "010110010" => data <= conv_std_logic_vector(903255,20);
WHEN "010110011" => data <= conv_std_logic_vector(902601,20);
WHEN "010110100" => data <= conv_std_logic_vector(901949,20);
WHEN "010110101" => data <= conv_std_logic_vector(901298,20);
WHEN "010110110" => data <= conv_std_logic_vector(900648,20);
WHEN "010110111" => data <= conv_std_logic_vector(900000,20);
WHEN "010111000" => data <= conv_std_logic_vector(899353,20);
WHEN "010111001" => data <= conv_std_logic_vector(898708,20);
WHEN "010111010" => data <= conv_std_logic_vector(898064,20);
WHEN "010111011" => data <= conv_std_logic_vector(897421,20);
WHEN "010111100" => data <= conv_std_logic_vector(896780,20);
WHEN "010111101" => data <= conv_std_logic_vector(896140,20);
WHEN "010111110" => data <= conv_std_logic_vector(895501,20);
WHEN "010111111" => data <= conv_std_logic_vector(894864,20);
WHEN "011000000" => data <= conv_std_logic_vector(894228,20);
WHEN "011000001" => data <= conv_std_logic_vector(893594,20);
WHEN "011000010" => data <= conv_std_logic_vector(892961,20);
WHEN "011000011" => data <= conv_std_logic_vector(892329,20);
WHEN "011000100" => data <= conv_std_logic_vector(891699,20);
WHEN "011000101" => data <= conv_std_logic_vector(891070,20);
WHEN "011000110" => data <= conv_std_logic_vector(890442,20);
WHEN "011000111" => data <= conv_std_logic_vector(889816,20);
WHEN "011001000" => data <= conv_std_logic_vector(889191,20);
WHEN "011001001" => data <= conv_std_logic_vector(888567,20);
WHEN "011001010" => data <= conv_std_logic_vector(887944,20);
WHEN "011001011" => data <= conv_std_logic_vector(887323,20);
WHEN "011001100" => data <= conv_std_logic_vector(886703,20);
WHEN "011001101" => data <= conv_std_logic_vector(886085,20);
WHEN "011001110" => data <= conv_std_logic_vector(885467,20);
WHEN "011001111" => data <= conv_std_logic_vector(884851,20);
WHEN "011010000" => data <= conv_std_logic_vector(884237,20);
WHEN "011010001" => data <= conv_std_logic_vector(883623,20);
WHEN "011010010" => data <= conv_std_logic_vector(883011,20);
WHEN "011010011" => data <= conv_std_logic_vector(882400,20);
WHEN "011010100" => data <= conv_std_logic_vector(881791,20);
WHEN "011010101" => data <= conv_std_logic_vector(881182,20);
WHEN "011010110" => data <= conv_std_logic_vector(880575,20);
WHEN "011010111" => data <= conv_std_logic_vector(879969,20);
WHEN "011011000" => data <= conv_std_logic_vector(879365,20);
WHEN "011011001" => data <= conv_std_logic_vector(878762,20);
WHEN "011011010" => data <= conv_std_logic_vector(878159,20);
WHEN "011011011" => data <= conv_std_logic_vector(877559,20);
WHEN "011011100" => data <= conv_std_logic_vector(876959,20);
WHEN "011011101" => data <= conv_std_logic_vector(876361,20);
WHEN "011011110" => data <= conv_std_logic_vector(875763,20);
WHEN "011011111" => data <= conv_std_logic_vector(875167,20);
WHEN "011100000" => data <= conv_std_logic_vector(874573,20);
WHEN "011100001" => data <= conv_std_logic_vector(873979,20);
WHEN "011100010" => data <= conv_std_logic_vector(873387,20);
WHEN "011100011" => data <= conv_std_logic_vector(872796,20);
WHEN "011100100" => data <= conv_std_logic_vector(872206,20);
WHEN "011100101" => data <= conv_std_logic_vector(871617,20);
WHEN "011100110" => data <= conv_std_logic_vector(871030,20);
WHEN "011100111" => data <= conv_std_logic_vector(870443,20);
WHEN "011101000" => data <= conv_std_logic_vector(869858,20);
WHEN "011101001" => data <= conv_std_logic_vector(869274,20);
WHEN "011101010" => data <= conv_std_logic_vector(868691,20);
WHEN "011101011" => data <= conv_std_logic_vector(868110,20);
WHEN "011101100" => data <= conv_std_logic_vector(867529,20);
WHEN "011101101" => data <= conv_std_logic_vector(866950,20);
WHEN "011101110" => data <= conv_std_logic_vector(866372,20);
WHEN "011101111" => data <= conv_std_logic_vector(865795,20);
WHEN "011110000" => data <= conv_std_logic_vector(865219,20);
WHEN "011110001" => data <= conv_std_logic_vector(864644,20);
WHEN "011110010" => data <= conv_std_logic_vector(864070,20);
WHEN "011110011" => data <= conv_std_logic_vector(863498,20);
WHEN "011110100" => data <= conv_std_logic_vector(862927,20);
WHEN "011110101" => data <= conv_std_logic_vector(862357,20);
WHEN "011110110" => data <= conv_std_logic_vector(861788,20);
WHEN "011110111" => data <= conv_std_logic_vector(861220,20);
WHEN "011111000" => data <= conv_std_logic_vector(860653,20);
WHEN "011111001" => data <= conv_std_logic_vector(860087,20);
WHEN "011111010" => data <= conv_std_logic_vector(859523,20);
WHEN "011111011" => data <= conv_std_logic_vector(858959,20);
WHEN "011111100" => data <= conv_std_logic_vector(858397,20);
WHEN "011111101" => data <= conv_std_logic_vector(857836,20);
WHEN "011111110" => data <= conv_std_logic_vector(857276,20);
WHEN "011111111" => data <= conv_std_logic_vector(856717,20);
WHEN "100000000" => data <= conv_std_logic_vector(856159,20);
WHEN "100000001" => data <= conv_std_logic_vector(855602,20);
WHEN "100000010" => data <= conv_std_logic_vector(855046,20);
WHEN "100000011" => data <= conv_std_logic_vector(854491,20);
WHEN "100000100" => data <= conv_std_logic_vector(853938,20);
WHEN "100000101" => data <= conv_std_logic_vector(853385,20);
WHEN "100000110" => data <= conv_std_logic_vector(852834,20);
WHEN "100000111" => data <= conv_std_logic_vector(852283,20);
WHEN "100001000" => data <= conv_std_logic_vector(851734,20);
WHEN "100001001" => data <= conv_std_logic_vector(851186,20);
WHEN "100001010" => data <= conv_std_logic_vector(850638,20);
WHEN "100001011" => data <= conv_std_logic_vector(850092,20);
WHEN "100001100" => data <= conv_std_logic_vector(849547,20);
WHEN "100001101" => data <= conv_std_logic_vector(849003,20);
WHEN "100001110" => data <= conv_std_logic_vector(848460,20);
WHEN "100001111" => data <= conv_std_logic_vector(847918,20);
WHEN "100010000" => data <= conv_std_logic_vector(847377,20);
WHEN "100010001" => data <= conv_std_logic_vector(846837,20);
WHEN "100010010" => data <= conv_std_logic_vector(846298,20);
WHEN "100010011" => data <= conv_std_logic_vector(845761,20);
WHEN "100010100" => data <= conv_std_logic_vector(845224,20);
WHEN "100010101" => data <= conv_std_logic_vector(844688,20);
WHEN "100010110" => data <= conv_std_logic_vector(844153,20);
WHEN "100010111" => data <= conv_std_logic_vector(843619,20);
WHEN "100011000" => data <= conv_std_logic_vector(843087,20);
WHEN "100011001" => data <= conv_std_logic_vector(842555,20);
WHEN "100011010" => data <= conv_std_logic_vector(842024,20);
WHEN "100011011" => data <= conv_std_logic_vector(841494,20);
WHEN "100011100" => data <= conv_std_logic_vector(840966,20);
WHEN "100011101" => data <= conv_std_logic_vector(840438,20);
WHEN "100011110" => data <= conv_std_logic_vector(839911,20);
WHEN "100011111" => data <= conv_std_logic_vector(839385,20);
WHEN "100100000" => data <= conv_std_logic_vector(838861,20);
WHEN "100100001" => data <= conv_std_logic_vector(838337,20);
WHEN "100100010" => data <= conv_std_logic_vector(837814,20);
WHEN "100100011" => data <= conv_std_logic_vector(837292,20);
WHEN "100100100" => data <= conv_std_logic_vector(836771,20);
WHEN "100100101" => data <= conv_std_logic_vector(836251,20);
WHEN "100100110" => data <= conv_std_logic_vector(835733,20);
WHEN "100100111" => data <= conv_std_logic_vector(835215,20);
WHEN "100101000" => data <= conv_std_logic_vector(834698,20);
WHEN "100101001" => data <= conv_std_logic_vector(834182,20);
WHEN "100101010" => data <= conv_std_logic_vector(833666,20);
WHEN "100101011" => data <= conv_std_logic_vector(833152,20);
WHEN "100101100" => data <= conv_std_logic_vector(832639,20);
WHEN "100101101" => data <= conv_std_logic_vector(832127,20);
WHEN "100101110" => data <= conv_std_logic_vector(831616,20);
WHEN "100101111" => data <= conv_std_logic_vector(831105,20);
WHEN "100110000" => data <= conv_std_logic_vector(830596,20);
WHEN "100110001" => data <= conv_std_logic_vector(830087,20);
WHEN "100110010" => data <= conv_std_logic_vector(829580,20);
WHEN "100110011" => data <= conv_std_logic_vector(829073,20);
WHEN "100110100" => data <= conv_std_logic_vector(828568,20);
WHEN "100110101" => data <= conv_std_logic_vector(828063,20);
WHEN "100110110" => data <= conv_std_logic_vector(827559,20);
WHEN "100110111" => data <= conv_std_logic_vector(827056,20);
WHEN "100111000" => data <= conv_std_logic_vector(826554,20);
WHEN "100111001" => data <= conv_std_logic_vector(826053,20);
WHEN "100111010" => data <= conv_std_logic_vector(825553,20);
WHEN "100111011" => data <= conv_std_logic_vector(825053,20);
WHEN "100111100" => data <= conv_std_logic_vector(824555,20);
WHEN "100111101" => data <= conv_std_logic_vector(824058,20);
WHEN "100111110" => data <= conv_std_logic_vector(823561,20);
WHEN "100111111" => data <= conv_std_logic_vector(823065,20);
WHEN "101000000" => data <= conv_std_logic_vector(822571,20);
WHEN "101000001" => data <= conv_std_logic_vector(822077,20);
WHEN "101000010" => data <= conv_std_logic_vector(821584,20);
WHEN "101000011" => data <= conv_std_logic_vector(821092,20);
WHEN "101000100" => data <= conv_std_logic_vector(820600,20);
WHEN "101000101" => data <= conv_std_logic_vector(820110,20);
WHEN "101000110" => data <= conv_std_logic_vector(819621,20);
WHEN "101000111" => data <= conv_std_logic_vector(819132,20);
WHEN "101001000" => data <= conv_std_logic_vector(818644,20);
WHEN "101001001" => data <= conv_std_logic_vector(818157,20);
WHEN "101001010" => data <= conv_std_logic_vector(817671,20);
WHEN "101001011" => data <= conv_std_logic_vector(817186,20);
WHEN "101001100" => data <= conv_std_logic_vector(816702,20);
WHEN "101001101" => data <= conv_std_logic_vector(816219,20);
WHEN "101001110" => data <= conv_std_logic_vector(815736,20);
WHEN "101001111" => data <= conv_std_logic_vector(815254,20);
WHEN "101010000" => data <= conv_std_logic_vector(814774,20);
WHEN "101010001" => data <= conv_std_logic_vector(814294,20);
WHEN "101010010" => data <= conv_std_logic_vector(813814,20);
WHEN "101010011" => data <= conv_std_logic_vector(813336,20);
WHEN "101010100" => data <= conv_std_logic_vector(812859,20);
WHEN "101010101" => data <= conv_std_logic_vector(812382,20);
WHEN "101010110" => data <= conv_std_logic_vector(811906,20);
WHEN "101010111" => data <= conv_std_logic_vector(811431,20);
WHEN "101011000" => data <= conv_std_logic_vector(810957,20);
WHEN "101011001" => data <= conv_std_logic_vector(810484,20);
WHEN "101011010" => data <= conv_std_logic_vector(810012,20);
WHEN "101011011" => data <= conv_std_logic_vector(809540,20);
WHEN "101011100" => data <= conv_std_logic_vector(809069,20);
WHEN "101011101" => data <= conv_std_logic_vector(808599,20);
WHEN "101011110" => data <= conv_std_logic_vector(808130,20);
WHEN "101011111" => data <= conv_std_logic_vector(807662,20);
WHEN "101100000" => data <= conv_std_logic_vector(807194,20);
WHEN "101100001" => data <= conv_std_logic_vector(806727,20);
WHEN "101100010" => data <= conv_std_logic_vector(806261,20);
WHEN "101100011" => data <= conv_std_logic_vector(805796,20);
WHEN "101100100" => data <= conv_std_logic_vector(805332,20);
WHEN "101100101" => data <= conv_std_logic_vector(804869,20);
WHEN "101100110" => data <= conv_std_logic_vector(804406,20);
WHEN "101100111" => data <= conv_std_logic_vector(803944,20);
WHEN "101101000" => data <= conv_std_logic_vector(803483,20);
WHEN "101101001" => data <= conv_std_logic_vector(803023,20);
WHEN "101101010" => data <= conv_std_logic_vector(802563,20);
WHEN "101101011" => data <= conv_std_logic_vector(802104,20);
WHEN "101101100" => data <= conv_std_logic_vector(801646,20);
WHEN "101101101" => data <= conv_std_logic_vector(801189,20);
WHEN "101101110" => data <= conv_std_logic_vector(800733,20);
WHEN "101101111" => data <= conv_std_logic_vector(800277,20);
WHEN "101110000" => data <= conv_std_logic_vector(799822,20);
WHEN "101110001" => data <= conv_std_logic_vector(799368,20);
WHEN "101110010" => data <= conv_std_logic_vector(798915,20);
WHEN "101110011" => data <= conv_std_logic_vector(798462,20);
WHEN "101110100" => data <= conv_std_logic_vector(798011,20);
WHEN "101110101" => data <= conv_std_logic_vector(797560,20);
WHEN "101110110" => data <= conv_std_logic_vector(797109,20);
WHEN "101110111" => data <= conv_std_logic_vector(796660,20);
WHEN "101111000" => data <= conv_std_logic_vector(796211,20);
WHEN "101111001" => data <= conv_std_logic_vector(795763,20);
WHEN "101111010" => data <= conv_std_logic_vector(795316,20);
WHEN "101111011" => data <= conv_std_logic_vector(794870,20);
WHEN "101111100" => data <= conv_std_logic_vector(794424,20);
WHEN "101111101" => data <= conv_std_logic_vector(793979,20);
WHEN "101111110" => data <= conv_std_logic_vector(793535,20);
WHEN "101111111" => data <= conv_std_logic_vector(793092,20);
WHEN "110000000" => data <= conv_std_logic_vector(792649,20);
WHEN "110000001" => data <= conv_std_logic_vector(792207,20);
WHEN "110000010" => data <= conv_std_logic_vector(791766,20);
WHEN "110000011" => data <= conv_std_logic_vector(791325,20);
WHEN "110000100" => data <= conv_std_logic_vector(790885,20);
WHEN "110000101" => data <= conv_std_logic_vector(790446,20);
WHEN "110000110" => data <= conv_std_logic_vector(790008,20);
WHEN "110000111" => data <= conv_std_logic_vector(789571,20);
WHEN "110001000" => data <= conv_std_logic_vector(789134,20);
WHEN "110001001" => data <= conv_std_logic_vector(788698,20);
WHEN "110001010" => data <= conv_std_logic_vector(788262,20);
WHEN "110001011" => data <= conv_std_logic_vector(787828,20);
WHEN "110001100" => data <= conv_std_logic_vector(787394,20);
WHEN "110001101" => data <= conv_std_logic_vector(786960,20);
WHEN "110001110" => data <= conv_std_logic_vector(786528,20);
WHEN "110001111" => data <= conv_std_logic_vector(786096,20);
WHEN "110010000" => data <= conv_std_logic_vector(785665,20);
WHEN "110010001" => data <= conv_std_logic_vector(785235,20);
WHEN "110010010" => data <= conv_std_logic_vector(784805,20);
WHEN "110010011" => data <= conv_std_logic_vector(784376,20);
WHEN "110010100" => data <= conv_std_logic_vector(783948,20);
WHEN "110010101" => data <= conv_std_logic_vector(783520,20);
WHEN "110010110" => data <= conv_std_logic_vector(783093,20);
WHEN "110010111" => data <= conv_std_logic_vector(782667,20);
WHEN "110011000" => data <= conv_std_logic_vector(782242,20);
WHEN "110011001" => data <= conv_std_logic_vector(781817,20);
WHEN "110011010" => data <= conv_std_logic_vector(781393,20);
WHEN "110011011" => data <= conv_std_logic_vector(780969,20);
WHEN "110011100" => data <= conv_std_logic_vector(780547,20);
WHEN "110011101" => data <= conv_std_logic_vector(780125,20);
WHEN "110011110" => data <= conv_std_logic_vector(779703,20);
WHEN "110011111" => data <= conv_std_logic_vector(779283,20);
WHEN "110100000" => data <= conv_std_logic_vector(778863,20);
WHEN "110100001" => data <= conv_std_logic_vector(778443,20);
WHEN "110100010" => data <= conv_std_logic_vector(778025,20);
WHEN "110100011" => data <= conv_std_logic_vector(777607,20);
WHEN "110100100" => data <= conv_std_logic_vector(777189,20);
WHEN "110100101" => data <= conv_std_logic_vector(776773,20);
WHEN "110100110" => data <= conv_std_logic_vector(776357,20);
WHEN "110100111" => data <= conv_std_logic_vector(775942,20);
WHEN "110101000" => data <= conv_std_logic_vector(775527,20);
WHEN "110101001" => data <= conv_std_logic_vector(775113,20);
WHEN "110101010" => data <= conv_std_logic_vector(774700,20);
WHEN "110101011" => data <= conv_std_logic_vector(774287,20);
WHEN "110101100" => data <= conv_std_logic_vector(773875,20);
WHEN "110101101" => data <= conv_std_logic_vector(773464,20);
WHEN "110101110" => data <= conv_std_logic_vector(773053,20);
WHEN "110101111" => data <= conv_std_logic_vector(772643,20);
WHEN "110110000" => data <= conv_std_logic_vector(772234,20);
WHEN "110110001" => data <= conv_std_logic_vector(771825,20);
WHEN "110110010" => data <= conv_std_logic_vector(771417,20);
WHEN "110110011" => data <= conv_std_logic_vector(771010,20);
WHEN "110110100" => data <= conv_std_logic_vector(770603,20);
WHEN "110110101" => data <= conv_std_logic_vector(770197,20);
WHEN "110110110" => data <= conv_std_logic_vector(769791,20);
WHEN "110110111" => data <= conv_std_logic_vector(769387,20);
WHEN "110111000" => data <= conv_std_logic_vector(768982,20);
WHEN "110111001" => data <= conv_std_logic_vector(768579,20);
WHEN "110111010" => data <= conv_std_logic_vector(768176,20);
WHEN "110111011" => data <= conv_std_logic_vector(767774,20);
WHEN "110111100" => data <= conv_std_logic_vector(767372,20);
WHEN "110111101" => data <= conv_std_logic_vector(766971,20);
WHEN "110111110" => data <= conv_std_logic_vector(766570,20);
WHEN "110111111" => data <= conv_std_logic_vector(766171,20);
WHEN "111000000" => data <= conv_std_logic_vector(765772,20);
WHEN "111000001" => data <= conv_std_logic_vector(765373,20);
WHEN "111000010" => data <= conv_std_logic_vector(764975,20);
WHEN "111000011" => data <= conv_std_logic_vector(764578,20);
WHEN "111000100" => data <= conv_std_logic_vector(764181,20);
WHEN "111000101" => data <= conv_std_logic_vector(763785,20);
WHEN "111000110" => data <= conv_std_logic_vector(763390,20);
WHEN "111000111" => data <= conv_std_logic_vector(762995,20);
WHEN "111001000" => data <= conv_std_logic_vector(762601,20);
WHEN "111001001" => data <= conv_std_logic_vector(762207,20);
WHEN "111001010" => data <= conv_std_logic_vector(761814,20);
WHEN "111001011" => data <= conv_std_logic_vector(761422,20);
WHEN "111001100" => data <= conv_std_logic_vector(761030,20);
WHEN "111001101" => data <= conv_std_logic_vector(760639,20);
WHEN "111001110" => data <= conv_std_logic_vector(760248,20);
WHEN "111001111" => data <= conv_std_logic_vector(759858,20);
WHEN "111010000" => data <= conv_std_logic_vector(759469,20);
WHEN "111010001" => data <= conv_std_logic_vector(759080,20);
WHEN "111010010" => data <= conv_std_logic_vector(758692,20);
WHEN "111010011" => data <= conv_std_logic_vector(758304,20);
WHEN "111010100" => data <= conv_std_logic_vector(757917,20);
WHEN "111010101" => data <= conv_std_logic_vector(757531,20);
WHEN "111010110" => data <= conv_std_logic_vector(757145,20);
WHEN "111010111" => data <= conv_std_logic_vector(756760,20);
WHEN "111011000" => data <= conv_std_logic_vector(756375,20);
WHEN "111011001" => data <= conv_std_logic_vector(755991,20);
WHEN "111011010" => data <= conv_std_logic_vector(755608,20);
WHEN "111011011" => data <= conv_std_logic_vector(755225,20);
WHEN "111011100" => data <= conv_std_logic_vector(754843,20);
WHEN "111011101" => data <= conv_std_logic_vector(754461,20);
WHEN "111011110" => data <= conv_std_logic_vector(754080,20);
WHEN "111011111" => data <= conv_std_logic_vector(753699,20);
WHEN "111100000" => data <= conv_std_logic_vector(753319,20);
WHEN "111100001" => data <= conv_std_logic_vector(752940,20);
WHEN "111100010" => data <= conv_std_logic_vector(752561,20);
WHEN "111100011" => data <= conv_std_logic_vector(752183,20);
WHEN "111100100" => data <= conv_std_logic_vector(751805,20);
WHEN "111100101" => data <= conv_std_logic_vector(751428,20);
WHEN "111100110" => data <= conv_std_logic_vector(751051,20);
WHEN "111100111" => data <= conv_std_logic_vector(750675,20);
WHEN "111101000" => data <= conv_std_logic_vector(750300,20);
WHEN "111101001" => data <= conv_std_logic_vector(749925,20);
WHEN "111101010" => data <= conv_std_logic_vector(749551,20);
WHEN "111101011" => data <= conv_std_logic_vector(749177,20);
WHEN "111101100" => data <= conv_std_logic_vector(748804,20);
WHEN "111101101" => data <= conv_std_logic_vector(748431,20);
WHEN "111101110" => data <= conv_std_logic_vector(748059,20);
WHEN "111101111" => data <= conv_std_logic_vector(747687,20);
WHEN "111110000" => data <= conv_std_logic_vector(747317,20);
WHEN "111110001" => data <= conv_std_logic_vector(746946,20);
WHEN "111110010" => data <= conv_std_logic_vector(746576,20);
WHEN "111110011" => data <= conv_std_logic_vector(746207,20);
WHEN "111110100" => data <= conv_std_logic_vector(745838,20);
WHEN "111110101" => data <= conv_std_logic_vector(745470,20);
WHEN "111110110" => data <= conv_std_logic_vector(745102,20);
WHEN "111110111" => data <= conv_std_logic_vector(744735,20);
WHEN "111111000" => data <= conv_std_logic_vector(744369,20);
WHEN "111111001" => data <= conv_std_logic_vector(744002,20);
WHEN "111111010" => data <= conv_std_logic_vector(743637,20);
WHEN "111111011" => data <= conv_std_logic_vector(743272,20);
WHEN "111111100" => data <= conv_std_logic_vector(742908,20);
WHEN "111111101" => data <= conv_std_logic_vector(742544,20);
WHEN "111111110" => data <= conv_std_logic_vector(742180,20);
WHEN "111111111" => data <= conv_std_logic_vector(741817,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_invsqr_core.vhd
|
10
|
8541
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** FP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 36 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_core IS
GENERIC (
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_core;
ARCHITECTURE rtl OF fp_invsqr_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(36 DOWNTO 18),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 12 LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 12 LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>36,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone,databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
invroot <= multonethr(36 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_clz36.vhd
|
10
|
4897
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_mul18usus.vhd
|
10
|
4361
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_mul18usus.vhd
|
10
|
4361
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_div_est.vhd
|
10
|
6558
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse ***
--*** ***
--*** Used by both single and double dividers ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_div_est;
ARCHITECTURE rtl OF fp_div_est IS
type twodelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type ziplutdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (17 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal twodelff : twodelfftype;
signal ziplutdelff : ziplutdelfftype;
signal invdivisorff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 17 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= divisor(18 DOWNTO 10);
two <= divisor(9 DOWNTO 1);
-- these register seperate to make the LUTs into memories
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
onelutff <= onelut;
ziplutff <= ziplut;
END IF;
END IF;
END PROCESS;
upper: fp_div_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_div_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 20 LOOP
invdivisorff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invdivisorff <= ziplutdelff(2)(20 DOWNTO 1) -
(zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
invdivisor <= invdivisorff(20 DOWNTO 3);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_implementation.vhd
|
10
|
516240
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27S_L2.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 mixed sign ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 2 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27S_L2 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27S_L2;
architecture rtl of hcc_MA2_27Ux27S_L2 is
constant PROD_WIDTH : positive := widthaa + widthbb + 1;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg : signed(widthaa+1 downto 1);
signal b0_reg, b1_reg : signed(widthbb downto 1);
signal p0_res, p1_res : signed(SUM2_WIDTH downto 1);
signal s1_reg : signed(SUM2_WIDTH downto 1);
begin
-- first DSP block
p0_res <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= SIGNED('0' & a0);
b0_reg <= SIGNED(b0);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= SIGNED('0' & a1);
b1_reg <= SIGNED(b1);
s1_reg <= p0_res + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27U_L2.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 unsigned ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 2 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27U_L2 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27U_L2;
architecture rtl of hcc_MA2_27Ux27U_L2 is
constant PROD_WIDTH : positive := widthaa + widthbb;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg : unsigned(widthaa downto 1);
signal b0_reg, b1_reg : unsigned(widthbb downto 1);
signal p0_res, p1_res : unsigned(SUM2_WIDTH downto 1);
signal s1_reg : unsigned(SUM2_WIDTH downto 1);
begin
-- first DSP block
p0_res <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= UNSIGNED(a0);
b0_reg <= UNSIGNED(b0);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= UNSIGNED(a1);
b1_reg <= UNSIGNED(b1);
s1_reg <= p0_res + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27U_L3.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 unsigned ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 3 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27U_L3 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27U_L3;
architecture rtl of hcc_MA2_27Ux27U_L3 is
constant PROD_WIDTH : positive := widthaa+widthbb;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg, a1_del_reg : unsigned(widthaa downto 1);
signal b0_reg, b1_reg, b1_del_reg : unsigned(widthbb downto 1);
signal p0_reg, p1_res : unsigned(SUM2_WIDTH downto 1);
signal s1_reg : unsigned(SUM2_WIDTH downto 1);
begin
-- external registers to match pipeline delay
process (clk, aclr)
begin
if (aclr = '1') then
a1_del_reg <= (others => '0');
b1_del_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (en = '1') then
a1_del_reg <= UNSIGNED(a1);
b1_del_reg <= UNSIGNED(b1);
end if;
end if;
end process;
-- first DSP block
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
p0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= UNSIGNED(a0);
b0_reg <= UNSIGNED(b0);
p0_reg <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= a1_del_reg;
b1_reg <= b1_del_reg;
s1_reg <= p0_reg + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPEB.VHD ***
--*** ***
--*** Function: Behavioral Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipeb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipeb;
ARCHITECTURE rtl of hcc_addpipeb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
ccnode <= aa + bb + (zerovec & carryin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPES.VHD ***
--*** ***
--*** Function: Synthesizable Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipes IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipes;
ARCHITECTURE syn of hcc_addpipes IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-- same as v1 except 32 bit mantissa input Normalize to base level on output
ENTITY hcc_aludot_v2 IS
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_aludot_v2;
ARCHITECTURE rtl OF hcc_aludot_v2 IS
constant iopipe : integer := 0;
constant shiftspeed : integer := 0;
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal exponentnormff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal invertleftff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal invertrightff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normalizeff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (4+shiftspeed DOWNTO 1);
signal mantissaleft : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaright : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissarightbus : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal alucarrybitnode, normalizecarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftmantissaleft, shiftmantissaright : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normalizenode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normshift : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO 32 LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aasign;
bbsignff <= bbsign;
aamantissaff <= aamantissa;
bbmantissaff <= bbmantissa;
aaexponentff <= aaexponent;
bbexponentff <= bbexponent;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (iopipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (iopipe = 0) GENERATE
aasignnode <= aasign;
bbsignnode <= bbsign;
aamantissanode <= aamantissa;
bbmantissanode <= bbmantissa;
aaexponentnode <= aaexponent;
bbexponentnode <= bbexponent;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
-- mantissa [27:1] will be "0001XXX" or "001XXX"
gen_shift_two: FOR k IN 1 TO 32 GENERATE
mantissaleft(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissaright(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
exponentnormff <= conv_std_logic_vector (0,10);
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO 32 LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
normalizeff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissaleftff <= mantissaleft;
mantissarightff <= mantissaright;
-- only use if shiftspeed = 1
--mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
exponentbaseff(2)(10 DOWNTO 1) <= exponentbaseff(1)(10 DOWNTO 1) - 129;
FOR k IN 3 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
exponentnormff <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1) + ("00000000" & normshift);
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
invertrightff(3+shiftspeed) <= invertrightff(2+shiftspeed);
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode;-- + alucarrybitnode;
normalizeff <= normalizenode;-- + normalizecarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 4+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO 32 GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
normalizecarrybitnode <= invertrightff(3+shiftspeed);
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
mantissarightbus <= mantissarightff;
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightbus,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightbus,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
-- maximum input mantissas are "001XXX" + "001XXX", maximum aluff is "01XXX"
-- or negative equivalent "100XXX"
-- need to shift to 0001XXXX
prc_norm: PROCESS (aluff)
BEGIN
CASE aluff(32 DOWNTO 29) IS
WHEN "0000" => normshift <= "00";
WHEN "0001" => normshift <= "01";
WHEN "0010" => normshift <= "10";
WHEN "0011" => normshift <= "10";
WHEN "0100" => normshift <= "11";
WHEN "0101" => normshift <= "11";
WHEN "0110" => normshift <= "11";
WHEN "0111" => normshift <= "11";
WHEN "1000" => normshift <= "11";
WHEN "1001" => normshift <= "11";
WHEN "1010" => normshift <= "11";
WHEN "1011" => normshift <= "11";
WHEN "1100" => normshift <= "10";
WHEN "1101" => normshift <= "10";
WHEN "1110" => normshift <= "01";
WHEN "1111" => normshift <= "00";
WHEN others => normshift <= "00";
END CASE;
END PROCESS;
gen_norm: FOR k IN 1 TO 29 GENERATE
normalizenode(k) <= (aluff(k) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(k+1) AND NOT(normshift(2)) AND normshift(1)) OR
(aluff(k+2) AND normshift(2) AND NOT(normshift(1))) OR
(aluff(k+3) AND normshift(2) AND normshift(1));
END GENERATE;
normalizenode(30) <= (aluff(30) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(31) AND NOT(normshift(2)) AND normshift(1)) OR
(aluff(32) AND normshift(2));
normalizenode(31) <= (aluff(31) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(32) AND (normshift(2) OR normshift(1)));
normalizenode(32) <= aluff(32);
--*** OUTPUT ***
cc <= normalizeff & exponentnormff;
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
ccnan <= ccnanff(4+shiftspeed);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1_DOT.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder (Signed Magnitude for first level ***
--*** Vector Optimized Structure) ***
--*** ***
--*** 15/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--*** TBD - what if exponents negative ***
ENTITY hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1_dot;
ARCHITECTURE rtl OF hcc_alufp1_dot IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO mantissa LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
bbsatff <= '0';
aazipff <= '0';
bbzipff <= '0';
aananff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aa(mantissa+10);
bbsignff <= bb(mantissa+10);
aamantissaff <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissaff <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentff <= aa(10 DOWNTO 1);
bbexponentff <= bb(10 DOWNTO 1);
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aasignnode <= aa(mantissa+10);
bbsignnode <= bb(mantissa+10);
aamantissanode <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissanode <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentnode <= aa(10 DOWNTO 1);
bbexponentnode <= bb(10 DOWNTO 1);
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissarightff(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** 04/05/10 - optimized structure ***
--*** 15/10/10 - bug in shiftcheckbit ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aanode, bbnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal addsubctlff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aanode <= aaff;
bbnode <= bbff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aanode <= aa;
bbnode <= bb;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3+shiftspeed LOOP
addsubctlff(k) <= addsub_resetval;
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addsubctlff(1) <= addsubnode;
FOR k IN 2 TO 2+shiftspeed LOOP
addsubctlff(k) <= addsubctlff(k-1);
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aanode(k+10) AND NOT(switch)) OR (bbnode(k+10) AND switch);
mantissarightff(k) <= (bbnode(k+10) AND NOT(switch)) OR (aanode(k+10) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aanode(k) AND NOT(switch)) OR (bbnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= addsubnode AND switch;
invertrightff(1) <= addsubnode AND NOT(switch);
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
alucarrybitnode <= addsubctlff(2+shiftspeed);
subexponentone <= aanode(10 DOWNTO 1) - bbnode(10 DOWNTO 1);
subexponenttwo <= bbnode(10 DOWNTO 1) - aanode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
-- 15/10/10 - was down to exponentshiftff(5) - zeroed any shift >= 16. Old design was ok because it
-- used shiftcheck subtract 31, not caught because unlikely to cause differences for small designs
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= addsub_resetval;
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR aasatff OR bbsatff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
ccnanff(k) <= ccnanff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
ccnan <= ccnanff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOF.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** IEEE Single Format ***
--*** ***
--*** 11/11/09 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 2 ***
--***************************************************
ENTITY hcc_castdtof IS
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtof;
ARCHITECTURE rtl OF hcc_castdtof IS
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal signnode : STD_LOGIC;
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentbiasnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaprenode, mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal upperrangecheck, lowerrangecheck : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal overrangenode, underrangenode : STD_LOGIC;
signal exponentmaxnode, zipnode, mantissanonzeronode : STD_LOGIC;
signal saturatenode, nannode, zeronode : STD_LOGIC;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 32 LOOP
ccff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
ccff <= signnode & exponentnode & mantissanode;
END IF;
END IF;
END PROCESS;
signnode <= aaff(64);
gmana: FOR k IN 1 TO 23 GENERATE
mantissanode(k) <= (mantissaprenode(k) OR nannode) AND NOT(zeronode) AND NOT(overrangenode);
END GENERATE;
gexpa: FOR k IN 1 TO 8 GENERATE
exponentnode(k) <= (exponentbiasnode(k) OR overrangenode OR nannode) AND NOT(zeronode);
END GENERATE;
-- if exponent = 2047 => saturate, if 0 => 0
exponentmaxnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
mantissanonzeronode <= aaff(52) OR aaff(51) OR aaff(50) OR aaff(49) OR
aaff(48) OR aaff(47) OR aaff(46) OR aaff(45) OR
aaff(44) OR aaff(43) OR aaff(42) OR aaff(41) OR
aaff(40) OR aaff(39) OR aaff(38) OR aaff(37) OR
aaff(36) OR aaff(35) OR aaff(34) OR aaff(33) OR
aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR
aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR
aaff(24) OR aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
upperrangecheck <= aaff(63 DOWNTO 53) - 1151; -- 1150 = 254, 1151 = 255
lowerrangecheck <= aaff(63 DOWNTO 53) - 897; -- 897 = 1, 896 = 0
overrangenode <= NOT(upperrangecheck(11)) AND NOT(lowerrangecheck(11)) AND NOT(nannode);
underrangenode <= lowerrangecheck(11);
saturatenode <= overrangenode AND NOT(mantissanonzeronode);
nannode <= exponentmaxnode AND mantissanonzeronode;
zeronode <= zipnode OR underrangenode;
exponentbiasnode <= aaff(63 DOWNTO 53) - 896;
gra: IF (roundconvert = 0) GENERATE
mantissaprenode <= aaff(52 DOWNTO 30);
END GENERATE;
grb: IF (roundconvert = 1) GENERATE
mantissaprenode <= aaff(52 DOWNTO 30) + aaff(29);
END GENERATE;
-- OUTPUTS
cc <= ccff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** if (swRoundConvert == 0 && ***
--*** swOutputPipe == 0) : ***
--*** 1 + swNormSpeed + 1 ***
--*** else ***
--*** 2 + swDoubleSpeed*swRoundConvert + ***
--*** swNormSpeed + 1 ***
--***************************************************
ENTITY hcc_castdtol IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtol;
ARCHITECTURE rtl OF hcc_castdtol IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,outputpipe=>1,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytol
GENERIC MAP (normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** if (swRoundConvert == 0 && ***
--*** swOutputPipe == 0) : 1 ***
--*** else ***
--*** 2 + swDoubleSpeed*swRoundConvert ***
--***************************************************
ENTITY hcc_castdtoy IS
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castdtoy;
ARCHITECTURE rtl OF hcc_castdtoy IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (53+11*target DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expmaxnode, zipnode, mannonzeronode : STD_LOGIC;
signal satnode, nannode : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentff : exponentfftype;
signal satdelff, zipdelff, nandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- ieee754: sign (64), 8 exponent (63:53), 52 mantissa (52:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(13:1)
-- multiplier, divider : (SIGN)('1')(52:1), exponent(13:1)
-- (multiplier & divider use unsigned numbers, sign packed with input)
gza: IF (roundconvert = 1) GENERATE
gzb: FOR k IN 1 TO 53+11*target GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
-- if exponent = 1023 => saturate, if 0 => 0
expmaxnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
mannonzeronode <= aaff(52) OR aaff(51) OR aaff(50) OR aaff(49) OR
aaff(48) OR aaff(47) OR aaff(46) OR aaff(45) OR
aaff(44) OR aaff(43) OR aaff(42) OR aaff(41) OR
aaff(40) OR aaff(39) OR aaff(38) OR aaff(37) OR
aaff(36) OR aaff(35) OR aaff(34) OR aaff(33) OR
aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR
aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR
aaff(24) OR aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
satnode <= expmaxnode AND NOT(mannonzeronode);
nannode <= expmaxnode AND mannonzeronode;
gexpa: FOR k IN 1 TO 11 GENERATE
expnode(k) <= (aaff(k+52) OR expmaxnode) AND NOT(zipnode);
END GENERATE;
expnode(12) <= '0';
expnode(13) <= '0';
--**************************************
--*** direct to multipier or divider ***
--**************************************
gmda: IF (target = 0) GENERATE
-- already in "01"&mantissa format used by multiplier and divider
fracnode <= aaff(64) & '1' & aaff(52 DOWNTO 1);
gmdb: IF (outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
gmdc: IF (outputpipe = 1) GENERATE
pmda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 67 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fracnode & expnode;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
END GENERATE;
--***********************
--*** internal format ***
--***********************
gxa: IF (target = 1) GENERATE
fracnode(64) <= aaff(64);
fracnode(63) <= aaff(64);
fracnode(62) <= aaff(64);
fracnode(61) <= aaff(64);
fracnode(60) <= aaff(64);
fracnode(59) <= NOT(aaff(64)); -- '1' XOR sign
gfa: FOR k IN 1 TO 52 GENERATE
fracnode(k+6)<= (aaff(k) XOR aaff(64));
END GENERATE;
gfb: FOR k IN 1 TO 6 GENERATE
fracnode(k)<= aaff(64); -- '0' XOR sign
END GENERATE;
--*** OUTPUT STAGE(S) ***
gsa: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
gsb: IF (outputpipe = 1 AND
((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0))) GENERATE
gsc: IF (roundconvert = 0) GENERATE
mantissanode <= fracnode;
END GENERATE;
gsd: IF (roundconvert = 1) GENERATE
mantissanode <= fracnode + (zerovec(63 DOWNTO 1) & aaff(64));
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= mantissanode & expnode;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
gse: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsf: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
prcb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
END LOOP;
satdelff <= "00";
zipdelff <= "00";
nandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentff(1)(13 DOWNTO 1) <= expnode;
exponentff(2)(13 DOWNTO 1) <= exponentff(1)(13 DOWNTO 1);
satdelff(1) <= satnode;
satdelff(2) <= satdelff(1);
zipdelff(1) <= zipnode;
zipdelff(2) <= zipdelff(1);
nandelff(1) <= nannode;
nandelff(2) <= nandelff(1);
END IF;
END IF;
END PROCESS;
cc <= mantissanode & exponentff(2)(13 DOWNTO 1);
ccsat <= satdelff(2);
cczip <= zipdelff(2);
ccnan <= nandelff(2);
END GENERATE;
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOD.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** IEEE Double Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 2 ***
--***************************************************
ENTITY hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castftod;
ARCHITECTURE rtl OF hcc_castftod IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal signnode : STD_LOGIC;
signal exponentnode, exponentbiasnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal tailnode : STD_LOGIC_VECTOR (29 DOWNTO 1);
signal exponentmaxnode, zipnode, mantissanonzeronode : STD_LOGIC;
signal saturatenode, nannode : STD_LOGIC;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
-- FOR k IN 1 TO 32 LOOP
-- aaff(k) <= '0';
-- END LOOP;
FOR k IN 1 TO 64 LOOP
ccff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= signnode & exponentnode & mantissanode;
END IF;
END IF;
END PROCESS;
aaff <= aa;
signnode <= aaff(32);
mantissanode <= aaff(23 DOWNTO 1) & "00000000000000000000000000000";
gexpa: FOR k IN 1 TO 11 GENERATE
exponentnode(k) <= (exponentbiasnode(k) OR exponentmaxnode) AND NOT(zipnode);
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
exponentmaxnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
-- mantissanonzeronode <= aaff(23) OR aaff(22) OR aaff(21) OR
-- aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
-- aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
-- aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
-- aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
-- aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
saturatenode <= exponentmaxnode AND NOT(mantissanonzeronode);
nannode <= exponentmaxnode AND mantissanonzeronode;
-- gta: FOR k IN 1 TO 29 GENERATE
-- tailnode(k) <= nannode;
-- END GENERATE;
exponentbiasnode <= ("000" & aaff(31 DOWNTO 24)) + 896;
-- OUTPUTS
cc <= ccff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 3 + swSingleNormSpeed ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - divider mantissa aa to aaff ***
--*** 16/04/09 - add NAN support ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 1 + swOutputPipe (target = 0,1) ***
--*** 1 (target = 2) ***
--***************************************************
ENTITY hcc_castftox IS
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castftox;
ARCHITECTURE rtl OF hcc_castftox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmaxnode, mannonzeronode : STD_LOGIC;
signal satnode, zipnode, nannode : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC;
BEGIN
-- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1)
-- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1)
-- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x)
gza: IF (roundconvert = 1) GENERATE
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gro: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fractional & exponent;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
expmaxnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
mannonzeronode <= aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
satnode <= expmaxnode AND NOT(mannonzeronode);
nannode <= expmaxnode AND mannonzeronode;
gexpa: FOR k IN 1 TO 8 GENERATE
expnode(k) <= (aaff(k+23) OR expmaxnode) AND NOT(zipnode);
END GENERATE;
expnode(9) <= '0';
expnode(10) <= '0';
--*** internal format ***
gxa: IF (target = 0) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= aaff(32);
fracnode(mantissa-2) <= aaff(32);
fracnode(mantissa-3) <= aaff(32);
fracnode(mantissa-4) <= aaff(32);
fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign
gxb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gxc: FOR k IN 1 TO mantissa-29 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gxd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gxe: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
exponent <= expnode;
END GENERATE;
--*** direct to multiplier ***
gma: IF (target = 1) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign
gmb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gmc: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gmd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gme: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
-- never register output
--*** direct to divider ***
gda: IF (target = 2) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= '1';
fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1);
gfb: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= '0';
END GENERATE;
fractional <= fracnode;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
--*** OUTPUTS ***
goa: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
gob: IF ((target = 0 AND outputpipe = 0) OR
(target = 1 AND outputpipe = 0) OR
(target = 2)) GENERATE
cc <= fractional & exponent;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- castftoy : float <=> internal double
ENTITY hcc_castftoy IS
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castftoy;
ARCHITECTURE rtl OF hcc_castftoy IS
signal floatnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
-- if ftoy target divider or multiplier, need unsigned output
-- if ftoy target = 1 (internal), ftox target = 0, xtoy target = 1
-- if ftoy target = 0 (multiplier, divider), ftox target = 2 (divider), xtoy target = 0 (mult&div)
gaa: IF (target = 1) GENERATE
one: hcc_castftox
GENERIC MAP(target=>0,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtoy
GENERIC MAP(target=>1,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END GENERATE;
gab: IF (target = 0) GENERATE
one: hcc_castftox
GENERIC MAP(target=>2,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtoy
GENERIC MAP(target=>0,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOD.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + ***
--*** swRoundConvert*(1 + swDoubleSpeed); ***
--***************************************************
ENTITY hcc_castltod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castltod;
ARCHITECTURE rtl OF hcc_castltod IS
signal fit : STD_LOGIC;
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
yvector(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
yvector(77 DOWNTO 73) <= "00000";
END GENERATE;
yvector(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
yvector(k) <= '0';
END GENERATE;
yvector(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
core: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOX.VHD ***
--*** ***
--*** Function: Cast Long to Internal Single ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltox IS
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castltox;
ARCHITECTURE rtl OF hcc_castltox IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aaff(32) & aaff(32) & aaff(32) & aaff(32) & aaff(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR aaff(28)) OR
(aaff(32) AND aaff(31) AND aaff(30) AND aaff(29) AND aaff(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR aaff(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
cc(k+10) <= (aaff(k) AND fit) OR (aaff(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aaff(32) OR aaff(31)) OR
(aaff(32) AND aaff(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aaff(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
cc(k+10) <= (aaff(k) AND fit) OR (aaff(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOY.VHD ***
--*** ***
--*** Function: Cast Long to Internal Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltoy IS
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castltoy;
ARCHITECTURE rtl OF hcc_castltoy IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gxa: IF (unsigned = 0) GENERATE
cc(77 DOWNTO 73) <= aaff(32) & aaff(32) & aaff(32) & aaff(32) & aaff(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(77 DOWNTO 73) <= "00000";
END GENERATE;
cc(72 DOWNTO 41) <= aaff;
gza: FOR k IN 14 TO 40 GENERATE
cc(k) <= '0';
END GENERATE;
cc(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
ccsat <= '0';
cczip <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip, yvectornan : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,aanan=>aanan,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip,ccnan=>yvectornan);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,aanan=>yvectornan,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOF.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support, also fixed zero/infinity/nan mantissa ***
--*** 29/04/09 - zero output if mantissa in zero ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--******************************************************************************
ENTITY hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtof;
ARCHITECTURE rtl OF hcc_castxtof IS
-- latency = 5 if normspeed = 1
-- latency = 7 if normspeed = 2 (extra pipe in normusgn3236 and output stage)
type exptopfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type expbotfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal count : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal absnode, absroundnode, absff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : expbotfftype;
signal roundoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC_VECTOR (3+normspeed DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2+2*normspeed DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal preexpnode, expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal mantissaroundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode, maxmantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal zeromantissaff, maxmantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
signal ccsgn : STD_LOGIC;
signal aaexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (23 DOWNTO 1);
component hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
absff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
roundoverflowff <= '0';
FOR k IN 1 TO 3+normspeed LOOP
satff(k) <= '0';
zipff(k) <= '0';
nanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2+2*normspeed LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 1+normspeed LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
absff <= absnode + absroundnode;
fracoutff <= fracout;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
-- add 4 because of maximum 4 bits wordgrowth in X mantissa
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) + "0000000100";
exptopff(3)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1) - ("0000" & count);
roundoverflowff <= roundoverflow(24);
satff(1) <= aasat;
FOR k IN 2 TO 3+normspeed LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO 3+normspeed LOOP
zipff(k) <= zipff(k-1);
END LOOP;
nanff(1) <= aanan;
FOR k IN 2 TO 3+normspeed LOOP
nanff(k) <= nanff(k-1);
END LOOP;
signff(1) <= aaff(mantissa+10);
FOR k IN 2 TO 2+2*normspeed LOOP
signff(k) <= signff(k-1);
END LOOP;
zeronumberff(1) <= NOT(zeronumber(mantissa));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsa: IF (normspeed = 1) GENERATE
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissanode(k) AND NOT(zeromantissanode)) OR maxmantissanode;
END LOOP;
END IF;
END IF;
END PROCESS;
preexpnode <= exptopff(3)(10 DOWNTO 1);
END GENERATE;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsb: IF (normspeed = 2) GENERATE
pnb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
expbotff(1)(10 DOWNTO 1) <= "0000000000";
expbotff(2)(10 DOWNTO 1) <= "0000000000";
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaroundff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(1)(10 DOWNTO 1) <= exptopff(3)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expnode;
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expbotff(2)(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
mantissaroundff <= mantissanode;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissaroundff(k) AND NOT(zeromantissaff)) OR maxmantissaff;
END LOOP;
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END IF;
END PROCESS;
preexpnode <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
-- round absolute value any way - need register on input of cntusgn
gaa: FOR k IN 1 TO mantissa GENERATE
absnode(k) <= aaff(k+10) XOR aaff(mantissa+10);
END GENERATE;
absroundnode <= zerovec(mantissa-1 DOWNTO 1) & aaff(mantissa+10);
zeronumber(1) <= absff(1);
gzma: FOR k IN 2 TO mantissa GENERATE
zeronumber(k) <= zeronumber(k-1) OR absff(k);
END GENERATE;
core: hcc_normusgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absff(mantissa DOWNTO 1),countout=>count,
fracout=>fracout);
roundoverflow(1) <= fracout(7);
gna: FOR k IN 2 TO 24 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+6);
END GENERATE;
expnode <= preexpnode(10 DOWNTO 1) + ("000000000" & roundoverflowff);
-- always round single output (round to nearest even)
roundbit <= (fracoutff(mantissa-24) AND fracoutff(mantissa-25)) OR
(NOT(fracoutff(mantissa-24)) AND fracoutff(mantissa-25) AND
(fracoutff(mantissa-26) OR fracoutff(mantissa-27) OR fracoutff(mantissa-28)));
mantissanode <= fracoutff(mantissa-2 DOWNTO mantissa-24) +
(zerovec(22 DOWNTO 1) & roundbit);
--ML March 8, 2011 consider expnode(10 DOWNTO 9) for zeroexpnode and maxexpnode calculation
zeroexpnode <= NOT(expnode(10) OR
expnode(9) OR expnode(8) OR expnode(7) OR
expnode(6) OR expnode(5) OR expnode(4) OR
expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(10)) AND NOT(expnode(9)) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- all following '1' when true
-- 24/03/09 - zeroexpnode, maxexpnode also zeros mantissa (SRC bug)
zeromantissanode <= roundoverflowff OR zeroexpnode OR maxexpnode OR
expnode(9) OR expnode(10) OR
zipff(3+normspeed) OR satff(3+normspeed) OR
zeronumberff(1+normspeed);
maxmantissanode <= nanff(3+normspeed);
zeroexponentnode <= zeroexpnode OR expnode(10) OR
zipff(3+normspeed) OR zeronumberff(1+normspeed);
maxexponentnode <= maxexpnode OR (expnode(9) AND NOT(expnode(10))) OR
satff(3+normspeed) OR nanff(3+normspeed);
--*** OUTPUTS ***
cc(32) <= signff(2+2*normspeed);
cc(31 DOWNTO 24) <= exponentff;
cc(23 DOWNTO 1) <= mantissaff(23 DOWNTO 1);
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccsgn <= signff(2+2*normspeed);
ccexp <= exponentff;
ccman <= mantissaff(23 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOL.VHD ***
--*** ***
--*** Function: Cast Internal Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 1 + swSingleNormSpeed ***
--***************************************************
ENTITY hcc_castxtol IS
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtol;
ARCHITECTURE rtl OF hcc_castxtol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout, nanout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
leftshiftnum <= aa(10 DOWNTO 1) - "0010011010"; -- 154 is 1.0 point
rightshiftnum <= "0010011010" - aa(10 DOWNTO 1);
leftshiftmax <= aa(10 DOWNTO 1) - "0010111010"; -- 186 is the max - if +ve, saturate
rightshiftmin <= aa(10 DOWNTO 1) - "0001111010"; -- 122 is the min - if -ve, zero
selectleftbit <= rightshiftnum(10);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(10));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(10);
gmab: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb32
PORT MAP (inbus=>aa(42 DOWNTO 11),shift=>leftshiftnum(5 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb32
PORT MAP (inbus=>aa(42 DOWNTO 11),shift=>rightshiftnum(5 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gmac: IF (normspeed = 2) GENERATE
sftlp: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(42 DOWNTO 11),shift=>leftshiftnum(5 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(42 DOWNTO 11),shift=>rightshiftnum(5 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbnan: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanan,cc=>nanout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus;
rightshiftbusff <= rightshiftbus;
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout OR nanout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOY.VHD ***
--*** ***
--*** Function: Cast Internal Single to ***
--*** Internal Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castxtoy;
ARCHITECTURE rtl OF hcc_castxtoy IS
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
BEGIN
-- x : 32/36 signed mantissa, 10 bit exponent
-- y : (internal) 64 signed mantissa, 13 bit exponent
exponentadjust <= conv_std_logic_vector (896,13);
cc(67+10*target DOWNTO 68+10*target-mantissa) <= aa(mantissa+10 DOWNTO 11);
gxa: FOR k IN 14 TO 67+10*target-mantissa GENERATE
cc(k) <= aa(11);
END GENERATE;
cc(13 DOWNTO 1) <= ("000" & aa(10 DOWNTO 1)) + exponentadjust;
ccsat <= aasat;
cczip <= aazip;
ccnan <= aanan;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support, also fixed zero/infinity/nan mantissa ***
--*** 29/04/09 - zero output if mantissa in zero ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swRoundConvert*swDoubleSpeed + ***
--*** swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff, nanff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode, maxmantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff, maxmantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff, maxmantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
nanff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
nanff(1) <= aanan;
FOR k IN 2 TO satffdepth LOOP
nanff(k) <= nanff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- zero mantissa if when 0 or infinity result
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
maxmantissanode <= nanff(satffdepth);
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 12/05/09 - make sure than exp = -1 doesn't trigger max node
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth) OR nanff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (fracoutff(k+10) AND NOT(zeromantissanode)) OR maxmantissanode;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissaroundff(k) OR maxmantissaff) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) OR maxexponentff) AND NOT(zeroexponentff);
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
maxmantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissaroundnode(k) AND NOT(zeromantissadelff)) OR maxmantissadelff;
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
maxmantissadelff <= maxmantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,aanan=>aanan,
cc=>midnode,
ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOL.VHD ***
--*** ***
--*** Function: Cast Internal Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: normspeed+1 ***
--***************************************************
ENTITY hcc_castytol IS
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytol;
ARCHITECTURE rtl OF hcc_castytol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout, nanout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_lsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
midpoint <= conv_std_logic_vector (1054,13);
maxpoint <= conv_std_logic_vector (1118,13);
minpoint <= conv_std_logic_vector (1022,13);
leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point
rightshiftnum <= midpoint - aa(13 DOWNTO 1);
-- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre
leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate
rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero
selectleftbit <= rightshiftnum(13);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(13));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13);
gsa: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gsb: IF (normspeed > 1) GENERATE
sftlp: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbnan: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanan,cc=>nanout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus(64 DOWNTO 33);
rightshiftbusff <= rightshiftbus(64 DOWNTO 33);
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout OR nanout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOX.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** Internal Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** support ***
--*** 24/08/10 - fixed multiple bugs ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : OPERATIONS ***
--***************************************************
-- input always signed y format (mult, divide, have output option
ENTITY hcc_castytox IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castytox;
ARCHITECTURE rtl OF hcc_castytox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal overflowcheck : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal exponentmaximum, exponentminimum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal chkexpsat, chkexpzip : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expsatbit, expzipbit : STD_LOGIC;
signal exponentnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC;
signal satoutff, zipoutff, nanoutff : STD_LOGIC;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
exponentmaximum <= conv_std_logic_vector (1151,13); -- 1151 = 1023+128 = 255
exponentminimum <= conv_std_logic_vector (897,13); -- 897 = 1023-126 = 1
exponentadjust <= conv_std_logic_vector (896,13); -- 896 = 1023-127
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satinff <= '0';
zipinff <= '0';
naninff <= '0';
satoutff <= '0';
zipoutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
ccff <= fractional & exponent;
satinff <= aasat;
zipinff <= aazip;
naninff <= aanan;
satoutff <= satinff OR expsatbit;
zipoutff <= zipinff OR expzipbit;
nanoutff <= naninff;
END IF;
END IF;
END PROCESS;
chkexpsat <= aaff(13 DOWNTO 1) - exponentmaximum; -- ok when -ve
chkexpzip <= aaff(13 DOWNTO 1) - exponentminimum; -- ok when +ve
expsatbit <= NOT(chkexpsat(13)) OR (NOT(aaff(13)) AND aaff(12));
expzipbit <= chkexpzip(13) OR aaff(13);
exponentnode <= aaff(13 DOWNTO 1) - exponentadjust;
gxa: FOR k IN 1 TO 8 GENERATE
exponent(k) <= (exponentnode(k) OR expsatbit) AND NOT(expzipbit);
END GENERATE;
exponent(10 DOWNTO 9) <= "00";
fracnode <= aaff(77 DOWNTO 78-mantissa);
gma: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gmb: IF (roundconvert = 1) GENERATE
-- issue is when max positive turned into negative number (01111XXX to 10000XXX)
-- min negative (11111) to min positive (00000) no issue
-- but this code zeros round bit if fracnode is "X1111...111"
overflowcheck(1) <= aaff(78-mantissa);
gmc: FOR k IN 2 TO mantissa-1 GENERATE
overflowcheck(k) <= overflowcheck(k-1) AND aaff(77-mantissa+k);
END GENERATE;
roundbit <= NOT(overflowcheck(mantissa-1)) AND aaff(77-mantissa);
fractional <= fracnode + (zerovec(mantissa-1 DOWNTO 1) & roundbit);
END GENERATE;
cc <= ccff;
ccsat <= satoutff;
cczip <= zipoutff;
ccnan <= nanoutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn32;
ARCHITECTURE rtl OF hcc_cntsgn32 IS
type positiontype IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(2) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(4) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(5) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(6) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(7) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(8) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(2) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(3) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(4) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(5) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(6) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(7) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(8) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 8 GENERATE
sec(k) <= (possec(k) AND NOT(frac(32))) OR (NOT(negsec(k)) AND frac(32));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(31 DOWNTO 28),
position=>position(1)(5 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(27 DOWNTO 24),
position=>position(2)(5 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(23 DOWNTO 20),
position=>position(3)(5 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(19 DOWNTO 16),
position=>position(4)(5 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(15 DOWNTO 12),
position=>position(5)(5 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(11 DOWNTO 8),
position=>position(6)(5 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(7 DOWNTO 4),
position=>position(7)(5 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>5)
PORT MAP (signbit=>frac(32),inbus=>lastfrac,
position=>position(8)(5 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(32);
gmc: FOR k IN 1 TO 5 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8));
END GENERATE;
count(6) <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn36;
ARCHITECTURE rtl OF hcc_cntsgn36 IS
type positiontype IS ARRAY (9 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32);
possec(2) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(3) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(4) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(5) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(6) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(7) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(8) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(9) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(35) AND frac(34) AND frac(33) AND frac(32);
negsec(2) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(3) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(4) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(5) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(6) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(7) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(8) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(9) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 9 GENERATE
sec(k) <= (possec(k) AND NOT(frac(36))) OR (NOT(negsec(k)) AND frac(36));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(9) <= sec(9) AND NOT(sec(8)) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND
NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(35 DOWNTO 32),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(31 DOWNTO 28),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(27 DOWNTO 24),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(23 DOWNTO 20),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(19 DOWNTO 16),
position=>position(5)(6 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(15 DOWNTO 12),
position=>position(6)(6 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(11 DOWNTO 8),
position=>position(7)(6 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(7 DOWNTO 4),
position=>position(8)(6 DOWNTO 1));
pnin: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>lastfrac,
position=>position(9)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(36);
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8)) OR
(position(9)(k) AND sel(9));
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSCOMB64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuscomb64 IS
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuscomb64;
ARCHITECTURE rtl of hcc_cntuscomb64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn36;
ARCHITECTURE rtl OF hcc_cntusgn36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32) OR frac(31) OR frac(30);
sec(2) <= frac(29) OR frac(28) OR frac(27) OR frac(26) OR frac(25) OR frac(24);
sec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20) OR frac(19) OR frac(18);
sec(4) <= frac(17) OR frac(16) OR frac(15) OR frac(14) OR frac(13) OR frac(12);
sec(5) <= frac(11) OR frac(10) OR frac(9) OR frac(8) OR frac(7) OR frac(6);
sec(6) <= frac(5) OR frac(4) OR frac(3) OR frac(2) OR frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(35 DOWNTO 30),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(29 DOWNTO 24),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(23 DOWNTO 18),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(17 DOWNTO 12),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(11 DOWNTO 6),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(5 DOWNTO 1) & '0';
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSPIPE64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuspipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuspipe64;
ARCHITECTURE rtl of hcc_cntuspipe64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroup, firstzeroff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
firstzeroff(1) <= zerogroup(1);
firstzeroff(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzeroff(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzeroff(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzeroff(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzeroff(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzeroff(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzeroff(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzeroff(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzeroff(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzeroff(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzeroff(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzeroff(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAYBIT.VHD ***
--*** ***
--*** Function: Delay a single bit an ***
--*** arbitrary number of stages ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
END hcc_delaybit;
ARCHITECTURE rtl OF hcc_delaybit IS
signal delff : STD_LOGIC_VECTOR (delay DOWNTO 1);
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
delff(1) <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
END IF;
END IF;
END PROCESS;
cc <= delff(1);
END GENERATE;
gdb: IF (delay > 1) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO delay LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
FOR k IN 2 TO delay LOOP
delff(k) <= delff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(delay);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELMEM.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** Note: this code megawizard generated ***
--*** ***
--*** 12/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delmem IS
GENERIC (
width : positive := 79;
delay : positive := 7
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delmem;
ARCHITECTURE SYN OF hcc_delmem IS
signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1);
COMPONENT altshift_taps
GENERIC (
lpm_hint : STRING;
lpm_type : STRING;
number_of_taps : NATURAL;
tap_distance : NATURAL;
width : NATURAL
);
PORT (
taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clken : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
delcore: altshift_taps
GENERIC MAP (
lpm_hint => "RAM_BLOCK_TYPE=M512",
lpm_type => "altshift_taps",
number_of_taps => 1,
tap_distance => delay,
width => width
)
PORT MAP (
clock => sysclk,
clken => enable,
shiftin => aa,
taps => dummy,
shiftout => cc
);
END SYN;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftcomb32;
ARCHITECTURE rtl OF hcc_lsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 64 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_lsftcomb64;
ARCHITECTURE rtl OF hcc_lsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
gcd: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE36.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftpipe36;
ARCHITECTURE rtl OF hcc_lsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE64.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 64 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_lsftpipe64;
ARCHITECTURE rtl OF hcc_lsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
gcd: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 2 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL2727S.VHD ***
--*** ***
--*** Function: 2 pipeline stage signed 27 bit ***
--*** SV(behavioral/synthesizable) ***
--*** ***
--*** 30/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul2727s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul2727s;
ARCHITECTURE rtl OF hcc_mul2727s IS
attribute preserve : boolean;
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
attribute preserve of aaff : signal is true;
attribute preserve of bbff : signal is true;
signal multiplyff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
multiplyff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
multiplyff <= aaff * bbff;
END IF;
END IF;
END PROCESS;
cc <= multiplyff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236B.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236b IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236b;
ARCHITECTURE rtl OF hcc_mul3236b IS
attribute preserve : boolean;
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
attribute preserve of aaff : signal is true;
attribute preserve of bbff : signal is true;
signal mulff, muloutff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
mulff(k) <= '0';
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= aaff * bbff;
muloutff <= mulff;
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236T.VHD ***
--*** ***
--*** Function: 3 pipeline stage signed 32 or ***
--*** 36 bit truncated multiplier ***
--*** with faithful rounding, for use ***
--*** with Arria V. ***
--*** ***
--*** 2012-04-17 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236t IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
BEGIN
assert (width <= 36);
END hcc_mul3236t;
ARCHITECTURE syn OF hcc_mul3236t IS
signal mulaah, mulbbh : STD_LOGIC_VECTOR(36 downto 19);
signal mulaal, mulbbl : STD_LOGIC_VECTOR(18 downto 1);
signal multone : STD_LOGIC_VECTOR(72 DOWNTO 37); -- 36 bits
signal multtwo : STD_LOGIC_VECTOR(55 DOWNTO 19); -- 37 bits
signal mulaaff, mulbbff, prodff : STD_LOGIC;
signal addmult : STD_LOGIC_VECTOR(72 DOWNTO 34);
signal addmultff : STD_LOGIC_VECTOR(72 DOWNTO (73 - width));
component hcc_mul2727s IS
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_MA2_27Ux27S_L2 is
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
aclr : IN STD_LOGIC;
clk : IN STD_LOGIC;
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
en : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
BEGIN
mulaah <= mulaa(width DOWNTO (width - 17));
mulaal <= mulaa((width - 18) DOWNTO 1) & ((36 - width) DOWNTO 1 => '0');
mulbbh <= mulbb(width DOWNTO (width - 17));
mulbbl <= mulbb((width - 18) DOWNTO 1) & ((36 - width) DOWNTO 1 => '0');
mone: hcc_mul2727s
GENERIC MAP (width=>18)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulaah,bb=>mulbbh,
cc=>multone);
mtwo: hcc_MA2_27Ux27S_L2
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>37)
PORT MAP (aclr=>reset,clk=>sysclk,
a0=>mulaal,
a1=>mulbbl,
b0=>mulbbh,
b1=>mulaah,
en=>enable,
result=>multtwo);
addmult <= (multone(72 DOWNTO 37) & '1' & prodff & '1') +
((72 DOWNTO 56 => multtwo(55)) & multtwo(55 DOWNTO 35) & '1');
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulaaff <= '0';
mulbbff <= '0';
prodff <= '0';
addmultff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulaaff <= mulaal(18);
mulbbff <= mulbbl(18);
prodff <= mulaaff AND mulbbff;
addmultff <= addmult(72 DOWNTO (73 - width));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END syn;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_28S.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 28S: Stratix 2, 8 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_28s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_28s;
ARCHITECTURE syn of hcc_mul54us_28s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecsix, vecsev : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(54 DOWNTO 19);
mulonebb <= mulbb(54 DOWNTO 19);
multwoaa <= mulaa(18 DOWNTO 1);
multwobb <= mulbb(36 DOWNTO 19);
multhraa <= mulaa(18 DOWNTO 1);
multhrbb <= mulbb(54 DOWNTO 37);
mulforaa <= mulbb(18 DOWNTO 1);
mulforbb <= mulaa(36 DOWNTO 19);
mulfivaa <= mulbb(18 DOWNTO 1);
mulfivbb <= mulaa(54 DOWNTO 37);
-- {A,C) * {B,D}
-- AAC
-- BBD
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= zerovec(22 DOWNTO 1) & multwoout;
vectwo <= zerovec(4 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(22 DOWNTO 1) & mulforout;
vecfor <= zerovec(4 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 58 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(57 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 58 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 58 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 72 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(57 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= zerovec(32 DOWNTO 1) & sumoneff(58 DOWNTO 19);
vecnin <= zerovec(32 DOWNTO 1) & caroneff(58 DOWNTO 19);
vecten <= muloneout(72 DOWNTO 1);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 9),
datab => cartwoff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_29S.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 Created from HCC_MUL54USS ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_29s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_29s;
ARCHITECTURE syn of hcc_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 9),
datab => cartwoff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY hcc_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_38s;
ARCHITECTURE rtl OF hcc_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (64 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone(72 DOWNTO 9) +
(zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 27));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_3XS.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 3XS: Stratix 3, 10 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** For QII8.0 LPM_MULT always creates a 10 ***
--*** 18x18 multiplier 54x54 core ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_3xs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_3xs;
ARCHITECTURE syn of hcc_mul54us_3xs IS
component lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end component;
BEGIN
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => 4,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 54,
lpm_widthb => 54,
lpm_widthp => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_57S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 57S: Stratix V/Arria V; 3 27x27, 1 18x18 ***
--*** ***
--*** 2012-04-13 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_57s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR(54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR(54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR(64 DOWNTO 1)
);
END hcc_mul54us_57s;
ARCHITECTURE rtl OF hcc_mul54us_57s IS
-- width of first adder including carry (register/FMax trade-off)
constant ADD1WIDTH : positive := 35;
signal multone : STD_LOGIC_VECTOR(108 DOWNTO 55); -- 54 bits
signal multtwo : STD_LOGIC_VECTOR(82 DOWNTO 28); -- 55 bits (sum-of-2)
signal multthree : STD_LOGIC_VECTOR(54 DOWNTO 23); -- 32 bits
constant HI : positive := 2*54;
constant LO : positive := (HI - 64) + 1;
constant H2 : positive := HI;
constant L2 : positive := LO + ADD1WIDTH - 1;
constant H1 : positive := LO + ADD1WIDTH - 2;
constant L1 : positive := LO;
constant LX : positive := LO - 1;
signal argone : STD_LOGIC_VECTOR(H2 DOWNTO LX);
signal argtwo : STD_LOGIC_VECTOR(H2 DOWNTO LX);
signal argoneff : STD_LOGIC_VECTOR(H2 DOWNTO L2);
signal argtwoff : STD_LOGIC_VECTOR(H2 DOWNTO L2);
signal stageone : STD_LOGIC_VECTOR(L2 DOWNTO LX);
signal stagetwo : STD_LOGIC_VECTOR(H2 DOWNTO H1);
signal stageoneff : STD_LOGIC_VECTOR(L2 DOWNTO L1);
signal addmultff : STD_LOGIC_VECTOR(H2 DOWNTO L1);
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component hcc_MA2_27Ux27U_L2 is
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
aclr : IN STD_LOGIC;
clk : IN STD_LOGIC;
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
en : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
BEGIN
mone: fp_mul2s
GENERIC MAP (widthaa=>27,widthbb=>27,widthcc=>54)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 28),databb=>mulbb(54 DOWNTO 28),
result=>multone);
mtwo: hcc_MA2_27Ux27U_L2
GENERIC MAP (widthaa=>27,widthbb=>27,widthcc=>55)
PORT MAP (aclr=>reset,clk=>sysclk,
a0=>mulaa(27 DOWNTO 1),
a1=>mulbb(27 DOWNTO 1),
b0=>mulbb(54 DOWNTO 28),
b1=>mulaa(54 DOWNTO 28),
en=>enable,
result=>multtwo);
mthree: fp_mul2s
GENERIC MAP (widthaa=>16,widthbb=>16,widthcc=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(27 DOWNTO 12),databb=>mulbb(27 DOWNTO 12),
result=>multthree);
argone <= multone(108 DOWNTO 55) & multthree(54 DOWNTO LX);
argtwo <= (108 DOWNTO 83 => '0') & multtwo(82 DOWNTO LX);
stageone <= ('0' & argone(H1 DOWNTO LX)) +
('0' & argtwo(H1 DOWNTO LX));
stagetwo <= (argoneff(H2 DOWNTO L2) & stageoneff(L2)) +
(argtwoff(H2 DOWNTO L2) & '1');
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
argoneff <= (others => '0');
argtwoff <= (others => '0');
stageoneff <= (others => '0');
addmultff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
argoneff <= argone(H2 DOWNTO L2);
argtwoff <= argtwo(H2 DOWNTO L2);
stageoneff <= stageone(L2 DOWNTO L1);
addmultff(H2 DOWNTO L2) <= stagetwo(H2 DOWNTO L2);
addmultff(H1 DOWNTO L1) <= stageoneff(H1 DOWNTO L1);
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USB.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 31/01/08 ML see below ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- 31/01/08 - output right shifted so same as synthesable core
-- (now "001X" >= 2, "0001X" < 2
ENTITY hcc_mul54usb IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0 -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54usb;
ARCHITECTURE rtl OF hcc_mul54usb IS
constant delaydepth : integer := 4 - 2*device;
type muldelfftype IS ARRAY (delaydepth DOWNTO 1) OF STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal muldelff : muldelfftype;
signal mulnode : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal mulonenode, multwonode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multhrnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 72 GENERATE
zerovec(k) <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 108 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO delaydepth LOOP
FOR j IN 1 TO 72 LOOP
muldelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= mulnode;
muldelff(1)(72 DOWNTO 1) <= mulff(108 DOWNTO 37);
FOR k IN 2 TO delaydepth LOOP
muldelff(k)(72 DOWNTO 1) <= muldelff(k-1)(72 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- full multiplier
gpa: IF (doubleaccuracy = 1) GENERATE
mulonenode <= zerovec(54 DOWNTO 1);
multwonode <= zerovec(54 DOWNTO 1);
multhrnode <= zerovec(72 DOWNTO 1);
mulnode <= aaff * bbff;
END GENERATE;
-- pruned multiplier (18x18 LSB contribution missing)
gpb: IF (doubleaccuracy = 0) GENERATE
mulonenode <= aaff(18 DOWNTO 1) * bbff(54 DOWNTO 19);
multwonode <= bbff(18 DOWNTO 1) * aaff(54 DOWNTO 19);
multhrnode <= aaff(54 DOWNTO 19) * bbff(54 DOWNTO 19);
mulnode <= (multhrnode & zerovec(36 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & mulonenode & zerovec(18 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & multwonode & zerovec(18 DOWNTO 1));
END GENERATE;
cc <= muldelff(delaydepth)(72 DOWNTO 9);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
ENTITY hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_muldot_v1;
ARCHITECTURE rtl OF hcc_muldot_v1 IS
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC;
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC;
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_svmult1
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
end component;
BEGIN
biasvalue <= conv_std_logic_vector (127,10);
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
exponentff <= conv_std_logic_vector (0,10);
aasignff <= '0';
bbsignff <= '0';
signff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff);-- - biasvalue;
aasignff <= aa(32);
bbsignff <= bb(32);
signff <= aasignff XOR bbsignff;
END IF;
END IF;
END PROCESS;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
--bmult5: hcc_mul2727s
-- GENERIC MAP (width=>27)
-- PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
-- aa=>aamantissa,bb=>bbmantissa,
-- cc=>multiply);
multcore: hcc_svmult1
PORT MAP (clock0=>sysclk,reset=>reset,dataa_0=>aamantissa,datab_0=>bbmantissa,result=>multiply);
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
--normalize(mantissa DOWNTO mantissa-2) <= "000";
--gnma: FOR k IN 1 TO mantissa-3 GENERATE
-- normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
-- (multiply(56-mantissa+k) AND NOT(multiply(52)));
--END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= '0';
ccsatff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
-- a x inf = inf
ccsatff <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
-- 0 x inf = nan
-- a x nan = nan
ccnanff <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
--cczipff <= '0';
--ccsatff <= '0';
--ccnanff <= '0';
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- multiplier will either be "0001XXXX" or "001XXXX"
-- use this as worst case next level will be "001111" + "001111" = "01111" or negative equivalent
ccmantissa <= multiply (54 DOWNTO 23);
ccsign <= signff;
ccexponent <= exponentff(10 DOWNTO 1);
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1VEC.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 29/04/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1vec IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 1; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1vec;
ARCHITECTURE rtl OF hcc_mulfp1vec IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "00";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - "0001111111";
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_older: IF (device < 2) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
END GENERATE;
gen_twos_newer: IF (device = 2) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--*** OUTPUTS ***
cc(mantissa+10 DOWNTO 11) <= mantissaff;
gen_out_older: IF (device < 2) GENERATE
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
gen_out_newer: IF (device = 2) GENERATE
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1X.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** 11/08/09 - add divider interface output ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0;
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1x;
ARCHITECTURE rtl OF hcc_mulfp1x IS
signal mulinaa, mulinbb : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal mulinaasat, mulinaazip, mulinaanan : STD_LOGIC;
signal mulinbbsat, mulinbbzip, mulinbbnan : STD_LOGIC;
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccsatnode, cczipnode, ccnannode : STD_LOGIC;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmantissa, divposmantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normmantissa : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal normshiftbit : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC;
signal manmultff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expmultff : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- ieee output
signal absnode : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal absolute : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal absoluteff : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal manroundnode : STD_LOGIC_VECTOR (26 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal expplusnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, manoutmax : STD_LOGIC;
signal expoutzero, expoutmax : STD_LOGIC;
component hcc_mulfp3236 IS
GENERIC (
mantissa : positive; -- 32 or 36
device : integer;
synthesize : integer
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfppn3236 IS
GENERIC (
mantissa : positive; -- 32 or 36
device : integer;
synthesize : integer
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
mulinaa <= aa;
mulinbb <= bb;
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinaanan <= aanan;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
mulinbbnan <= bbnan;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
gma: IF (outputscale = 0) GENERATE
mulone: hcc_mulfp3236
GENERIC MAP (mantissa=>mantissa,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bb=>mulinbb,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
cc=>ccnode,ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
END GENERATE;
gmb: IF (outputscale = 1) GENERATE
multwo: hcc_mulfppn3236
GENERIC MAP (mantissa=>mantissa,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bb=>mulinbb,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
cc=>ccnode,ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
END GENERATE;
--*** OUTPUTS ***
--***********************
--*** INTERNAL FORMAT ***
--***********************
gxo: IF (xoutput = 1) GENERATE
cc <= ccnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
ccnan <= ccnannode;
END GENERATE;
--*******************************************
--*** ANOTHER SINGLE PRECISION MULTIPLIER ***
--*******************************************
gmo: IF (multoutput = 1) GENERATE
-- lose 4 bits of precision for now, update hcc_mulfp3236 later
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 2's complement
gna: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
pmo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
manmultff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expmultff(k) <= '0';
END LOOP;
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manmultff <= normmantissa(mantissa-4 DOWNTO 1) & "0000";
expmultff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= manmultff;
cc(10 DOWNTO 1) <= expmultff;
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END GENERATE;
--**********************************
--*** A SINGLE PRECISION DIVIDER ***
--**********************************
gdo: IF (divoutput = 1) GENERATE
-- lose 4 bits of precision for now, update hcc_mulfp3236 later
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 2's complement
gda: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
-- do not need to trap overflow, as maximum -ve number cannot happen, as inputs
-- will be 0111...*10000
divmantissa <= normmantissa(mantissa-4 DOWNTO 1) & "0000";
gdb: FOR k IN 1 TO mantissa-1 GENERATE
divposmantissa(k) <= divmantissa(k) XOR mantissanode(mantissa);
END GENERATE;
-- divider output is signed magnitude
divposmantissa(mantissa) <= mantissanode(mantissa);
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
pmo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
manmultff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expmultff(k) <= '0';
END LOOP;
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manmultff <= divposmantissa + mantissanode(mantissa);
expmultff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= manmultff;
cc(10 DOWNTO 1) <= expmultff;
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END GENERATE;
--**********************
--*** IEEE754 Output ***
--**********************
gio: IF (ieeeoutput = 1) GENERATE
-- +ve result: 000001XXXXX or 00001XXXXX
-- -ve result: 111110XXXXX or 11110XXXXX
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 1's complement
gna: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
gaa: FOR k IN 1 TO mantissa-3 GENERATE
absnode(k) <= normmantissa(k) XOR normmantissa(mantissa-3);
END GENERATE;
absolute <= absnode(mantissa-3 DOWNTO 1) + normmantissa(mantissa-3);
pia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa-3 LOOP
absoluteff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= "00";
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absoluteff <= absolute;
expshiftff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (manroundnode(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (expplusnode(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff(1) <= normmantissa(mantissa-4);
signoutff(2) <= signoutff(1);
END IF;
END IF;
END PROCESS;
roundbit <= absoluteff(mantissa-29);
manroundnode <= absoluteff(mantissa-3 DOWNTO mantissa-28)+ roundbit;
overflownode(1) <= roundbit;
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= overflownode(k-1) AND absoluteff(mantissa-30+k);
END GENERATE;
expplusnode <= expshiftff + ("000000000" & overflownode(24));
-- both '1' when true
expmax <= expplusnode(8) AND expplusnode(7) AND expplusnode(6) AND expplusnode(5) AND
expplusnode(4) AND expplusnode(3) AND expplusnode(2) AND expplusnode(1);
expzero <= NOT(expplusnode(8) OR expplusnode(7) OR expplusnode(6) OR expplusnode(5) OR
expplusnode(4) OR expplusnode(3) OR expplusnode(2) OR expplusnode(1));
manoutzero <= ccsatff OR cczipff OR expmax OR expzero OR
expshiftff(10) OR expshiftff(9);
manoutmax <= ccnanff;
expoutzero <= cczipff OR expzero OR expshiftff(10);
expoutmax <= expmax OR expshiftff(9) OR ccnanff;
cc(32) <= signoutff(2);
cc(31 DOWNTO 24) <= expoutff;
cc(23 DOWNTO 1) <= manoutff;
-- dummy
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= ccnode(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP2X.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/01/08 - see notes below ***
--*** 21/04/09 - add NAN support, also fix zero ***
--*** infinity and nan mantissa for ieee output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 28/01/08 - correct manoverflow for ieee ***
--*** output, effects of mantissa shift for both ***
--*** ieee and mult output, test output widths, ***
--*** also reversed exp and man order in ieee ***
--*** output ***
--*** 31/08/08 - behavioral and synth mults both ***
--*** now return "001X" (> 2) OR "0001X" (<2) ***
--*** change xoutput to 1 bit less right shift ***
--***(behavioral mult changed) ***
--***************************************************
ENTITY hcc_mulfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier or divider (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4), 2 = "Stratix V"
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp2x;
ARCHITECTURE rtl OF hcc_mulfp2x IS
-- 5 if stratix 2, 3 if stratix 3/4, 3 also for SV/AV.
function pipeline_latency(device : integer) return positive is
begin
case device is
when 0 => return 5;
when others => return 3;
end case;
end function pipeline_latency;
constant signdepth : positive := pipeline_latency(device);
type ccxexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type cceexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- multiplier core interface
signal mulinaaman, mulinbbman : STD_LOGIC_VECTOR(54 DOWNTO 1);
signal mulinaaexp, mulinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal mulinaasat, mulinaazip, mulinaanan : STD_LOGIC;
signal mulinbbsat, mulinbbzip, mulinbbnan : STD_LOGIC;
signal mulinaasign, mulinbbsign : STD_LOGIC;
signal mulinaasignff, mulinbbsignff : STD_LOGIC;
signal mulsignff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal ccmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccexpnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatnode, cczipnode, ccnannode : STD_LOGIC;
-- output section (x out)
signal ccmanshiftnode, signedccxmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccxsatff, ccxzipff, ccxnanff : STD_LOGIC;
signal ccxexpdelff : ccxexpdelfftype;
signal ccxsatdelff, ccxzipdelff, ccxnandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
-- output section (ieeeout)
signal shiftroundbit : STD_LOGIC;
signal cceroundnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal cceround : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceroundcarry : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccemannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal ccemanoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal cceexpoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ccesignbitff : STD_LOGIC;
signal cceroundff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatff, ccezipff, ccenanff : STD_LOGIC;
signal ccesignff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal cceexpdelff : cceexpdelfftype;
signal ccesatdelff, ccezipdelff, ccenandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal ccesigndelff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal cceexpbase, cceexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatbase, ccezipbase, ccenanbase : STD_LOGIC;
signal cceexpmax, cceexpzero : STD_LOGIC;
signal manoutzero, manoutmax, expoutzero, expoutmax : STD_LOGIC;
signal manoverflow : STD_LOGIC;
-- output section (multout)
signal shiftmanbit : STD_LOGIC;
signal manshiftnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manshiftff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccexpdelff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatdelff, cczipdelff, ccnandelff : STD_LOGIC;
signal muloutsignff : STD_LOGIC;
-- debug
signal aaexp, bbexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (11 + 2*multoutput + 2*xoutput DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (54+10*xoutput DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_mulufp54
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section - Normalization, if required ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT IN ALL CASES SIGN BIT IS PACKED IN MSB ***
--*** OF UNSIGNED MULTIPLIER ***
--********************************************************
--*** ieee754 input when multiplier input is from cast ***
--*** cast now creates different ***
--*** formats for multiplier, divider, and alu ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from another double multiplier (special ***
--*** output mode normalizes to 54 bit mantissa and ***
--*** 13 bit exponent ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from internal format, must be normed ***
--*** by normfp2x first, creates [S][1][mantissa...] ***
--********************************************************
mulinaaman <= '0' & aa(66 DOWNTO 14);
mulinaaexp <= aa(13 DOWNTO 1);
mulinbbman <= '0' & bb(66 DOWNTO 14);
mulinbbexp <= bb(13 DOWNTO 1);
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinaanan <= aanan;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
mulinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
mulinaasign <= aa(67);
mulinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Multiplier Section ***
--*** ***
--**************************************************
mult: hcc_mulufp54
GENERIC MAP (doubleaccuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mulinaaman,aaexp=>mulinaaexp,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bbman=>mulinbbman,bbexp=>mulinbbexp,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
ccman=>ccmannode,ccexp=>ccexpnode,
ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulinaasignff <= '0';
mulinbbsignff <= '0';
FOR k IN 1 TO signdepth LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulinaasignff <= mulinaasign;
mulinbbsignff <= mulinbbsign;
mulsignff(1) <= mulinaasignff XOR mulinbbsignff;
FOR k IN 2 TO signdepth LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
-- result will be "001X" (>2) or "0001X" (<2)
-- Y is SSSSS1 (<2) - therefore right shift 2 bits
-- 31/08/08 - behavioral mult changed to be same as synth one
ccmanshiftnode <= "00" & ccmannode(64 DOWNTO 3);
goxb: FOR k IN 1 TO 64 GENERATE
signedccxmannode(k) <= ccmanshiftnode(k) XOR mulsignff(signdepth);
END GENERATE;
goxc: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= signedccxmannode;
cc(13 DOWNTO 1) <= ccexpnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
ccnan <= ccnannode;
END GENERATE;
goxd: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goxe: IF (roundconvert = 0) GENERATE
ccxroundnode <= signedccxmannode;
END GENERATE;
goxf: IF (roundconvert = 1) GENERATE
ccxroundnode <= signedccxmannode + (zerovec(63 DOWNTO 1) & mulsignff(signdepth));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
ccxroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccxexpff(k) <= '0';
END LOOP;
ccxsatff <= '0';
ccxzipff <= '0';
ccxnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxroundff <= ccxroundnode;
ccxexpff <= ccexpnode;
ccxsatff <= ccsatnode;
ccxzipff <= cczipnode;
ccxnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundff;
cc(13 DOWNTO 1) <= ccxexpff(13 DOWNTO 1);
ccsat <= ccxsatff;
cczip <= ccxzipff;
ccnan <= ccxnanff;
END GENERATE;
goxg: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
ccxexpdelff(1)(k) <= '0';
ccxexpdelff(2)(k) <= '0';
END LOOP;
ccxsatdelff <= "00";
ccxzipdelff <= "00";
ccxnandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxexpdelff(1)(13 DOWNTO 1) <= ccexpnode;
ccxexpdelff(2)(13 DOWNTO 1) <= ccxexpdelff(1)(13 DOWNTO 1);
ccxsatdelff(1) <= ccsatnode;
ccxsatdelff(2) <= ccxsatdelff(1);
ccxzipdelff(1) <= cczipnode;
ccxzipdelff(2) <= ccxzipdelff(1);
ccxnandelff(1) <= ccnannode;
ccxnandelff(2) <= ccxnandelff(1);
END IF;
END IF;
END PROCESS;
goxh: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(signdepth),
cc=>ccxroundnode);
END GENERATE;
goxi: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(signdepth),
cc=>ccxroundnode);
END GENERATE;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundnode;
cc(13 DOWNTO 1) <= ccxexpdelff(2)(13 DOWNTO 1);
ccsat <= ccxsatdelff(2);
cczip <= ccxzipdelff(2);
ccnan <= ccxnandelff(2);
END GENERATE;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftroundbit <= NOT(ccmannode(62));
goeb: FOR k IN 1 TO 55 GENERATE -- format "01"[52..1]R
cceroundnode(k) <= (ccmannode(k+7) AND shiftroundbit) OR
(ccmannode(k+8) AND NOT(shiftroundbit));
END GENERATE;
goec: IF (roundconvert = 0) GENERATE
ccemannode <= cceroundnode(53 DOWNTO 2);
poia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (ccemannode(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR manoutmax;
END LOOP;
ccesignbitff <= mulsignff(signdepth);
END IF;
END IF;
END PROCESS;
cceexpplus <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit)); -- change 28/01/08
ccesatbase <= ccsatnode;
ccezipbase <= cczipnode;
ccenanbase <= ccnannode;
manoverflow <= '0'; -- change 28/01/08
--*** OUTPUTS ***
cc(64) <= ccesignbitff;
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goed: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
cceroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
cceexpff(k) <= '0';
END LOOP;
ccesatff <= '0';
ccezipff <= '0';
ccenanff <= '0';
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
cceroundff <= cceroundnode(55 DOWNTO 2) + cceroundcarry;
-- change 28/01/08
cceexpff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
ccesatff <= ccsatnode;
ccezipff <= cczipnode;
ccenanff <= ccnannode;
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (cceroundff(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
ccesignff(1) <= mulsignff(signdepth);
ccesignff(2) <= ccesignff(1);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundff(54);
cceexpbase <= cceexpff(13 DOWNTO 1);
ccesatbase <= ccesatff;
ccezipbase <= ccezipff;
ccenanbase <= ccenanff;
cceexpplus <= cceexpbase + ("000000000000" & cceroundff(54));
--*** OUTPUTS ***
cc(64) <= ccesignff(2);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goef: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
goeg: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceround);
END GENERATE;
goeh: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceround);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
cceexpdelff(1)(k) <= '0';
cceexpdelff(2)(k) <= '0';
END LOOP;
ccesatdelff <= "00";
ccezipdelff <= "00";
ccenandelff <= "00";
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesigndelff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- change 28/01/08
cceexpdelff(1)(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
cceexpdelff(2)(13 DOWNTO 1) <= cceexpdelff(1)(13 DOWNTO 1);
ccesatdelff(1) <= ccsatnode;
ccesatdelff(2) <= ccesatdelff(1);
ccezipdelff(1) <= cczipnode;
ccezipdelff(2) <= ccezipdelff(1);
ccenandelff(1) <= ccnannode;
ccenandelff(2) <= ccenandelff(1);
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (cceround(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
ccesigndelff(1) <= mulsignff(signdepth);
ccesigndelff(2) <= ccesigndelff(1);
ccesigndelff(3) <= ccesigndelff(2);
END IF;
END IF;
END PROCESS;
manoverflow <= cceround(54);
cceexpbase <= cceexpdelff(2)(13 DOWNTO 1);
ccesatbase <= ccesatdelff(2);
ccezipbase <= ccezipdelff(2);
ccenanbase <= ccenandelff(2);
cceexpplus <= cceexpbase + ("000000000000" & cceround(54));
--*** OUTPUTS ***
cc(64) <= ccesigndelff(3);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
cceexpmax <= cceexpplus(11) AND cceexpplus(10) AND cceexpplus(9) AND cceexpplus(8) AND
cceexpplus(7) AND cceexpplus(6) AND cceexpplus(5) AND cceexpplus(4) AND
cceexpplus(3) AND cceexpplus(2) AND cceexpplus(1);
cceexpzero <= NOT(cceexpplus(11) OR cceexpplus(10) OR cceexpplus(9) OR cceexpplus(8) OR
cceexpplus(7) OR cceexpplus(6) OR cceexpplus(5) OR cceexpplus(4) OR
cceexpplus(3) OR cceexpplus(2) OR cceexpplus(1));
-- zip or exp condition turns mantissa zero
manoutzero <= ccesatbase OR ccezipbase OR
cceexpmax OR cceexpzero OR
cceexpplus(13) OR cceexpplus(12) OR
manoverflow;
manoutmax <= ccenanbase;
expoutzero <= ccezipbase OR cceexpzero OR cceexpplus(13);
expoutmax <= cceexpmax OR cceexpplus(12) OR ccenanbase;
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
--********************************************************
--*** if output directly into DP mult, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required, no round ***
--********************************************************
goma: IF (multoutput = 1) GENERATE -- to another multiplier
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftmanbit <= NOT(ccmannode(62));
gomb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]
manshiftnode(k) <= (ccmannode(k+8) AND shiftmanbit) OR
(ccmannode(k+9) AND NOT(shiftmanbit));
END GENERATE;
poma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccexpdelff(k) <= '0';
END LOOP;
ccsatdelff <= '0';
cczipdelff <= '0';
ccnandelff <= '0';
muloutsignff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manshiftff <= manshiftnode;
-- change 28/01/08
ccexpdelff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftmanbit));
ccsatdelff <= ccsatnode;
cczipdelff <= cczipnode;
ccnandelff <= ccnannode;
muloutsignff <= mulsignff(signdepth);
END IF;
END IF;
END PROCESS;
cc(67) <= muloutsignff;
cc(66 DOWNTO 14) <= manshiftff(53 DOWNTO 1);
cc(13 DOWNTO 1) <= ccexpdelff(13 DOWNTO 1);
ccsat <= ccsatdelff;
cczip <= cczipdelff;
ccnan <= ccnandelff;
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
aaman <= aa(67 DOWNTO 14);
bbman <= bb(67 DOWNTO 14);
gdba: IF (xoutput = 1) GENERATE
gdbb: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
ccman <= signedccxmannode;
ccexp <= ccexpnode;
END GENERATE;
gdbc: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
ccman <= ccxroundff;
ccexp <= ccxexpff(13 DOWNTO 1);
END GENERATE;
gdbd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
ccman <= ccxroundnode;
ccexp <= ccxexpdelff(2)(13 DOWNTO 1);
END GENERATE;
END GENERATE;
-- change 28/01/08
gdbe: IF (ieeeoutput = 1) GENERATE
ccexp <= cceexpoutff;
ccman <= "01" & ccemanoutff;
END GENERATE;
-- change 28/01/08
gdbf: IF (multoutput = 1) GENERATE
ccexp <= ccexpdelff(13 DOWNTO 1);
ccman <= '0' & manshiftff(53 DOWNTO 1);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff, bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236t
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
ccsatff <= "00";
cczipff <= "00";
ccnanff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
ccnanff(2) <= ccnanff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1 AND device /= 3) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gsc: IF (synthesize = 1 AND device = 3) GENERATE
tmult: hcc_mul3236t
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout(2*mantissa DOWNTO mantissa+1));
mulout(mantissa DOWNTO 1) <= (others => '0');
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc <= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFPPN3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function, with post-norm ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfppn3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfppn3236;
ARCHITECTURE rtl OF hcc_mulfppn3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aamanff, bbmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff : STD_LOGIC;
signal bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aapos, aaneg, bbpos, bbneg : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal aanumff, bbnumff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal selnode : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal sel, selff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal expadjff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal expadjnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- assume that result > 2
-- if output likely in [62..59] shift 0, if in [58..55] shift 4,
-- if in [54..51] shift 8, else shift 12 (adjust exponent accordingly)
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aamanff(k) <= '0';
bbmanff(k) <= '0';
END LOOP;
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 3 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
ccsatff <= "000";
cczipff <= "000";
ccnanff <= "000";
aanumff <= "0000";
bbnumff <= "0000";
selff <= "0000";
expadjff <= "0000";
FOR k IN 1 TO mantissa LOOP
manoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman;
bbmanff <= bbman;
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
expff(3)(10 DOWNTO 1) <= expff(2)(10 DOWNTO 1) + expadjnode;
FOR k IN 1 TO 4 LOOP
aanumff(k) <= (aapos(k) AND NOT(aa(32))) OR (aaneg(k) AND aa(32));
bbnumff(k) <= (bbpos(k) AND NOT(bb(32))) OR (bbneg(k) AND bb(32));
END LOOP;
selff <= sel;
-- "0" when sel(1), "4" when sel(2), "8" when sel(3), "12" when sel(4)
-- don't adjust during a saturate or zero condition
expadjff(2 DOWNTO 1) <= "00";
expadjff(3) <= (sel(2) OR sel(4)) AND NOT(ccsatff(1) OR cczipff(1));
expadjff(4) <= (sel(3) OR sel(4)) AND NOT(ccsatff(1) OR cczipff(1));
-- output left shift
-- mulpipe is [64..1], 44 bit output is in [62..19] for 32 bit
-- mulpipe is [72..1], 44 bit output is in [70..27] for 36 bits
FOR k IN mantissa DOWNTO 1 LOOP
manoutff(k) <= (mulout(k+mantissa-2) AND selff(1)) OR
(mulout(k+mantissa-6) AND selff(2)) OR
(mulout(k+mantissa-10) AND selff(3)) OR
(mulout(k+mantissa-14) AND selff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
aapos(1) <= aamanff(mantissa-1) OR aamanff(mantissa-2) OR aamanff(mantissa-3) OR aamanff(mantissa-4);
aapos(2) <= aamanff(mantissa-5) OR aamanff(mantissa-6) OR aamanff(mantissa-7) OR aamanff(mantissa-8);
aapos(3) <= aamanff(mantissa-9) OR aamanff(mantissa-10) OR aamanff(mantissa-11) OR aamanff(mantissa-12);
aapos(4) <= aamanff(mantissa-13) OR aamanff(mantissa-14) OR aamanff(mantissa-15) OR aamanff(mantissa-16);
bbpos(1) <= bbmanff(mantissa-1) OR bbmanff(mantissa-2) OR bbmanff(mantissa-3) OR bbmanff(mantissa-4);
bbpos(2) <= bbmanff(mantissa-5) OR bbmanff(mantissa-6) OR bbmanff(mantissa-7) OR bbmanff(mantissa-8);
bbpos(3) <= bbmanff(mantissa-9) OR bbmanff(mantissa-10) OR bbmanff(mantissa-11) OR bbmanff(mantissa-12);
bbpos(4) <= bbmanff(mantissa-13) OR bbmanff(mantissa-14) OR bbmanff(mantissa-15) OR bbmanff(mantissa-16);
aaneg(1) <= aamanff(mantissa-1) AND aamanff(mantissa-2) AND aamanff(mantissa-3) AND aamanff(mantissa-4);
aaneg(2) <= aamanff(mantissa-5) AND aamanff(mantissa-6) AND aamanff(mantissa-7) AND aamanff(mantissa-8);
aaneg(3) <= aamanff(mantissa-9) AND aamanff(mantissa-10) AND aamanff(mantissa-11) AND aamanff(mantissa-12);
aaneg(4) <= aamanff(mantissa-13) AND aamanff(mantissa-14) AND aamanff(mantissa-15) AND aamanff(mantissa-16);
bbneg(1) <= bbmanff(mantissa-1) AND bbmanff(mantissa-2) AND bbmanff(mantissa-3) AND bbmanff(mantissa-4);
bbneg(2) <= bbmanff(mantissa-5) AND bbmanff(mantissa-6) AND bbmanff(mantissa-7) AND bbmanff(mantissa-8);
bbneg(3) <= bbmanff(mantissa-9) AND bbmanff(mantissa-10) AND bbmanff(mantissa-11) AND bbmanff(mantissa-12);
bbneg(4) <= bbmanff(mantissa-13) AND bbmanff(mantissa-14) AND bbmanff(mantissa-15) AND bbmanff(mantissa-16);
selnode(1) <= aanumff(1) AND bbnumff(1);
selnode(2) <= (aanumff(1) AND bbnumff(2)) OR
(aanumff(2) AND bbnumff(1));
selnode(3) <= (aanumff(2) AND bbnumff(2)) OR
(aanumff(1) AND bbnumff(3)) OR
(aanumff(3) AND bbnumff(1));
sel(1) <= selnode(1); -- shift 0
sel(2) <= NOT(selnode(1)) AND selnode(2); -- shift 4
sel(3) <= NOT(selnode(1)) AND NOT(selnode(2)) AND selnode(3); -- shift 8
sel(4) <= NOT(selnode(1)) AND NOT(selnode(2)) AND NOT(selnode(3)); -- shift 12
expadjnode <= "000000" & expadjff;
--***************
--*** OUTPUTS ***
--***************
cc <= manoutff(mantissa) & manoutff(mantissa) & manoutff(mantissa DOWNTO 3) & expff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONG.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullong IS
GENERIC (
unsigned : integer := 0; -- 0 = signed, 1 = unsigned
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullong;
ARCHITECTURE rtl OF hcc_mullong IS
component hcc_mullongb
GENERIC (unsigned : integer := 0); -- 0 = signed, 1 = unsigned
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_mullongs
GENERIC (unsigned : integer := 0); -- 0 = signed, 1 = unsigned
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gba: IF (synthesize = 0) GENERATE
mulb: hcc_mullongb
GENERIC MAP (unsigned=>unsigned)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,
cc=>cc);
END GENERATE;
gsa: IF (synthesize = 1) GENERATE
muls: hcc_mullongs
GENERIC MAP (unsigned=>unsigned)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,
cc=>cc);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGB.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** behavioral ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongb IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongb;
ARCHITECTURE rtl OF hcc_mullongb IS
signal aabit, bbbit : STD_LOGIC;
signal aaff, bbff : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (66 DOWNTO 1);
signal muloutff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
aabit <= aa(32);
bbbit <= bb(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
aabit <= '0';
bbbit <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 33 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 66 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 32 LOOP
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aabit & aa;
bbff <= bbbit & bb;
mulff <= aaff * bbff;
muloutff <= mulff(32 DOWNTO 1);
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGS.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** synthesizable ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongs IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongs;
ARCHITECTURE syn OF hcc_mullongs IS
signal mulnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gsa: IF (unsigned = 0) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
gua: IF (unsigned = 1) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
mulcc <= mulnode(32 DOWNTO 1);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
-- 5 if stratix 2, 3 if stratix 3/4, 3 also for SV/AV.
function pipeline_latency(device : integer) return positive is
begin
case device is
when 0 => return 5;
when others => return 3;
end case;
end function pipeline_latency;
constant normtype : integer := 0;
constant pipedepth : positive := pipeline_latency(device);
type expfftype IS ARRAY (pipedepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff : STD_LOGIC;
signal bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (pipedepth DOWNTO 1);
component hcc_mul54usb
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0 -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_3xs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_28s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_29s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_38s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_57s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO pipedepth LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
FOR k IN 1 TO pipedepth LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO pipedepth LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO pipedepth LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
FOR k IN 2 TO pipedepth LOOP
ccnanff(k) <= ccnanff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO pipedepth LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
GENERIC MAP (doubleaccuracy=>doubleaccuracy,device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
gma: IF (device = 0 AND doubleaccuracy = 0) GENERATE
smone: hcc_mul54us_28s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmb: IF (device = 0 AND doubleaccuracy = 1) GENERATE
smtwo: hcc_mul54us_29s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmc: IF (device = 1 AND doubleaccuracy = 0) GENERATE
smthr: hcc_mul54us_38s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmd: IF ((device = 1 OR device = 2) AND doubleaccuracy = 1) GENERATE
smfor: hcc_mul54us_3xs
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gme: IF (device = 2 AND doubleaccuracy = 0) GENERATE
smfiv: hcc_mul54us_57s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(pipedepth)(13 DOWNTO 1);
ccsat <= ccsatff(pipedepth);
cczip <= cczipff(pipedepth);
ccnan <= ccnanff(pipedepth);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** 16/04/09 - add NAN support ***
--*** 08/11/10 - +0,-0 mantissa case ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : ***
--***************************************************
--***************************************************
--*** NOTES: ***
--*** normalize signed numbers (x input format) ***
--*** for 1x multipliers ***
--*** format signed32/36 bit mantissa and 10 bit ***
--*** exponent ***
--*** unsigned numbers for divider (S,1,23 bit ***
--*** mantissa for divider) divider packed into ***
--*** 32/36bit mantissa + exponent ***
--***************************************************
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff, aananff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal maximumnumberff : STD_LOGIC;
signal zeroexponent, zeroexponentff : STD_LOGIC;
signal exponentmiddle : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatdelff, aazipdelff, aanandelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
ccnan <= aananff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
maximumnumberff <= '0';
zeroexponentff <= '0';
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
aanandelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exponentmiddle;
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
-- 08/11/09
maximumnumberff <= aaff(mantissa+10) XOR aaff(mantissa+9);
zeroexponentff <= zeroexponent;
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
aanandelff(1) <= aanan;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
aanandelff(k) <= aanandelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
-- 08/11/10 - also where exponentmiddle is used
-- '1' if true : if countsign 0, then "111...111" (-0) or "000...000" (+0) case, zero exponent output
zeroexponent <= NOT(countsign(6) OR countsign(5) OR countsign(4) OR
countsign(3) OR countsign(2) OR countsign(1) OR maximumnumberff);
gen_exp_mid: FOR k IN 1 TO 10 GENERATE
exponentmiddle(k) <= exptopff(2)(k) AND NOT(zeroexponentff);
END GENERATE;
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
ccnan <= aanandelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
ccnan <= aanandelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
ccnan <= aanandelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** check in target=0 code ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal overflowcondition : STD_LOGIC;
signal overflowconditionff : STD_LOGIC;
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
aananff(1) <= aanan;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
aananff(k) <= aananff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth = 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(2)(13 DOWNTO 1);
END GENERATE;
gxc: IF (expbotffdepth > 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth-1 LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) +
("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
overflowcondition <= '0'; -- 20/05/09 used in exponent calculation
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
overflowbitnode(1) <= normalaaff(1);
gova: FOR k IN 2 TO 55 GENERATE
overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k);
END GENERATE;
gng: IF (doublespeed = 0) GENERATE
overflowcondition <= overflowbitnode(55);
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
overflowconditionff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
overflowconditionff <= overflowbitnode(55);
END IF;
END IF;
END PROCESS;
overflowcondition <= overflowconditionff;
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
-- overflow cannot happen here, dont insert
overflowcondition <= '0'; -- 20/05/09 used for exponent
pnf: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
png: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
end rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftcomb32;
ARCHITECTURE rtl OF hcc_rsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(32) AND shift(5));
END GENERATE;
levthr(32) <= levtwo(32);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftcomb36;
ARCHITECTURE rtl OF hcc_rsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(36) AND shift(6));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(36) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(36) <= levtwo(36);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE36.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftpipe36;
ARCHITECTURE rtl OF hcc_rsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(36) AND shiftff(2));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(36) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(36) <= levtwoff(36);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SGNPSTN.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small signed ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_sgnpstn IS
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_sgnpstn;
ARCHITECTURE rtl OF hcc_sgnpstn IS
signal pluspos, minuspos : STD_LOGIC_VECTOR (width DOWNTO 1);
BEGIN
paa: PROCESS (inbus)
BEGIN
CASE inbus IS
WHEN "0000" => pluspos <= conv_std_logic_vector (0,width);
WHEN "0001" => pluspos <= conv_std_logic_vector (offset+3,width);
WHEN "0010" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0011" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0100" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0101" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0110" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0111" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "1000" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1001" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1010" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1011" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1100" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1101" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1110" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1111" => pluspos <= conv_std_logic_vector (offset,width);
WHEN others => pluspos <= conv_std_logic_vector (0,width);
END CASE;
CASE inbus IS
WHEN "0000" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0001" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0010" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0011" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0100" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0101" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0110" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0111" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "1000" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1001" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1010" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1011" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1100" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1101" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1110" => minuspos <= conv_std_logic_vector (offset+3,width);
WHEN "1111" => minuspos <= conv_std_logic_vector (0,width);
WHEN others => minuspos <= conv_std_logic_vector (0,width);
END CASE;
END PROCESS;
gaa: FOR k IN 1 TO width GENERATE
position(k) <= (pluspos(k) AND NOT(signbit)) OR (minuspos(k) AND signbit);
END GENERATE;
END rtl;
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: svmult1.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altmult_add ACCUM_SLOAD_REGISTER="UNREGISTERED" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_AUTO_BLACKBOX="ALL" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_REGISTER="UNREGISTERED" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Stratix V" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_C0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=27 WIDTH_B=27 WIDTH_RESULT=54 clock0 dataa datab result
--VERSION_BEGIN 11.1SP1 cbx_alt_ded_mult_y 2011:11:23:21:10:03:SJ cbx_altera_mult_add 2011:11:23:21:10:03:SJ cbx_altmult_add 2011:11:23:21:10:03:SJ cbx_cycloneii 2011:11:23:21:10:03:SJ cbx_lpm_add_sub 2011:11:23:21:10:03:SJ cbx_lpm_mult 2011:11:23:21:10:03:SJ cbx_mgl 2011:11:23:21:12:10:SJ cbx_padd 2011:11:23:21:10:03:SJ cbx_parallel_add 2011:11:23:21:10:03:SJ cbx_stratix 2011:11:23:21:10:03:SJ cbx_stratixii 2011:11:23:21:10:03:SJ cbx_util_mgl 2011:11:23:21:10:03:SJ VERSION_END
--synthesis_resources = altera_mult_add 1 dsp_mac 1 reg 54
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY svmult1_mult_add_3jm3 IS
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END svmult1_mult_add_3jm3;
ARCHITECTURE RTL OF svmult1_mult_add_3jm3 IS
signal dataaff, databff: unsigned (26 DOWNTO 0);
signal prod : unsigned (53 DOWNTO 0);
BEGIN
pmult: process( clock0, reset, dataa, dataaff, datab, databff)
begin
if reset = '1' then
dataaff <= (others => '0');
databff <= (others => '0');
prod <= (others => '0');
elsif (clock0'event and clock0='1') then
dataaff <= UNSIGNED(dataa);
databff <= UNSIGNED(datab);
prod <= dataaff * databff;
end if;
end process;
result <= STD_LOGIC_VECTOR(prod);
END RTL; --svmult1_mult_add_3jm3
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY hcc_svmult1 IS
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END hcc_svmult1;
ARCHITECTURE RTL OF hcc_svmult1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (53 DOWNTO 0);
COMPONENT svmult1_mult_add_3jm3
PORT (
clock0 : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(53 DOWNTO 0);
svmult1_mult_add_3jm3_component : svmult1_mult_add_3jm3
PORT MAP (
clock0 => clock0,
reset => reset,
dataa => dataa_0,
datab => datab_0,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: C_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: C_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: ENABLE_PRELOAD_CONSTANT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: LOADCONST_VALUE NUMERIC "64"
-- Retrieval info: PRIVATE: MULT_COEFSEL STRING "0"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGC NUMERIC "0"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REG_ACCUM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: MULT_REG_SYSTOLIC_DELAY NUMERIC "0"
-- Retrieval info: PRIVATE: NUM_MULT STRING "1"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "0"
-- Retrieval info: PRIVATE: RNFORMAT STRING "54"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "54"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SYSTOLIC_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: SYSTOLIC_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "27"
-- Retrieval info: PRIVATE: WIDTHB STRING "27"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUM_SLOAD_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: COEF0_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEFSEL0_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_C0 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_0 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_1 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_2 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_3 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_MODE STRING "SIMPLE"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SYSTOLIC_DELAY1 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: SYSTOLIC_DELAY3 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "54"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 27 0 INPUT GND "dataa_0[26..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 27 0 INPUT GND "datab_0[26..0]"
-- Retrieval info: USED_PORT: result 0 0 54 0 OUTPUT GND "result[53..0]"
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 27 0 dataa_0 0 0 27 0
-- Retrieval info: CONNECT: @datab 0 0 27 0 datab_0 0 0 27 0
-- Retrieval info: CONNECT: result 0 0 54 0 @result 0 0 54 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1_inst.vhd FALSE
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_normfp1x.vhd
|
10
|
10480
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** ***
--***************************************************
-- normalize signed numbers (x input format) - for 1x multipliers
-- format signed32/36 bit mantissa, 10 bit exponent
-- unsigned numbers for divider (S,1,23 bit mantissa for divider)
-- divider packed into 32/36bit mantissa + exponent
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_normfp1x.vhd
|
10
|
10480
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** ***
--***************************************************
-- normalize signed numbers (x input format) - for 1x multipliers
-- format signed32/36 bit mantissa, 10 bit exponent
-- unsigned numbers for divider (S,1,23 bit mantissa for divider)
-- divider packed into 32/36bit mantissa + exponent
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
|
mit
|
amerc/TCP3
|
ininex.vhd
|
2
|
2893
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:08:11 04/06/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/ininex.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: initPhyNexys3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ininex IS
END ininex;
ARCHITECTURE behavior OF ininex IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT initPhyNexys3
PORT(
clk : IN std_logic;
reset : IN std_logic;
phy_reset : OUT std_logic;
out_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal phy_reset : std_logic;
signal out_en : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: initPhyNexys3 PORT MAP (
clk => clk,
reset => reset,
phy_reset => phy_reset,
out_en => out_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*400;
-- insert stimulus here
--reset <= '1';
-----
-- when 320 => tmpreset <= '1'; tmpouten <= '1'; (32.05 ns)
-- when 131147 => tmpreset <= '0'; tmpouten <= '1'; (2.62 ms)
-- when 1250000 => tmpreset <= '0'; tmpouten <= '0';(25 ms)
-- when 1499900 => tmpreset <= '0'; tmpouten <= '0'; (30 ms)
-- when 1499998 => tmpreset <= '1'; tmpouten <= '0'; (40 ns)
-- when 1500000 => tmpreset <= '1'; tmpouten <= '1'; (20 ns)
wait for clk_period*4;
reset <= '0';
wait for 40 ns;
reset <= '0';
wait for 60 ms;
reset <= '0';
wait for 4 ns;
reset <= '0';
wait for 58 ms;
reset <= '0';
wait for 250 ms;
reset <= '1';
wait for 5 ms;
--reset <= '1';
wait for 6 ms;
reset <= '0';
wait for 45 ms;
wait;
end process;
END;
|
mit
|
peteg944/music-fpga
|
Enlightened Main Project/adau1761_izedboard.vhd
|
3
|
4422
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity adau1761_izedboard is
Port ( clk_48 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
hphone_l : in std_logic_vector(15 downto 0);
hphone_r : in std_logic_vector(15 downto 0);
line_in_l : out std_logic_vector(15 downto 0);
line_in_r : out std_logic_vector(15 downto 0);
new_sample: out std_logic
);
end adau1761_izedboard;
architecture Behavioral of adau1761_izedboard is
COMPONENT i2c
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic);
END COMPONENT;
COMPONENT ADAU1761_interface
PORT(
clk_48 : IN std_logic;
codec_master_clk : OUT std_logic
);
END COMPONENT;
COMPONENT i2s_bit_clock
PORT(
clk_48 : IN std_logic;
pulse_per_bit : OUT std_logic;
i2s_clk : OUT std_logic
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
COMPONENT audio_signal
PORT(
clk : IN std_logic;
sample_taken : IN std_logic;
audio_l : OUT std_logic_vector(15 downto 0);
audio_r : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT i2s_data_interface
PORT(
clk : IN std_logic;
audio_l_in : IN std_logic_vector(15 downto 0);
audio_r_in : IN std_logic_vector(15 downto 0);
i2s_bclk : IN std_logic;
i2s_lr : IN std_logic;
audio_l_out : OUT std_logic_vector(15 downto 0);
audio_r_out : OUT std_logic_vector(15 downto 0);
new_sample : OUT std_logic;
i2s_d_out : OUT std_logic;
i2s_d_in : IN std_logic
);
END COMPONENT;
signal audio_l : std_logic_vector(15 downto 0);
signal audio_r : std_logic_vector(15 downto 0);
signal codec_master_clk : std_logic;
signal i2c_scl : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_sda_t : std_logic;
signal i2s_mosi : std_logic;
signal i2s_miso : std_logic;
signal i2s_bclk : std_logic;
signal i2s_lr : std_logic;
begin
AC_ADR0 <= '1';
AC_ADR1 <= '1';
AC_GPIO0 <= i2s_MISO;
i2s_MOSI <= AC_GPIO1;
i2s_bclk <= AC_GPIO2;
i2s_lr <= AC_GPIO3;
AC_MCLK <= codec_master_clk;
AC_SCK <= i2c_scl;
i_i2s_sda_obuf : IOBUF
port map (
IO => AC_SDA, -- Buffer inout port (connect directly to top-level port)
O => i2c_sda_i, -- Buffer output (to fabric)
I => i2c_sda_o, -- Buffer input (from fabric)
T => i2c_sda_t -- 3-state enable input, high=input, low=output
);
Inst_i2c: i2c PORT MAP(
clk => CLK_48,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
i2c_scl => i2c_scl
);
i_ADAU1761_interface: ADAU1761_interface PORT MAP(
clk_48 => clk_48 ,
codec_master_clk => codec_master_clk
);
Inst_i2s_data_interface: i2s_data_interface PORT MAP(
clk => clk_48,
audio_l_out => line_in_l,
audio_r_out => line_in_r,
audio_l_in => hphone_l,
audio_r_in => hphone_r,
new_sample => new_sample,
i2s_bclk => i2s_bclk,
i2s_d_out => i2s_MISO,
i2s_d_in => i2s_MOSI,
i2s_lr => i2s_lr
);
end Behavioral;
|
mit
|
fortesit/MIPS-CPU-simulator
|
regtable.vhd
|
1
|
2352
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity regtable is
port (
clk : in std_logic;
rst : in std_logic;
raddrA : in std_logic_vector(4 downto 0);
raddrB : in std_logic_vector(4 downto 0);
wen : in std_logic;
waddr : in std_logic_vector(4 downto 0);
din : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0);
extaddr : in std_logic_vector(4 downto 0);
extdout : out std_logic_vector(31 downto 0)
);
end regtable;
architecture arch_regtable of regtable is
type regdata is array (0 to 31) of std_logic_vector(31 downto 0);
signal RT : regdata;
begin
process(clk, rst)
variable addri : integer;
begin
if rst = '1' then
RT(0) <= (others => '0');
RT(1) <= (others => '0');
RT(2) <= (others => '0');
RT(3) <= (others => '0');
RT(4) <= (others => '0');
RT(5) <= (others => '0');
RT(6) <= (others => '0');
RT(7) <= (others => '0');
RT(8) <= (others => '0');
RT(9) <= (others => '0');
RT(10) <= (others => '0');
RT(11) <= (others => '0');
RT(12) <= (others => '0');
RT(13) <= (others => '0');
RT(14) <= (others => '0');
RT(15) <= (others => '0');
RT(16) <= (others => '0');
RT(17) <= (others => '0');
RT(18) <= (others => '0');
RT(19) <= (others => '0');
RT(20) <= (others => '0');
RT(21) <= (others => '0');
RT(22) <= (others => '0');
RT(23) <= (others => '0');
RT(24) <= (others => '0');
RT(25) <= (others => '0');
RT(26) <= (others => '0');
RT(27) <= (others => '0');
RT(28) <= "00000000000000001100000000000000";
RT(29) <= "00000000000000001111111111111100";
RT(30) <= (others => '0');
RT(31) <= (others => '0');
elsif clk'event and clk = '1' then
if wen = '1' then
addri := conv_integer(waddr);
if not(addri = 0) then
RT(addri) <= din;
end if;
end if;
end if;
end process;
process(raddrA, raddrB, extaddr, RT)
variable addrAi, addrBi, extaddri : integer;
begin
addrAi := conv_integer(raddrA);
addrBi := conv_integer(raddrB);
extaddri := conv_integer(extaddr);
doutA <= RT(addrAi);
doutB <= RT(addrBi);
extdout <= RT(extaddri);
end process;
end arch_regtable;
|
mit
|
peteg944/music-fpga
|
Experimental/RainbowMatrix and Partial Spectrum/i2c.vhd
|
3
|
2393
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral;
|
mit
|
amerc/TCP3
|
source/nexys3.vhd
|
1
|
32886
|
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
--- :Modified by Amer Al-Canaan, June 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> (100 MHz) |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (25MHz) ->+ ODDR2 +-->[GTXCLK] *** Not used in Nexys3
--- | | | **not |
--- | +-- CLK3_N (25MHZ) ->+ used |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK]<----->+ (25 MHz) |
--- | |
---[TXCLK] ----->+ (25 MHz) |
--- | |
--- [RXD]<----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER]<----->+ +<------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity NEXYS3 is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;--************* To be checked
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : inout std_logic; --* inout
RXCLK : inout std_logic; --* inout
RXD : inout std_logic_vector(3 downto 0); --* inout
TXCLK : in std_logic;
TXD : out std_logic_vector(3 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
PhyCol : inout std_logic; --* inout
CRS : in std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
--fx2Clk_pin : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
-- 7 seg out
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
-- Cellular RAM
RamCLK : out std_logic;
MemAdr : out std_logic_vector(22 downto 0);
RamAdv : out std_logic; -- Adress is valid
RamCS : out std_logic; -- CE
RamCRE : out std_logic;
MemOE : out std_logic;
RamWait : out std_logic;
MemWE : out std_logic;
MemDB : inout std_logic_vector(15 downto 0)
);
end entity NEXYS3;
architecture RTL of NEXYS3 is
component ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_25_MHZ : in std_logic;
--MII IF
TXCLK : in std_logic; --
TXER : out std_logic; --
TXEN : out std_logic; --
TXD : out std_logic_vector(3 downto 0); --
PHY_RESET : out std_logic; --
RXCLK : in std_logic; --
RXER : in std_logic;--
RXDV : in std_logic; --
RXD : in std_logic_vector(3 downto 0); --
COL : in std_logic;-- *input Added .. Collision indication
PhyCRS : in std_logic;-- *input Added .. Carrier sense
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic;
-- LEDS --AMER
GPIO_LEDS : out std_logic_vector(3 downto 0);
BtnL : in std_logic;
SW0 : in std_logic;
--7 seg
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0) -- seven-segment display anodes (one for each digit)
-- RAM
-- MemWE : out std_logic
);
end component ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component initPhyNexys3 is
port(
clk : in std_logic;
reset : in std_logic;
phy_reset : out std_logic;
out_en : out std_logic
);
end component initPhyNexys3;
-- COMPONENT STREAMS_VHDL_MODEL
-- PORT(
-- CLK : IN std_logic;
-- RST : IN std_logic;
-- TX : OUT std_logic
-- );
-- END COMPONENT;
COMPONENT CELLRAM
PORT(
CLK : IN std_logic;
ReadMem : IN std_logic;
RESET : IN std_logic;
WriteMem : IN std_logic;
ADR : OUT std_logic_vector(22 downto 0);
ADV : OUT std_logic;
CE : OUT std_logic;
CRE : OUT std_logic;
MemIDLE : OUT std_logic;
OE : OUT std_logic;
WAIT_dat_strb : OUT std_logic;
WE : OUT std_logic
);
END COMPONENT;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
signal nOEN : std_logic;
--signal toPhyReset : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk0_N : std_logic;
signal clk2x : std_logic;
signal clk50 : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT1_N : std_logic;
signal CLK_OUT50 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT2_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
--signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_TXCLK : std_logic;
-- signal INTERNAL_TXCLK_BUF_180 : std_logic;
signal TXCLK_BUF : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal RXCLK_INT : std_logic; -- Here
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal RXER_BUF : std_logic; --Added signal
signal RXD_BUF : std_logic_vector(3 downto 0); --Added signal
---Below added by AMER
signal INTERNAL_TXD : std_logic_vector(3 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
---Up added by AMER
signal COL_BUF : std_logic; --Added signal
signal ToEXTERNAL_TXER : std_logic; --Added signal
-- signal nINT : std_logic; --Added signal
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
--signal fx2Clk : std_logic;
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
signal ReadMem : std_logic;
signal WriteMem : std_logic;
signal MemIDLE : std_logic;
signal DB_i : std_logic_vector(15 downto 0);
signal DB_o : std_logic_vector(15 downto 0);
signal CellRAM_WE : std_logic;
-- --SSeg output
-- signal Tosseg_dat : std_logic_vector(15 downto 0);
-- signal ssflags : std_logic_vector;
begin
--
-- Inst_STREAMS_VHDL_MODEL: STREAMS_VHDL_MODEL PORT MAP(
-- CLK => CLK,
-- RST => INTERNAL_RST,
-- OneBitTx =>
-- );
initPhyNexys3_inst1 : initPhyNexys3 port map (
clk => CLK,
reset => RST,
phy_reset => PHY_RESET,
out_en => nOEN
);
ethernet_inst_1 : ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
CLK_25_MHZ => CLK_OUT3,
--MII IF
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
PHY_RESET => open,
RXCLK => INTERNAL_RXCLK,--ok
RXER => RXER_BUF,
RXDV => RXDV,
RXD => RXD_BUF, -- ok
COL => COL_BUF, -- ok
PhyCRS => CRS, -- ok
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK,
BtnL => GPIO_BUTTONS(0),
SW0 => GPIO_SWITCHES(0),
--LEDs and 7seg AMER
GPIO_LEDS => GPIO_LEDS(7 downto 4),
sseg_out => sseg_out,
anodes_out => anodes_out
-- RAM
--MemWE => CellRAM_WE
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 50000000,--48000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,--fx2Clk, --AMER
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,--48000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,--fx2Clk, -- AMER
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
-- Desactivated 4 leds to be used as test indicators
if OUTPUT_LEDS_STB = '1' then --AMER
GPIO_LEDS(3 downto 0) <= OUTPUT_LEDS(3 downto 0); -- AMER
end if;-- AMER
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 25.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000 ****** the main clock on Nexys3 is 100 Mhz
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
BUFG_INST9 : BUFG
port map
(O => RXCLK_BUF,
I => RXCLK_INT);
-- fx2Clk_in_buf : IBUFG
-- port map
-- (O => fx2Clk,
-- I => fx2Clk_pin);
--- The DCM has an active high RST input so RST_INV hould be same as RST
RST_INV <= RST;------------not RST; -- AMER
dcm_sp_inst: DCM_SP ----------------------------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8, -- to get 25 MHz
CLKFX_MULTIPLY => 2, -- to get 25 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0, -- input main clock = 100 MHz
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1, -- main clock input = 100 MHz
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0, -- 100 MHz
CLK90 => open,
CLK180 => clk0_N,
CLK270 => open,
CLK2X => clk2x,-- 200 MHz
CLK2X180 => open,
CLKFX => clkfx, -- 25 MHz
CLKFX180 => clkfx180, -- 25 MHz @ 180 deg.
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
----------------------------------------------------------- AMER
dcm_sp_inst2: DCM_SP -------------RXCLK----------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 40.0, -- for rxclk = 25 MHz
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF, -- 25 MHz from Phy
CLKFB => INTERNAL_RXCLK, --ok
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
--------------------------------------------------------- AMER
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2; -- 100 MHz
--
-- BUFG_INST11 : OBUF
-- port map
-- (O => RamCLK,
-- I => CLK_OUT1);
-- BUFG_INST21 : BUFG
-- port map
-- (O => MemWE,
-- I => CellRAM_WE);
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2, -- 100 MHz
I => clk0);
BUFG_INST22 : BUFG
port map
(O => CLK_OUT2_N, -- 100 MHz @180 deg.
I => clk0_N);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
-- Input buffering
IOBUF_INST10 : IOBUF
port map
(O => DB_i(0), --data bus as Output
IO => MemDB(0), -- RXCLK/PHYAD1 io pin
I => DB_o(0), -- data bus as Output
T => CellRAM_WE); --3-state enable input
--------------
IOBUF_INST11 : IOBUF
port map
(O => DB_i(1), --data bus as Output
IO => MemDB(1), -- RXCLK/PHYAD1 io pin
I => DB_o(1), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST12 : IOBUF
port map
(O => DB_i(2), --data bus as Output
IO => MemDB(2), -- RXCLK/PHYAD1 io pin
I => DB_o(2), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST13 : IOBUF
port map
(O => DB_i(3), --data bus as Output
IO => MemDB(3), -- RXCLK/PHYAD1 io pin
I => DB_o(3), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST14 : IOBUF
port map
(O => DB_i(4), --data bus as Output
IO => MemDB(4), -- RXCLK/PHYAD1 io pin
I => DB_o(4), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST15 : IOBUF
port map
(O => DB_i(5), --data bus as Output
IO => MemDB(5), -- RXCLK/PHYAD1 io pin
I => DB_o(5), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST16 : IOBUF
port map
(O => DB_i(6), --data bus as Output
IO => MemDB(6), -- RXCLK/PHYAD1 io pin
I => DB_o(6), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST17 : IOBUF
port map
(O => DB_i(7), --data bus as Output
IO => MemDB(7), -- RXCLK/PHYAD1 io pin
I => DB_o(7), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST18 : IOBUF
port map
(O => DB_i(8), --data bus as Output
IO => MemDB(8), -- RXCLK/PHYAD1 io pin
I => DB_o(8), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST19 : IOBUF
port map
(O => DB_i(9), --data bus as Output
IO => MemDB(9), -- RXCLK/PHYAD1 io pin
I => DB_o(9), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST20 : IOBUF
port map
(O => DB_i(10), --data bus as Output
IO => MemDB(10), -- RXCLK/PHYAD1 io pin
I => DB_o(10), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST21 : IOBUF
port map
(O => DB_i(11), --data bus as Output
IO => MemDB(11), -- RXCLK/PHYAD1 io pin
I => DB_o(11), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST22 : IOBUF
port map
(O => DB_i(12), --data bus as Output
IO => MemDB(12), -- RXCLK/PHYAD1 io pin
I => DB_o(12), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST23 : IOBUF
port map
(O => DB_i(13), --data bus as Output
IO => MemDB(13), -- RXCLK/PHYAD1 io pin
I => DB_o(13), -- data bus as Output
T => CellRAM_WE); --3-state enable input
------------------------
IOBUF_INST24 : IOBUF
port map
(O => DB_i(14), --data bus as Output
IO => MemDB(14), -- RXCLK/PHYAD1 io pin
I => DB_o(14), -- data bus as Output
T => CellRAM_WE); --3-state enable input
--------------
IOBUF_INST25 : IOBUF
port map
(O => DB_i(15), --data bus as Output
IO => MemDB(15), -- RXCLK/PHYAD1 io pin
I => DB_o(15), -- data bus as Output
T => CellRAM_WE); --3-state enable input
-------------------- RXCLK/PHYAD1 io pin --------
IOBUF_INST1 : IOBUF
port map
(O => RXCLK_INT,
IO => RXCLK, -- RXCLK/PHYAD1 io pin
I => '1', ---PhyAddress 1
T => nOEN); --3-state enable input
-------------------------- RXER/RXD4/PHYAD0 --------------------------
IOBUF_INST2 : IOBUF
port map
(O => RXER_BUF,
IO => RXER,
I => '1', ---(PhyAddress bit 0) = 1
T => nOEN); --3-state enable input
---------------------------- COL/CRS_DV/MODE2 -------------------------------------
IOBUF_INST3 : IOBUF
port map
(O => COL_BUF,
IO => PhyCol, --COL_BUF
I => '0', ---(MODE2 bit) = 0
T => nOEN); --3-state enable input
------------------------------- nINT/TXER/TXD4-----------------------
-----------------------------------------------------------------
IOBUF_INST5 : IOBUF ------- RXD0/MODE0----
port map
(O => RXD_BUF(0), ---RXD0 input pin
IO => RXD(0), -- RXD0/MODE0 io pin
I => '1', -- MODE0 (mode bit0) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST6 : IOBUF ------- RXD1/MODE1----
port map
(O => RXD_BUF(1), ---(interrupt input) = 1, not used
IO => RXD(1), -- RXD1/MODE1 io pin
I => '1', -- MODE1 (mode bit1) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST7 : IOBUF ------- RXD2/RMIISEL----
port map
(O => RXD_BUF(2), ---(interrupt input) = 1, not used
IO => RXD(2), -- RXD2/RMIISEL io pin
I => '0', -- RMIISEL = 0 (MII mode is selected)
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBU_INST8 : IOBUF ------- RXD3/PHYAD2----
port map
(O => RXD_BUF(3), ---(interrupt input) = 1, not used
IO => RXD(3), -- RXD3/PHYAD2 io pin
I => '0', -- PHYAD2 (Phy address bit 2)= 0
T => nOEN); --3-state enable input
-----------------------------------------------------------------
LOCKED_INTERNAL <= TX_LOCKED;
------------------------------------------------------ AMER
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 3 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--------------******************************
ODDR2_INST5 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => MemWE, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => CellRAM_WE, -- 1-bit data input (associated with C0)
D1 => CellRAM_WE, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-------------------------------------------
ODDR2_INST25 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => RamCLK, -- 1-bit output data
C0 => CLK_OUT1, -- 1-bit clock input
C1 => CLK_OUT1_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-------------------------------------------
Inst_CELLRAM: CELLRAM PORT MAP(
ADR => MemAdr,
CLK => CLK,
ReadMem => ReadMem,
RESET => INTERNAL_RST,
WriteMem => WriteMem,
ADV => RamAdv,
CE => RamCS,
CRE => RamCRE,
MemIDLE => MemIDLE,
OE => MemOE,
WAIT_dat_strb => RamWait,
WE => CellRAM_WE --
);
------------------------------------------------------ AMER
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--RamCLK <= CLK_OUT1; --50 MHz
--RamCLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --25 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
|
mit
|
thoralt/KCVGA
|
FPGA/SCREENSAVER_ROM.vhd
|
1
|
83526
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY SCREENSAVER_ROM IS PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DATA : OUT STD_LOGIC
);
END SCREENSAVER_ROM;
ARCHITECTURE Behavioral OF SCREENSAVER_ROM IS
SIGNAL rdata : STD_LOGIC;
TYPE rom_type IS ARRAY (0 TO 16383) OF STD_LOGIC;
CONSTANT ROM : rom_type := (
'1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '0', '0', '1',
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'1', '0', '0', '0', '0', '0', '1', '0', '1', '0', '0', '1', '0', '0', '1', '1', '0', '0', '1', '0', '0', '0', '0', '1', '1', '1', '0', '1', '0', '0', '0', '1', '0', '0', '1', '1', '1', '0', '0', '0', '1', '1', '1', '0', '0', '1', '1', '0', '0', '0', '1', '1', '0', '0', '0', '1', '1', '1', '0', '1', '0', '0', '1', '1', '0', '0', '1', '0', '1', '0', '1', '0', '0', '1', '1', '1', '0', '1', '0', '1', '0', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '0', '1', '0', '1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
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'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
'1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
'1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1'
);
BEGIN
rdata <= ROM(conv_integer(ADDR));
PROCESS (CLK)
BEGIN
IF rising_edge(CLK) THEN
DATA <= rdata;
END IF;
END PROCESS;
END Behavioral;
|
mit
|
migueljiarr/RV32I
|
src/right_arith_XLEN_barrel_shifter.vhd
|
1
|
1366
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_arith_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_arith_XLEN_barrel_shifter;
architecture structural of right_arith_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i(31) & i(31 downto 1);
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= i(31) & i(31) & s1(31 downto 2);
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= i(31) & i(31) & i(31) & i(31) & s2(31 downto 4);
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & s3(31 downto 8);
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & s4(31 downto 16);
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
|
mit
|
SRI-CSL/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/SinPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for SinPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinPiDPStratixVf400_safe_path;
PACKAGE body SinPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_mul3236s.vhd
|
10
|
4308
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/math_package_cmd.vhd
|
10
|
16872
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE math_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component fp_inv
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component fp_invsqr
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_exp
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC;
oneout : OUT STD_LOGIC
);
end component;
component fp_log
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_sin
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_cos
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_tan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_asin
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_acos
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_atan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component dp_inv
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_invsqr
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_exp
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_log
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END component;
component dp_floatfix IS
GENERIC (
unsigned : integer := 1; -- unsigned = 0, signed = 1
decimal : integer := 14;
fractional : integer := 6;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
sign : IN STD_LOGIC;
exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1);
fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1)
);
END component;
END math_package_cmd;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_rsftpipe64.vhd
|
10
|
5204
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_ldexp.vhd
|
10
|
4877
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_ldexp;
ARCHITECTURE rtl OF dp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 11 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(13 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 11 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(11)) OR (NOT(expzeronode(11)) AND NOT(expnode(12))) OR (expnode(13));
expmaxout <= expmaxin(11) OR (expmaxnode(11) AND NOT(expnode(12))) OR (expnode(12) AND NOT(expnode(13)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(52));
mannonzero <= manzeroin(52);
satnode <= (expmaxin(11) AND NOT(manzeroin(52))) OR expmaxout;
zeronode <= NOT(expzeroin(11)) OR expzeroout;
nannode <= expmaxin(11) AND manzeroin(52);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_neg1x.vhd
|
10
|
5243
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG1X.VHD ***
--*** ***
--*** Function: Negate Variable ***
--*** ***
--*** Input is normalized S,'1',mantissa,exp ***
--*** ***
--*** 14/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg1x IS
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg1x;
ARCHITECTURE rtl OF hcc_neg1x IS
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
-- x output
signal ccxman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccxexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- function output
signal ccfuncman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccfuncexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- ieee output
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, expoutzero, expoutmax : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
--******************************
--*** internal format output ***
--******************************
goxa: IF (xoutput = 1) GENERATE
goxb: FOR k IN 1 TO mantissa GENERATE
ccxman(k) <= NOT(aaff(k+10));
END GENERATE;
ccxexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccxman & ccxexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--***************************************
--*** internal function format output ***
--***************************************
gofa: IF (funcoutput = 1) GENERATE
ccfuncman(mantissa) <= NOT(aaff(mantissa+10));
ccfuncman(mantissa-1 DOWNTO 1) <= aaff(mantissa+9 DOWNTO 11);
ccfuncexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccfuncman & ccfuncexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--**************************
--*** IEEE format output ***
--**************************
goia: IF (ieeeoutput = 1) GENERATE
expnode <= aaff(10 DOWNTO 1);
pio: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= aaff(k+mantissa-15) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (expnode(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
END IF;
END PROCESS;
expmax <= expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
expzero <= NOT(expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
manoutzero <= aasatff OR aazipff OR expmax OR expzero OR expnode(10) OR expnode(9);
expoutzero <= aazipff OR expzero OR expnode(10);
expoutmax <= aasatff OR expmax OR (NOT(expnode(10)) AND expnode(9));
-- OUTPUTS
cc <= NOT(aaff(mantissa+10)) & expoutff & manoutff;
ccsat <= '0';
cczip <= '0';
END GENERATE;
END rtl;
|
mit
|
bpervan/simple-soc
|
pcores/uart_cntrl_v1_00_a/hdl/vhdl/BaudRateGenerator.vhd
|
1
|
1381
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:25 03/11/2014
-- Design Name:
-- Module Name: BaudRateGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BaudRateGenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end BaudRateGenerator;
architecture Behavioral of BaudRateGenerator is
signal brojac, brojacNext : unsigned (9 downto 0);
begin
process (clk, rst)
begin
if(rst = '0') then
brojac <= "0000000000";
else
if (clk'event and clk = '1') then
brojac <= brojacNext;
end if;
end if;
end process;
brojacNext <= "0000000000" when brojac = 651 else
brojac + 1;
tick <= '1' when brojac = 651 else '0';
end Behavioral;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_mul3s.vhd
|
10
|
5539
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_sqr.vhd
|
10
|
8540
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** DP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 57 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY dp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_sqr;
ARCHITECTURE rtl OF dp_sqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 54
-- top latency = core + 1 (input) + 2 (output) = 57
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_lnrnd.vhd
|
10
|
5431
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/dp_lnrnd.vhd
|
10
|
5431
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_castytof.vhd
|
10
|
3181
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>midnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,
cc=>cc);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_inv_core.vhd
|
10
|
9935
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - CORE ***
--*** ***
--*** DP_INV_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublepeed ***
--*** SIII Latency = 18 + doublespeed ***
--***************************************************
ENTITY dp_inv_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
END dp_inv_core;
ARCHITECTURE rtl OF dp_inv_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaleden : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal twonode, subscaleden : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessone : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteval : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal absolutevalff, absoluteff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal abscarryff : STD_LOGIC;
signal iteratenumnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal iteratenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteerror : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal mulabsguessff : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal mulabsguess : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(54 DOWNTO 36),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8+speed
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(54 DOWNTO 1);
gta: FOR k IN 1 TO 54 GENERATE
subscaleden(k) <= NOT(scaleden(k));
END GENERATE;
subscaleden(55) <= '1';
-- in level 8+doublespeed, outlevel 9+2*doublespeed
addtwoone: dp_fxadd
GENERIC MAP (width=>55,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>twonode,bb=>subscaleden,carryin=>'1',
cc=>guessone);
guessonevec <= guessone(54 DOWNTO 1);
-- absolute value of guess lower 36 bits
-- this is still correct, because (for positive), value will be 1.(17 zeros)error
-- can also be calculated from guessonevec (code below)
-- gabs: FOR k IN 1 TO 36 GENERATE
-- absoluteval(k) <= guessonevec(k) XOR NOT(guessonevec(54));
-- END GENERATE;
gabs: FOR k IN 1 TO 36 GENERATE
absoluteval(k) <= scaleden(k) XOR NOT(scaleden(54));
END GENERATE;
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
absolutevalff(k) <= '0';
absoluteff(k) <= '0';
END LOOP;
abscarryff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absolutevalff <= absoluteval; -- out level 9+speed
abscarryff <= NOT(scaleden(54));
absoluteff <= absolutevalff + (zerovec(35 DOWNTO 1) & abscarryff); -- out level 10+speed
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>18,pipes=>4+2*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invdivisor,
cc=>delinvdivisor);
-- in level 9+2*doublespeed, out level 12+3*doublespeed
muloneone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>delinvdivisor,
result=>iteratenumnode);
-- in level 10+doublespeed, out level 13+doublespeed
mulonetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>absoluteff,databb=>absoluteff,
result=>absoluteerror);
-- if speed = 0, delay absoluteerror 1 clock, else 2
-- this guess always positive (check??)
-- change here, error can be [19:1], not [18:1] - this is because (1.[17 zeros].error)^2
-- gives 1.[34 zeros].error
pgaa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 19 LOOP
mulabsguessff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulabsguessff <= absoluteerror(72 DOWNTO 54) +
(zerovec(18 DOWNTO 1) & absoluteerror(53));
END IF;
END IF;
END PROCESS;
mulabsguess(19 DOWNTO 1) <= mulabsguessff;
gmga: FOR k IN 20 TO 53 GENERATE
mulabsguess(k) <= '0';
END GENERATE;
mulabsguess(54) <= '1';
-- mulabsguess at 14+doublespeed depth
-- iteratenum at 12+3*doublespeed depth
-- mulabsguess 5 (5)clocks from absolutevalff
-- iteratenum 3+2doublespeed (3/5)clocks from abssolutevalff
-- delay iterate num
gdoa: IF (doublespeed = 0) GENERATE
delonetwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>iteratenumnode,
cc=>iteratenum);
END GENERATE;
gdob: IF (doublespeed = 1) GENERATE
iteratenum <= iteratenumnode;
END GENERATE;
--*********************
--*** OUTPUT SCALE ***
--*********************
-- in level 14+doublespeed
-- SII out level 19+2*doublespeed
-- SIII/IV out level 18+doublespeed
mulout: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>iteratenum,databb=>mulabsguess,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 17);
END rtl;
|
mit
|
ou-cse-378/vhdl-tetris
|
acode.vhd
|
1
|
1116
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: acode.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity Acode is
port (
Aen : in STD_LOGIC_VECTOR (3 downto 0);
Asel : in STD_LOGIC_VECTOR (1 downto 0);
A : out STD_LOGIC_VECTOR (3 downto 0)
);
end Acode;
architecture Acode_arch of Acode is
begin
process(Aen, Asel)
begin
A <= "0000";
case Asel is
when "00" =>
if Aen(0) = '1' then
A <= "1000";
end if;
when "01" =>
if Aen(1) = '1' then
A <= "0100";
end if;
when "10" =>
if Aen(2) = '1' then
A <= "0010";
end if;
when others =>
if Aen(3) = '1' then
A <= "0001";
end if;
end case;
end process;
end Acode_arch;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_mulfp3236.vhd
|
10
|
5397
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00";
cczipff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc<= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
END rtl;
|
mit
|
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